A simulation method and device for single event effects of a three-dimensional monolithic integrated circuit

Abstract

The application provides a three-dimensional monolithic integrated circuit single particle effect simulation method and device, the method comprising: creating a three-dimensional monolithic integrated circuit model corresponding to a target device; creating a corresponding energy deposition model for each layer of circuit structure model; based on the target incident particles, energy deposition simulation is performed on each energy deposition model to obtain the target LET corresponding to each layer of circuit structure model; based on the target incident particles and the target linear energy transfer value corresponding to each layer of circuit structure model, the single particle effect simulation of the three-dimensional monolithic integrated circuit model is performed; in this way, a corresponding energy deposition model is created for each layer of circuit structure model, energy deposition simulation is performed on each energy deposition model, the target LET corresponding to each layer of circuit structure model is obtained, and the single particle effect simulation of the three-dimensional monolithic integrated circuit model is performed, so as to ensure the accuracy of the simulation result, adjust the structure and parameters of the three-dimensional monolithic integrated circuit according to the simulation result, and improve the reliability of the circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a simulation method and device for single event effects of three-dimensional monolithic integrated circuits. BACKGROUND

[0002] With the continuous reduction of transistor scale, interconnection delay becomes non-negligible, and three-dimensional monolithic (M3D) integration is considered as one of the effective ways to solve the physical limitations of Moore's law. This technology enables each layer to be stacked in order at the transistor scale. Compared with traditional planar integration, M3D integration can achieve higher integration density while reducing interconnection length and power consumption. Therefore, M3D technology has broad application prospects in the field of integrated circuits.

[0003] However, the radiation environment is on the earth where we live and in space and the universe, and the integrated circuits and electronic devices applied in different radiation environments may have corresponding radiation effects, such as single event effects. In terms of single event upset (SEU) type of single event effects, soft errors caused by single event upset will seriously affect the reliability of avionics products, especially the reliability of static random access memory (SRAM). Therefore, in order to improve the reliability of three-dimensional monolithic integrated circuits, it is necessary to simulate three-dimensional monolithic integrated circuits, and then improve the reliability of electronic products according to the simulation results.

[0004] In related technologies, most researches are still focused on single event effects in two-dimensional integrated SRAMs, therefore, it has become one of the problems to be solved by those skilled in the art to propose a method for simulating single event effects of three-dimensional monolithic integrated circuits. SUMMARY

[0005] In view of the problems in the prior art, the embodiments of the present application provide a simulation method and device for single event effects of three-dimensional monolithic integrated circuits, to solve the technical problems that the prior art cannot effectively simulate single event effects of three-dimensional monolithic integrated circuits, and thus cannot improve the reliability of three-dimensional monolithic integrated circuits.

[0006] The present application provides a simulation method for single event effects of three-dimensional monolithic integrated circuits, the method comprising:

[0007] creating a three-dimensional monolithic integrated circuit model corresponding to a target device, the three-dimensional monolithic integrated circuit model comprising at least two layer circuit structure models;

[0008] creating a corresponding energy deposition model for each layer circuit structure model;

[0009] determining a target incident particle, performing energy deposition simulation on each of the energy deposition models based on the target incident particle, and obtaining a target linear energy transfer value corresponding to each layer of the circuit structure model;

[0010] performing single event effect simulation on the three-dimensional monolithic integrated circuit model based on the target incident particle and the target linear energy transfer value corresponding to each layer of the circuit structure model.

[0011] Optionally, when the three-dimensional monolithic integrated circuit model includes two layers of circuit structure models, the three-dimensional monolithic integrated circuit model includes:

[0012] a substrate;

[0013] a first buried oxide layer located above the substrate;

[0014] a first active region located above the first buried oxide layer;

[0015] an intermediate layer dielectric layer located above the first active region;

[0016] a second buried oxide layer located above the intermediate layer dielectric layer;

[0017] a second active region located above the second buried oxide layer.

[0018] Optionally, the three-dimensional monolithic integrated circuit model includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, and a second PMOS transistor; wherein,

[0019] the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are located in the second active region;

[0020] the first PMOS transistor and the second PMOS transistor are located in the first active region.

[0021] Optionally, the creating of the corresponding energy deposition model for each layer of the circuit structure model includes:

[0022] for any one of the circuit structure models, determining a target energy deposition area corresponding thereto; the center of the target energy deposition area is concentric with the center of the drain of the MOS transistor in the corresponding circuit structure model;

[0023] for any one of the target energy deposition areas, determining a target radius of the target energy deposition area.

[0024] Optionally, the determining of the target energy deposition area includes:

[0025] For any layer, the circuit structure model determines the maximum reference radius and the minimum reference radius of the energy deposition area;

[0026] A plurality of reference deposition energy areas with a radius difference of 1 nm are established between the maximum reference radius and the minimum reference radius;

[0027] According to the order of the reference energy deposition area radius from small to large, the energy deposition simulation is sequentially performed on the energy deposition model, and the reference deposition energy corresponding to each reference energy deposition area is obtained.

[0028] When it is determined that the reference deposition energy is less than the minimum deposition energy, the corresponding target reference energy deposition area is obtained, and the target reference energy deposition area is the target energy deposition area; wherein the minimum deposition energy is 3.6eV.

[0029] The application also provides a simulation device for single particle effect of three-dimensional monolithic integrated circuit, the device comprises:

[0030] The first creating unit is used for creating a three-dimensional monolithic integrated circuit model corresponding to a target device, and the three-dimensional monolithic integrated circuit model comprises at least two layers of circuit structure models.

[0031] The second creating unit is used for creating an energy deposition model corresponding to each layer of circuit structure model.

[0032] The first simulation unit is used for determining a target incident particle, performing energy deposition simulation on each energy deposition model based on the target incident particle, and obtaining a target linear energy transfer value corresponding to each layer of circuit structure model.

[0033] The second simulation unit is used for performing single particle effect simulation on the three-dimensional monolithic integrated circuit model based on the target incident particle and the target linear energy transfer value corresponding to each layer of circuit structure model.

[0034] Optionally, when the three-dimensional monolithic integrated circuit model comprises two layers of circuit structure models, the three-dimensional monolithic integrated circuit model comprises:

[0035] A substrate;

[0036] A first buried oxygen layer is located above the substrate;

[0037] A first active region is located above the first buried oxygen layer;

[0038] An intermediate layer dielectric layer is located above the first buried oxygen layer;

[0039] A second buried oxygen layer is located above the intermediate layer dielectric layer;

[0040] A second active region is located above the second buried oxide layer.

[0041] Optionally, the three-dimensional monolithic integrated circuit model comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor and a second PMOS transistor; wherein,

[0042] The first NMOS transistor, the second NMOS transistor, the third NMOS transistor and the fourth NMOS transistor are located in the second active region;

[0043] The first PMOS transistor and the second PMOS transistor are located in the first active region.

[0044] Optionally, the second creating unit is specifically configured to:

[0045] For any layer of the circuit structure model, a corresponding target energy deposition area is determined; the center of the target energy deposition area is concentric with the drain center of the MOS transistor in the corresponding circuit structure model;

[0046] For any target energy deposition area, the radius of the target energy deposition area is determined.

[0047] Optionally, the second creating unit is specifically configured to:

[0048] For any layer of the circuit structure model, the maximum reference radius and the minimum reference radius of the energy deposition area are determined;

[0049] A plurality of reference deposition energy areas with a radius difference of 1 nm are established between the maximum reference radius and the minimum reference radius;

[0050] According to the order of the reference energy deposition area radius from small to large, the energy deposition simulation is sequentially performed on the energy deposition model to obtain the reference deposition energy corresponding to each reference energy deposition area;

[0051] When it is determined that the reference deposition energy is less than the minimum deposition energy, a corresponding target reference energy deposition area is obtained, and the target reference energy deposition area is the target energy deposition area; wherein the minimum deposition energy is 3.6eV.

[0052] This invention provides a simulation method and apparatus for single-event effects in a three-dimensional monolithic integrated circuit. The method includes: creating a three-dimensional monolithic integrated circuit model corresponding to a target device, wherein the three-dimensional monolithic integrated circuit model includes at least two circuit structure models; creating a corresponding energy deposition model for each circuit structure model; determining a target incident particle; performing energy deposition simulation on each of the energy deposition models based on the target incident particle to obtain the target linear energy transfer value corresponding to each circuit structure model; and performing single-event effect simulation on the three-dimensional monolithic integrated circuit model based on the target incident particle and the target linear energy transfer value corresponding to each circuit structure model. The three-dimensional monolithic integrated circuit structure is a unique stacked structure. When particles pass through the transistors of each layer, the energy deposition in each layer of the circuit varies greatly due to scattering. Therefore, this invention creates a corresponding energy deposition model for each layer of the circuit structure model, performs energy deposition simulation on each energy deposition model, obtains the target linear energy transfer value corresponding to each layer of the circuit structure model, and then uses the target linear energy transfer value of each layer to perform single-event effect simulation on the three-dimensional monolithic integrated circuit model to ensure more accurate simulation results. Based on the simulation results, the structure and parameters of the three-dimensional monolithic integrated circuit can be precisely adjusted to improve the reliability of the three-dimensional monolithic integrated circuit. Attached Figure Description

[0053] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0054] Figure 1 A schematic flowchart illustrating the simulation method for single-event effects on a three-dimensional monolithic integrated circuit provided in an embodiment of the present invention;

[0055] Figure 2 A schematic diagram of the structure of a three-dimensional monolithic integrated circuit model when the target device provided in the embodiments of the present invention is an SRAM with an integrated two-layer circuit structure;

[0056] Figure 3 Circuit diagram of a three-dimensional monolithic integrated circuit model provided in the embodiments of the present invention;

[0057] Figure 4 This is another structural diagram of the three-dimensional monolithic integrated circuit model provided in the embodiments of the present invention;

[0058] Figure 5 This is a top view of the energy deposition region corresponding to each circuit layer in the three-dimensional monolithic integrated circuit model provided in this embodiment of the invention;

[0059] Figure 6 A structure diagram of a simulation device for single event effect of three-dimensional monolithic integrated circuit is provided for an embodiment of the present application. DETAILED DESCRIPTION

[0060] In order to solve the technical problem that the single event effect of three-dimensional monolithic integrated circuit cannot be simulated effectively in the prior art, and the reliability of three-dimensional monolithic integrated circuit cannot be improved, an embodiment of the present application provides a simulation method and device for single event effect of three-dimensional monolithic integrated circuit.

[0061] In order to better understand the above technical solution, the technical solution of the embodiment of the present application will be described in detail below with reference to the drawings and specific embodiments. It should be understood that the specific features in the embodiments of the present application and the embodiments are detailed descriptions of the technical solution of the embodiment of the present application, and are not limitations of the technical solution of the present application. In the case of no conflict, the technical features in the embodiments of the present application and the embodiments can be combined with each other.

[0062] Embodiment one

[0063] The embodiment provides a simulation method for single event effect of three-dimensional monolithic integrated circuit, as shown in the method, the method comprises the following steps: Figure 1

[0064] S110, creating a three-dimensional monolithic integrated circuit model corresponding to a target device, the three-dimensional monolithic integrated circuit model comprising at least two layers of circuit structure models;

[0065] The target device described herein is a semiconductor device based on three-dimensional monolithic integrated circuit. The target device can be a memory (such as SRAM), or a non-memory type semiconductor device.

[0066] Firstly, a simulation tool (TCAD, Technology Computer Aided Design) can be used to create a three-dimensional monolithic integrated circuit model corresponding to a target device, and the three-dimensional monolithic integrated circuit model comprises at least two layers of circuit structure models. For example, the three-dimensional monolithic integrated circuit model can comprise two layers of circuit structure models, three layers of circuit structure models, or four layers of circuit structure models. The target device in the embodiment of the present application is an SRAM integrated with two layers of circuit structure.

[0067] When the target device is an SRAM integrated with two layers of circuit structure, the created three-dimensional monolithic integrated circuit model also comprises two layers of circuit structure models, which can refer to Figure 2 The three-dimensional monolithic integrated circuit model comprises:

[0068] a substrate 21;

[0069] ​A first buried oxide layer 22 is located above the substrate 21; a first active region 23 is located above the first buried oxide layer 22;

[0070] An intermediate dielectric layer 24 is located above the first active region 23;

[0071] A second buried oxide layer 25 is located above the intermediate dielectric layer 24;

[0072] A second active region 26 is located above the second buried oxide layer 25.

[0073] The material of the substrate 21 can be Si; the first buried oxide layer 22 can be understood as a bottom buried oxide layer, and the material of the first buried oxide layer 22 is SiO2; the first active region 23 can be understood as a bottom active region, and the material of the first active region 23 is Si; the material of the intermediate dielectric layer 24 is SiO2; the second buried oxide layer 25 can be understood as a top buried oxide layer, and the material of the second buried oxide layer 25 is SiO2; the second active region 26 can be understood as a top active region, and the material of the second active region 26 is Si.

[0074] Here, the first buried oxide layer 22 and the first active region 23 are located in a bottom circuit structure, the second buried oxide layer 25 and the second active region 26 are located in a top circuit structure, and the top circuit structure and the bottom circuit structure are connected through an interlayer hole 27. The interlayer hole 27 between the two layers is located in the intermediate dielectric layer 24. In addition, in the bottom circuit structure, Figure 2 Here, the mark 29 is a gate, and the mark 28 is an interconnection line.

[0075] Here, referring to Figure 3 , the three-dimensional monolithic integrated circuit model comprises: a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3, a fourth NMOS transistor M4, a first PMOS transistor M5, and a second PMOS transistor M6; wherein,

[0076] The first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3, and the fourth NMOS transistor M4 are located in the second active region 26;

[0077] The first PMOS transistor M5 and the second PMOS transistor M6 are located in the first active region 23.

[0078] Referring to Figure 4 , M2 and M3 are transmission tubes; M1 and M5 are a first inverter, and M4 and M6 are a second inverter, and the first inverter and the second inverter are two pairs of interlocked inverters.

[0079] In addition, in the three-dimensional monolithic integrated circuit model, Figure 4 Here, the mark WL is a word line, the mark BL is a bit line, the mark V DD is a power supply, and the marks Q and Qn are storage nodes.

[0080] It should be noted that the positions of M1, M2, M3 and M4 in the embodiment of the present application can also be located in the first active region, and the positions of M5 and M6 can also be located in the second active region, which is not limited herein.

[0081] S111, creating a corresponding energy deposition model for each layer of the circuit structure model;

[0082] Since the M3D integrated SRAM has a unique stacked structure, particles passing through upper and lower transistors will have a large difference in energy deposition due to scattering and other reasons. Therefore, in order to ensure the accuracy of the simulation results, the embodiment of the present application needs to create a corresponding energy deposition model for each layer of the circuit structure model.

[0083] In the embodiment, a charge deposition simulation tool can be used to create a corresponding energy deposition model for each layer of the circuit structure model. For example, the charge deposition simulation tool can be GEANT4 simulation tool.

[0084] Since the drain center of each MOS transistor is the most sensitive node, and the existence of the interconnection line has a significant impact on the particle track, the impact of the interconnection line needs to be considered when creating the energy deposition model. Therefore, creating a corresponding energy deposition model for each layer of the circuit structure model includes:

[0085] For any layer of the circuit structure model, a corresponding target energy deposition region is determined; the center of the target energy deposition region is concentric with the drain center of the MOS transistor in the corresponding circuit structure model.

[0086] For any target energy deposition region, a target radius of the target energy deposition region is determined.

[0087] That is, for the target energy deposition region of the upper layer of the circuit structure model, the center of the target energy deposition region is concentric with the drain center of M1, M2, M3 and M4; for the target energy deposition region of the lower layer of the circuit structure model, the center of the target energy deposition region is concentric with the drain center of M5 and M6.

[0088] Reference can be made to Figure 5 , the energy deposition region 51 is circular, and the energy deposition at different layers is obtained by collecting the energy deposition region after the particle is incident. The target radius of each target energy deposition region is the corresponding radius when the deposited energy is reduced to the minimum deposited energy for generating electron-hole pairs; the minimum deposited energy is 3.6eV.

[0089] Specifically, determining the target energy deposition region includes:

[0090] For any layer of circuit structure model, the maximum reference radius and the minimum reference radius of the energy deposition region are determined; wherein the minimum reference radius can be understood as the radius set when the initial simulation is performed, and the maximum reference radius and the minimum reference radius can be determined according to historical experience data; the minimum reference radius is 1nm;

[0091] A plurality of reference energy deposition regions with a radius difference of 1nm are established between the minimum reference radius and the maximum reference radius;

[0092] In order to the energy deposition model, the energy deposition simulation is performed in the order of the reference energy deposition region radius from small to large, and the reference deposition energy corresponding to each reference energy deposition region is obtained.

[0093] When the reference deposition energy is determined to be less than the minimum deposition energy, the corresponding target reference energy deposition region is obtained, and the target reference energy deposition region is the target energy deposition region. Wherein, the target reference energy deposition region is the reference energy deposition region corresponding to the reference deposition energy less than the minimum deposition energy.

[0094] It should be noted that each time the energy deposition model is simulated based on the reference energy deposition region, the reference deposition energy is compared with the minimum deposition energy, if the reference deposition energy is less than the minimum deposition energy, the energy deposition simulation is terminated; if the reference deposition energy is greater than the minimum deposition energy, the radius of the reference energy deposition region is increased, and the energy deposition model is simulated again until the reference deposition energy is less than the minimum deposition energy.

[0095] Here, after each energy deposition simulation of the energy deposition model, the corresponding charge curve can be obtained, and the reference deposition energy is determined according to the charge curve. Wherein, the charge curve can be a current-time curve, or a voltage-time curve.

[0096] It should be noted that the target radius of the energy deposition region also needs to determine the target incident particle, and the specific determination method of the target incident particle will be described in detail in the following step S112, so it is not repeated here.

[0097] And when the particle type includes multiple types, the critical charge corresponding to each particle can also be obtained when the energy deposition simulation is performed each time, and each particle and the corresponding critical charge are stored in the database for the convenience of other staff.

[0098] Wherein, the target radius of the energy deposition region in each layer of circuit structure model is different, which can continue to refer to Figure 2 , the energy deposition region of the top layer circuit structure model is shown as mark 30, and the energy deposition region of the bottom layer circuit structure model is shown as mark 31.

[0099] S112, determine target incident particles, perform energy deposition simulation on each energy deposition model based on the target incident particles, and obtain target linear energy transfer values corresponding to each layer of the circuit structure model;

[0100] In this embodiment, since the M3D integrated SRAM unit occupies a small space (<100 nm), a high-precision particle beam needs to be used for heavy ion experiments, and existing accelerators cannot provide a high-precision particle beam. Moreover, the laser widely used in two-dimensional circuits cannot penetrate the metal covering the sensitive area of the M3D device, and is not suitable for heavy ion experiments of M3D integrated SRAM.

[0101] Therefore, in this embodiment, the SRIM simulation tool is used to determine the target incident particles. For different types of particles, when the particles are incident, the SRIM simulation tool can be used to measure the penetration depth and trajectory of the particles in different layers of the circuit structure after the particles are incident, and then the target incident particles are determined according to the penetration depth and trajectory. It should be noted that the corresponding target incident particles should be different in different environments.

[0102] After the target incident particles are determined, the charge deposition simulation tool is used to perform energy deposition simulation on each energy deposition model based on the target incident particles, and obtain target linear energy transfer values (LET, Linear Energy Transfer) corresponding to each layer of the circuit structure model.

[0103] In this way, the target linear energy transfer values of each layer of the circuit structure in the three-dimensional monolithic integrated circuit can be accurately obtained, and the simulation accuracy can be ensured when the target linear energy transfer values are used to simulate the single event effect of the three-dimensional monolithic integrated circuit in the subsequent process.

[0104] S113, based on the target incident particles and the target linear energy transfer values corresponding to each layer of the circuit structure model, perform single event effect simulation on the three-dimensional monolithic integrated circuit model.

[0105] After the target linear energy transfer values corresponding to each layer of the circuit structure model are determined, the TCAD simulation tool is used to perform single event effect simulation on the three-dimensional monolithic integrated circuit model based on the target incident particles, and obtain the electrical characteristic curve of the three-dimensional monolithic integrated circuit model, such as the current curve.

[0106] Then, the electrical parameters and circuit structure of the three-dimensional monolithic integrated circuit can be determined according to the electrical characteristic curve to improve the reliability of the three-dimensional monolithic integrated circuit.

[0107] In the embodiment of the present application, since the three-dimensional monolithic integrated circuit structure is a unique stacked structure, the energy deposition in each layer of circuit has a large difference due to scattering when particles pass through the transistors of each layer. Therefore, the embodiment of the present application creates a corresponding energy deposition model for each layer of circuit structure model, performs energy deposition simulation on each energy deposition model, obtains the target line performance energy transfer value corresponding to each layer of circuit structure model, and then performs single event effect simulation on the three-dimensional monolithic integrated circuit model using the target line performance energy transfer value of each layer, so as to ensure that more accurate simulation results can be obtained, and then the current structure and parameters of the three-dimensional monolithic integrated circuit can be accurately adjusted according to the simulation results, thereby improving the reliability of the three-dimensional monolithic integrated circuit.

[0108] Based on the same inventive concept as the foregoing embodiment, the embodiment of the present application also provides a simulation device for single event effect of three-dimensional monolithic integrated circuit, as shown in Figure 6 The device comprises:

[0109] A first creating unit 61 is configured to create a three-dimensional monolithic integrated circuit model corresponding to a target device, and the three-dimensional monolithic integrated circuit model comprises at least two layers of circuit structure models.

[0110] A second creating unit 62 is configured to create a corresponding energy deposition model for each layer of circuit structure model.

[0111] A first simulation unit 63 is configured to determine a target incident particle, perform energy deposition simulation on each energy deposition model based on the target incident particle, and obtain a target line performance energy transfer value corresponding to each layer of circuit structure model.

[0112] A second simulation unit 64 is configured to perform single event effect simulation on the three-dimensional monolithic integrated circuit model based on the target incident particle and the target line performance energy transfer value corresponding to each layer of circuit structure model.

[0113] The target device described herein is a semiconductor device based on a three-dimensional monolithic integrated circuit, and the target device can be a memory (such as SRAM) or a non-memory type semiconductor device.

[0114] Firstly, the first creating unit 61 can create a three-dimensional monolithic integrated circuit model corresponding to a target device by using a simulation tool TCAD, and the three-dimensional monolithic integrated circuit model comprises at least two layers of circuit structure models. For example, the three-dimensional monolithic integrated circuit model can comprise two layers of circuit structure models, three layers of circuit structure models, or four layers of circuit structure models. The target device in the embodiment of the present application is an SRAM integrated with two layers of circuit structure.

[0115] When the target device is an SRAM integrated with two layers of circuit structure, the created three-dimensional monolithic integrated circuit model also comprises two layers of circuit structure models, which can be referred to as Figure 2A three-dimensional monolithic integrated circuit model comprises:

[0116] A substrate 21;

[0117] A first buried oxide layer 22 is located above the substrate 21; a first active region 23 is located above the first buried oxide layer 22;

[0118] An intermediate dielectric layer 24 is located above the first active region 23;

[0119] A second buried oxide layer 25 is located above the intermediate dielectric layer 24;

[0120] A second active region 26 is located above the second buried oxide layer 25.

[0121] The material of the substrate 21 can be Si; the first buried oxide layer 22 can be understood as a bottom buried oxide layer, and the material of the first buried oxide layer 22 is SiO2; the first active region 23 can be understood as a bottom active region, and the material of the first active region 23 is Si; the material of the intermediate dielectric layer 24 is SiO2; the second buried oxide layer 25 can be understood as a top buried oxide layer, and the material of the second buried oxide layer 25 is SiO2; the second active region 26 can be understood as a top active region, and the material of the second active region 26 is Si.

[0122] Here, the first buried oxide layer 22 and the first active region 23 are located in a bottom circuit structure, the second buried oxide layer 25 and the second active region 26 are located in a top circuit structure, and the top circuit structure and the bottom circuit structure are connected through an interlayer hole 27. The interlayer hole 27 between the two layers is located in the intermediate dielectric layer 24. In addition, in Figure 2 The mark 29 is a gate, and the mark 28 is an interconnection line.

[0123] Here, referring to Figure 3 A three-dimensional monolithic integrated circuit model comprises: a first NMOS transistor M1, a second NMOS transistor M2, a third NMOS transistor M3, a fourth NMOS transistor M4, a first PMOS transistor M5, and a second PMOS transistor M6; wherein,

[0124] The first NMOS transistor M1, the second NMOS transistor M2, the third NMOS transistor M3, and the fourth NMOS transistor M4 are located in the second active region 26;

[0125] The first PMOS transistor M5 and the second PMOS transistor M5 are located in the first active region 23.

[0126] Referring to Figure 4 M2 and M3 are transmission tubes; M1 and M5 are a first inverter, M4 and M6 are a second inverter, and the first inverter and the second inverter are two pairs of interlocked inverters.

[0127] In addition, inFigure 4 In the figure, the mark WL is a word line, the mark BL is a bit line, the mark V DD is a power supply, and the marks Q and Qn are storage nodes.

[0128] It should be noted that the positions of M1, M2, M3, and M4 in the embodiment of the present application can also be located in the first active region, and the positions of M5 and M6 can also be located in the second active region, which is not limited herein.

[0129] Since the M3D integrated SRAM has a unique stacked structure, particles passing through upper and lower transistors will have a large difference in energy deposition in each layer due to scattering and other reasons. Therefore, in order to ensure the accuracy of the simulation results, the second creating unit 62 needs to create a corresponding energy deposition model for each layer of circuit structure model.

[0130] In the embodiment, a charge deposition simulation tool can be used to create a corresponding energy deposition model for each layer of circuit structure model. For example, the charge deposition simulation tool can be GEANT4 simulation tool.

[0131] Since the drain center of each MOS transistor is the most sensitive node, and the existence of the interconnection line has a significant impact on the particle track, the influence of the interconnection line needs to be considered when creating the energy deposition model. Therefore, the second creating unit 62 creates a corresponding energy deposition model for each layer of circuit structure model, including:

[0132] For any layer of circuit structure model, a corresponding target energy deposition region is determined; the center of the target energy deposition region is concentric with the drain center of the MOS transistor in the corresponding circuit structure model;

[0133] For any target energy deposition region, a target radius of the target energy deposition region is determined.

[0134] That is, for the target energy deposition region of the upper layer of circuit structure model, the center of the target energy deposition region is concentric with the drain center of M1, M2, M3, and M4; for the target energy deposition region of the lower layer of circuit structure model, the center of the target energy deposition region is concentric with the drain center of M5 and M6.

[0135] For reference Figure 5 , the energy deposition region 51 is circular, and the energy deposition in different layers is obtained by collecting the energy deposition region after the particle is incident. The target radius of each target energy deposition region is the corresponding radius when the deposited energy is reduced to the minimum deposited energy for generating an electron-hole pair; the minimum deposited energy is 3.6eV.

[0136] Specifically, the target energy deposition region is determined, including:

[0137] For any layer of circuit structure model, the maximum reference radius and the minimum reference radius of the energy deposition region are determined; wherein the minimum reference radius can be understood as the radius set when the initial simulation is performed, and the maximum reference radius and the minimum reference radius can be determined according to historical experience data; the minimum reference radius is 1 nm;

[0138] A plurality of reference energy deposition regions with a radius difference of 1 nm are established between the minimum reference radius and the maximum reference radius;

[0139] According to the order of the reference energy deposition region radius from small to large, the energy deposition simulation is performed on the energy deposition model in turn, and the reference deposition energy corresponding to each reference energy deposition region is obtained.

[0140] When it is determined that the reference deposition energy is less than the minimum deposition energy, the corresponding target reference energy deposition region is obtained, and the target reference energy deposition region is the target energy deposition region. Wherein, the target reference energy deposition region is the reference energy deposition region corresponding to the reference deposition energy less than the minimum deposition energy.

[0141] It should be noted that each time the energy deposition model is simulated based on the reference energy deposition region to obtain the corresponding reference deposition energy, the reference deposition energy is compared with the minimum deposition energy. If the reference deposition energy is less than the minimum deposition energy, the energy deposition simulation is terminated; if the reference deposition energy is greater than the minimum deposition energy, the radius of the reference energy deposition region is increased, and the energy deposition model is simulated again until the reference deposition energy is less than the minimum deposition energy.

[0142] Here, after each energy deposition simulation of the energy deposition model, the corresponding charge curve can be obtained, and whether the reference deposition energy is less than the minimum deposition energy is determined according to the charge curve. Wherein, the charge curve can be a current-time curve, or a voltage-time curve.

[0143] It should be noted that the target radius of the energy deposition region also needs to determine the target incident particle, and the specific determination method of the target incident particle will be described in detail below, so it is not repeated here.

[0144] And when the particle type includes multiple types, the critical charge corresponding to each particle can also be obtained when the energy deposition simulation is performed each time, and each particle and the corresponding critical charge are stored in the database for the convenience of other staff.

[0145] Wherein, the target radius of the energy deposition region in each layer of circuit structure model is different, which can continue to refer to Figure 2 , the energy deposition region of the top layer circuit structure model is shown as mark 30, and the energy deposition region of the bottom layer circuit structure model is shown as mark 31.

[0146] In the embodiment, since the M3D integrated SRAM unit occupies a small space (<100 nm), a high-precision particle beam needs to be used for heavy ion experiments, and the existing accelerator cannot provide a high-precision particle beam. In addition, the laser widely used in two-dimensional circuits cannot penetrate the metal covering the sensitive area of the M3D device, and is not suitable for heavy ion experiments of the M3D integrated SRAM.

[0147] Therefore, in the embodiment, the SRIM simulation tool is used to determine the target incident particle. For different types of particles, when the particles are incident, the SRIM simulation tool can be used to measure the penetration depth and penetration trajectory of the particles in different layer circuit structures after the particles are incident, and then the target incident particle is determined according to the penetration depth and the penetration trajectory. It should be noted that the corresponding target incident particle should be different in different environments.

[0148] After the target incident particle is determined, the first simulation unit 63 uses the charge deposition simulation tool to perform energy deposition simulation on each energy deposition model based on the target incident particle, and obtains the target linear energy transfer (LET) value corresponding to each layer circuit structure model.

[0149] In this way, the target linear energy transfer value of each layer circuit structure in the three-dimensional monolithic integrated circuit can be accurately obtained, and when the target linear energy transfer value is used to simulate the single event effect of the three-dimensional monolithic integrated circuit in the subsequent process, the simulation accuracy can be ensured.

[0150] After the target linear energy transfer value corresponding to each layer circuit structure model is determined, the second simulation unit 64 uses the TCAD simulation tool to simulate the single event effect of the three-dimensional monolithic integrated circuit model based on the target incident particle, and obtains the electrical characteristic curve of the three-dimensional monolithic integrated circuit model, such as the current curve.

[0151] Then, the electrical parameters and circuit structure of the three-dimensional monolithic integrated circuit can be determined according to the electrical characteristic curve to improve the reliability of the three-dimensional monolithic integrated circuit.

[0152] The beneficial effects brought by the one or more embodiments of the present application are at least:

[0153] The application provides a simulation method and device for single event effect of three-dimensional monolithic integrated circuit, the method comprises the following steps: creating a three-dimensional monolithic integrated circuit model corresponding to a target device, the three-dimensional monolithic integrated circuit model comprises at least two layers of circuit structure models; creating an energy deposition model corresponding to each layer of circuit structure model; determining a target incident particle, performing energy deposition simulation on each energy deposition model based on the target incident particle, and obtaining a target linear energy transfer value corresponding to each layer of circuit structure model; performing single event effect simulation on the three-dimensional monolithic integrated circuit model based on the target incident particle and the target linear energy transfer value corresponding to each layer of circuit structure model; thus, since the three-dimensional monolithic integrated circuit structure is a unique stacked structure, the energy deposition in each layer of circuit caused by scattering when the particle passes through each layer of transistor has a large difference, therefore, the application creates an energy deposition model corresponding to each layer of circuit structure model, performs energy deposition simulation on each energy deposition model, obtains a target linear energy transfer value corresponding to each layer of circuit structure model, and then performs single event effect simulation on the three-dimensional monolithic integrated circuit model by using the target linear energy transfer value of each layer, so as to ensure that a more accurate simulation result can be obtained, and then the structure and parameters of the three-dimensional monolithic integrated circuit can be accurately adjusted according to the simulation result, and the reliability of the three-dimensional monolithic integrated circuit is improved.

[0154] Those skilled in the art will understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0155] The present application is described with reference to flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of flows and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device that implements the functions specified in the flowcharts and / or block diagrams. Figure 1 The functions specified in one flow or multiple flows and / or blocks Figure 1 The functions specified in one flow or multiple flows and / or blocks

[0156] These computer program instructions can also be stored in a computer readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture including instructions which implement the Figure 1 function specified in the flow or flows and / or blocks Figure 1 of the block or blocks.

[0157] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions that are executed on the computer or other programmable apparatus provide steps for implementing the Figure 1 function specified in the flow or flows and / or blocks Figure 1 of the block or blocks.

[0158] Although preferred embodiments of the application have been described herein, additional alternatives, modifications, and variations that are apparent to one skilled in the art can be made to the described embodiments without departing from the scope of the application. Accordingly, it is intended to embrace all such alternatives, modifications, and variations as fall within the scope of the application. All publications, patents, and patent applications cited herein, including any of the above, are hereby incorporated by reference in their entirety for all purposes.

[0159] The above description is only preferred embodiments of the present application, not intended to limit the protection scope of the present application. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present application should be included in the protection scope of the present application.

Claims

1. A method of simulating single event effects in a three-dimensional monolithic integrated circuit, comprising: The method comprises: creating a three-dimensional monolithic integrated circuit model corresponding to a target device, the three-dimensional monolithic integrated circuit model comprising at least two layers of circuit structure models; creating, for each layer of the circuit structure models, a corresponding energy deposition model; determining a target incident particle, performing energy deposition simulation on each of the energy deposition models based on the target incident particle, and obtaining a target linear energy transfer value corresponding to each layer of the circuit structure models; performing single event effect simulation on the three-dimensional monolithic integrated circuit model based on the target incident particle and the target linear energy transfer value corresponding to each layer of the circuit structure models; wherein the creating, for each layer of the circuit structure models, a corresponding energy deposition model comprises: for any layer of the circuit structure models, determining a target energy deposition area corresponding thereto; the center of the target energy deposition area is concentric with the center of the drain of a MOS transistor in the corresponding circuit structure model; for any target energy deposition area, determining a target radius of the target energy deposition area.

2. The method of claim 1, wherein, When the three-dimensional monolithic integrated circuit model comprises two layers of circuit structure models, the three-dimensional monolithic integrated circuit model comprises: a substrate; a first buried oxygen layer located above the substrate; a first active region located above the first buried oxygen layer; an intermediate dielectric layer located above the first active region; a second buried oxygen layer located above the intermediate dielectric layer; a second active region located above the second buried oxygen layer.

3. The method of claim 2, wherein, The three-dimensional monolithic integrated circuit model comprises a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a first PMOS transistor, and a second PMOS transistor; wherein the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, and the fourth NMOS transistor are located in the second active region; the first PMOS transistor and the second PMOS transistor are located in the first active region.

4. The method of claim 1, wherein, The determining the target energy deposition area comprises: for any layer of the circuit structure models, determining a maximum reference radius and a minimum reference radius of the energy deposition area; establishing a plurality of reference deposition energy areas with a radius difference of 1 nm between the maximum reference radius and the minimum reference radius; performing energy deposition simulation on the energy deposition model in order of increasing reference energy deposition area radius to obtain a reference deposition energy corresponding to each of the reference energy deposition areas; when the reference deposition energy is determined to be less than a minimum deposition energy, obtaining a corresponding target reference energy deposition area, the target reference energy deposition area being the target energy deposition area; wherein the minimum deposition energy is 3.6 eV.

5. A device for simulating single event effects in a three-dimensional monolithic integrated circuit, characterized in that The apparatus comprises: a first creating unit configured to create a three-dimensional monolithic integrated circuit model corresponding to a target device, the three-dimensional monolithic integrated circuit model comprising at least two layers of circuit structure models; a second creating unit configured to create, for each layer of the circuit structure models, a corresponding energy deposition model; The first simulation unit is configured to determine a target incident particle, perform energy deposition simulation on each energy deposition model based on the target incident particle, and obtain a target linear energy transfer value corresponding to each layer of the circuit structure model; The second simulation unit is configured to perform single event effect simulation on the three-dimensional monolithic integrated circuit model based on the target incident particle and the target linear energy transfer value corresponding to each layer of the circuit structure model; wherein, The second creation unit is specifically configured to: For any layer of the circuit structure model, determine a target energy deposition area corresponding thereto; the center of the target energy deposition area is concentric with the center of the drain of a MOS tube in the corresponding circuit structure model; For any target energy deposition area, determine the radius of the target energy deposition area.

6. The apparatus of claim 5, wherein, When the three-dimensional monolithic integrated circuit model includes two layers of circuit structure models, the three-dimensional monolithic integrated circuit model includes: a substrate; a first buried oxygen layer located above the substrate; a first active region located above the first buried oxygen layer; an intermediate layer dielectric layer located above the first buried oxygen layer; a second buried oxygen layer located above the intermediate layer dielectric layer; a second active region located above the second buried oxygen layer.

7. The apparatus of claim 6, wherein, The three-dimensional monolithic integrated circuit model includes a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a first PMOS tube, and a second PMOS tube; wherein, The first NMOS tube, the second NMOS tube, the third NMOS tube, and the fourth NMOS tube are located in the second active region; The first PMOS tube and the second PMOS tube are located in the first active region.

8. The apparatus of claim 5, wherein, The second creation unit is specifically configured to: For any layer of the circuit structure model, determine a maximum reference radius and a minimum reference radius of the energy deposition area; establish a plurality of reference deposition energy areas with a radius difference of 1 nm between the maximum reference radius and the minimum reference radius; perform energy deposition simulation on the energy deposition model in order of reference energy deposition area radius from small to large, to obtain a reference deposition energy corresponding to each reference energy deposition area; When it is determined that the reference deposition energy is less than a minimum deposition energy, a target reference energy deposition area corresponding thereto is obtained, and the target reference energy deposition area is the target energy deposition area; wherein, the minimum deposition energy is 3.6 eV.

Images