Method for manufacturing semiconductor device and non-transitory computer-readable storage medium

Abstract

A method includes receiving a design rule set, the design rule set including a predetermined set of widths and spacings associated with active areas. The method also includes providing a cell library including cells having corresponding active areas, wherein the widths and spacings of the active areas are selected from the predetermined set of the design rule set. The method includes placing a first cell and a second cell from the cell library in a design layout. The first cell has a cell height in a first direction, and the first cell has a first active area with a first width in the first direction. The second cell has a cell height, and the second cell has a second active area with a second width in the first direction. The second width is different from the first width. The method also includes manufacturing a semiconductor device according to the design layout. Embodiments of the present invention also relate to methods of manufacturing semiconductor devices and non-transitory computer-readable storage media.

Description

Technical Field

[0001] Embodiments of the present invention relate to a method of manufacturing a semiconductor device and a non-transitory computer-readable storage medium. Background Art

[0002] Electronic devices involving semiconductor devices are essential to many modern applications. Technological advances in materials and design have produced generations of semiconductor devices, each of which includes smaller and more complex circuits than the previous generation. In the process of progress and innovation, functional density (i.e., the number of interconnected devices per chip area) generally increases, while geometric size (i.e., the smallest component that can be created using a manufacturing process) decreases. This progress increases the complexity of processing and manufacturing semiconductor devices. Therefore, there is a constant need to modify the structure and manufacturing methods of the devices to improve the robustness of the devices and reduce manufacturing costs and processing time. Among various research on semiconductor devices, advanced types of field-effect transistors (FETs) (such as nanosheet FETs) have attracted widespread attention due to their superior performance (e.g., better gate control and improved short-channel effects). Summary of the Invention

[0003] An embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: receiving a design rule group, the design rule group including a predetermined set of widths and spacings associated with active areas; providing a cell library including cells, the cells including corresponding active areas, wherein the widths and spacings of the active areas are selected from the predetermined set of the design rule group; placing a first cell from the cell library in a design layout, wherein the first cell has a cell height in a first direction and the first cell includes a first active area having a first width in the first direction; placing a second cell from the cell library in the design layout, wherein the second cell has the cell height and the second cell includes a second active area having a second width in the first direction, the second width being different from the first width; and manufacturing the semiconductor device according to the design layout.

[0004] Another embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising: placing a first unit in a first row of a design layout, wherein the first unit includes a first active region and a second active region, wherein the first active region is separated from the second active region by a first distance in a first direction; placing a second unit in the first row of the design layout, wherein the second unit includes a third active region and a fourth active region, wherein the third active region is separated from the fourth active region by a second distance in the first direction, and the second distance is different from the first distance; and manufacturing the semiconductor device according to the design layout.

[0005] Yet another embodiment of the present invention provides a non-transitory computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to: perform a circuit simulation of an operation of a design layout comprising a first cell, wherein the first cell has a cell height in a first direction and comprises a plurality of first nanosheets having a first width in the first direction; in response to the circuit simulation failing to meet a design requirement, replace the first cell in the design layout with a second cell to obtain a modified design layout, wherein the second cell has the cell height in the first direction and comprises a plurality of second nanosheets having a second width in the first direction, the second width being greater than the first width; and control the manufacture of a semiconductor device according to the modified design layout. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

[0007] Figure 1A is a perspective view of a nanosheet field effect transistor (FET) device according to some embodiments of the present invention.

[0008] Figure 1B According to some embodiments of the present invention Figure 1A Cross-sectional view of the nanosheet FET device shown.

[0009] Figure 2 is a schematic diagram of a design layout according to some embodiments of the present invention.

[0010] Figure 3A and Figure 3B is a schematic diagram of a design layout for a standard cell according to various embodiments of the present invention.

[0011] Figure 3C Included are tables for determining the width and spacing of active areas in various standard cells according to some embodiments of the present invention.

[0012] Figure 4A 、 Figure 4B 、 Figure 4C and Figure 4D is a schematic diagram of a design layout for a standard cell according to various embodiments of the present invention.

[0013] Figure 5A 、 Figure 5B 、 Figure 5C 、 Figure 5D and Figure 5Eis a schematic diagram of a design layout for a standard cell according to various embodiments of the present invention.

[0014] Figure 6A is a flow chart of a layout method according to some embodiments.

[0015] Figure 6B is a flow chart of a layout method according to some embodiments.

[0016] Figure 7A is a schematic diagram illustrating an integrated circuit (IC) manufacturing system according to some embodiments.

[0017] Figure 7B is used to generate a design layout according to some embodiments Figure 7A Figure 1 is a schematic diagram of the design subsystem in the IC manufacturing system. DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly in contact, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, indicate a relationship between the individual embodiments and / or configurations discussed.

[0019] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or during operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0020] Although the numerical ranges and parameters setting forth the broad scope of the present invention are approximate, the numerical values ​​set forth in the specific examples are reported as precisely as possible. However, any numerical value inherently contains certain errors, which are necessarily caused by deviations typically found in the corresponding test measurements. Moreover, as used herein, the terms "about," "substantially," or "substantially" generally mean within 10%, 5%, 1%, or 0.5% of a given value or range. Alternatively, the terms "about," "substantially," or "substantially" mean within the acceptable standard error of the mean value as considered by one of ordinary skill in the art. Except in the operating / working examples, or unless otherwise expressly provided, all numerical ranges, quantities, values, and percentages (such as those disclosed herein for amounts of materials, durations, temperatures, operating conditions, quantitative ratios, etc.) should be understood in all cases as modified by the terms "about," "substantially," or "substantially." Therefore, unless otherwise indicated, the numerical parameters set forth in the present invention and the appended claims are approximate values ​​that can be varied as needed. At a minimum, each numerical parameter should at least be interpreted in light of the number of reported significant figures and by applying ordinary rounding techniques. Ranges may be expressed herein as from one endpoint to the other endpoint or between two endpoints. Unless otherwise stated, all ranges disclosed herein include the endpoints.

[0021] The term "standard cell" or "cell" as used throughout this disclosure refers to a group of circuit patterns in a design layout to implement a specific function of a circuit. A standard cell consists of various patterns in one or more layers and can be represented as a union of polygons. The design layout can be initially constructed by placing a combination of the same or different standard cells during the layout design phase. The geometry of the patterns in the cell can be adjusted at different stages of the layout design to compensate for design and process effects. A standard cell can cover circuits corresponding to part or all of the die to be manufactured. Standard cells can be accessed from a cell library provided by the semiconductor circuit manufacturer or designer.

[0022] Some embodiments of the present invention discuss methods for generating standard cells associated with nanosheet field effect transistor (FET) devices. Due to the fact that the width and spacing of nanosheets are irregular discrete numbers, a lot of work may be required in the layout modification stage to modify the design layout to meet the design rules while maintaining the area and power efficiency of the circuit. Through the design method of the proposed scheme, a set of standard cells associated with nanosheets is generated. In this set, the standard cells are provided with individual nanosheet widths and spacings selected from a finite set of widths and spacings for nanosheets to achieve the goal of equal cell heights between standard cells, thereby simplifying the work and cost of modifying standard cells in the layout modification stage.

[0023] Some embodiments of the present invention also discuss layout methods and associated structures for semiconductor devices based on one or more nanosheet field-effect transistor (FET) devices. Through the proposed layout scheme, the semiconductor device is configured to accommodate different types of nanosheet FETs with different device sizes and capabilities. For example, different standard cells associated with the nanosheet FET can be designed to have the same cell height with different nanosheet sizes and spacings to meet the design rules of the nanosheet size. In this way, the design cycle can be improved when seeking to meet the required nanosheet size and spacing, while achieving a better balance between area, power, and performance.

[0024] Figure 1A is a perspective view of a semiconductor device 100 according to some embodiments of the present invention. Figure 1A , the semiconductor device 100 is a nanosheet FET device. However, other types of semiconductor devices may also be used for the semiconductor device 100, such as nanowire FET, fin FET, etc. Figure 1A , the semiconductor device 100 includes substrates 102 and 112 , an isolation region 104 , gate electrodes 106 and 108 , and nanosheet stacks 114 and 124 .

[0025] Substrates 102 and 112 are formed from the same substrate wafer (not shown) and can be considered as two protruding parts of the substrate wafer. In some embodiments, substrates 102 and 112 are in the form of strips extending on the x-axis. Substrates 102 and 112 can be formed from semiconductor substrates, such as bulk semiconductors, semiconductor-on-insulator (SOI) substrates, etc., which can be doped (e.g., doped with p-type or n-type dopants) or undoped. Typically, an SOI substrate includes a semiconductor material layer formed on an insulator layer. The insulator layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is provided on a substrate (typically a silicon substrate or a glass substrate). Other substrates, such as multilayer substrates or gradient substrates, can also be used. In some embodiments, the semiconductor material of substrates 102 and 112 may include silicon; germanium; compound semiconductors including silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; alloy semiconductors including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and / or GaInAsP; combinations thereof, etc.

[0026] Isolation region 104 is formed in a trench between substrates 102 and 112. In some embodiments, isolation region 104 has an upper surface that is flush with the upper surfaces of substrates 102 and 112. Isolation region 114 may include an insulating material, such as a dielectric material, for example, silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like. Isolation region 114 may be formed by chemical vapor deposition (CVD), high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), atomic layer deposition (ALD), physical vapor deposition (PVD), combinations thereof, or the like. Other insulating materials formed by any suitable process may also be used. In some embodiments, an annealing process may be performed after depositing the insulating material of isolation region 114.

[0027] Gate electrodes 106 and 108 are formed over substrates 102 and 112 and isolation region 104. Gate electrodes 106 and 108 may extend in a direction (e.g., the y-axis) perpendicular to the direction in which substrates 102 and 112 extend. In some embodiments, each of gate electrodes 106 and 108 is made of one or more layers of conductive material, such as doped polysilicon or a metal material, for example, Co, Ru, Al, Ag, Au, W, Ni, Ti, Cu, Mn, Pd, Re, Ir, Pt, Zr, alloys thereof, combinations thereof, etc., and may also include other work function adjustment metals, diffusion barrier materials, or adhesion layers.

[0028] Each of the nanosheet stacks 114 and 124 includes a plurality of separated nanosheets in a stacked form and is arranged above the substrates 102 and 112 and the isolation region 104. A nanosheet in the nanosheet stack 114 or 124 generally refers to a two-dimensional semiconductor plate having a length or width greater than about 100 nm and a thickness less than about 20 nm. The nanosheet stacks 114 and 124 may extend in a direction (e.g., the x-axis) in which the substrates 102 and 112 extend. In some embodiments, the nanosheet stacks 114 and 124 extend in a direction perpendicular to the direction in which the gate electrodes 106 and 108 extend. The nanosheet stacks 114 and 124 may overlap with the gate electrodes 106 and 108. In some embodiments, a portion of each nanosheet in the nanosheet stacks 114 and 124 is surrounded by the gate electrodes 106 and 108.

[0029] In some embodiments, nanosheet stacks 114 and 124 and substrates 102 and 112 are formed from the same substrate wafer and are formed using photolithography and etching operations on the substrate wafer. Nanosheet stacks 114 or 124 can be doped with n-type impurities (e.g., arsenic, phosphorus, etc.) to form n-type nanosheet FETs, or can be doped with p-type impurities (e.g., boron, etc.) to form p-type nanosheet FETs. The stacked nanosheets of the same nanosheet stack 114 or 124 are configured to form a combined channel region or a combined source / drain region of a nanosheet FET. For example, the portion of each nanosheet of the nanosheet stack 114 that overlaps with the gate electrode 106 serves as the combined channel region of the first nanosheet FET, while the other portions of each nanosheet of the nanosheet stack 114 located on both sides of the channel region serve as the source / drain regions of the first nanosheet FET. Similarly, the portion of each nanosheet of nanosheet stack 124 that overlaps gate electrode 106 serves as a combined channel region of the second nanosheet FET, while the other portions of each nanosheet of nanosheet stack 124 on either side of the channel region serve as source / drain regions of the second nanosheet FET.

[0030] In the depicted example, the number of nanosheet stacks 114 and 124 is set to two. However, the present invention is not limited to this, and the number of nanosheet stacks of semiconductor device 100 may be less than or greater than two. In the depicted example, each of nanosheet stacks 114 and 124 has four nanosheets stacked on top of each other. However, the present invention is not limited to this, and nanosheet stacks 114 and 124 may have any number of nanosheets. In the depicted example, the number of gate electrodes is two. However, the present invention is not limited to this, and the number of gate electrodes of semiconductor device 100 may be less than or greater than two.

[0031] In some embodiments, the nanosheets in the same stack 114 or 124 are formed to have substantially equal dimensions, such as nanosheet length measured on the x-axis, nanosheet width measured on the y-axis, and nanosheet thickness measured on the z-axis. In some embodiments, the nanosheet dimensions of one nanosheet stack (e.g., nanosheet stack 114) may be different from the nanosheet dimensions of another nanosheet stack (e.g., nanosheet stack 124). In some embodiments, nanosheet stacks 114 and 124 have substantially equal nanosheet thicknesses and different nanosheet widths or nanosheet lengths.

[0032] Figure 1B According to some embodiments of the present invention Figure 1A A cross-sectional view of nanosheet FET 100 is shown. Figure 1B The cross-sectional view along the cutting Figure 1A The gate electrode 108 is taken along the section line AA. Figure 1A and Figure 1BThe nanosheet FET device 100 further includes a gate insulating layer 116 or 126 located between the gate electrode 108 and each nanosheet of the nanosheet stack 114, 124. The gate insulating layer 116 or 126 may be formed of one or more dielectric materials, such as oxides, nitrides, oxynitrides, or high-k dielectric materials, such as Al2O3, HfO2, ZrO2, HfO x N y 、ZrO x N y 、HfSi x O y 、ZrSi x O y 、HfSi x O y N z 、ZrSi x O y N z , TiO2, Ta2O5, La2O3, CeO2, Bi4Si2O 12 、WO3、Y2O3、LaAlO3、Ba 1-x Sr x TiO3, PbTiO3, BaTiO3 (BTO), SrTiO3 (STO), BaSrTiO3 (BST), PbZrO3, lead strontium titanate (PST), lead zinc niobate (PZN), lead zirconium titanate (PZT), lead magnesium niobium (PMN), yttria-stabilized zirconia (YSZ), ZnO / Ag / ZnO (ZAZ), and combinations thereof.

[0033] In some embodiments, the nanosheet FET 100 further includes a work function adjustment layer 118, 128 located between the gate electrode 108 and each of the gate insulating layers 116, 126. In embodiments of the n-type nanosheet FET 100, the work function adjustment layer 118, 128 is formed of Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaC, TaCN, TaSiN, TaAlC, Mn, Zr, combinations thereof, and the like, and can be formed by a deposition method such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), combinations thereof, and the like to wrap around the gate insulating layers 116, 126. In embodiments of the p-type nanosheet FET 100, the work function adjustment layer 118, 128 is formed of TiN, WN, TaN, Ru, Co, combinations thereof, and the like, and can be formed by ALD, CVD, PVD, combinations thereof, and the like to wrap around the gate insulating layers 116, 126.

[0034] Figure 22 is a schematic diagram of a design layout according to some embodiments of the present invention. The design layout 200 may include at least one semiconductor device, such as a complementary metal oxide semiconductor (CMOS) device, and may be implemented using FET devices, such as Figure 1A Nanosheet FET 100 is shown. In some other embodiments, design layout 200 includes a gate-all-around (GAA) device, a nanowire device, etc.

[0035] The design layout 200 includes two exemplary rows R1 and R2 extending in the row direction along the x-axis. In the depicted example, in the design layout 200, only two rows are arranged in the column direction (perpendicular to the row direction) along the y-axis. However, the present invention is not limited thereto and more than two rows are possible. The design layout 200 also includes first power rails V1 and second power rails V2 (for simplicity, the first power rails V1 and V2 are alternately arranged and extend in the row direction) Figure 2 Only one second power rail V2 is shown. Each of the first power rail V1 and the second power rail V2 is arranged on the upper side or the lower side of one of the rows R1 and R2. In some embodiments, the centerline of each of the first power rail V1 and the second power rail V2 is aligned with the upper side or the lower side of the row R or R2. In some embodiments, the first power rail V1 is configured to provide a first voltage, and the second power rail V2 is configured to provide a second voltage different from the first voltage. In some embodiments, the first voltage is VDD and the second voltage is ground, or vice versa.

[0036] refer to Figure 2 , the design layout 200 includes a plurality of standard cells, such as standard cells SC1, SC2, SC3, SC4, and SC5. The standard cells SC1, SC2, and SC3 may be predetermined and stored in a cell library and accessible to a circuit designer. During the placement operation, the standard cells SC1, SC2, and SC3 are placed in row R1, and the standard cells SC4 and SC5 are placed in row R2. Although Figure 2 Only two or three standard cells are shown in a row, and the number of standard cells arranged in a row can be greater than three. In addition, in some embodiments, some standard cells are in contact with each other, such as standard cells SC1 and SC2; in some other embodiments, the standard cells are separated from each other, such as standard cells SC4 and SC5.

[0037] The dimensions of the standard cells SC1 to SC5 are defined by their respective cell boundaries, where each cell boundary includes upper and lower cell sides (each extending in the row direction) and left and right cell sides (each extending in the column direction). The standard cells SC1 to SC5 can be separated from each other or share at least one cell side. In some embodiments, the standard cells SC1 to SC5 have their respective upper and lower cell sides aligned with the centerline of the first power rail V1 or the second power rail V2. Each standard cell SC1 to SC5 can have the same or different cell lengths in the row direction.

[0038] In some embodiments, the row height RH1 of the first row R1 is defined as the distance in the column direction between the centerline CL1 of the lower first power rail V1, which extends in the row direction, and the centerline CL2 of the second power rail V2, which extends in the row direction. In some embodiments, the cell height CH1 is determined based on the pitch between the lower first power rail V1 and the second power rail V2. Similarly, the row height RH2 of the second row R2 is defined as the distance in the column direction between the centerline CL2 and the centerline CL3 of the upper first power rail V1. In some embodiments, the row height RH2 is determined based on the pitch between the second power rail V2 and the upper first power rail V1. In some embodiments, the row height RH1 and the row height RH2 are the same or different.

[0039] In some embodiments, the cell height CH1 of standard cell SC1, SC2, or SC3 is determined based on row height RH1. In some embodiments, cell height CH1 is determined based on the pitch between lower first power rail V1 and lower second power rail V2. In some embodiments, cell height CH1 is equal to row height RH1. Similarly, cell height CH4 of standard cell SC4 or SC5 is equal to row height RH2.

[0040] Each of rows R1 and R2 defines one or more (row) active regions NOD and POD (indicated by dashed boxes) along the row direction, where the active regions POD and NOD have opposite conductivities. For example, active region NOD represents an active region doped with an n-type dopant, while active region POD represents an active region doped with a p-type dopant. Each of standard cells SC1 to SC5 includes one or more (cell) active regions (indicated by solid boxes), the dimensions of which are defined by the cell boundary of the corresponding standard cell and the boundary of the corresponding (row) active region NOD or POD. For example, standard cell SC1 includes an n-type active region NOD1 and a p-type cell active region POD1, where the n-type active region NOD1 is defined by the cell boundary of standard cell SC1 and the boundary of the row active region NOD in row R1, while the p-type active region POD1 is defined by the cell boundary of standard cell SC1 and the boundary of the row active region POD in row R1. The (cell) active area NODxy or PODxy (x represents the index of the standard cell, and y is optionally used to represent a sequence number to distinguish multiple similar active areas) within each standard cell SC1 to SC5 shown in design layout 200 (e.g., active area NOD1 and POD1) corresponds to a top view of the nanosheet stack (e.g., nanosheet stack 114 or 124) of the semiconductor device in the corresponding standard cell SC1 to SC5. As a result, the configuration of the aforementioned (cell) active area will determine the planar size of the nanosheet in the nanosheet FET of the corresponding standard cell SC1 to SC5.

[0041] refer to Figure 2 Standard cells SC1, SC2, and SC3 include respective n-type active regions NOD1, NOD2, and NOD3 located within a row active region NOD, overlapping each other in the row direction. In some embodiments, the active regions NOD1, NOD2, and NOD3 have different active region widths measured in the column direction, referred to herein as OD (oxide-defined) widths. In some embodiments, although the widths of the active regions NOD1, NOD2, and NOD3 are different, each of these active regions has at least one side, such as an upper side, aligned with one side of the other active regions.

[0042] Similarly, standard cells SC1, SC2, and SC3 include respective n-type active regions POD1, POD2, and POD3 located within a row of active regions POD, overlapping each other in the row direction. In some embodiments, active regions POD1, POD2, and POD3 have different OD widths. In some embodiments, although active regions POD1, POD2, and POD3 have different widths, each of these active regions has at least one side, such as a lower side, aligned with one side of the other active regions.

[0043] about Figure 2 Of the standard cells SC1 to SC5 shown in FIG, only the (cell) active area is shown for clarity. Other cell components, such as the gate electrode, are described in more detail below.

[0044] Figure 3A is a schematic diagram of a design layout for standard cells 300A and 300B according to various embodiments of the present invention. In some embodiments, standard cells 300A and 300B correspond to standard cells arranged in the same row (e.g., row R1 or R2). Standard cells 300A and 300B are defined by their respective cell boundaries CB and have a height equal to the row height (e.g., Figure 2 The unit height CH1 of RH1 or RH2).

[0045] The standard cells 300A and 300B include respective gate electrodes GT1 and GT2 extending in the column direction over a substrate (not shown). The materials of the gate electrodes GT1 and GT2 are similar to those of Figure 1A The standard cell 300A further includes two active regions (OD) OD11 and OD12 extending in the row direction, wherein the channel regions of the active regions OD11 and OD12 are surrounded by the gate electrode GT1. Similarly, the standard cell 300B further includes two active regions (OD) OD21 and OD22 extending in the row direction, wherein the channel regions of the active regions OD21 and OD22 are surrounded by the gate electrode GT2.

[0046] Standard cells 300A and 300B further include conductive lines MD1 and MD2, respectively, extending in the column direction between adjacent gate electrodes GT1 and GT2. Conductive lines MD1 and MD2 are arranged in a layer overlapping gate electrodes GT1 and GT2 and are electrically coupled to active regions OD11, OD12, OD21, and OD22. Conductive lines MD1 and MD2 are configured to electrically couple the source / drain regions of active regions OD11, OD12, OD21, and OD22 in standard cells 300A and 300B to upper or lower layers of standard cells 300A and 300B. Conductive lines MD1 and MD2 can be formed from doped polysilicon or a metal material such as copper, tungsten, titanium, titanium nitride, tantalum, or tantalum nitride.

[0047] The standard cell 300A or 300B further includes line separation patterns CMD extending in the row direction on the upper and lower cell sides of the standard cell 300A or 300B, referred to herein as "cutting MD patterns." The cutting MD patterns CMD are used to represent an MD separation step during a semiconductor manufacturing process, by which a continuous conductive line MD1 or MD2 extending in the column direction is divided into aligned conductive line segments MD1 or MD2 having a predetermined line length, as shown in the standard cell 300A or 300B. For illustrative purposes, the lines CMD and MD patterns are arranged in a row direction. Figure 3A The position of the cutting MD pattern CMD is shown in . The cutting MD pattern CMD may also be arranged at other positions of the standard cell 300A or 300B to separate the conductive line MD1 or MD2 extending through the standard cell 300A or 300B.

[0048] Each of the standard cells 300A and 300B includes a nanosheet FET formed by two active regions OD11 and OD12 or OD21 and OD22. In some embodiments, the two active regions OD11 and OD12 (or OD21 and OD22) are grouped and formed by one n-type active region and one p-type active region, or vice versa, and serve as a basic unit for constructing a semiconductor logic gate device, such as a NAND gate, an inverter gate, an XOR gate, an AND gate, a NOR gate, an AOI gate, or other suitable logic gate devices.

[0049] The grouped active areas OD11 and OD12 have equal nanosheet lengths L1 measured in the row direction, and the grouped active areas OD21 and OD22 have equal nanosheet lengths L2 measured in the row direction. In some embodiments, the nanosheet lengths L1 and L2 can be equal or different depending on various design requirements.

[0050] The grouped active areas OD11 and OD12 have nanosheet widths W11 and W12, respectively, measured in the column direction, and the grouped active areas OD21 and OD22 have nanosheet widths W21 and W22, respectively, measured in the column direction. The boundaries of these grouped active areas in each standard cell 300A or 300B are defined by lines K1 and K2. Lines K1 and K2 are defined as lines extending in the row direction parallel to the upper or lower cell side of the standard cell 300A or 300B, where line K1 is spaced an edge distance M1 from the upper cell side, and line K2 is spaced an edge distance M2 from the lower cell side. Lines K1 and K2 define a flexible width T1, measured in the column direction. The upper sides of the active areas OD11 and OD21 are aligned with each other at line K1, while the lower sides of the active areas OD12 and OD22 are aligned with each other at line K2. In some embodiments, the edge distances M1 and M2 and the flex width T1 are predetermined cell parameters subject to the following constraints on the cell height CH1 of the standard cell 300A or 300B:

[0051] CH1=M1+T1+M2.

[0052] The spacing between the grouped active regions OD11 and OD12 in the standard cell 300A has a spacing width S11, and the spacing between the grouped active regions OD21 and OD22 in the standard cell 300B has a spacing width S21, where the following equation holds:

[0053] T1=S11+W11+W12=S21+W21+W22.

[0054] In some embodiments, the width and spacing of the active area (e.g., widths W11, W12, W21, and W22, and spacings S11 and S21) are not only determined by the designer, but are also subject to manufacturing capabilities. In some embodiments, although the values ​​of widths W11, W12, W21, and W22 and spacings S11 and S21 can be arbitrary within a certain range for the designer, these value ranges may not pass design rule checks due to manufacturing limitations. In some embodiments, the active areas of standard cells 300A and 300B utilize nanosheets, and the widths and spacings of the associated nanosheets provided only include a predetermined set of values ​​that meet manufacturer requirements. In some embodiments, these values ​​are neither related nor predictable in equations or formulas.

[0055] Given the unpredictability of the chosen width and spacing of the nanosheets, adjusting the size of the nanosheets during the layout modification phase can be a time-consuming endeavor. This is because small increments of the initially chosen nanosheet width (pitch) from the set may not be included in the same set and may require larger increments, which typically exceed the cell height of the standard cell in question. Thus, attempting to adjust the width of a single nanosheet may inevitably involve changing the cell height over a large area of ​​the design layout. Due to the modified design layout in the context of a nanosheet FET, the design cycle, area, and power of the modified design layout may not be optimized.

[0056] In view of the above, some embodiments of the present invention propose a process for providing a standard cell library by generating multiple standard cells for nanosheet FETs having different selected nanosheet widths and pitches selected from a predetermined set of widths and pitches, while ensuring that these standard cells have equal cell heights to facilitate design layout.

[0057] Figure 3C A table is included for determining the width and spacing of active areas in various standard cells according to some embodiments. Figure 3C The width and spacing of the active area are referred to as the nanosheet width and nanosheet spacing, respectively. Tables (a) and (b) include example formulas for determining combinations of nanosheet width and nanosheet spacing that will produce cells with different nanosheet widths but the same cell height. Tables (c) and (d) include specific examples of applying the predetermined sets of nanosheet widths and nanosheet spacings in Tables (a) and (b).

[0058] In Table (a), the first row and the first column list the nanosheet widths W1, W2, W3, W4 from a predetermined set of nanosheet widths. Figure 3AEach nanosheet width W11, W12, W21, and W22 in the graph is configured to have one of the predetermined nanosheet widths W1, W2, W3, and W4. In this example, W11 = W12 and W21 = W22, and W11 and W21 are listed in Table (a). The formula ΔW = 2*(|W11-W21|) is listed in each cell of Table (a). For example, the cell at the column corresponding to W3 and the row corresponding to W1 has the formula 2*(|W1-W3|).

[0059] In Table (b), the first row and the first column list the nanosheet spacings S1, S2, S3, S4, S5 in a predetermined set of nanosheet spacings. Figure 3A Each nanosheet spacing S11, S21 in the graph is configured to have one of the predetermined nanosheet spacings S1, S2, S3, S4, and S5. The formula ΔS = |S11-S21| is listed in each cell of Table (b). For example, the cell at the column corresponding to S3 and the row corresponding to S1 has the formula |S1-S3|.

[0060] As discussed in this article, Figure 3A In the example configuration in FIG, in order to achieve the same cell height CH1 in various cells, the flexible width T1 in these cells is configured to be the same, that is, T1 = S11 + W11 + W12 = S21 + W21 + W22. This relationship of T1 is satisfied when ΔS = ΔW. In some embodiments, Table (a) and Table (b) are used to calculate the respective values ​​of ΔS and ΔW. The cell in Table (a) and the cell in Table (b) having the same value (non-zero) indicate that ΔS = ΔW, and the corresponding combination of nanosheet width and nanosheet spacing will result in cells with the same T1 and the same cell height.

[0061] Table (c) and Table (d) show specific numerical examples of Table (a) and Table (b). The first row and the first column of Table (c) list exemplary nanosheet widths selected from a predetermined set of nanosheet widths in nanometers, while the first row and the first column of Table (d) list exemplary nanosheet spacings selected from a predetermined set of nanosheet spacings in nanometers. Any nanosheet width or nanosheet spacing value that is not included in the predetermined set of nanosheet widths or nanosheet spacings may not pass the design rule check in the initial layout design stage or the layout modification stage. The values ​​in the cells (x, y) of Table (c) represent the width difference ΔW calculated for the nanosheet widths in the xth row and the yth column as described in Table (a). Similarly, the values ​​in the cells (x, y) of Table (d) represent the spacing difference ΔS calculated for the nanosheet spacing in the xth row and the yth column as described in Table (b). The cells in table (c) and the cells in table (d) having the same value are indicated by the same label, for example, one of L_a1, L_a2, L_a3, L_b1, L_b2, and L_c1.

[0062] The nanosheet widths W11, W12, W21, and W22 selected to generate standard cells 300A and 300B, and the corresponding nanosheet spacings S11 and S21, can be obtained from Table (c) and Table (d). For example, in Table (c), the set of selected values ​​for widths W11=W12 and W21=W22 is provided as 15, 22, 35, and 41 (nm), while in Table (d), the set of selected values ​​for spacings S11 and S21 is provided as 28, 34, 36, 40, 66, and 80 (nm, units omitted below for brevity). Given a finite number of selected widths and spacings, there are a finite number of combinations of nanosheet widths and nanosheet spacings that satisfy the same flexible width T1 of standard cells 300A and 300B.

[0063] An exemplary satisfied condition is given by referring to the entry labeled L_a1 in Table (c) and Table (d), which indicates that in the standard cell 300A, the flexible width T1 is maintained at 110, W11=W12=15, and S11=80, and in the standard cell 300B, W21=W22=22, and S21=66. Similarly, another satisfied condition is given by referring to the entry labeled L_a2 in Table (c) and Table (d), which indicates that in the standard cell 300A, the flexible width T1 is maintained at 110, W11=W12=15, and S11=80, and in the standard cell 300B, W21=W22=35, and S21=40. Further satisfaction conditions are given by the entries with label L_a3 in reference tables (c) and (d), which show that in standard cell 300A, the flexible width T1 remains 110, W11=W12=15 and S11=80, and in standard cell 300B, W21=W22=41 and S21=28.

[0064] Given the above, standard cells 300A or 300B can be generated that share the same flexible width T1=110, with four different combinations of selected nanosheet widths and nanosheet spacings. Assuming that the edge distances M1 and M2 are set equal in standard cells 300A and 300B, the cell height CH1 of different standard cells can remain unchanged, while the nanosheet dimensions (e.g., nanosheet width and / or nanosheet spacing) can be made different, i.e., selected from a predetermined set of nanosheet widths and nanosheet spacings in standard cells 300A and 300B.

[0065] like Figure 3C As shown, Figure 3C The six entries in Table (c) and Table (d) are labeled with labels (e.g., L_a1, L_a2, L_a3, L_b1, L_b2, and L_c1) to indicate compliant combinations of nanosheet widths and nanosheet spacings to achieve equal compliant widths T1, thereby achieving equal cell heights for standard cells 300A and 300B. In some embodiments, some entries in Table (c) and Table (d) do not have any labels, indicating that no compliant combinations of nanosheet widths and nanosheet spacings exist to achieve equal compliant widths T1, and therefore these combinations are considered discarded during standard cell generation for the standard cell library.

[0066] The edge distance M1 or M2 is selected in a similar way to the reference Figure 3C Choose the method that conforms to the nanosheet width and nanosheet spacing. Figure 2 and Figure 3A , the edge distance M1 or M2 can be set to half the spacing between two adjacent active regions of two adjacent standard cells (for example, the spacing Sx between active regions NOD3 and NOD42), that is, M1 = Sx / 2. For example, the edge distance M1 or M2 is selected from the set formed by the numbers {14, 17, 18, 20, 33, 40}, which are Figure 3C In this way, when two standard cells are adjacent in the column direction, the adjacent edge distance M1 or M2 of each standard cell contributes half of the spacing between the cell boundary and the nearest nanosheet, so the total spacing between two adjacent nanosheets of the adjacent standard cells meets the requirements provided in the set of spacings shown in Table (d).

[0067] In some embodiments, the grouped active areas OD11 and OD12 (or the grouped active areas OD21 and OD22) have equal nanosheet widths to maintain comparable electrical performance of the grouped active areas OD11 and OD12 (or the grouped active areas OD21 and OD22). Under this assumption, the above formula can be further simplified as follows.

[0068] T1=S11+2*W11=S21+2*W21.

[0069] According to the above formula, nanosheet width W11 can differ from nanosheet width W21 by an amount D = |S11 - S21| / 2 to provide design flexibility between standard cells 300A and 300B within the constraint of equal cell height CH1 of standard cells 300A and 300B. In some embodiments, due to process variations during the manufacture of nanosheets OD11 and OD21, the difference between widths W11 and W21 is greater than a tolerance level. In some embodiments, nanosheet width W11 differs from nanosheet width W21 by at least 2.5% of nanosheet width W11, at least 5% of nanosheet width W11, or at least 10% of nanosheet width W11. Thus, due to process variations during the manufacture of nanosheets OD11 and OD21, width S11 differs from width S21 by an amount greater than a tolerance level. In some embodiments, spacing width S11 differs from spacing width S21 by at least 5%, 10%, or 20% of nanosheet width W11.

[0070] In some embodiments, the nanosheet width W11 or W12 in the standard cell 300A is a multiple of the nanosheet width W21 or W22 in the standard cell 300B, respectively.

[0071] In some embodiments, the flexible widths T1 in standard cells 300A and 300B remain equal, but may not be flush with each other along lines K1 and K2. In other words, the edge distances M1 and M2 in standard cell 300A may not be equal to the corresponding edge distances M1 and M2 in standard cell 300B. In some embodiments, to ensure that the cell heights CH1 of standard cells 300A and 300B are equal, the sum of the edge distances M1 + M2 in standard cell 300A is set equal to the sum of the edge distances M1 + M2 in standard cell 300B, where the individual edge distances M1 and M2 of standard cells 300A and 300B are selected to be half of any of the spacings in Table (d). In this way, the requirement for equal cell height CH1 can still be maintained, and greater design flexibility for the standard cells can be achieved.

[0072] As previously discussed, the planar area of ​​the nanosheet, determined by the nanosheet length and width, is closely related to the electrical performance of the nanosheet FET. Due to some manufacturing constraints, the nanosheet width and nanosheet spacing can be selected from a predetermined set of specific values ​​of the nanosheet width and nanosheet spacing. Therefore, the proposed framework for standard cell generation provides as many compatible combinations of nanosheet width and nanosheet spacing as possible for standard cells of the same type, such as standard cells with the same function, having the same cell height. For example, a standard cell library is provided or generated to include multiple inverter cells with the same cell height but different nanosheet widths and / or nanosheet spacings. These inverter cells can be replaced with each other during the circuit design phase. This will provide benefits when the placed cell layout needs to be modified during the circuit design phase to meet design requirements. For example, a placed cell that fails a circuit simulation may not need to be redesigned from scratch. Instead, a faulty cell (e.g., an inverter cell) can be effectively replaced with a similar standard cell, such as another inverter cell that has the same cell height but a different nanosheet width, without having to modify other parts of the already placed layout or change the cell height. As a result, a better trade-off is achieved between performance, area, and power, while improving design cycle time.

[0073] Figure 3B 300D according to various embodiments of the present invention. The arrangement of the standard cells 300C and 300D is similar to that of the standard cells 300A and 300B. For the sake of brevity, the description of similar aspects will not be repeated here. Figure 3A and Figure 3B New lines K3 and K4 are used to define the flexible width T2, where line K3 is aligned with the upper cell side of standard cells 300C and 300D, and the lower sides of active areas OD11 and OD21 are aligned with each other at line K4. Lines K4 and K2 are used to define the flexible width T4. Therefore, the nanosheet widths W11, W12, W21, and W22 can be adjusted according to the following formula:

[0074] T2=S21+W11=S22+W21.

[0075] T3=S31+W12=S32+W22.

[0076] Determined by similar Figure 3A The flexible width T1 shown in the discussed manner, Figure 3C The determination of the compliance width T2 and the selection of the conforming nanosheet widths W11, W21 and the nanosheet spacings S21, S22 are performed with the help of the tables (a) and (b) or (c) and (d) shown. Figure 3A The flexible width T1 shown in the discussed manner, Figure 3C The determination of the compliant width T3 and the selection of the corresponding nanosheet widths W12, W22 and nanosheet spacings S31, S32 are performed with the aid of Tables (a) and (b) or Tables (c) and (d). With the above arrangement, under the constraint of compliant width T2, the active region OD12 can be designed to have a nanosheet width W12 that is independent of the nanosheet width W11 of the active region OD11. Similarly, under the constraint of compliant width T3, the active region OD22 can be designed to have a nanosheet width W22 that is independent of the nanosheet width W21 of the active region OD21.

[0077] According to the above formula, nanosheet width W12 can differ from nanosheet width W22 by an amount D = |S31 - S32| to provide design flexibility between standard cells 300A and 300B within the constraints of the flexible width T3 of standard cells 300A and 300B. In some embodiments, due to process variations during the manufacture of nanosheets OD12 and OD22, the difference between widths W12 and W22 is greater than a tolerance level. In some embodiments, nanosheet width W12 differs from nanosheet width W22 by at least 2.5%, 5%, or 10% of nanosheet width W12. Therefore, due to process variations during the manufacture of nanosheets OD21 and OD22, spacing width S31 differs from spacing width S32 by an amount greater than a tolerance level. In some embodiments, spacing width S21 differs from spacing width S22 by at least 2.5%, 5%, or 10% of nanosheet width W21.

[0078] Figure 4A Schematic diagrams of design layouts for standard cells 400A and 400B according to various embodiments of the present invention are shown. The arrangement of standard cells 400A and 400B is similar to that of standard cells 300A and 300B, and for the sake of brevity, the description of similar aspects will not be repeated here. Figure 4A , the active regions OD11, OD12, OD21, OD22 and lines K1, K2 in standard cells 400A and 400B are similar to those in standard cells 300A and 300B. Each of standard cells 400A and 400B further includes third active regions OD13 and OD23 having respective nanosheet widths W13 and W23 measured in the column direction. In some embodiments, active region OD13 or OD23 is configured to be paired with another active region of another standard cell used to form a nanosheet FET, wherein the paired active region standard cells will be arranged in adjacent rows during a cell placement operation.

[0079] The nanosheet widths W11, W12, W21, and W22 of the grouped active areas OD11, OD12, OD21, and OD22 are defined by lines K1 and K2 and a flexible width T1. A third line K3 is defined as a line extending in a row direction parallel to the upper or lower cell side of the standard cells 300A and 300B, wherein the distance between line K3 and the lower cell side of the standard cells 300A and 300B is an edge distance M2, and the distance between line K2 and line K3 is a flexible width T2. In some embodiments, the edge distances M1 and M2 and the flexible widths T1 and T2 are predetermined cell parameters and are subject to the following constraints on the cell height CH1:

[0080] CH1=M1+T1+T2+M2.

[0081] The upper sides of the active regions OD11 and OD21 are aligned with each other at the K1 line, and the lower sides of the active regions OD12 and OD22 are aligned with each other at the K2 line, where the following formula holds true:

[0082] T1=S11+W11+W12=S21+W21+W22.

[0083] Similarly, the lower sides of the active regions OD13 and OD23 are aligned with each other at line K3, and there is a spacing width S12 or S22 between the active regions OD12 and OD13 or between the active regions OD22 and OD23, where the following formula holds true:

[0084] T2=S12+W13=S22+W23.

[0085] In some embodiments, the nanosheet width W11 , W12 , or W13 in the standard cell 400A is a multiple of the nanosheet width W21 , W22 , or W23 associated with the same flexible width T1 or T2 of the standard cell 400B.

[0086] Different flexible widths T1 and T2 can be different from each other, and the spacing widths S11, S12, S21, and S22 can be different from each other. Therefore, under the constraint of flexible width T1, the active area OD13 can be designed to have an adjustable nanosheet width W13 that is independent of the adjustable nanosheet widths W11 or W12. Similarly, under the constraint of flexible width T2, the active area OD23 can be designed to have an adjustable nanosheet width W23 that is independent of the adjustable nanosheet widths W21 or W22.

[0087] Figure 4B Schematic diagrams of the design layout of standard cells 400C and 400D according to various embodiments of the present invention are shown. The arrangement of standard cells 400C and 400D is similar to that of standard cells 400A and 400B. For the sake of brevity, the description of similar aspects will not be repeated here. Figure 4A and Figure 4B The standard cells 400C and 400D further include defining a flexible width T3 for the active regions OD13 and OD23 (instead of Figure 4A The upper sides of the active areas OD13 and OD23 are aligned with each other at line K4, while line K5 is aligned with the lower cell sides of the standard cells 400C and 400D. The distance between line K2 and line K4 is the edge distance M3, not Figure 4A The edge distance in is M2. Therefore, the following formula holds:

[0088] T3=S13+W13=S23+W23.

[0089] CH1=M1+T1+M3+T3.

[0090] Figure 4C Schematic diagrams of the design layout of standard cells 400E and 400F according to various embodiments of the present invention are shown. The arrangement of standard cells 400E and 400F is similar to that of standard cells 400A and 400B. For the sake of brevity, the description of similar aspects will not be repeated here. Figure 4A and Figure 4C The standard cells 400E and 400F further include defining a flexible width T4 for the active regions OD11 and OD21 (instead of Figure 4A Line K7 also defines with line K2 the flexible width T5 for active areas OD12 and OD22 instead of Figure 4A The flexible width T1 in the standard cells 400E and 400F is aligned with the upper cell side of the standard cells 400E and 400F, while the lower sides of the active regions OD11 and OD21 are aligned with each other at line K7. The spacing width S14 or S24 is defined as the distance between the line K6 and the upper side of the active region OD11 or OD21. The spacing width S15 or S25 is defined as the distance between the line K7 and the upper side of the active region OD12 or OD22. Therefore, the following formula holds:

[0091] T4=S14+W11=S24+W21.

[0092] T5=S15+W12=S25+W22.

[0093] CH1=T4+T5+T2+M2.

[0094] Figure 4DSchematic diagrams of the design layout of standard cells 400G and 400H according to various embodiments of the present invention are shown. The arrangement of standard cells 400G and 400H is similar to that of standard cells 400C, 400D, 400E, and 400F. For the sake of brevity, the description of similar aspects will not be repeated here. Figure 4B 、 Figure 4C and Figure 4D , standard cells 400G and 400H can be seen as Figure 4B and Figure 4C By using lines K6, K7, K2, K4 and K5 to define flexible widths T4, T5 and T3, as discussed above, the following equation holds:

[0095] CH1=T4+T5+M3+T3.

[0096] Figure 5A Schematic diagram of the design layout of standard cells 500A and 500B according to various embodiments of the present invention. The arrangement of standard cells 500A and 500B is similar to that of standard cells 400A and 400B. For the sake of brevity, the description of similar aspects will not be repeated here. Figure 4A and Figure 5A , the active regions OD11, OD12, OD21, OD22 and lines K1, K2 in standard cells 500A and 500B are similar to those in standard cells 400A and 400B, wherein the grouped active regions OD11 and OD12 (or OD21 and OD22) are configured to form a first nanosheet FET of standard cell 500A (or 500B). Each of standard cells 500A and 500B also includes fourth active regions OD14 and OD24 having respective nanosheet widths W14 and W24 measured in the column direction. In some embodiments, active region OD13 or OD23 is grouped with active region OD14 or OD24, and the grouped active regions OD13 / OD23 and OD14 / OD24 are configured to form a second nanosheet FET.

[0097] The nanosheet widths and related parameters of the active areas OD11 to OD14 and OD21 to OD24 described above are defined in a manner similar to those discussed in the previous embodiments. For example, the nanosheet widths W11, W12, W21, and W22 of the grouped active areas OD11, OD12, OD21, and OD22 are defined by lines K1 and K2, the compliant width T1, and the spacing widths S11 and S21. The nanosheet widths W13, W14, W23, and W24 of the grouped active areas OD13, OD14, OD23, and OD24 are defined by lines K3 and K4, the compliant width T2, and the spacing widths S21 and S22. Lines K1 to K4 are defined as lines extending in a row direction parallel to the upper or lower cell side of the standard cells 500A and 500B. The distances between lines K1 and K4 and the upper and lower cell sides of the standard cells 500A and 500B, respectively, are edge distances M1 and M2. The distance between line K2 and line K3 is edge distance M3. In some embodiments, edge distances M1, M2, and M3 and flexible widths T1 and T2 are predetermined cell parameters and follow the following constraints of cell height CH1:

[0098] CH1=M1+T1+M3+T2+M2.

[0099] The upper sides of the active regions OD11 and OD21 are aligned with each other at the K1 line, and the lower sides of the active regions OD12 and OD22 are aligned with each other at the K2 line, where the following formula holds true:

[0100] T1=S11+W11+W12=S21+W21+W22.

[0101] The upper sides of the active regions OD13 and OD23 are aligned with each other on line K3, and the lower sides of the active regions OD14 and OD24 are aligned with each other at line K4, where the following formula holds true:

[0102] T2=S12+W13+W14=S22+W23+W24.

[0103] In some embodiments, the active areas of the group (such as active areas OD11 and OD12, OD21 and OD22, OD13 and OD23, and OD14 and OD24) have equal nanosheet widths to maintain comparable electrical performance between the active areas of the group. Under this assumption, the above formula can be further simplified as follows:

[0104] T1=S11+2*W11=S21+2*W21.

[0105] T2=S12+2*W13=S22+2*W23.

[0106] In some embodiments, the nanosheet width W11, W12, W13, or W14 in the standard cell 500A is a multiple of the nanosheet width W21, W22, W23, or W24 associated with the same flexible width T1, T2 in the standard cell 500B.

[0107] Figure 5B Schematic diagrams of design layouts for standard cells 500C and 500D according to various embodiments of the present invention are shown. The layout of standard cells 500C and 500D is similar to that of standard cells 500A and 500B, and for the sake of brevity, the description of similar aspects will not be repeated here. Figure 5A and Figure 5B , the standard cells 500C and 500D also include defined flexible widths T3, T4, and T5 and corresponding spacing widths S13, S23, S14, S24, S15, and S25 (instead of Figure 4A New lines K5, K6, K7, K8, K9, and K10 (with flexible widths T1 and T2 in the standard cells) are formed. Lines K5 and K10 are aligned with the upper and lower cell sides of standard cells 500A and 500B, respectively. The lower sides of active areas OD11 and OD21 are aligned with each other at line K6. The upper sides of active areas OD12 and OD22 are aligned with each other at line K7, while the lower sides of active areas OD13 and OD23 are aligned with each other at line K8. The upper sides of active areas OD14 and OD24 are aligned with each other at line K9.

[0108] The distance between line K6 and line K7 is edge distance M4, and the distance between line K8 and line K9 is edge distance M5. Therefore, the following formula holds:

[0109] T3=S13+W11=S23+W21.

[0110] T4=S14+W12+W13=S24+W22+W23.

[0111] T5=S15+W14=S25+W24.

[0112] CH1=T3+M4+T4+M5+T5.

[0113] Figure 5C Schematic diagrams of design layouts for standard cells 500E and 500F according to various embodiments of the present invention are shown. The layout of standard cells 500E and 500F is similar to that of standard cells 500A, 500B, 500C, and 500D. For the sake of brevity, the description of similar aspects will not be repeated here. Figure 5A 、 Figure 5B and Figure 5C , standard cells 500E and 500F can be viewed as Figure 5A and Figure 5Bwhere the new flex widths T6 and T7 are defined by lines K7, K3, and K9 and the corresponding spacing widths S16, S26, S17, and S27 that replace the flex width T4. Therefore, the following formula holds:

[0114] CH1=T3+M4+T6+T7+T5.

[0115] In this way, under the constraint of the flexible width T6, the active region OD12 or OD22 can be designed to have a nanosheet width W12 or W22 that is independent of the nanosheet width W13 or W23 of the active region OD13 or OD23. ​​Similarly, under the constraint of the flexible width T7, the active region OD13 or OD23 can be designed to have a nanosheet width W13 or W23 that is independent of the nanosheet width W12 or W22 of the active region OD12 or OD22.

[0116] Figure 5D Schematic diagrams of design layouts for standard cells 500G and 500H according to various embodiments of the present invention are shown. The arrangement of standard cells 500G and 500H is similar to that of standard cells 500A, 500B, 500C, and 500D. For the sake of brevity, the description of similar aspects will not be repeated here. Figure 5A 、 Figure 5B and Figure 5D , standard cells 500G and 500H can be seen as Figure 5A and Figure 5B where the new flex widths T8 and T9 are defined by lines K6, K2, and K8 and the corresponding spacing widths S18, S28, S19, and S29 that replace the flex width T4. Therefore, the following formula holds:

[0117] CH1=T3+T8+T9+M5+T5.

[0118] Figure 5E Schematic diagrams of design layouts for standard cells 500I and 500J according to various embodiments of the present invention are shown. The arrangement of standard cells 500I and 500J is similar to that of standard cells 500A, 500B, 500C, and 500D. For the sake of brevity, the description of similar aspects will not be repeated here. Figure 5A 、 Figure 5B and Figure 5E , standard cells 500I and 500J can be seen as Figure 5A and Figure 5B , where flexible widths T7 and T8 are defined instead of flexible width T4. Therefore, the following formula holds:

[0119] CH1=T3+T8+M3+T7+T5.

[0120] Figure 6A 6 is a flow chart of a layout method 600A according to some embodiments. It should be understood that additional steps may be provided before, during, and after the steps shown in these figures, and that some of the steps described below may be replaced or eliminated in other embodiments of the method 600A. The order of the steps may be interchangeable.

[0121] At step 602, design data for a semiconductor device is generated or received. The design data may be represented as a netlist, schematic, circuit diagram, or the like. In some embodiments, the semiconductor device includes at least one electronic circuit, which may be various types of logic gate devices, such as a NAND gate, an inverter gate, an XOR gate, an AND gate, a NOR gate, an AOI gate, or other suitable logic gate devices. In some embodiments, the design data in step 602 is generated during a synthesis phase of a design flow for manufacturing the semiconductor device.

[0122] At step 604, a design rule set is received. In some embodiments, the design rule set includes design rules, such as a predetermined set of specified values ​​for width and spacing associated with the active area. In some embodiments, the active area is implemented by nanosheets, and the predetermined set includes specified values ​​for the nanosheet width and the nanosheet spacing. In some embodiments, the specified width and spacing are provided by a semiconductor manufacturer or circuit designer. In some embodiments, the specified values ​​for the width and spacing are independent of each other and cannot be predicted by an equation or formula. In some embodiments, the specified values ​​for the width and spacing are elements of an irregular data sequence.

[0123] At step 606, a standard cell library is provided based on the design data, and the standard cell library includes a first cell and a second cell, such as standard cells 300A and 300B. The first cell includes a first active area having a first width, and the second cell includes a second active area having a second width different from the first width. In some embodiments, each of the first cell and the second cell includes a nanosheet FET having a corresponding nanosheet stack, wherein the first nanosheet stack of the first cell overlaps the second nanosheet stack of the second cell in a row direction. The first cell and the second cell have equal cell heights. In some embodiments, the first nanosheet stack and the second nanosheet stack have different nanosheet widths and nanosheet spacings, which are selected from a predetermined set of widths and spacings of a design rule set. The first cell and the second cell are discussed above and are not repeated for brevity.

[0124] At step 608, a design layout is generated based on the design data by placing the first cell and the second cell, for example, in the same row.Step 608 may be performed during a place and route phase of a design flow for manufacturing a semiconductor device.

[0125] At step 610, a photolithography mask is fabricated according to the design layout. At step 611, a semiconductor device is fabricated, wherein layers of the semiconductor device are formed according to the photolithography mask. In some embodiments, the semiconductor device is fabricated according to the design layout.

[0126] Figure 6B 6 is a flow chart of a layout method 600B according to some embodiments. It should be understood that additional steps may be provided before, during, and after the steps shown in these figures, and that some of the steps described below may be replaced or eliminated in other embodiments of method 600B. The order of the steps may be interchangeable.

[0127] Steps 602, 604, 606, 610, and 611 of method 600B are similar to those of method 600A, and therefore the description of these steps is simplified. At step 602, design data for a semiconductor device is generated or received. At step 604, a design rule set is received, the design rule set including a predetermined set of prescribed values ​​for the width and spacing of active areas, such as nanosheet widths and nanosheet spacings. At step 606, a standard cell library including a first cell and a second cell is provided based on the design data. In some embodiments, the first cell and the second cell have equal cell heights, and the corresponding first active area and the second active area have different first and second widths. In some embodiments, the first active area and the second active area include a first nanosheet stack and a second nanosheet stack having different nanosheet widths and nanosheet spacings. In some embodiments, the different nanosheet widths and nanosheet spacings are selected from a predetermined set of nanosheet widths and nanosheet spacings of the design rule set.

[0128] At step 612, a design layout is generated by placing the first cell in a row.Step 612 may be performed during a place and route phase of a design flow for fabricating a semiconductor device.

[0129] At step 614, circuit simulation is performed to check the physical and electrical properties of the design layout. In some embodiments, circuit simulation includes post-layout simulation. In some embodiments, additional steps, such as parasitic parameter extraction and timing analysis, may be performed to provide layout-related information to support circuit simulation. At step 616, a determination is made based on the circuit simulation results as to whether the design layout meets the design requirements.

[0130] If yes, a photolithography mask is manufactured according to the design layout at step 610. A semiconductor device is manufactured at step 611, wherein layers of the semiconductor device are formed according to the photolithography mask. In some embodiments, the semiconductor device is manufactured according to the design layout.

[0131] If it is determined that the first cell fails the circuit simulation, it means that the circuit needs to be modified. At step 618, the first cell is replaced with a second cell of the same cell height, and method 600B loops back to step 616 to perform another circuit simulation. In some embodiments, the nanosheet width of the second cell is greater than the nanosheet width of the first cell, and thus can provide higher circuit performance than the first cell with the same cell height. In some embodiments, since the second cell is similar to the first cell in most of the cell layout except for the nanosheet width, the difference between the original design layout containing the first cell and the modified design layout containing the second cell is minimized. In this way, the possibility of modifying the remaining part of the modified design layout is correspondingly reduced or minimized, thereby greatly shortening the cycle of modifying the design layout.

[0132] Figure 7A Schematic diagram 700 of an integrated circuit (IC) manufacturing system according to some embodiments is shown. IC manufacturing system 700 is configured to manufacture IC devices 780 through multiple entities, such as a design subsystem 710, a mask subsystem 720, and a manufacturing subsystem 730. The entities in IC manufacturing system 700 can be linked by communication channels (such as wired or wireless channels) and interact with each other through a network (e.g., an intranet or the Internet). In an embodiment, design subsystem 710, mask subsystem 720, and manufacturing subsystem 730 belong to a single entity or are operated by independent parties.

[0133] A design subsystem 710, which may be provided by a design house or layout design provider, generates a design layout 750, such as design layout 200, during the design phase of an IC device 780 to be manufactured. The design subsystem 710 may execute the layout methods discussed herein to generate the design layout 750, such as the design layouts shown with reference to the accompanying drawings. In an embodiment, the design subsystem 710 operates a circuit design process to generate the design layout 750. The design subsystem 710 may also include one or more steps, such as logic design, physical design, pre-layout simulation, placement and routing, timing analysis, parameter extraction, design rule checking, and post-layout simulation, to generate the design layout 750. The design layout 750 may be converted from a descriptive text to its visual equivalent to display the physical layout of the depicted patterns, such as their size, shape, and position. In an embodiment, the design layout 750 may be expressed in a suitable file format, such as GDSII, DFII, OASIS, or the like.

[0134] The mask subsystem 720 receives the design layout 750 from the design subsystem 710 and manufactures one or more masks (photomasks, photolithography masks, or reticles) according to the design layout 750. In an embodiment, the mask subsystem 720 includes a mask data preparation block 722, a mask fabrication block 724, and a mask inspection block 726. The mask data preparation block 722 modifies the design layout 750 so that the modified design layout 760 can allow a mask writer to convert the design layout 750 into a format readable by the writer.

[0135] The mask fabrication block 724 is configured to fabricate one or more masks by preparing a substrate based on a design layout 760 provided by the mask data preparation block 722. The mask substrate is exposed to a radiation beam based on the pattern of the design layout 760 in the write operation, followed by an etching operation to leave a pattern corresponding to the design layout 760. In an embodiment, the mask fabrication block 724 includes an inspection process to ensure that the layout data 760 meets the requirements of the mask writer and / or mask manufacturer to generate the mask as required. The pattern can be transferred using an electron beam (e-beam), multiple electron beams, an ion beam, a laser beam, or other suitable writer source.

[0136] After fabricating one or more masks, the mask inspection block 726 inspects the fabricated masks to determine if there are any defects in the fabricated masks, such as full height and non-full height defects. If any defects are detected, the masks can be cleaned or the design layout in the masks can be modified.

[0137] The manufacturing subsystem 730 is an IC manufacturing entity that includes multiple manufacturing facilities or tools for manufacturing various IC devices 780. The manufacturing subsystem 730 uses masks manufactured by the mask subsystem 720 to manufacture wafers 770 having multiple IC devices 780 thereon. The wafer 770 includes a semiconductor substrate and various layers optionally formed thereon. The operations provided by the manufacturing facilities or tools may include, but are not limited to, photolithography, deposition, sputtering, etching, diffusion, ion implantation, and annealing. In some embodiments, test structures may be formed on the wafer 770 to generate test data indicating the quality of the manufactured wafer 770. In an embodiment, the manufacturing subsystem 730 includes a wafer test block 732 configured to ensure that the wafer 770 meets physical manufacturing specifications and mechanical and / or electrical performance specifications. After the wafer 770 passes the test process performed by the wafer test block 732, the wafer 770 can be cut (or sliced) along the scribe line area to form individual IC devices 780. The cutting process can be accomplished by scribing and breaking, by mechanical sawing (eg, with a dicing saw), or laser cutting.

[0138] Figure 7B7 is a schematic diagram of a system 700 for implementing or storing the design layout discussed above, according to some embodiments. System 700 includes a processor 701, a network interface 703, an input and output (I / O) device 705, a storage device 707, a memory 709, and a bus 708. Bus 708 couples network interface 703, I / O device 705, storage device 707, memory 709, and processor 701 to one another.

[0139] Processor 701 is configured to execute program instructions including tools configured to generate the design layouts described and illustrated with reference to the figures of the present invention.

[0140] Network interface 703 is configured to access program instructions and data accessed by remotely stored program instructions over a network (not shown).

[0141] I / O devices 705 include input devices and output devices that are configured to enable a user to interact with system 700. In some embodiments, input devices include, for example, a keyboard, a mouse, and other devices. Additionally, output devices include, for example, a display, a printer, and other devices.

[0142] The memory device 707 is configured to store a design layout, one or more cell libraries (including configurations and settings of standard cells as discussed above), program instructions, and data accessed by the program instructions. In some embodiments, the memory device 707 includes a non-transitory computer-readable storage medium such as a magnetic disk or optical disk.

[0143] Memory 709 is configured to store program instructions executed by processor 701 and data accessed by the program instructions. In some embodiments, memory 709 includes any combination of random access memory (RAM), some other volatile storage device, read only memory (ROM), and some other non-volatile storage device.

[0144] According to an embodiment, a method includes receiving a design rule set including a predetermined set of widths and spacings associated with active areas. The method also includes providing a cell library including cells having corresponding active areas, wherein the widths and spacings of the active areas are selected from the predetermined set of the design rule set. The method includes placing a first cell and a second cell from the cell library in a design layout. The first cell has a cell height in a first direction, and the first cell includes a first active area having a first width in the first direction. The second cell has a cell height, and the second cell includes a second active area having a second width in the first direction. The second width is different from the first width. The method also includes manufacturing a semiconductor device according to the design layout.

[0145] In the above method, the first active region and the second active region overlap in a second direction perpendicular to the first direction.

[0146] In the above method, the first active region has a first side extending in a second direction perpendicular to the first direction, and the second active region has a second side extending in the second direction and aligned with the first side.

[0147] In the above method, the first unit includes a third active region separated from the first active region in the first direction, and the third active region has a third width in the first direction, and the second unit includes a fourth active region separated from the second active region in the first direction, and the fourth active region has a fourth width in the first direction, and the fourth width is different from the third width.

[0148] In the above method, the first unit includes a third active region separated from the first active region in the first direction, the third active region has a third width in the first direction, and the second unit includes a fourth active region separated from the second active region in the first direction, the fourth active region has a fourth width in the first direction, the fourth width is different from the third width, the third active region is separated from the first active region by a first distance, the fourth active region is separated from the second active region by a second distance, and the sum of the first width, the third width and the first distance is equal to the sum of the second width, the fourth width and the second distance.

[0149] In the above method, the first unit includes a third active region separated from the first active region in the first direction, the third active region has a third width in the first direction, and the second unit includes a fourth active region separated from the second active region in the first direction, the fourth active region has a fourth width in the first direction, the fourth width is different from the third width, the third active region is separated from the first active region by a first distance, the fourth active region is separated from the second active region by a second distance, and the sum of the first width and the first distance is equal to the sum of the second width and the second distance.

[0150] In the above method, the first unit includes a third active region separated from the first active region in the first direction, the third active region has a third width in the first direction, and the second unit includes a fourth active region separated from the second active region in the first direction, the fourth active region has a fourth width in the first direction, the fourth width is different from the third width, the third active region is separated from the first active region by a first distance, the fourth active region is separated from the second active region by a second distance, and the first distance is equal to the second distance.

[0151] In the above method, the first unit includes a third active region separated from the first active region in the first direction, and the third active region has a third width in the first direction, and the second unit includes a fourth active region separated from the second active region in the first direction, and the fourth active region has a fourth width in the first direction, the fourth width is different from the third width, and the first width is equal to the third width.

[0152] In the above method, each of the first active region and the second active region includes a plurality of nanosheets.

[0153] In the above method, wherein the distance between the upper cell side of the first cell and the lower side of the first active region is equal to the distance between the upper cell side of the second cell and the lower side of the second active region.

[0154] In the above method, wherein a distance between a lower cell side of the first cell and an upper side of the first active region is equal to a distance between a lower cell side of the second cell and an upper side of the second active region.

[0155] In the above method, wherein the difference between the first width and the second width is at least 2.5% of the first width.

[0156] According to an embodiment, a method includes placing a first cell and a second cell in a first row of a design layout. The first cell includes a first active area and a second active area. The first active area is separated from the second active area by a first distance in a first direction. The second cell includes a third active area and a fourth active area. The third active area is separated from the fourth active area by a second distance in the first direction. The second distance is different from the first distance. The method also includes manufacturing a semiconductor device according to the design layout.

[0157] In the above method, a first width between an upper side of the first active region and a lower side of the second active region is equal to a second width between an upper side of the third active region and a lower side of the fourth active region.

[0158] In the above method, the first unit further includes a fifth active region adjacent to the second active region and a sixth active region adjacent to the fifth active region, and the fifth active region is separated from the sixth active region by a third distance in the first direction, and the third distance is different from the first distance.

[0159] In the above method, the first unit further includes a fifth active region adjacent to the second active region and a sixth active region adjacent to the fifth active region, and the fifth active region is separated from the sixth active region by a third distance in the first direction, and the third distance is different from the first distance; the second unit includes a seventh active region adjacent to the fourth active region and an eighth active region adjacent to the seventh active region, and the seventh active region is separated from the eighth active region by a fourth distance in the first direction, and the fourth distance is different from the third distance.

[0160] In the above method, the first unit further includes a fifth active region adjacent to the second active region and a sixth active region adjacent to the fifth active region, and the fifth active region and the sixth active region are separated by a third distance in the first direction, and the third distance is different from the first distance; the second unit includes a seventh active region adjacent to the fourth active region and an eighth active region adjacent to the seventh active region, and the seventh active region and the eighth active region are separated by a fourth distance in the first direction, and the fourth distance is different from the third distance; the distance between the second active region and the fifth active region is equal to the distance between the fourth active region and the seventh active region.

[0161] In the above method, the first unit further includes a fifth active region adjacent to the second active region and a sixth active region adjacent to the fifth active region, and the fifth active region and the sixth active region are separated by a third distance in the first direction, and the third distance is different from the first distance; the second unit includes a seventh active region adjacent to the fourth active region and an eighth active region adjacent to the seventh active region, and the seventh active region and the eighth active region are separated by a fourth distance in the first direction, and the fourth distance is different from the third distance; the distance between the upper side of the first active region and the lower side of the sixth active region is equal to the distance between the upper side of the third active region and the lower side of the eighth active region.

[0162] In the above method, an upper side of the first active region is aligned with an upper side of the third active region, and a lower side of the second active region is aligned with a lower side of the fourth active region.

[0163] According to an embodiment, a non-transitory computer-readable storage medium includes instructions that, when executed by a processor, cause the processor to perform a circuit simulation of an operation of a design layout including a first cell. The first cell has a cell height in a first direction and includes a plurality of first nanosheets having a first width in the first direction. In response to the circuit simulation failing to meet design requirements, the processor is caused to replace the first cell in the design layout with a second cell to obtain a modified design layout. The second cell has a cell height and includes a plurality of second nanosheets having a second width in the first direction. The second width is greater than the first width. The processor is further caused to control the fabrication of a semiconductor device based on the modified design layout.

[0164] The features of several embodiments have been summarized above so that those skilled in the art can better understand aspects of the present invention. Those skilled in the art will appreciate that they can easily use the present invention as a substrate to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent configurations do not depart from the spirit and scope of the present invention, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present invention.

Claims

1. A method for manufacturing a semiconductor device, comprising: receiving a set of design rules comprising a predetermined set of discrete values ​​for widths and spacings associated with active areas consistent with manufacturing requirements; providing a cell library comprising cells having equal cell heights and including corresponding active areas, wherein widths and spacings of the active areas are selected from a predetermined set of the set of design rules; placing a first cell from the cell library in a design layout, wherein the first cell has a cell height in a first direction and includes a first active area having a first width in the first direction; placing a second cell from the cell library in the design layout, wherein the second cell has a cell height that is the same as the cell height of the first cell, and the second cell includes a second active area having a second width in the first direction, the second active area is spaced apart from the first active area in a second direction perpendicular to the first direction, and the second width is different from the first width; and A semiconductor device is manufactured according to the design layout.

2. The method according to claim 1, wherein The first active region and the second active region overlap in the second direction.

3. The method according to claim 1, wherein The first active region has a first side extending in a second direction perpendicular to the first direction, and The second active region has a second side extending in the second direction and aligned with the first side.

4. The method according to claim 1, wherein The first cell includes a third active region spaced apart from the first active region in the first direction, the third active region having a third width in the first direction, and The second cell includes a fourth active region spaced apart from the second active region in the first direction, the fourth active region having a fourth width in the first direction, the fourth width being different from the third width.

5. The method according to claim 4, wherein The third active region is separated from the first active region by a first distance, The fourth active region is separated from the second active region by a second distance, and The sum of the first width, the third width, and the first distance is equal to the sum of the second width, the fourth width, and the second distance.

6. The method according to claim 4, wherein: The third active region is separated from the first active region by a first distance, The fourth active region is separated from the second active region by a second distance, and The sum of the first width and the first distance is equal to the sum of the second width and the second distance.

7. The method according to claim 4, wherein: The third active region is separated from the first active region by a first distance, The fourth active region is separated from the second active region by a second distance, and The first distance is equal to the second distance.

8. The method according to claim 4, wherein: The first width is equal to the third width.

9. The method according to claim 1, wherein Each of the first active region and the second active region includes a plurality of nanosheets.

10. The method according to claim 1, wherein A distance between an upper cell side of the first cell and a lower side of the first active region is equal to a distance between an upper cell side of the second cell and a lower side of the second active region.

11. The method according to claim 1, wherein A distance between a lower cell side of the first cell and an upper side of the first active region is equal to a distance between a lower cell side of the second cell and an upper side of the second active region.

12. The method according to claim 1, wherein A difference between the first width and the second width is at least 2.5% of the first width.

13. A method for manufacturing a semiconductor device, comprising: placing a first cell in a first row extending in a horizontal direction of a design layout, wherein the first row is any one of a plurality of rows of the design layout, the first cell comprising a first active area and a second active area, wherein the first active area is separated from the second active area by a first distance in a vertical direction, the first distance being a distance measured between adjacent edges of the first active area and the second active area; placing a second cell in the first row of the design layout, wherein the second cell includes a third active area and a fourth active area, wherein the third active area is vertically separated from the fourth active area by a second distance, the second distance being different from the first distance, the second distance being measured between adjacent edges of the third active area and the fourth active area; and A semiconductor device is manufactured according to the design layout.

14. The method according to claim 13, wherein A first width between an upper side of the first active region and a lower side of the second active region is equal to a second width between an upper side of the third active region and a lower side of the fourth active region.

15. The method according to claim 13, wherein The first unit further includes a fifth active region adjacent to the second active region and a sixth active region adjacent to the fifth active region, and The fifth active region is separated from the sixth active region by a third distance in the vertical direction, and the third distance is different from the first distance.

16. The method according to claim 15, wherein The second unit includes a seventh active region adjacent to the fourth active region and an eighth active region adjacent to the seventh active region, and The seventh active region is separated from the eighth active region by a fourth distance in the vertical direction, and the fourth distance is different from the third distance.

17. The method according to claim 16, wherein A distance between the second active region and the fifth active region is equal to a distance between the fourth active region and the seventh active region.

18. The method according to claim 16, wherein A distance between an upper side of the first active region and a lower side of the sixth active region is equal to a distance between an upper side of the third active region and a lower side of the eighth active region.

19. The method according to claim 13, wherein The upper side of the first active region is aligned with the upper side of the third active region, and A lower side of the second active region is aligned with a lower side of the fourth active region.

20. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processor, cause the processor to: performing a circuit simulation of an operation including a design layout of the first cell, wherein The first unit has a unit height in a first direction, and the first unit includes a plurality of first nanosheets having a first width in the first direction; In response to the first cell being a failed cell and the circuit simulation failing, replacing the first cell in the design layout with a second cell to obtain a modified design layout, wherein the second cell has a cell height in the first direction that is the same as the cell height of the first cell, and the second cell includes a plurality of second nanosheets having a second width in the first direction, the second width being greater than the first width; and Manufacturing of the semiconductor device is controlled according to the modified design layout.

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