Bare IC packaging method and system

Abstract

The present invention provides a bare chip IC packaging method and system, including: obtaining parameter information of the IC to be packaged; the parameter information includes the size of the IC to be packaged and the position of the corresponding bonding solder joint; determining the packaging simulation scheme of the IC to be packaged according to the parameter information of the IC to be packaged; the packaging simulation scheme includes the bonding solder joints of the IC to be packaged and the corresponding PCB pin bonding wire simulation scheme; verifying and adjusting the packaging simulation scheme based on preset packaging requirements until the packaging requirements are met to obtain the verified packaging simulation scheme; packaging the IC to be packaged based on the verified packaging simulation scheme. In this scheme, before packaging the bare chip IC to be packaged, the bonding solder joints of the IC to be packaged and the corresponding PCB pin bonding wire simulation scheme are pre-designed, and when the verification simulation scheme meets the packaging requirements, formal packaging is performed, which can reduce the risk of packaging revision and alleviate the problem of extended project development cycle caused by design revision.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit boards, and in particular to a packaging method and system for bare chip ICs. Background Art

[0002] Bare chip ICs have a price advantage in mass production and are currently widely used in mass-produced electronic products such as electronic scales, electronic blood pressure monitors, and various electronic toys. When using bare chip ICs (Integrated Circuit Chips, IC chips) to design PCB (Printed Circuit Board, printed circuit board) circuit boards, each new bare chip IC requires a new PCB package to be designed for it. The current general design is to design the substrate size of the bare chip IC based on the bonding data of the bare chip IC, and design the bonding pins on the PCB based on the number of IC pins.

[0003] Since the existing PCB packaging scheme is designed only based on the substrate size information and the number of bonding pins in the bonding data, when the board is printed for actual bonding verification, it is often easy to have the spacing between adjacent bonding wires or between adjacent bonding wires and solder joints too close, or even worse, adjacent bonding wires are easy to touch each other, or adjacent bonding wires and solder joints are easy to short-circuit. This situation will lead to the need to revise the PCB packaging scheme, thereby affecting the sample production and mass production of the product. Revising the PCB packaging scheme will also extend the project development cycle. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide a packaging method and system for bare chip ICs. Before packaging the bare chip ICs to be packaged, a simulation scheme for bonding the bonding points of the ICs to be packaged and the corresponding PCB pins is pre-designed. After verifying that the simulation scheme meets the packaging requirements, formal packaging is performed, which can reduce the risk of packaging revisions and alleviate the problem of extended project development cycles caused by design revisions.

[0005] In a first aspect, an embodiment of the present invention provides a method for packaging a bare chip IC, comprising: obtaining parameter information of the IC to be packaged; the parameter information includes the size of the IC to be packaged and the corresponding bonding solder joint positions; determining a packaging simulation scheme for the IC to be packaged based on the parameter information of the IC to be packaged; the packaging simulation scheme includes a bonding solder joint of the IC to be packaged and a wire bonding simulation scheme for the corresponding PCB pins; verifying and adjusting the packaging simulation scheme based on preset packaging requirements until the packaging requirements are met to obtain a verified packaging simulation scheme; and packaging the IC to be packaged based on the verified packaging simulation scheme.

[0006] Furthermore, according to the parameter information of the IC to be packaged, the step of determining the packaging simulation scheme of the IC to be packaged includes: calculating the minimum angle between the bonding wires corresponding to adjacent bonding solder points according to the positions of the bonding solder points; calculating the number of PCB pins required for the PCB pin surrounding circle according to the minimum angle, and calculating the average angle between the bonding wires corresponding to adjacent bonding solder points; wherein the PCB pin surrounding circle is formed by the PCB pins being evenly surrounded with the physical center of the IC to be packaged as the center; determining the position of the reference pin of the PCB pin surrounding circle, and calculating the surrounding radius of the PCB pin surrounding circle according to the position of the reference pin; determining the bonding wire simulation scheme of the PCB pin according to the number of PCB pins, the average angle and the surrounding radius.

[0007] Furthermore, according to the positions of the bonding solder joints, the step of calculating the minimum angle between the bonding wires corresponding to the adjacent bonding solder joints comprises: according to the positions of the bonding solder joints, selecting one bonding solder joint in the clockwise direction on each side of the IC to be packaged as the first bonding solder joint, and selecting one bonding solder joint in the counterclockwise direction on each side of the IC to be packaged as the second bonding solder joint; starting from the center of the circle, drawing leads to the first bonding solder joint and the second bonding solder joint respectively to form the corresponding angle of each side; wherein the first bonding solder joint is not adjacent to the second bonding solder joint; calculating the total number of bonding solder joints between the first bonding solder joint and the second bonding solder joint, and calculating the angle between the bonding wires corresponding to the adjacent bonding solder joints on each side according to the corresponding angle and the bonding joints on each side; and determining the minimum angle among the angles between the bonding wires corresponding to the adjacent bonding solder joints on each side as the minimum angle.

[0008] Furthermore, the steps of calculating the number of PCB pins required for the PCB pins to surround the circle based on the minimum angle, and calculating the average angle of the bonding wires corresponding to the adjacent bonding solder joints, include: calculating the number of PCB pins required for the PCB pins to surround the circle based on the minimum angle and the circumferential angle; calculating the average angle of the bonding wires corresponding to the adjacent bonding solder joints based on the number of PCB pins.

[0009] Furthermore, the position of the reference pin of the PCB pin surrounding circle is determined, and the step of calculating the surrounding radius of the PCB pin surrounding circle through the position of the reference pin includes: determining the bonding solder point on the side with the most bonding solder points and with a horizontal coordinate and / or a vertical coordinate of 0 as the reference pin; and determining the distance from the midpoint of the reference pin to the midpoint of the IC to be packaged as the surrounding radius of the PCB pin surrounding circle.

[0010] Further, determining the position of the reference pin of the PCB pin surrounding circle, and calculating the surrounding radius of the PCB pin surrounding circle by the position of the reference pin, further includes: according to the number of the PCB pins, arranging the PCB pins in a balanced manner around the physical center of the IC to be packaged as the center of the circle; wherein a preset pin safety distance is maintained between adjacent PCB pins; drawing an inner circle with the distance from the center of the circle to the inner edge of each reference pin as the radius; and calculating the surrounding radius of the PCB pin surrounding circle according to the following formula:

[0011]

[0012] Where r is the radius of the circle around the PCB pin, r 内 is the radius of the inner circle, w 引 is the width of the PCB pin, l 引 is the length of the PCB pin, l 预 is the preset pin safety distance, and n is the number of PCB pins.

[0013] Furthermore, the preset packaging requirements include: the distance between adjacent bonding wires meets the preset bonding wire distance; and / or the distance between each bonding wire and the corresponding bonding solder joint meets the preset spacing; and / or the distance between the inner edges of adjacent PCB pins meets the preset pin safety distance.

[0014] Furthermore, the step of verifying and adjusting the packaging simulation scheme based on the preset packaging requirements until the packaging requirements are met to obtain a verified packaging simulation scheme includes: verifying the packaging simulation scheme based on the preset packaging requirements, and if the packaging simulation scheme does not meet the packaging requirements, adjusting the number of PCB pins and / or the radius of the circle surrounding the PCB pins until the packaging requirements are met to obtain a verified packaging simulation scheme.

[0015] In a second aspect, an embodiment of the present invention provides a packaging system for a bare chip IC, comprising: a parameter information acquisition module, used to acquire parameter information of the IC to be packaged; the parameter information includes the size of the IC to be packaged and the corresponding bonding solder joint positions; a packaging simulation scheme determination module, used to determine the packaging simulation scheme of the IC to be packaged according to the parameter information of the IC to be packaged; the packaging simulation scheme includes the bonding solder joints of the IC to be packaged and the bonding wire simulation scheme of the corresponding PCB pins; a packaging simulation scheme verification and adjustment module, used to verify and adjust the packaging simulation scheme based on preset packaging requirements until the packaging requirements are met to obtain a verified packaging simulation scheme; a packaging module, used to package the IC to be packaged based on the verified packaging simulation scheme.

[0016] In a third aspect, an embodiment of the present invention provides an electronic device, including a memory and a processor, wherein the memory stores a computer program executable on the processor, and the processor implements the method described above when executing the computer program.

[0017] The embodiment of the present invention provides a bare chip IC packaging method and system, including: obtaining parameter information of the IC to be packaged; the parameter information includes the size of the IC to be packaged and the corresponding bonding solder joint position; determining the packaging simulation scheme of the IC to be packaged according to the parameter information of the IC to be packaged; the packaging simulation scheme includes the bonding solder joints of the IC to be packaged and the bonding wire simulation scheme of the corresponding PCB pins; verifying and adjusting the packaging simulation scheme based on preset packaging requirements until the packaging requirements are met to obtain a verified packaging simulation scheme; packaging the IC to be packaged based on the verified packaging simulation scheme. In this scheme, before packaging the bare chip IC to be packaged, the bonding solder joints of the IC to be packaged and the bonding wire simulation scheme of the corresponding PCB pins are pre-designed, and when the verification simulation scheme meets the packaging requirements, formal packaging is performed, which can reduce the risk of packaging revision and alleviate the problem of extended project development cycle caused by design revision.

[0018] Other features and advantages of the present invention will be described in the following description, and partly become apparent from the description, or understood by practicing the present invention. The purpose and other advantages of the present invention are realized and obtained by the structures particularly pointed out in the description, claims and drawings.

[0019] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0021] Figure 1 A flow chart of a bare chip IC packaging method provided in Embodiment 1 of the present invention;

[0022] Figure 2 A flow chart of a packaging simulation scheme for determining an IC to be packaged provided in the first embodiment of the present invention;

[0023] Figure 3 Reference information of IC to be packaged and schematic diagram of pad position provided in the second embodiment of the present invention;

[0024] Figure 4 A schematic diagram of the angle of the IC to be packaged provided in the second embodiment of the present invention;

[0025] Figure 5 A schematic diagram of calculating the radius of a PCB pin surrounding circle provided in the second embodiment of the present invention;

[0026] Figure 6 A schematic diagram of software parameter settings provided in Embodiment 2 of the present invention;

[0027] Figure 7 This is a diagram showing the effect of a PCB pin surrounding a circle provided in the second embodiment of the present invention;

[0028] Figure 8 The overall effect diagram of the simulated pre-Labon line provided in the second embodiment of the present invention;

[0029] Fig. 9 An equivalent detailed diagram of an IC to be packaged provided in the second embodiment of the present invention;

[0030] Fig.10 A PCB packaging effect diagram after the design is completed provided in the second embodiment of the present invention;

[0031] Fig.11 This is a module diagram of a bare chip IC packaging system provided in Embodiment 3 of the present invention.

[0032] Icons: 1- parameter information acquisition module; 2- packaging simulation scheme determination module; 3- packaging simulation scheme verification and adjustment module; 4- packaging module. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] In the related art, because bare chip IC has a price advantage in mass production, it is still widely used in mass-produced electronic products, such as electronic scales, electronic blood pressure monitors, and various electronic toys. Usually, in the PCB package design corresponding to the bare chip IC, the substrate size of the bare chip IC is designed according to the bonding data of the bare chip IC, and the bonding pins on the PCB are designed according to the number of IC pins. In this way, a simple and rough PCB package corresponding to the bare chip can be designed. However, since the design verification process is not introduced, after the PCB design is completed and the proof is returned, the adjacent bonding wires will be too close or the adjacent bonding wires will touch the solder joints. Often, this package designed based on experience cannot withstand the test of the actual bonding process.

[0035] Based on this, an embodiment of the present invention provides a bare chip IC packaging method and system. This technology can well predict these situations and handle them in advance, so that the designed bare chip IC PCB package can be smoothly bonded, greatly reducing the risk of board modification and saving project development time.

[0036] To facilitate understanding of this embodiment, the embodiment of the present invention is described in detail below.

[0037] Embodiment 1:

[0038] Figure 1 This is a flow chart of a bare chip IC packaging method provided in Embodiment 1 of the present invention.

[0039] Reference Figure 1 , the packaging method of the bare chip IC includes the following steps:

[0040] Step S101, obtaining parameter information of the IC to be packaged; the parameter information includes the size of the IC to be packaged and the corresponding bonding pad position.

[0041] Step S102, determining a packaging simulation scheme of the IC to be packaged according to parameter information of the IC to be packaged; the packaging simulation scheme includes a bonding solder joint of the IC to be packaged and a bonding wire simulation scheme of the corresponding PCB pins.

[0042] Step S103, verifying and adjusting the packaging simulation solution based on the preset packaging requirements until the packaging requirements are met, thereby obtaining a verified packaging simulation solution;

[0043] Step S104 , packaging the IC to be packaged based on the verified packaging simulation solution.

[0044] Here, the parameter information of the IC to be packaged includes BONGDING PAD LOCATION (bonding soldering point coordinates), pad (soldering point) size and the size of the IC to be packaged, etc., among which BONGDING PAD LOCATION is used to determine the corresponding bonding soldering point position, and the corresponding PCB pin diagram is drawn according to the parameter information of the IC to be packaged.

[0045] By introducing a mindset that simulates actual bonding verification, the packaging solution is verified and adjusted until the packaging requirements are met and the IC to be packaged is packaged.

[0046] Among them, the preset packaging requirements include: the distance between adjacent bonding wires meets the preset bonding wire distance; and / or the distance between each bonding wire and the corresponding bonding solder joint meets the preset spacing; and / or the distance between the inner edges of adjacent PCB pins meets the preset pin safety distance.

[0047] In one embodiment, referring to Figure 2 As shown in the flowchart of determining the packaging simulation scheme of the IC to be packaged, the above step S102 can be implemented by the following steps S201 to S204:

[0048] Step S201, calculating the minimum angle between the bonding wires corresponding to the adjacent bonding welding points according to the positions of the bonding welding points;

[0049] Step S202, calculating the number of PCB pins required for the PCB pin surrounding circle according to the minimum angle, and calculating the average angle of the bonding wires corresponding to the adjacent bonding solder joints; wherein the PCB pin surrounding circle is formed by the PCB pins surrounding the physical center of the IC to be packaged as the center;

[0050] Step S203, determining the position of the reference pin of the circle surrounding the PCB pin, and calculating the surrounding radius of the circle surrounding the PCB pin according to the position of the reference pin;

[0051] Step S204, determining a wire bonding simulation scheme for the PCB pins according to the number of PCB pins, the average angle and the wrap radius.

[0052] Here, the number of PCB pins, average angle and wrap radius are input into the design software (PCB layout, etc.), and then a wire bonding simulation scheme for the PCB pins can be drawn out based on the special paste function of the design software.

[0053] In one implementation manner, the above step S201 may be implemented by the following steps:

[0054] According to the positions of the bonding soldering points, one bonding soldering point is selected in the clockwise direction on each side of the IC to be packaged as the first bonding soldering point, and one bonding soldering point is selected in the counterclockwise direction on each side of the IC to be packaged as the second bonding soldering point;

[0055] Drawing leads from the center of the circle to the first bonding point and the second bonding point respectively to form a corresponding angle of each side; wherein the first bonding point is not adjacent to the second bonding point;

[0056] Calculate the total number of bonding points between the first bonding point and the second bonding point, and calculate the angle between the bonding wires corresponding to the adjacent bonding points on each side according to the angle and bonding points corresponding to each side;

[0057] The smallest angle among the angles between the adjacent bonding points on each side and the corresponding bonding wires is determined as the minimum angle.

[0058] Here, two leads are drawn from the center of the circle to each side, and the angles of the corresponding bonding wires of the adjacent bonding points on the side are calculated based on the corresponding angles. The angle with the smallest value is taken as the minimum angle by comparison. The safe distance between the lead and the pad outside the angle is more than 1 mil.

[0059] In one implementation manner, the above step S202 may be implemented by the following steps:

[0060] According to the minimum included angle and the circumference angle, calculate the number of PCB pins required for the PCB pins to surround the circle;

[0061] According to the number of PCB pins, calculate the average angle between the bonding wires of adjacent bonding solder joints.

[0062] Here, the corresponding number of PCB pins required to form a circle around the PCB pins can be obtained based on the minimum included angle and the circumferential angle, wherein the number of pins is an integer.

[0063] In one implementation manner, the above step S203 may be implemented by the following steps:

[0064] The bonding solder joint with the largest number of bonding solder joints and whose abscissa and / or ordinate is 0 is determined as the reference pin;

[0065] The distance from the midpoint of the reference pin to the midpoint of the IC to be packaged is determined as the surrounding radius of the circle surrounding the PCB pin.

[0066] Here, observe the pad arrangement of the IC to be packaged, set the reference pin on the longest side with the most pads, and determine the location of the selected reference pin based on the BONGDING PAD LOCATION.

[0067] Based on the reference pin, other pins are evenly arranged around the physical center of the IC to be packaged by a special pasting method according to the number of PCB pins; wherein, a preset pin safety distance is maintained between adjacent PCB pins;

[0068] Draw an inner circle with the distance from the center of the circle to the inner edge of each reference pin as the radius;

[0069] Calculate the radius of the circle surrounding the PCB pin according to formula (1):

[0070]

[0071] Among them, r is the radius of the circle around the PCB pin, r 内 is the radius of the inner circle, w 引 is the width of the PCB pin, l 引 is the length of the PCB pin, l 预 is the preset pin safety distance, and n is the number of PCB pins.

[0072] Here, the radius of the circle around the PCB pin is calculated using the principle of pi and proximity, and can be fine-tuned to achieve the ideal design size.

[0073] In one implementation manner, the above step S103 may be implemented by the following steps:

[0074] The packaging simulation solution is verified based on the preset packaging requirements. If the packaging simulation solution does not meet the packaging requirements, the number of PCB pins and / or the radius of the circle surrounding the PCB pins are adjusted until the packaging requirements are met, thereby obtaining a verified packaging simulation solution.

[0075] Here, the pin winding effect diagram is drawn through the special paste function of the design software, and the overall effect diagram of the simulated pre-Labelin is obtained by simulating the Labelin between the pad of the IC to be packaged and the PCB pin. The overall effect diagram is used to check whether the spacing between the lead and the pad is reasonable, so as to verify the packaging simulation plan.

[0076] Among them, check and evaluate whether the spacing between adjacent bonding wires and pads is appropriate, and whether the spacing between the inner edges of PCB pins is reasonable. Here, the spacing between adjacent bonding wires and pads and the spacing between the inner edges of PCB pins can be set according to actual conditions. Generally, the spacing between adjacent bonding wires and pads is more than 1mil, and the spacing between the inner edges of PCB pins is 0.2mm (millimeter). According to the above design method, if adjustments are needed, they can be adjusted by increasing or decreasing the number of PCB pins and the radius of the circle around the PCB pins until the packaging requirements are met.

[0077] The embodiment of the present invention provides a method for packaging a bare chip IC, including: obtaining parameter information of the IC to be packaged; the parameter information includes the size of the IC to be packaged and the corresponding bonding solder joint position; determining a packaging simulation scheme for the IC to be packaged according to the parameter information of the IC to be packaged; the packaging simulation scheme includes the bonding solder joints of the IC to be packaged and the bonding wire simulation scheme of the corresponding PCB pins; verifying and adjusting the packaging simulation scheme based on preset packaging requirements until the packaging requirements are met to obtain a verified packaging simulation scheme; and packaging the IC to be packaged based on the verified packaging simulation scheme. In this embodiment, before packaging the bare chip IC to be packaged, the bonding solder joints of the IC to be packaged and the bonding wire simulation scheme of the corresponding PCB pins are pre-designed, and when the verification simulation scheme meets the packaging requirements, formal packaging is performed, which can reduce the risk of packaging revision and alleviate the problem of extended project development cycle caused by design revision.

[0078] Embodiment 2:

[0079] The Substrate Area (PCB copper exposed area where the bare IC is placed) of the IC to be packaged used in this embodiment is 3500um*3700um, including 70 pads.

[0080] Figure 3 Reference information of the IC to be packaged and a schematic diagram of the pad position provided in the second embodiment of the present invention.

[0081] Figure 4 This is a schematic diagram of the angle of the IC to be packaged provided in the second embodiment of the present invention.

[0082] Reference Figure 3 and Figure 4 , determine the physical center of the IC to be packaged according to the reference information of the IC to be packaged, draw leads from the physical center to each side, one lead passes through the second pad in the clockwise direction of each side, and one lead passes through the second to last pad in the counterclockwise direction of each side, and each lead maintains a safe distance of more than 1mil from the pad outside the angle. Measure the angles formed by the leads drawn on the four sides respectively. From the angle of the pad on the first side above, the angles of the bonding wires corresponding to two adjacent pads are: A1 = 4.4°, A2 = 4.5°, A3 = 6.6°, A4 = 4.82°. By comparison, 4.4° is taken as the minimum angle of the bonding wires corresponding to adjacent bonding solder joints. With the physical center of the chip as the center of the circle, the number of pins required to form a PCB pin surrounding circle by balancing the PCB pins is 360°÷4.4°=81.8pcs. Here, an integer of 82pcs is taken for design, of which 82-70=12pcs of pins are dummy pins (pins that do not need to be bonded). The average angle between the bonding wires of adjacent bonding solder joints calculated based on the number of pins is 360°÷82=4.390°.

[0083] Reference Figure 5 , there are 20 pads on the left, the largest number, so the reference pin is the pin with the ordinate 0 on the left. According to the general design of PCB pins, the length and width of the PCB pin size are 0.6*0.2mm, and the PCB pin edge requires a 0.2mm spacing. In this way, take the inner edge of the PCB pin as a reference and draw a circle through the inner edge. The radius of this circle is r 内 According to the circumference formula of a circle, we can calculate Draw a circle with the radius from the midpoint of the reference pin to the physical midpoint of the IC to be packaged. The circle is the PCB pin surrounding circle. The radius of the PCB pin surrounding circle is After rounding, the radius of the PCB pin surrounding the circle is 5.5 mm. The above calculation is an approximate calculation, and the ideal design size can be achieved by fine-tuning the surrounding radius.

[0084] Reference Figure 6 , through the special paste function of the design software, taking the physical center of the IC to be packaged as the reference point, and the distance from the midpoint of the reference pin to the physical center of the IC to be packaged as the radius, the total number of 82pcs pins and the average angle of 4.390° corresponding to the bonding wires of the adjacent bonding solder joints are input into the design software, and the result is Figure 7 The effect diagram of the PCB pins surrounding the circle.

[0085] Simulate the bonding wire between the pad of the IC to be packaged and the PCB pin, and set the lead of the simulated bonding wire to 1mil width. Figure 8 The overall effect diagram of the simulated pre-Labon line and Fig. 9 Equivalent detailed drawing of the IC to be packaged, check whether the spacing between the bonding wire and the pad meets the safety distance of 1mil, and whether the spacing between the inner edges of the pad pins meets 0.2mm. If the packaging simulation solution does not meet the packaging requirements, adjust the number of PCB pins and / or the radius of the circle surrounding the PCB pins until the packaging requirements are met, and obtain the verified packaging simulation solution.

[0086] Reference Fig.10Based on the verified packaging simulation scheme, the IC to be packaged is packaged. The substrate pad is designed according to the Substrate Area3500um*3700um in the IC data to be packaged, and is placed in the center of the original IC to be packaged. The original IC pins to be packaged and the corresponding analog bonding wires are deleted; the bonding diagram is drawn with the silk screen layer. Because the original chip area is very small, it is generally necessary to expand the silk screen of the bonding IC area outward to better show it to the bonding staff. The 70 pin numbers actually used in the PCB are adjusted to the corresponding bonding pad numbers, and the remaining 12 dummy pin numbers that are not used are all set to 00. Two crosses are added as bonding reference coordinates. The position of the cross can be placed at a suitable position on the extension line of the diagonal of the exposed copper substrate.

[0087] Among them, A is the silk-screen area around the IC package to be packaged, and the sealing black glue is within this range; B is the pin for PCB bonding; C is the exposed copper substrate where the IC to be packaged is placed; D is a schematic diagram of the bonding wire; E is a virtual PCB pin; F is two cross exposed copper, which serve as bonding reference coordinates.

[0088] The embodiment of the present invention provides a bare chip IC packaging method, including: obtaining parameter information of the IC to be packaged; the parameter information includes the size of the IC to be packaged and the corresponding bonding pressure welding point position; determining the packaging simulation scheme of the IC to be packaged according to the parameter information of the IC to be packaged; the packaging simulation scheme includes the bonding pressure welding points of the IC to be packaged and the bonding wire simulation scheme of the corresponding PCB pins; verifying and adjusting the packaging simulation scheme based on preset packaging requirements until the packaging requirements are met to obtain a verified packaging simulation scheme; packaging the IC to be packaged based on the verified packaging simulation scheme. By performing the bonding simulation verification method in advance according to the actual size of the bare chip IC, the PCB packaging scheme design has a basis, a demonstration, and a clever method, which can better meet the bonding requirements.

[0089] Embodiment three:

[0090] Fig.11 This is a module diagram of a bare chip IC packaging system provided in Embodiment 3 of the present invention.

[0091] Reference Fig.11 , the packaging system of bare chip IC includes:

[0092] Parameter information acquisition module 1, used to acquire parameter information of the IC to be packaged; the parameter information includes the size of the IC to be packaged and the corresponding bonding solder joint position;

[0093] The packaging simulation scheme determination module 2 is used to determine the packaging simulation scheme of the IC to be packaged according to the parameter information of the IC to be packaged; the packaging simulation scheme includes the bonding solder joints of the IC to be packaged and the bonding wire simulation scheme of the corresponding PCB pins;

[0094] The packaging simulation scheme verification and adjustment module 3 is used to verify and adjust the packaging simulation scheme based on the preset packaging requirements until the packaging requirements are met to obtain a verified packaging simulation scheme;

[0095] The packaging module 4 is used to package the IC to be packaged based on the verified packaging simulation solution.

[0096] The embodiment of the present invention provides a bare chip IC packaging system, including: obtaining parameter information of the IC to be packaged; the parameter information includes the size of the IC to be packaged and the corresponding bonding solder joint position; determining the packaging simulation scheme of the IC to be packaged according to the parameter information of the IC to be packaged; the packaging simulation scheme includes the bonding solder joints of the IC to be packaged and the bonding wire simulation scheme of the corresponding PCB pins; verifying and adjusting the packaging simulation scheme based on preset packaging requirements until the packaging requirements are met to obtain a verified packaging simulation scheme; packaging the IC to be packaged based on the verified packaging simulation scheme. In this embodiment, before packaging the bare chip IC to be packaged, the bonding solder joints of the IC to be packaged and the bonding wire simulation scheme of the corresponding PCB pins are pre-designed, and when the verification simulation scheme meets the packaging requirements, formal packaging is performed, which can reduce the risk of packaging revision and alleviate the problem of extended project development cycle caused by design revision.

[0097] An embodiment of the present invention further provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the steps of the bare chip IC packaging method provided in the above embodiment are implemented.

[0098] The computer program product provided in the embodiment of the present invention includes a computer-readable storage medium storing program code. The instructions included in the program code can be used to execute the method described in the previous method embodiment. The specific implementation can be found in the method embodiment and will not be repeated here.

[0099] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system and device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0100] In addition, in the description of the embodiments of the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0101] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc., which can store program codes.

[0102] In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.

[0103] Finally, it should be noted that the above-described embodiments are only specific implementations of the present invention, which are used to illustrate the technical solutions of the present invention, rather than to limit them. The protection scope of the present invention is not limited thereto. Although the present invention is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed by the present invention, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be based on the protection scope of the claims.

Claims

1. A bare chip IC packaging method, characterized in that: include: Get parameter information of the IC to be packaged; The parameter information includes the size of the IC to be packaged and the corresponding bonding solder joint position; Determining a packaging simulation scheme for the IC to be packaged according to parameter information of the IC to be packaged; The packaging simulation scheme includes a bonding simulation scheme of the bonding points of the IC to be packaged and the corresponding PCB pins; Verifying and adjusting the packaging simulation solution based on preset packaging requirements until the packaging requirements are met, thereby obtaining a verified packaging simulation solution; Packaging the IC to be packaged based on the verified packaging simulation solution; The step of determining a packaging simulation scheme of the IC to be packaged according to the parameter information of the IC to be packaged comprises: According to the positions of the bonding pressure welding points, the minimum angles of the bonding wires corresponding to the adjacent bonding pressure welding points are calculated; The number of PCB pins required for the PCB pin surrounding circle is calculated according to the minimum angle, and the average angle of the bonding wires corresponding to the adjacent bonding solder joints is calculated; wherein the PCB pin surrounding circle is formed by the PCB pins being evenly surrounded with the physical center of the IC to be packaged as the center; Determine the position of the reference pin of the circle surrounding the PCB pin, and calculate the surrounding radius of the circle surrounding the PCB pin according to the position of the reference pin; Determine a wire bonding simulation scheme for the PCB pins according to the number of the PCB pins, the average angle and the surrounding radius; The step of determining the position of the reference pin of the PCB pin surrounding circle and calculating the surrounding radius of the PCB pin surrounding circle according to the position of the reference pin comprises: The bonding solder joint with the largest number of bonding solder joints and whose abscissa and / or ordinate is 0 is determined as the reference pin; Determine the distance from the midpoint of the reference pin to the midpoint of the IC to be packaged as the surrounding radius of the PCB pin surrounding circle; According to the number of the PCB pins, the PCB pins are evenly arranged around the physical center of the IC to be packaged; wherein a preset pin safety distance is maintained between adjacent PCB pins; Draw an inner circle with the distance from the center of the circle to the inner edge of each reference pin as the radius; The radius of the circle surrounding the PCB pin is calculated according to the following formula: Where r is the radius of the circle around the PCB pin, r 内 is the radius of the inner circle, w 引 is the width of the PCB pin, l 引 is the length of the PCB pin, l 预 is the preset pin safety distance, and n is the number of PCB pins.

2. The method according to claim 1, characterized in that The step of calculating the minimum angle between bonding wires corresponding to adjacent bonding welding points according to the bonding welding point positions comprises: According to the bonding soldering point positions, one bonding soldering point is selected in a clockwise direction on each side of the IC to be packaged as a first soldering point, and one bonding soldering point is selected in a counterclockwise direction on each side of the IC to be packaged as a second soldering point; Drawing leads from the center of the circle to the first bonding point and the second bonding point respectively to form a corresponding angle of each side; wherein the first bonding point is not adjacent to the second bonding point; Calculate the total number of bonding points between the first bonding point and the second bonding point, and calculate the angle of the bonding wires corresponding to the adjacent bonding bonding points on each side according to the corresponding angle of each side and the bonding points; The smallest angle among the angles between the bonding wires corresponding to the adjacent bonding pressure welding points on each side is determined as the smallest angle.

3. The method according to claim 1, characterized in that The step of calculating the number of PCB pins required for the PCB pins to surround the circle according to the minimum angle, and calculating the average angle of the bonding wires corresponding to the adjacent bonding solder joints includes: Calculate the number of PCB pins required for the PCB pins to surround the circle according to the minimum included angle and the circumference angle; According to the number of the PCB pins, the average angle of the bonding wires corresponding to the adjacent bonding solder joints is calculated.

4. The method according to claim 1, characterized in that: The preset packaging requirements include: The distance between adjacent bonding wires meets the preset bonding wire distance; and / or The distance between each bonding wire and the corresponding bonding pressure welding point meets the preset spacing; and / or The distance between the inner edges of adjacent PCB pins meets the preset pin safety distance.

5. The method according to claim 1, characterized in that The step of verifying and adjusting the packaging simulation solution based on the preset packaging requirements until the packaging requirements are met to obtain the verified packaging simulation solution includes: The packaging simulation scheme is verified based on preset packaging requirements. If the packaging simulation scheme does not meet the packaging requirements, the number of PCB pins and / or the radius of the circle surrounding the PCB pins are adjusted until the packaging requirements are met, thereby obtaining a verified packaging simulation scheme.

6. A bare chip IC packaging system, characterized in that: include: A parameter information acquisition module, used to acquire parameter information of the IC to be packaged; The parameter information includes the size of the IC to be packaged and the corresponding bonding solder joint position; A packaging simulation scheme determination module, used to determine the packaging simulation scheme of the IC to be packaged according to the parameter information of the IC to be packaged; the packaging simulation scheme includes the bonding solder joints of the IC to be packaged and the bonding wire simulation scheme of the corresponding PCB pins; A packaging simulation scheme verification and adjustment module, used to verify and adjust the packaging simulation scheme based on preset packaging requirements until the packaging requirements are met to obtain a verified packaging simulation scheme; A packaging module, used for packaging the IC to be packaged based on the verified packaging simulation scheme; The package simulation scheme determination module is also used to calculate the minimum angle of the bonding wires corresponding to adjacent bonding solder joints according to the positions of the bonding solder joints; calculate the number of PCB pins required for the PCB pin surrounding circle according to the minimum angle, and calculate the average angle of the bonding wires corresponding to the adjacent bonding solder joints; wherein the PCB pin surrounding circle is formed by the PCB pins surrounding the physical center of the IC to be packaged as the center of the circle in a balanced manner; determine the position of the reference pin of the PCB pin surrounding circle, and calculate the surrounding radius of the PCB pin surrounding circle according to the position of the reference pin; determine the bonding wire simulation scheme of the PCB pin according to the number of PCB pins, the average angle and the surrounding radius; The packaging simulation scheme determination module is further used to determine the bonding solder joints with the largest number of bonding solder joints and whose horizontal coordinates and / or vertical coordinates are 0 as reference pins; determine the distance from the midpoint of the reference pin to the midpoint of the IC to be packaged as the surrounding radius of the circle surrounding the PCB pins; according to the number of PCB pins, arrange the PCB pins in a balanced surrounding manner with the physical center of the IC to be packaged as the center of the circle; wherein a preset pin safety distance is maintained between adjacent PCB pins; draw an inner circle with the distance from the center of the circle to the inner edge of each reference pin as the radius; and calculate the surrounding radius of the circle surrounding the PCB pins according to the following formula: Where r is the radius of the circle around the PCB pin, r 内 is the radius of the inner circle, w 引 is the width of the PCB pin, l 引 is the length of the PCB pin, l 预 is the preset pin safety distance, and n is the number of PCB pins.

7. An electronic device comprising a memory and a processor, wherein the memory stores a computer program that can be run on the processor, characterized in that: When the processor executes the computer program, the method according to any one of claims 1 to 5 is implemented.

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