A storage device, authentication method, and memory system

Abstract

The application discloses a storage device, a verification method and a memory system. The storage device comprises: a storage unit array, storage units in the storage unit array are arranged in rows and columns; a sensing circuit coupled to the storage unit array, the sensing circuit comprises a first sensing circuit, a second sensing circuit and a third sensing circuit coupled to a sensing node; a control logic coupled to the storage unit array and the sensing circuit, the control logic is configured to pre-charge the sensing node to a predetermined initial voltage, and change a sensing time point to make the sensing node present at least three different potentials; the first sensing circuit, the second sensing circuit and the third sensing circuit respectively sense first verification information, second verification information and third verification information according to at least three different potentials of the sensing node.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a storage device, verification method, and memory system. Background Technology

[0002] Currently, NAND flash memory is typically programmed using Incremental Stepped Pulse Programming (ISPP). This involves sequentially programming the memory cells using multiple progressively increasing pulse programming voltages. Each programming operation can include a programming operation followed by a verification operation. During the programming process, a verification voltage is used to verify the memory cells after each programming operation.

[0003] However, in the current verification operation, memory cells belonging to different programming levels or states need to be verified using different verification voltages. The verification process is cumbersome, resulting in excessive verification time and affecting programming efficiency. Summary of the Invention

[0004] This application aims to provide a storage device, a verification method, and a memory system.

[0005] The technical solution of this application is implemented as follows:

[0006] A first aspect of this application provides a storage device, the storage device comprising:

[0007] A storage cell array, wherein the storage cells in the storage cell array are arranged in rows and columns;

[0008] A sensing circuit coupled to the memory cell array, the sensing circuit including a first sensing circuit, a second sensing circuit and a third sensing circuit coupled to a sensing node;

[0009] Control logic coupled to the memory cell array and the sensing circuit is configured to precharge the sensing node to a predetermined initial voltage and change the sensing time point so that the sensing node presents at least three different potentials; the first sensing circuit, the second sensing circuit and the third sensing circuit respectively sense first verification information, second verification information and third verification information based on the at least three different potentials of the sensing node;

[0010] Wherein, the potential of the sensing node corresponding to the first verification information is greater than the potential of the sensing node corresponding to the third verification information, and the potential of the sensing node corresponding to the second verification information is greater than the potential of the sensing node corresponding to the third verification information.

[0011] Optionally, the potential of the sensing node corresponding to the first verification information is greater than the potential of the sensing node corresponding to the second verification information;

[0012] After obtaining the first verification information, the control logic is further configured to recharge the sensing node to a predetermined initial voltage and change the sensing time point so that the sensing node presents at least two different potentials; the second sensing circuit and the third sensing circuit respectively sense the second verification information and the third verification information based on the at least two different potentials of the sensing node.

[0013] Optionally, the potential of the sensing node corresponding to the first verification information is greater than the potential of the sensing node corresponding to the second verification information;

[0014] After obtaining the second verification information, the control logic is further configured to recharge the sensing node to a predetermined initial voltage and change the sensing time point so that the sensing node presents at least two different potentials; the first sensing circuit and the third sensing circuit respectively sense the first verification information and the third verification information based on the at least two different potentials of the sensing node.

[0015] Optionally, the control logic is specifically configured to precharge the sensing node to a predetermined initial voltage, then discharge the sensing node, and change the sensing time point during the discharge of the sensing node so that the sensing node presents at least three different potentials.

[0016] Wherein, the potential of the sensing node corresponding to the first verification information is the first sensing potential; the potential of the sensing node corresponding to the second verification information is the second sensing potential; and the potential of the sensing node corresponding to the third verification information is the third sensing potential.

[0017] Optionally, the control logic is further configured to: compare the first sensed potential with a first preset voltage to obtain first verification information;

[0018] Wherein, if the first sensing potential is greater than or equal to the first preset voltage, the first verification information is used to indicate the first storage unit that has passed the verification of the first verification voltage.

[0019] Optionally, the control logic is further configured to: compare the second sensed potential with a second preset voltage to obtain second verification information;

[0020] If the second sensing potential is greater than or equal to the second preset voltage, the second verification information is used to indicate the second storage unit that has passed the verification of the second verification voltage.

[0021] Optionally, the control logic is further configured to: compare the third sensing potential with a third preset voltage to obtain third verification information;

[0022] If the third sensing potential is greater than or equal to the third preset voltage, the third verification information is used to indicate the third storage unit that has passed the verification of the third verification voltage.

[0023] Optionally, the first verification voltage is less than the second verification voltage, and the second verification voltage is less than the third verification voltage.

[0024] Optionally, the control logic is further configured to: apply a first bit line voltage to the first bit line connected to the first forcing unit, apply a second bit line voltage to the second bit line connected to the second forcing unit, apply a programmable disable bit line voltage to the third bit line connected to the third memory unit, and apply a programming voltage to the selected word line, based on the first verification information, the second verification information, and the third verification information; wherein the first bit line voltage is greater than the ground voltage and less than the programmable disable bit line voltage, and the second bit line voltage is greater than the first bit line voltage.

[0025] Optionally, the first forcing unit is a storage unit in the first storage unit other than the second storage unit and the third storage unit;

[0026] The second forced unit is a storage unit in the second storage unit other than the third storage unit.

[0027] Optionally, the first sensing circuit includes a first latch for storing the first verification information; the second sensing circuit includes a second latch for storing the second verification information; and the third sensing circuit includes a third latch for storing the third verification information.

[0028] A second aspect of this application provides a verification method, including:

[0029] Precharge the sensing nodes to a predetermined initial voltage;

[0030] The sensing time point is changed so that the sensing node presents at least three different potentials;

[0031] The first sensing circuit, the second sensing circuit, and the third sensing circuit are controlled to obtain first verification information, second verification information, and third verification information respectively based on at least three different potentials of the sensing node;

[0032] Wherein, the potential of the sensing node corresponding to the first verification information is greater than the potential of the sensing node corresponding to the third verification information, and the potential of the sensing node corresponding to the second verification information is greater than the potential of the sensing node corresponding to the third verification information.

[0033] Optionally, the potential of the sensing node corresponding to the first verification information is greater than the potential of the sensing node corresponding to the second verification information; the control of the first sensing circuit, the second sensing circuit, and the third sensing circuit to sense the first verification information, the second verification information, and the third verification information based on at least three different potentials of the sensing node includes:

[0034] After obtaining the first verification information, the sensing node is recharged to a predetermined initial voltage, and the sensing time point is changed so that the sensing node presents at least two different potentials; the second sensing circuit and the third sensing circuit respectively sense the second verification information and the third verification information based on the at least two different potentials of the sensing node.

[0035] Optionally, the potential of the sensing node corresponding to the first verification information is greater than the potential of the sensing node corresponding to the second verification information; the control of the first sensing circuit, the second sensing circuit, and the third sensing circuit to sense the first verification information, the second verification information, and the third verification information based on at least three different potentials of the sensing node includes:

[0036] After obtaining the second verification information, the sensing node is recharged to a predetermined initial voltage, and the sensing time point is changed so that the sensing node presents at least two different potentials; the first sensing circuit and the third sensing circuit respectively sense the first verification information and the third verification information based on the at least two different potentials of the sensing node.

[0037] Optionally, changing the sensing time point to make the sensing node present at least three different potentials includes:

[0038] After precharging the sensing node to a predetermined initial voltage, the sensing node is discharged, and the sensing time point is changed during the discharge of the sensing node so that the sensing node presents at least three different potentials.

[0039] Wherein, the potential of the sensing node corresponding to the first verification information is the first sensing potential; the potential of the sensing node corresponding to the second verification information is the second sensing potential; and the potential of the sensing node corresponding to the third verification information is the third sensing potential.

[0040] Optionally, the control of the first sensing circuit, the second sensing circuit, and the third sensing circuit obtains first verification information, second verification information, and third verification information respectively based on at least three different potentials of the sensing node, including:

[0041] The first sensed potential is compared with the first preset voltage to obtain the first verification information;

[0042] Wherein, if the first sensing potential is greater than or equal to the first preset voltage, the first verification information is used to indicate the first storage unit that has passed the verification of the first verification voltage.

[0043] Optionally, the control of the first sensing circuit, the second sensing circuit, and the third sensing circuit to obtain first verification information, second verification information, and third verification information respectively based on at least three different potentials of the sensing node further includes:

[0044] The second sensed potential is compared with the second preset voltage to obtain the second verification information;

[0045] If the second sensing potential is greater than or equal to the second preset voltage, the second verification information is used to indicate the second storage unit that has passed the verification of the second verification voltage.

[0046] Optionally, the control of the first sensing circuit, the second sensing circuit, and the third sensing circuit to obtain first verification information, second verification information, and third verification information respectively based on at least three different potentials of the sensing node further includes:

[0047] The third sensing potential is compared with the third preset voltage to obtain the third verification information;

[0048] If the third sensing potential is greater than or equal to the third preset voltage, the third verification information is used to indicate the third storage unit that has passed the verification of the third verification voltage.

[0049] Optionally, the first verification voltage is less than the second verification voltage, and the second verification voltage is less than the third verification voltage.

[0050] Optionally, based on the first verification information, the second verification information, and the third verification information, a first bit line voltage is applied to the first bit line connected to the first forced cell, a second bit line voltage is applied to the second bit line connected to the second forced cell, a programmable inhibit bit line voltage is applied to the third bit line connected to the third memory cell, and a programming voltage is applied to the selected word line; wherein, the first bit line voltage is greater than the ground voltage and less than the programmable inhibit bit line voltage, and the second bit line voltage is greater than the first bit line voltage.

[0051] Optionally, the first forcing unit is a storage unit in the first storage unit other than the second storage unit and the third storage unit;

[0052] The second forced unit is a storage unit in the second storage unit other than the third storage unit.

[0053] Optionally, the method further includes: storing the first verification information into a first latch in the first sensing circuit;

[0054] The second verification information is stored in the second latch of the second sensing circuit;

[0055] The third verification information is stored in the third latch in the third sensing circuit.

[0056] A third aspect of this application provides a memory system, including:

[0057] The controller and the storage device described in the first aspect; the controller is coupled to the storage device and is used to control the storage device.

[0058] This application discloses a storage device, verification method, and memory system. The storage device includes: a storage cell array, where storage cells are arranged in rows and columns; a sensing circuit coupled to the storage cell array, including a first sensing circuit, a second sensing circuit, and a third sensing circuit coupled to a sensing node; and control logic coupled to the storage cell array and the sensing circuit, configured to precharge the sensing node to a predetermined initial voltage and change the sensing time point to make the sensing node present at least three different potentials; the first sensing circuit, the second sensing circuit, and the third sensing circuit respectively sense first verification information, second verification information, and third verification information based on the at least three different potentials of the sensing node. This application embodiment reduces the number of times the sensing node needs to be charged during the sensing process by precharging the sensing node to a predetermined initial voltage and then discharging it, thereby completing the sensing of different potentials and saving verification time. Attached Figure Description

[0059] Figure 1 This is a schematic diagram of the structure of a storage device provided in an embodiment of this application;

[0060] Figure 2 A circuit diagram of a sensing circuit provided for an embodiment of this application;

[0061] Figure 3 Voltage timing of a sensing node provided as a specific example of this application Figure 1 ;

[0062] Figure 4 Voltage timing of a sensing node provided as a specific example of this application Figure 2 ;

[0063] Figure 5 Voltage timing of a sensing node provided as a specific example of this application Figure 3 ;

[0064] Figure 6 Threshold voltage distribution diagram of the memory cell provided in the embodiments of this application;

[0065] Figure 7 A flowchart illustrating a verification method provided in an embodiment of this application;

[0066] Figure 8 This is a block diagram of a memory system according to an exemplary embodiment of this application;

[0067] Figure 9A This is a schematic diagram illustrating a memory card according to an exemplary embodiment of this application;

[0068] Figure 9B This is a schematic diagram of a solid-state drive (SSD) according to an exemplary embodiment of this application. Detailed Implementation

[0069] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0070] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this application. However, it will be apparent to those skilled in the art that this application can be practiced without one or more of these details. In other instances, to avoid confusion with this application, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0071] Furthermore, the accompanying drawings are merely illustrative of this application and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0072] The flowchart shown in the attached diagram is merely an illustrative example and does not necessarily include all steps. For example, some steps may be broken down, while others may be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0073] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0074] In this embodiment, the storage device includes a storage cell array. The storage cells in the array are arranged in rows and columns. Each storage cell can be a Single-Level Cell (SLC), Multi-Level Cell (MLC), Trinary-Level Cell (TLC), Quad-Level Cell (QLC), Penta-Level Cell (PLC), or a higher level type. Each SLC cell can store 1 bit of data, each MLC cell can store 2 bits of data, each TLC cell can store 3 bits of data, each QLC cell can store 4 bits of data, and each PLC cell can store 5 bits of data. Each storage cell can hold one of Q possible data states, where Q is a positive integer equal to or greater than 2. For example, for SLC, Q = 2; for MLC, Q = 4; for TLC, Q = 8; for QLC, Q = 16; and for PLC, Q = 32. The Q possible data states can include an erase state S(0) and programming states S(1) to S(Q-1), where programming state S(1) is the lowest programming state and programming state S(Q-1) is the highest programming state. In one example, the TLC can be programmed into one of eight possible data states, where programming state S(1) is the lowest programming state and programming state S(7) is the highest programming state.

[0075] In the programming verification operation of a memory device, each programming state corresponds to a verification voltage. When verifying at least one memory cell in the same programming state, the corresponding verification voltage is applied to the selected word line WL. Based on the verification voltage and the predetermined voltage of the memory cell in that programming state, it is determined whether the memory cell passes the verification. Considering that the predetermined voltages corresponding to different programming states are different, multiple verification processes are required. Typically, the memory cell needs to be charged to a higher potential and then discharged multiple times. The voltage at the sensing node (SO) of the memory cell at different stages is detected by the sensing circuit. The sensing results can be used to complete the verification of the memory cell. The verification results can be stored in the latch of the page cache to determine the programming result of the memory cell.

[0076] After the memory cell completes its programming operation, a corresponding verification operation is required. This verification operation includes a SO discharge process, where the charge accumulated at the sensing node SO is discharged through the bit line BL and the channel. If the total discharge during the predetermined discharge period is sufficient to cause a significant voltage drop at the sensing node SO, the threshold voltage of the corresponding memory cell is considered to be lower than the verification voltage. This indicates that the memory cell has failed verification and needs to be reprogrammed and verified. Conversely, if the total discharge during the predetermined discharge period is small, meaning the remaining charge or voltage after discharge is higher than the predetermined voltage, the memory cell has passed verification and is restricted from programming in the next programming cycle. However, in the current verification operation, memory cells in different programming states require different verification voltages for verification. Furthermore, the discharge process at the memory cell's SO node involves multiple charging operations, making the verification process cumbersome and time-consuming, thus affecting programming efficiency.

[0077] Based on this, this application provides a storage device. Please refer to [link / reference]. Figure 1 , Figure 1 This is a schematic diagram of a storage device provided in an embodiment of this application. The storage device includes:

[0078] Storage cell array 110, wherein the storage cells in storage cell array 110 are arranged in rows and columns;

[0079] The sensing circuit 120 is coupled to the memory cell array 110. The sensing circuit 120 includes a first sensing circuit 121, a second sensing circuit 122 and a third sensing circuit 123 coupled to the sensing node SO.

[0080] Control logic 140, coupled to memory cell array 110 and sensing circuit 120, is configured to precharge sensing nodes to a predetermined initial voltage and change sensing time points to make sensing nodes present at least three different potentials; first sensing circuit 121, second sensing circuit 122 and third sensing circuit 123 respectively sense first verification information, second verification information and third verification information based on at least three different potentials of sensing nodes;

[0081] Among them, the potential of the sensing node corresponding to the first verification information is greater than the potential of the sensing node corresponding to the third verification information, and the potential of the sensing node corresponding to the second verification information is greater than the potential of the sensing node corresponding to the third verification information.

[0082] Here, the control logic 140 is connected to the memory cell array 110 through the sensing circuit 120 and the row decoder 130. The sensing circuit 120, the row decoder 130, and the control logic 140 can be implemented in the peripheral circuitry of the memory device.

[0083] In this embodiment, the memory cell array 110 can be connected to the line decoder 130 via word lines WL0 to WLn-1, cell string select line SSL, and ground select line GSL. The memory cell array 110 can also be connected to the sensing circuit 120 via bit lines BL0 to BLm-1. The memory cell array 120 can include multiple memory cell strings. Each memory cell string can be connected to the bit lines via a cell string select transistor SST. The memory cell array 110 can be formed from a memory plane including multiple memory blocks, each memory block including multiple memory pages, and each memory page including multiple memory cells. Furthermore, although the storage device is shown as a flash memory device as an example, it is understood that this application is not limited to flash memory devices and can be applied to any type of non-volatile memory, such as read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), erasable programmable read-only memory (EEPROM), NAND flash memory, vertical NAND flash memory, NOR flash memory, phase-change random access memory (PRAM), magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), ferroelectric random access memory (FRAM), etc.

[0084] The sensing circuit 120 can be used as a write driver or a sensing amplifier depending on the operating mode. During programming operations, the sensing circuit 120 can transmit a bit line voltage corresponding to the memory cell to be programmed to the bit lines of the memory cell array 110. During read operations, the sensing circuit 120 can sense the data stored in the selected memory cell through the sensing node. The sensing circuit 120 can latch verification data and output verification data.

[0085] For example, the first sensing circuit may include a first latch for storing first verification information; the second sensing circuit may include a second latch for storing second verification information; and the third sensing circuit may include a third latch for storing third verification information.

[0086] The row decoder 130 can select any one of the memory blocks in the memory cell array 110 in response to address ADDR. The row decoder 130 can select any one word line from the word lines of the selected memory block. The row decoder 130 can transmit word line voltage to the word lines of the selected memory block.

[0087] Control logic 140 can receive programming command CMD and output various control signals for controlling sensing circuit 120 and line decoder 130 to perform programming operations in response to programming command CMD. Additionally, control logic 140 is configured to pre-charge sensing node SO to a predetermined initial voltage, then discharge sensing node SO, changing the sensing time point during the discharge of sensing node SO to make sensing node SO present at least three different potentials, and comparing these at least three different potentials with different preset voltages to obtain first verification information, second verification information, and third verification information. Wherein, the potential of the sensing node corresponding to the first verification information is the first sensing potential; the potential of the sensing node corresponding to the second verification information is the second sensing potential; and the potential of the sensing node corresponding to the third verification information is the third sensing potential.

[0088] Figure 2 The circuit diagram of the sensing circuit provided in the embodiment of this application is shown. The sensing circuit 120 includes a first sensing circuit, a second sensing circuit and a third sensing circuit. The first sensing circuit includes a first latch 1211 for storing first verification information, the second sensing circuit includes a second latch 1221 for storing second verification information, and the third sensing circuit includes a third latch 1231 for storing third verification information.

[0089] In a specific example, the first latch 1211 and the second latch 1221 can store information about bit-line forcing operations. This information corresponds to different bit-line voltages that need to be applied to the corresponding bit lines during programming, controlled by the programming command CMD. In this embodiment, four different bit-line voltages can be latched during programming using the first latch 1211 and the second latch 1221. Later, reference will be made to... Figure 6 The following describes its detailed specifications.

[0090] In this embodiment, the sensing circuit further includes: a first precharge path 124 for generating a first bit line voltage; the first precharge path 124 is connected to the bit line via a sensing node SO; the first precharge path 124 is configured to apply a first bit line voltage greater than ground voltage and less than the programmable bit line voltage to the first bit line connected to the first forcing unit. It should be noted that the first precharge path 124 is also configured to apply a programmable bit line voltage to the third bit line connected to the third memory cell. Here, the third memory cell is the programmable memory cell.

[0091] In this embodiment of the application, the sensing circuit further includes: a second pre-charge path 125 for generating a second bit line voltage, the second pre-charge path 125 being connected to the bit line through a sensing node SO; the second pre-charge path 125 is configured to apply a second bit line voltage greater than the first bit line voltage to the second bit line connected to the second forcing unit.

[0092] It should be noted that the bit lines in the memory cell array are connected to the sensing node, the first precharge circuit, and the second precharge circuit via transistors. By applying a bias signal to the transistor, such as VPASS-HV, VBLBIAS, or VBLBIAS2, the bit lines can be connected to the sensing node, the first precharge circuit, and the second precharge circuit, thereby programming and verifying the corresponding memory cells.

[0093] Figure 3 Voltage timing of a sensing node provided as a specific example of this application Figure 1 , refer to Figure 3The control logic is configured to precharge the sensing node to a predetermined initial voltage by applying a precharge signal Prech-sel, and to discharge and stop discharging the sensing node SO by a control signal Vsoblk. When the control signal Vsoblk is high, the sensing node SO discharges; when the control signal Vsoblk is low, the sensing node SO stops discharging. At time t1, the sensing node SO is charged by applying the precharge signal Prech-sel to bring it to a predetermined initial voltage. At time t2, the sensing node SO is discharged. After a first predetermined sensing time, the first latch, by setting the signal Rst_2 = 1, senses the first verification information based on the first sensing potential of the sensing node SO. At time t3, the sensing node SO is charged again by applying the precharge signal Prech-sel to bring it to the predetermined initial voltage again. At time t4, the sensing node SO is discharged. After a second predetermined sensing time, the second latch, by setting the signal Rst_3 = 1, senses the second verification information based on the second sensing potential of the sensing node SO. At time t5, the sensing node SO is discharged again. After a third predetermined sensing time, the third latch, by setting the signal Set_s = 1, senses the third verification information based on the third sensing potential of the sensing node SO. Here, the first sensing potential is greater than the second sensing potential, and the second sensing potential is greater than the third sensing potential. It should be noted that the first predetermined sensing time, the second predetermined sensing time, and the third predetermined sensing time correspond to different sensing time points.

[0094] In some embodiments, refer again Figure 3 The potential of the sensing node corresponding to the first verification information is greater than the potential of the sensing node corresponding to the second verification information. After obtaining the first verification information, the control logic is further configured to recharge the sensing node to a predetermined initial voltage and change the sensing time point so that the sensing node presents at least two different potentials. The second sensing circuit and the third sensing circuit respectively sense the second verification information and the third verification information based on the at least two different potentials of the sensing node.

[0095] In this embodiment, obtaining the first verification information includes: comparing a first sensing potential with a first preset voltage to obtain the first verification information; wherein, if the first sensing potential is greater than or equal to the first preset voltage, the first verification information is used to indicate a first memory cell that has passed the verification of the first verification voltage; conversely, if the first sensing potential is less than the first preset voltage, the first verification information is used to indicate a memory cell that has not passed the verification of the first verification voltage. Here, the first verification voltage is a voltage used to distinguish the programming state of the memory cell.

[0096] The sensing node is pre-charged to a predetermined initial voltage. After discharging for a first predetermined sensing time, the voltage at the sensing node is lower than the predetermined initial voltage. After obtaining first verification information, the sensing node is recharged to the predetermined initial voltage. After discharging for a second predetermined sensing time, second verification information is obtained. Here, the first predetermined sensing time and the second predetermined sensing time are different. In some embodiments, the first predetermined sensing time is shorter than the second predetermined sensing time.

[0097] The embodiments of this application charge the sensing node at the initial moment and after the first sensing, requiring only two charging operations to complete at least three verification operations, reducing the number of times the sensing node needs to be charged during the sensing process and saving verification time.

[0098] In some embodiments, please refer to Figure 4 , Figure 4 Voltage timing of a sensing node provided as a specific example of this application Figure 2 The potential of the sensing node corresponding to the first verification information is greater than the potential of the sensing node corresponding to the second verification information. After obtaining the second verification information, the control logic is further configured to recharge the sensing node to a predetermined initial voltage and change the sensing time point so that the sensing node presents at least two different potentials. The first sensing circuit and the third sensing circuit respectively sense the first verification information and the third verification information based on the at least two different potentials of the sensing node.

[0099] In this embodiment, obtaining the second verification information includes: comparing a second sensing potential with a second preset voltage to obtain the second verification information; wherein, if the second sensing potential is greater than or equal to the second preset voltage, the second verification information is used to indicate a second memory cell that has passed the verification of the second verification voltage; conversely, if the second sensing potential is less than the second preset voltage, the second verification information is used to indicate a memory cell that has not passed the verification of the second verification voltage. Here, the second verification voltage is a voltage used to distinguish the programming state of the memory cell.

[0100] Please refer to Figure 4The sensing node SO is precharged to a predetermined initial voltage by applying a precharge signal Prech-sel, and discharged and stopped by a control signal Vsoblk. At time t1, the sensing node SO is charged by applying the precharge signal Prech-sel to reach the predetermined initial voltage, and discharged at time t2. After a second predetermined sensing time, the second latch can sense the second verification information based on the second sensing potential of the sensing node SO by signal Rst_3=1. At time t3, the sensing node SO is charged again by applying the precharge signal Prech-sel to reach the predetermined initial voltage again, and discharged at time t4. After a first predetermined sensing time, the first latch can sense the first verification information based on the first sensing potential of the sensing node SO by signal Rst_2=1. At time t5, the sensing node SO is discharged again. After a fourth predetermined sensing time, the third latch can sense the third verification information based on the third sensing potential of the sensing node SO by signal Set_s=1. Here, the first sensing potential is greater than the second sensing potential, and the second sensing potential is greater than the third sensing potential. It should be noted that the first predetermined sensing time, the second predetermined sensing time, and the fourth predetermined sensing time correspond to different sensing time points.

[0101] In this embodiment, at least three verification operations can be completed with only two charging operations, which reduces the number of times the sensing node needs to be charged during the sensing process, saves verification time, and the potential change is more significant when discharging from the first sensing potential with a large potential difference to the third sensing potential, thus increasing the accuracy of sensing.

[0102] In some embodiments, please refer to Figure 5 , Figure 5 Voltage timing of a sensing node provided as a specific example of this application Figure 3 The potential of the sensing node corresponding to the first verification information is greater than the potential of the sensing node corresponding to the second verification information. After obtaining the first verification information, the control logic is also configured to change the sensing time point so that the sensing node presents at least two different potentials. The second sensing circuit and the third sensing circuit respectively sense the second verification information and the third verification information based on the at least two different potentials of the sensing node.

[0103] In this embodiment, the sensing node is pre-charged to a predetermined initial voltage by applying a pre-charge signal Prech-sel, and the sensing node SO is discharged and stopped by the control signal Vsoblk. At time t1, the sensing node SO is charged by applying the pre-charge signal Prech-sel to bring it to the predetermined initial voltage. At time t2, the sensing node SO is discharged. After a first predetermined sensing time, the first latch stores the first verification information sensed based on the first sensing potential of the sensing node SO by signal Rst_2 = 1. At time t3, the sensing node SO is discharged again. After a fifth predetermined sensing time, the second latch senses the second verification information based on the second sensing potential of the sensing node SO by signal Rst_3 = 1. At time t4, the sensing node SO is discharged again. After a third predetermined sensing time, the third latch senses the third verification information based on the third sensing potential of the sensing node SO by signal Set_s = 1. Here, the first sensing potential is greater than the second sensing potential, and the second sensing potential is greater than the third sensing potential. It should be noted that the first predetermined sensing time, the fifth predetermined sensing time, and the third predetermined sensing time correspond to different sensing time points.

[0104] It should be noted that, Figures 3-5 The example used is changing the sensing time point to make the sensing node present three different potentials.

[0105] The embodiments of this application charge the sensing node at the initial moment, requiring only one charging operation to complete at least three verification operations on the sensing node, reducing the number of times the sensing node needs to be charged during the sensing process, saving verification time, and thus improving programming efficiency.

[0106] In this embodiment, taking the ISPP (Incremental Step-Pulse Programming) programming scheme of a 3D NAND flash memory storage device as an example, in different programming stages of an ISPP programming process, in order to optimize the threshold voltage distribution and make the threshold voltage of the memory cell more concentrated in the threshold voltage region of the corresponding data state, different bit line voltages are biased on the bit lines of memory cells of different bit lines, that is, bit line forcing operation is implemented. In this way, even if the programming voltage Vpgm of the gate (applied through the word line) of the memory cells of different bit lines is the same, the programming effect will be different. The memory cells with large current threshold voltage differences will have their threshold voltage differences reduced after being programmed and will be relatively closer to the ideal threshold voltage region of the corresponding data state.

[0107] Figure 6This is a threshold voltage distribution diagram of the memory cell provided in an embodiment of this application. Here, Vfc1 is the first verification voltage, Vfc2 is the second verification voltage, and Vvfy is the third verification voltage. (Refer to...) Figure 6 The first latch may include first verification information DL corresponding to the first verification voltage Vfc1, as forced information for the first forced operation. The first verification voltage Vfc1 may be less than the third verification voltage Vvfy. In the example embodiments of this application, a memory cell having a voltage greater than the first verification voltage Vfc1 is a first memory cell that has passed the verification of the first verification voltage, a memory cell having a voltage greater than the second verification voltage Vfc2 is a second memory cell that has passed the verification of the second verification voltage, and a memory cell having a voltage greater than the third verification voltage Vvfy is a third memory cell that has passed the verification of the third verification voltage. A memory cell with a threshold voltage greater than the first verification voltage Vfc1 and less than the third verification voltage Vvfy can be a memory cell to be subjected to a forced operation. Here, the memory cells to be subjected to a forced operation include a first forcing cell and a second forcing cell. A memory cell with a threshold voltage greater than the first verification voltage Vfc1 and less than the second verification voltage Vfc2 can be a first forcing cell to be subjected to a first forced operation, and a memory cell with a threshold voltage greater than the second verification voltage Vfc2 and less than the third verification voltage Vvfy can be a second forcing cell to be subjected to a second forced operation. The memory cells in the first memory cell other than the second and third memory cells are the first forcing cells to be subjected to the first forced operation. In other words, the first memory cell includes a first forcing cell to be subjected to a first forced operation, a second forcing cell to be subjected to a second forced operation, and a third memory cell to be disabled for programming. When the threshold voltage is greater than the first verification voltage Vfc1, the second latch can store "1" as the first verification information DL. Furthermore, if the storage cell with a threshold voltage smaller than the first verification voltage Vfc1 is a programming cell rather than a forced cell, then the first latch can store "0" as the first verification information DL.

[0108] The second latch may include second verification information DM corresponding to the second verification voltage Vfc2, as forced information for the second forced operation. The second verification voltage Vfc2 may be less than the third verification voltage Vvfy and greater than the first verification voltage Vfc1. In an example embodiment of this application, a memory cell having a threshold voltage greater than the second verification voltage Vfc2 and less than the third verification voltage Vvfy may be a memory cell to be subjected to the second forced operation, referred to here as the second forced cell. In other words, the second memory cell includes a second forced cell to be subjected to the second forced operation and a third memory cell to be disabled for programming. When the threshold voltage is greater than the second verification voltage Vfc2, the second latch may store "1" as the second verification information DM. Furthermore, a memory cell having a threshold voltage smaller than the second verification voltage Vfc2 is a memory cell that does not perform the second forced operation, and the second latch may store "0" as the second verification information DM.

[0109] The third latch can store the third verification information DS corresponding to the third verification voltage Vvfy. In the example embodiment of this application, the storage cell with a threshold voltage greater than the third verification voltage Vvfy can be an inhibiting cell, referred to here as the third storage cell, and the third latch can store "1" as the third verification information DS. Furthermore, the storage cell with a threshold voltage level smaller than the third verification voltage Vvfy can be a programming cell (PGMCell), and the third latch can store "0" as the third verification information. In other words, the programming cell includes a storage cell for normal programming operations, a first forcing cell, and a second forcing cell. It should be noted that the third verification voltage Vvfy can also be called the programming verification voltage Vvfy.

[0110] The first latch can store information used to distinguish between memory cells that will undergo bit line forcing operations and memory cells that will undergo disabling programming operations based on the first verification voltage Vfc1, that is, distinguishing between memory cells that will undergo normal programming operations and memory cells that will undergo bit line forcing operations and disabling programming operations.

[0111] The second latch can store information used to distinguish between memory cells that will undergo the second forced operation and memory cells that will undergo the disabling of programming operation based on the second verification voltage Vfc2. That is, information that distinguishes between memory cells that will undergo normal programming operation and first forced operation and memory cells that will undergo second forced operation and disabling of programming operation.

[0112] The third latch can latch information used to distinguish between memory cells that are to be disabled for programming operations based on the third verification voltage Vvfy. This information distinguishes between memory cells that are to be programmed and memory cells that are to be disabled for programming operations.

[0113] In this embodiment, based on the first verification information, the second verification information, and the third verification information, two bit-line forced operation programming methods can be used for different memory cells in a single programming process. This can prevent memory cells from being overprogrammed, thereby reducing the width of the threshold voltage distribution of multiple memory cells and improving the accuracy of programming operations.

[0114] In some embodiments, the control logic is further configured to: apply a first bit line voltage to a first bit line connected to a first forcing unit, apply a second bit line voltage to a second bit line connected to a second forcing unit, apply a programmable disable bit line voltage to a third bit line connected to a third memory cell, and apply a programming voltage to a selected word line, based on first verification information, second verification information, and third verification information; wherein the first bit line voltage is greater than ground voltage and less than programmable disable bit line voltage, and the second bit line voltage is greater than the first bit line voltage. Here, the first forcing unit is a memory cell in the first memory cell other than the second and third memory cells; the second forcing unit is a memory cell in the second memory cell other than the third memory cell. In some embodiments, the control logic is further configured to: apply a normal programming bit line voltage Vprog (e.g., ground voltage Vgnd) to a memory cell performing normal programming operations, based on the first verification information, second verification information, and third verification information. Here, the disable programming bit line voltage Vinh can be the power supply voltage Vdd. The first bit line voltage is greater than the ground voltage (normal programming bit line voltage Vprog) and less than the disable programming bit line voltage Vinh. The second bit line voltage is greater than the first bit line voltage and less than the disable programming bit line voltage Vinh.

[0115] In some embodiments, the first forcing unit is a storage unit in the first storage unit other than the second storage unit and the third storage unit; the second forcing unit is a storage unit in the second storage unit other than the third storage unit.

[0116] In programming processes such as ISPP, when applying the same programming voltage Vpgm to a selected row of memory cells for programming operations, the sensing circuit can use the first verification information DL, the second verification information DM, and the third verification information DS to apply corresponding bit line voltages to the corresponding memory cells, thereby allowing the memory cells to be differentiated for bit line forced operations. In other words, in this embodiment, different memory cells are classified for programming control, and the memory cells can be divided into normal programming cells, first forced cells that will undergo a first bit line forced operation, second forced cells that will undergo a second bit line forced operation, and third memory cells that will undergo a prohibited programming operation. Different bit line voltages are used to classify and program these four types of memory cells.

[0117] During the programming operation, in addition to using two bit line voltages—the disable programming bit line voltage Vinh (e.g., Vdd) and the normal programming bit line voltage Vprog (e.g., ground voltage Vgnd)—if only one forced bit line voltage (greater than the normal programming bit line voltage Vprog and less than the disable programming bit line voltage Vinh) is added to perform programming operations on multiple forced cells, although programming operations with a certain degree of differentiation can be achieved, the threshold voltage distribution of multiple memory cells after programming may not be narrow enough. Therefore, in the programming operation of this embodiment, in addition to using the disable programming bit line voltage Vinh (e.g., VDD) and the normal programming bit line voltage Vprog (e.g., ground voltage Vgnd), a first bit line voltage and a second bit line voltage (both greater than the normal programming bit line voltage Vprog and less than the disable programming bit line voltage Vinh) are also used to perform programming operations with finer differentiation on multiple memory cells.

[0118] In some embodiments, the information stored in the corresponding latch can also be updated based on the verification result of the storage unit. Specifically, the information stored in the first latch is updated based on the first verification information of the storage unit; the information stored in the second latch is updated based on the second verification information of the storage unit; and the information stored in the third latch is updated based on the third verification information of the storage unit.

[0119] This application provides a verification method. Please refer to the embodiments provided. Figure 7 , Figure 7 This is a flowchart illustrating a verification method provided in an embodiment of this application. The verification method includes:

[0120] S701, precharges the sensing node to a predetermined initial voltage;

[0121] S702, change the sensing time point so that the sensing node presents at least three different potentials;

[0122] S703, control the first sensing circuit, the second sensing circuit and the third sensing circuit to obtain the first verification information, the second verification information and the third verification information respectively based on at least three different potentials of the sensing node.

[0123] Among them, the potential of the sensing node corresponding to the first verification information is greater than the potential of the sensing node corresponding to the third verification information, and the potential of the sensing node corresponding to the second verification information is greater than the potential of the sensing node corresponding to the third verification information.

[0124] After pre-charging the sensing node SO to a predetermined initial voltage based on control information, the sensing node SO is discharged. During the discharge of the sensing node SO, the sensing time point is changed to make the sensing node SO present at least three different potentials. Based on the at least three different potentials and different preset voltages, first verification information, second verification information, and third verification information are obtained. The potential of the sensing node corresponding to the first verification information is the first sensing potential; the potential of the sensing node corresponding to the second verification information is the second sensing potential; and the potential of the sensing node corresponding to the third verification information is the third sensing potential.

[0125] In one example, the potential of the sensing node corresponding to the first verification information is greater than the potential of the sensing node corresponding to the second verification information. After obtaining the first verification information, the sensing node is recharged to a predetermined initial voltage, and the sensing time point is changed so that the sensing node presents at least two different potentials. Thus, the second verification information and the third verification information can be obtained.

[0126] In another example, the potential of the sensing node corresponding to the first verification information is greater than the potential of the sensing node corresponding to the second verification information. After obtaining the second verification information, the sensing node is recharged to a predetermined initial voltage, and the sensing time point is changed so that the sensing node presents at least two different potentials. Thus, the first verification information and the third verification information can be obtained.

[0127] The embodiments of this application charge the sensing node at the initial moment and after the first sensing, requiring only two charging operations to complete three verification operations, reducing the number of times the sensing node needs to be charged during the sensing process and saving verification time.

[0128] In some embodiments, changing the sensing time point to make the sensing node present at least three different potentials includes: pre-charging the sensing node to a predetermined initial voltage, discharging the sensing node, and changing the sensing time point during the discharge of the sensing node to make the sensing node present at least three different potentials; wherein, the potential of the sensing node corresponding to the first verification information is the first sensing potential; the potential of the sensing node corresponding to the second verification information is the second sensing potential; and the potential of the sensing node corresponding to the third verification information is the third sensing potential.

[0129] In some embodiments, controlling the first sensing circuit, the second sensing circuit, and the third sensing circuit to obtain first verification information, second verification information, and third verification information based on at least three different potentials of the sensing node includes: comparing the first sensing potential with a first preset voltage to obtain first verification information; wherein, if the first sensing potential is greater than or equal to the first preset voltage, the first verification information is used to indicate a first storage unit that has passed the verification of the first verification voltage.

[0130] In some embodiments, controlling the first sensing circuit, the second sensing circuit, and the third sensing circuit to obtain first verification information, second verification information, and third verification information respectively based on at least three different potentials of the sensing node, further includes: comparing the second sensing potential with a second preset voltage to obtain second verification information; wherein, if the second sensing potential is greater than or equal to the second preset voltage, the second verification information is used to indicate a second storage unit that has passed the verification of the second verification voltage.

[0131] In some embodiments, controlling the first sensing circuit, the second sensing circuit, and the third sensing circuit to obtain first verification information, second verification information, and third verification information respectively based on at least three different potentials of the sensing node, further includes: comparing the third sensing potential with a third preset voltage to obtain third verification information; wherein, if the third sensing potential is greater than or equal to the third preset voltage, the third verification information is used to indicate a third storage cell that has passed the verification of the third verification voltage.

[0132] In some embodiments, the first verification voltage is less than the second verification voltage, and the second verification voltage is less than the third verification voltage.

[0133] In this embodiment, the storage cell with a threshold voltage greater than the first verification voltage but less than the third verification voltage is the first forced cell, the storage cell with a threshold voltage greater than the second verification voltage but less than the third verification voltage is the second forced cell, and the storage cell with a threshold voltage greater than or equal to the third verification voltage is the disabled cell, which does not perform programming operations. For specific examples, please refer to the above device embodiment, which will not be repeated here.

[0134] In some embodiments, based on first verification information, second verification information, and third verification information, a first bit line voltage is applied to the first bit line connected to the first forcing unit, a second bit line voltage is applied to the second bit line connected to the second forcing unit, a programmable disable bit line voltage is applied to the third bit line connected to the third memory cell, and a programming voltage is applied to the selected word line; wherein, the first bit line voltage is greater than the ground voltage and less than the programmable disable bit line voltage, and the second bit line voltage is greater than the first bit line voltage. Here, the first forcing unit is a memory cell in the first memory cell other than the second and third memory cells; the second forcing unit is a memory cell in the second memory cell other than the third memory cell.

[0135] In some embodiments, the first verification information is stored in a first latch in a first sensing circuit; the second verification information is stored in a second latch in a second sensing circuit; and the third verification information is stored in a third latch in a third sensing circuit.

[0136] In some embodiments, the information stored in the corresponding latch can also be updated based on the verification result of the storage unit. Specifically, the information stored in the first latch is updated based on the first verification information of the storage unit; the information stored in the second latch is updated based on the second verification information of the storage unit; and the information stored in the third latch is updated based on the third verification information of the storage unit.

[0137] In some embodiments, such as Figure 8 As shown, Figure 8 This is a block diagram illustrating a memory system according to an exemplary embodiment of this application. The memory system can be applied to mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device having storage therein. Host 801 can be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). Device 802 can be a memory system of an electronic device, having a controller 804 and one or more storage devices 803.

[0138] In some embodiments, controller 804 is coupled to storage device 803 and host 801 and is configured to control storage device 803. Storage device 803 (e.g., NAND flash memory) can store more than a single bit of information in each memory cell in multiple levels (also known as states) to increase storage capacity and reduce cost per bit. Controller 804 can manage the data stored in storage device 803 and communicate with host 801. In some embodiments, controller 804 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, controller 804 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs) used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays. Controller 804 can be configured to control the operation of storage device 803 (e.g., read, erase, and program operations). Controller 804 can also be configured to manage various functions relating to data stored or to be stored in storage device 803, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, controller 804 is also configured to process error correction codes (ECC) relating to data read from or written to storage device 803. Controller 804 can also perform any other suitable function, such as formatting storage device 803. Controller 804 can communicate with external devices (e.g., host 601) according to specific communication protocols. For example, controller 804 can communicate with external devices via at least one of various interface protocols, such as USB, Multimedia Card (MMC), Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Device (IDE), FireWire, etc.

[0139] This application also provides a memory system, including a controller and the aforementioned storage device; the controller is coupled to the storage device and is used to control the storage device.

[0140] Storage devices and one or more storage devices can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, memory systems can be implemented and packaged into different types of end electronic products.

[0141] In one example, such as Figure 9A As shown, the controller 804 and a single storage device 803 can be integrated into the memory card 900a. The memory card 900a may include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, mini SD, microSD, SDHC), UFS, etc.

[0142] In another example, such as Figure 9B As shown, the controller 804 and multiple storage devices 803 can be integrated into the SSD 900b. In some embodiments, the storage capacity and / or operating speed of the SSD 900b is greater than the storage capacity and / or operating speed of the memory card 900a.

[0143] Of course, in other examples, the memory system may also include multiple storage devices and corresponding multiple controllers, which will not be enumerated.

[0144] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0145] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0146] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0147] In the several embodiments provided in this application, it should be understood that the disclosed methods and apparatus can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple modules or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or modules can be electrical, mechanical, or other forms.

[0148] The modules described above as separate components may or may not be physically separate. The components shown as modules may or may not be physical units, that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules may be selected to achieve the purpose of this embodiment according to actual needs.

[0149] In addition, each functional module in the various embodiments of this application can be integrated into one processing module, or each module can be a separate module, or two or more modules can be integrated into one module; the integrated module can be implemented in hardware or in the form of hardware plus software functional modules.

[0150] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A memory device, comprising: include: A storage cell array, wherein the storage cells in the storage cell array are arranged in rows and columns; A sensing circuit coupled to the memory cell array, the sensing circuit including a first sensing circuit, a second sensing circuit and a third sensing circuit coupled to the same sensing node; Control logic coupled to the memory cell array and the sensing circuit is configured to precharge the sensing node to a predetermined initial voltage and then discharge the sensing node so that the sensing node presents a potential during the discharge. The first sensing circuit obtains first verification information based on the potential sensing of the sensing node; The control logic is also configured to recharge the sensing node to a predetermined initial voltage and change the sensing time point so that the sensing node presents at least two different potentials; each of the at least two different potentials is different from the first potential. The second sensing circuit and the third sensing circuit respectively obtain second verification information and third verification information based on the at least two different potentials of the sensing node; Wherein, the potential of the sensing node corresponding to the first verification information is greater than the potential of the sensing node corresponding to the third verification information, and the potential of the sensing node corresponding to the second verification information is greater than the potential of the sensing node corresponding to the third verification information.

2. The memory device of claim 1, wherein, The potential of the sensing node corresponding to the first verification information is greater than the potential of the sensing node corresponding to the second verification information.

3. The memory device of claim 2, wherein, The potential of the sensing node corresponding to the first verification information is the first sensing potential; the potential of the sensing node corresponding to the second verification information is the second sensing potential; and the potential of the sensing node corresponding to the third verification information is the third sensing potential.

4. The memory device of claim 3, wherein, The control logic is further configured to: compare the first sensed potential with a first preset voltage to obtain first verification information; Wherein, if the first sensing potential is greater than or equal to the first preset voltage, the first verification information is used to indicate the first storage unit that has passed the verification of the first verification voltage.

5. The memory device of claim 4, wherein, The control logic is further configured to: compare the second sensed potential with a second preset voltage to obtain second verification information; If the second sensing potential is greater than or equal to the second preset voltage, the second verification information is used to indicate the second storage unit that has passed the verification of the second verification voltage.

6. The memory device of claim 5, wherein, The control logic is further configured to: compare the third sensing potential with a third preset voltage to obtain third verification information; If the third sensing potential is greater than or equal to the third preset voltage, the third verification information is used to indicate the third storage unit that has passed the verification of the third verification voltage.

7. The memory device of claim 6, wherein, The first verification voltage is less than the second verification voltage, and the second verification voltage is less than the third verification voltage.

8. The storage device according to claim 7, characterized in that, The control logic is further configured to: apply a first bit line voltage to the first bit line connected to the first forced unit, apply a second bit line voltage to the second bit line connected to the second forced unit, apply a programmable inhibit bit line voltage to the third bit line connected to the third memory unit, and apply a programming voltage to the selected word line, based on the first verification information, the second verification information, and the third verification information; wherein the first bit line voltage is greater than the ground voltage and less than the programmable inhibit bit line voltage, and the second bit line voltage is greater than the first bit line voltage.

9. The storage device according to claim 8, characterized in that, The first forced unit is a storage unit in the first storage unit other than the second storage unit and the third storage unit; The second forced unit is a storage unit in the second storage unit other than the third storage unit.

10. The memory device of claim 1, wherein, The first sensing circuit includes a first latch for storing the first verification information; the second sensing circuit includes a second latch for storing the second verification information; and the third sensing circuit includes a third latch for storing the third verification information.

11. A method of verification, characterized by, include: The same sensing node coupled to the first sensing circuit, the second sensing circuit and the third sensing circuit is precharged to a predetermined initial voltage; The sensing node is discharged so that it presents a potential during the discharge. The first sensing circuit is controlled to obtain first verification information based on the potential sensing of the sensing node; The sensing node is recharged to a predetermined initial voltage, and the sensing time point is changed so that the sensing node presents at least two different potentials; each of the at least two different potentials is different from the first potential. The second sensing circuit and the third sensing circuit are controlled to obtain second verification information and third verification information respectively based on the at least two different potentials of the sensing node; Wherein, the potential of the sensing node corresponding to the first verification information is greater than the potential of the sensing node corresponding to the third verification information, and the potential of the sensing node corresponding to the second verification information is greater than the potential of the sensing node corresponding to the third verification information.

12. The authentication method of claim 11, wherein, The potential of the sensing node corresponding to the first verification information is greater than the potential of the sensing node corresponding to the second verification information.

13. The verification method according to claim 12, characterized in that, The potential of the sensing node corresponding to the first verification information is the first sensing potential; the potential of the sensing node corresponding to the second verification information is the second sensing potential; and the potential of the sensing node corresponding to the third verification information is the third sensing potential.

14. The authentication method of claim 13, wherein, The control of the first sensing circuit obtains first verification information based on the potential sensing of the sensing node, including: The first sensed potential is compared with the first preset voltage to obtain the first verification information; Wherein, if the first sensing potential is greater than or equal to the first preset voltage, the first verification information is used to indicate the first storage unit that has passed the verification of the first verification voltage.

15. The method of claim 14, wherein, The control of the second sensing circuit and the third sensing circuit to obtain the second verification information and the third verification information respectively based on the at least two different potentials sensed by the sensing node further includes: The second sensed potential is compared with the second preset voltage to obtain the second verification information; If the second sensing potential is greater than or equal to the second preset voltage, the second verification information is used to indicate the second storage unit that has passed the verification of the second verification voltage.

16. The method of claim 15, wherein, The control of the second sensing circuit and the third sensing circuit to obtain the second verification information and the third verification information respectively based on the at least two different potentials sensed by the sensing node further includes: The third sensing potential is compared with the third preset voltage to obtain the third verification information; If the third sensing potential is greater than or equal to the third preset voltage, the third verification information is used to indicate the third storage unit that has passed the verification of the third verification voltage.

17. The method of claim 16, wherein, The first verification voltage is less than the second verification voltage, and the second verification voltage is less than the third verification voltage.

18. The method of claim 17, wherein, The method further includes: Based on the first verification information, the second verification information, and the third verification information, a first bit line voltage is applied to the first bit line connected to the first forced unit, a second bit line voltage is applied to the second bit line connected to the second forced unit, a programmable bit line voltage is applied to the third bit line connected to the third memory unit, and a programming voltage is applied to the selected word line; wherein, the first bit line voltage is greater than the ground voltage and less than the programmable bit line voltage, and the second bit line voltage is greater than the first bit line voltage.

19. The verification method according to claim 18, characterized in that, The first forced unit is a storage unit in the first storage unit other than the second storage unit and the third storage unit; The second forced unit is a storage unit in the second storage unit other than the third storage unit.

20. The method of claim 11, wherein, The method further includes: The first verification information is stored in the first latch of the first sensing circuit; The second verification information is stored in the second latch of the second sensing circuit; The third verification information is stored in the third latch in the third sensing circuit.

21. A memory system, comprising: It includes a controller and a storage device as described in any one of claims 1 to 10; the controller is coupled to the storage device and is used to control the storage device.

Images