Method for forming semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate having a plurality of discrete fin structures thereon; forming a plurality of first dummy gates on the substrate, each of which spans the fin structures; forming a dielectric layer on the substrate, the dielectric layer also being located on the sidewalls of the first dummy gates, with the top surfaces of the plurality of first dummy gates exposed on the surface of the dielectric layer; after forming the dielectric layer, removing the plurality of first dummy gates to form a plurality of gate openings within the dielectric layer; forming second dummy gates within the gate openings; and forming a gate isolation structure, wherein the gate isolation structure extends through at least one second dummy gate in a first direction perpendicular to the extension direction of the second dummy gates. This improves the performance and reliability of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for forming a semiconductor structure. Background Art

[0002] With the continuous advancement of integrated circuit manufacturing technology, the feature size of MOS transistors has become increasingly smaller. To reduce the parasitic capacitance of the MOS transistor gate and increase device speed, a gate stack structure consisting of a high-K gate dielectric layer and a metal gate has been introduced into MOS transistors. To prevent the metal gate's metal material from affecting other transistor structures, this gate stack structure is typically manufactured using a "gate-last" process.

[0003] However, the performance and reliability of existing semiconductor structures still need to be improved. Summary of the Invention

[0004] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure to improve the performance and reliability of the formed semiconductor structure.

[0005] In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, wherein the substrate has a plurality of mutually discrete fin structures; forming a plurality of first pseudo gates across the fin structures on the substrate; forming a dielectric layer on the substrate, wherein the dielectric layer is also located on the sidewalls of the first pseudo gates, and the surface of the dielectric layer exposes the top surfaces of the plurality of first pseudo gates; after forming the dielectric layer, removing the plurality of first pseudo gates and forming a plurality of gate openings in the dielectric layer; forming a second pseudo gate in the gate opening; forming a gate isolation structure, and the gate isolation structure penetrates at least one second pseudo gate in a first direction, and the first direction is perpendicular to the extension direction of the second pseudo gate.

[0006] Optionally, the method further includes: after forming the gate isolation structure, removing the second dummy gate in the gate opening; and after removing the second dummy gate, forming a metal gate structure in the gate opening.

[0007] Optionally, the method for removing the second dummy gate includes: etching the second dummy gate using a dry etching process to reduce the height of the second dummy gate to form an intermediate second dummy gate, wherein the surface of the intermediate second dummy gate is higher than the top surface of the fin structure; etching the intermediate second dummy gate using a wet etching process until the intermediate second dummy gate is removed.

[0008] Optionally, in the wet etching process used to etch the middle second dummy gate, the etchant used includes an alkaline solution.

[0009] Optionally, the method for removing the first dummy gate includes: etching the first dummy gate using a dry etching process to reduce the height of the first dummy gate to form an intermediate first dummy gate, wherein the surface of the intermediate first dummy gate is higher than the top surface of the fin structure; etching the intermediate first dummy gate using a wet etching process until the intermediate first dummy gate is removed.

[0010] Optionally, in the wet etching process used to etch the middle first dummy gate, the etchant used includes an alkaline solution.

[0011] Optionally, the method for forming the gate isolation structure includes: forming a first mask layer on the surface of the dielectric layer and the second dummy gate, the first mask layer exposing a portion of the surface of the second dummy gate; using the first mask layer as a mask, etching the second dummy gate to form a gate isolation opening in the dielectric layer, in the first direction, the gate isolation opening passes through at least one second dummy gate; and forming the gate isolation structure in the gate isolation opening.

[0012] Optionally, the process of etching the second dummy gate using the first mask layer as a mask includes a wet etching process.

[0013] Optionally, the method for forming the gate opening includes: forming a gate opening mask layer on the surface of the dielectric layer, the gate opening mask layer exposing the top surface of the first pseudo gate; using the gate opening mask layer as a mask, etching the first pseudo gate until the first pseudo gate is removed.

[0014] Optionally, before forming the dielectric layer, the method further includes: forming a gate spacer on the sidewall of the first dummy gate.

[0015] Optionally, the material of the gate isolation structure includes silicon nitride.

[0016] Optionally, the material of the first dummy gate includes amorphous silicon or polycrystalline silicon.

[0017] Optionally, the material of the second dummy gate includes amorphous silicon or polycrystalline silicon.

[0018] Optionally, the process of forming the dielectric layer includes a fluid chemical deposition process and an annealing process.

[0019] Optionally, the method further includes: forming a source-drain structure in the fin structure on both sides of the first dummy gate after forming the first dummy gate and before forming the dielectric layer.

[0020] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0021] In the method for forming a semiconductor structure provided by the technical solution of the present invention, since several of the first dummy gates are removed after forming the dielectric layer and before forming the gate isolation structure in the dielectric layer, the first dummy gates are completely exposed during the etching process for removing the first dummy gates, making it easier to etch and remove the material of the first dummy gates affected by the high-temperature process, so that the material of the first dummy gates is less likely to remain, thereby improving the performance and reliability of the semiconductor structure. On this basis, since the second dummy gate is formed in the gate opening after forming the dielectric layer and before forming the gate isolation structure, the high-temperature process after forming the first dummy gate and before forming the second dummy gate will not affect the material of the second dummy gate, so that during the process of forming the gate isolation structure, the etching process has a close or identical etching rate on the second dummy gate in all directions, thereby smoothing the sidewall surface of the opening for forming the gate isolation structure, making the sidewall surface of the gate isolation structure smooth, and further improving the performance and reliability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figures 1 to 5 The present invention is a structural schematic diagram of each step of a method for forming a semiconductor structure;

[0023] Figures 6 to 16 1 is a schematic structural diagram of each step of a method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] As described in the background art, the performance and reliability of existing semiconductor structures still need to be improved. The reasons why the performance and reliability of semiconductor structures still need to be improved are described in detail below with reference to the accompanying drawings.

[0025] Figures 1 to 5 The present invention is a structural schematic diagram of each step of a method for forming a semiconductor structure.

[0026] Please refer to Figure 1 and Figure 2 , Figure 2 yes Figure 1 Schematic diagram of the cross-sectional structure along the center direction A1-A2, Figure 1 yes Figure 2A schematic diagram of a top view structure along direction B is provided, providing a substrate 100, on which a plurality of mutually separated fins 101 are provided; a first dielectric layer 110 is formed on the surface of the substrate 100, and the first dielectric layer 110 covers a portion of the sidewall surface of the fin 101; a plurality of dummy gates 120 are formed on the first dielectric layer 110, spanning the fin 101, and the material of the dummy gate 120 is amorphous silicon or polycrystalline silicon; after the dummy gate 120 is formed, a second dielectric layer 130 is formed on the first dielectric layer 110, and the second dielectric layer 130 is also located on the sidewall surface of the dummy gate 120, and the surface of the second dielectric layer 130 exposes the top surface of the dummy gate 120.

[0027] In order to improve the filling property and surface flatness of the second dielectric layer 130, the second dielectric layer is formed by: forming an initial second dielectric material layer (not shown) on the surface of the first dielectric layer 110, the surface of the fin 101, and the surface of the dummy gate 120 using a flow chemical vapor deposition (FCVD) process; annealing the initial second dielectric material layer to form a second dielectric material layer; and planarizing the second dielectric material layer until the top surface of the dummy gate 120 is exposed to form the second dielectric layer 130.

[0028] Please refer to Figure 3 and Figure 4 , Figure 4 yes Figure 3 Schematic diagram of the cross-sectional structure along the center direction A1-A2, Figure 3 yes Figure 4 In a schematic diagram of a top view of the structure along direction B, a mask layer (not shown) is formed on the surface of the dummy gate 120 and the second dielectric layer 130, and the mask layer exposes a portion of the surface of the dummy gate 120; the dummy gate 120 is etched using the mask layer as a mask until the surface of the first dielectric layer 110 is exposed, and a gate isolation opening 131 is formed in the second dielectric layer 130, and in a direction perpendicular to the extension direction of the dummy gate 120, the gate isolation opening 131 penetrates one of the dummy gates 120.

[0029] In order to avoid damaging the fin 101 near the gate isolation opening 131, a wet etching process is used to etch the dummy gate 120 to form the gate isolation opening 131. The etchant of the wet etching process is an alkaline solution.

[0030] Please refer to Figure 5 , Figure 5 and Figure 4 In the same viewing direction, a gate isolation structure 140 is formed in the gate isolation opening 131; after the gate isolation structure 140 is formed, the dummy gate 120 is removed, and a gate opening (not shown) is formed in the second dielectric layer 130; and a metal gate 150 is formed in the gate opening.

[0031] However, in the above embodiment, on the one hand, due to the high temperature of the annealing process, the atoms in the material of the dummy gate 120 migrate and rearrange, resulting in the exposure of the (111) crystal plane in the etching path for forming the gate isolation opening 131. On the other hand, since the etching of silicon by the alkaline solution is anisotropic and the etching rate of the (111) crystal plane is very low, the etching is easily stopped at the (111) crystal plane in the etching path for forming the gate isolation opening 131, thereby causing the sidewall surface in the gate isolation opening 131 to be rough (such as Figure 4 ), resulting in a rough sidewall surface of the gate isolation structure 140 formed in the gate isolation opening 131. Furthermore, since the dummy gate 120 generates stress on the gate isolation structure 140, and compared to smooth walls, stress is more likely to concentrate on rough walls. That is, the rough sidewalls of the gate isolation structure 140 are subjected to greater stress. Therefore, when the dummy gate 120 is removed, a large amount of stress is released on the rough sidewalls of the gate isolation structure 140, exacerbating the deformation of the rough sidewalls. In other words, the sidewalls of the gate isolation structure 140 become very rough.

[0032] Since the sidewall surface of the gate isolation structure 140 is very rough, on the one hand, when the dummy gate 120 is subsequently removed, the material of the dummy gate 120 is easily blocked, forming an etching residue 121 (such as Figure 5 ), thereby affecting the electrical characteristics of the semiconductor structure, resulting in poor performance and reliability. Furthermore, gaps are easily formed between the sidewalls of the gate isolation structure 140 and the second dielectric layer 130. Consequently, in subsequent etching processes, the etchant in the etching process can easily pass through the gaps and etch into the fins 101 surrounding the gate isolation structure 140, resulting in poor performance and reliability of the semiconductor structure.

[0033] To address the above technical issues, embodiments of the present invention provide a method for forming a semiconductor structure. After forming the dielectric layer, several first dummy gates are removed, forming several gate openings within the dielectric layer; second dummy gates are formed within the gate openings; and a gate isolation structure is formed, wherein the gate isolation structure extends through at least one second dummy gate in a first direction perpendicular to the extension direction of the second dummy gate. This improves the performance and reliability of the semiconductor structure.

[0034] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0035] Figures 6 to 16 1 is a schematic structural diagram of each step of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0036] Please refer to Figure 6 , providing a substrate 200 having a plurality of mutually separated fin structures 201 thereon.

[0037] The substrate 200 is made of a semiconductor material.

[0038] In this embodiment, the substrate 200 is made of silicon.

[0039] In other embodiments, the substrate material includes silicon carbide, silicon germanium, a multinary semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). Among them, the multinary semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP.

[0040] In this embodiment, before subsequently forming the first dummy gate, a first dielectric layer 210 is formed on the substrate 200. The first dielectric layer 210 is also located on a portion of the sidewall surface of the fin structure 201. The first dielectric layer 210 can electrically insulate adjacent fin structures 201 and between the semiconductor device and the substrate 200.

[0041] Please refer to Figure 7 and Figure 8 , Figure 8 yes Figure 7 Schematic diagram of the cross-sectional structure along the center direction A1-A2, Figure 7 yes Figure 8 In a schematic top view of the structure along a center direction B, a plurality of first dummy gates 220 are formed on the substrate 200 and span the fin structure 201 .

[0042] In this embodiment, the material of the first dummy gate 220 includes amorphous silicon or polycrystalline silicon.

[0043] In the subsequent process of forming the second dummy gate, the first dummy gate 220 is used to define the pattern of the second dummy gate.

[0044] In this embodiment, the method for forming the first dummy gate 220 includes: forming a first dummy gate material film (not shown) covering the surface of the fin structure 201 on the substrate 200; patterning the first dummy gate material film until the surface of the substrate 200 is exposed, so as to form a plurality of mutually separate first dummy gates 220 on the substrate 200, wherein the first dummy gates 220 span the fin structure 201, and the top surface of the first dummy gate 220 is higher than the top surface of the fin structure 201.

[0045] The formation process of the first dummy gate material film includes a deposition process, and the deposition process is, for example, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0046] The process of patterning the first dummy gate material film includes at least one of a dry etching process and a wet etching process.

[0047] Please refer to Figure 9 , Figure 9 and Figure 7 A dielectric layer 230 is formed on the substrate 200 , and the dielectric layer 230 is also located on the sidewalls of the first dummy gate 220 . The surface of the dielectric layer 230 exposes a portion of the top surface of the first dummy gate 220 .

[0048] In this embodiment, the dielectric layer 230 is made of silicon oxide.

[0049] In other embodiments, the material of the dielectric layer includes at least one of SiOCH, SiOH, and SiCN.

[0050] In this embodiment, the method for forming the dielectric layer 230 includes: forming a dielectric material layer (not shown) on the surface of the first dummy gate 220 and the substrate 200, wherein the surface of the dielectric material layer is higher than the top surface of the first dummy gate 220; and planarizing the dielectric material layer until the top surface of the first dummy gate 220 is exposed.

[0051] In this embodiment, the process of forming the dielectric material layer includes a fluid chemical vapor deposition (FCVD) process and an annealing process.

[0052] In other embodiments, the process of forming the dielectric material layer includes a spin coating process, a thermal oxidation process, a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0053] The process of planarizing the dielectric material layer includes an etch-back process or a chemical mechanical polishing process.

[0054] In this embodiment, after forming the first dummy gate 220 and before forming the dielectric layer 230 , a gate spacer (not shown) is formed on the sidewall of the first dummy gate 220 .

[0055] The gate spacer is used to define the formation position of the source and drain structures in the subsequent process.

[0056] In this embodiment, the gate spacer is made of a material comprising a combination of multiple low-K dielectric materials (K is less than 3.9), such as SiOC, SiOCN, and SiBCN.

[0057] In this embodiment, the method for forming the gate sidewall includes: depositing a sidewall material film (not shown) on the surface of the substrate 200 and the surface of the first dummy gate 220; using an anisotropic etching process to etch back the sidewall material film until the sidewall material film on the surface of the substrate 200 and the top surface of the first dummy gate 220 is removed, and a gate sidewall is formed on the sidewall of the first dummy gate 220.

[0058] In this embodiment, after forming the first dummy gate 220 and before forming the dielectric layer 230 , source and drain structures (not shown) are formed in the fin structure on both sides of the first dummy gate 220 .

[0059] Specifically, the method for forming the source-drain structure includes: after forming the gate sidewall and before forming the dielectric layer 230, forming source-drain openings (not shown) in the fin structure 201 on both sides of the first pseudo gate 220; and forming the source-drain structure in the source-drain openings using an epitaxial growth process.

[0060] In other embodiments, the method for forming the source-drain structure includes: after forming the gate sidewall, forming a source-drain mask layer on the top surface of the gate sidewall and the top surface of the first pseudo gate; before forming the dielectric layer, using the gate sidewall and the source-drain mask layer as masks, performing an ion implantation process on the exposed substrate to form doped regions in the substrate on both sides of the first pseudo gate to form a source-drain structure in the fin structure on both sides of the first pseudo gate.

[0061] Please refer to Figure 10 , Figure 10 and Figure 9 In the same viewing direction, after the dielectric layer 230 is formed, a number of the first dummy gates 220 are removed, and a number of gate openings 221 are formed in the dielectric layer 230 .

[0062] Since a number of the first dummy gates 220 are removed after the dielectric layer 230 is formed and before the gate isolation structure is subsequently formed in the dielectric layer 230, the first dummy gates 220 are completely exposed during the etching process for removing the first dummy gates 220, making it easier to etch and remove the material of the first dummy gates 220 affected by the high-temperature process. As a result, the material of the first dummy gates 220 is less likely to remain, thereby improving the performance and reliability of the semiconductor structure.

[0063] In this embodiment, the method for forming the gate opening 221 includes: forming a gate opening mask layer (not shown) on the surface of the dielectric layer 230, wherein the gate opening mask layer exposes the top surface of the first pseudo gate 220; using the gate opening mask layer as a mask, etching the first pseudo gate 220 until the first pseudo gate 220 is removed.

[0064] In this embodiment, the method for removing the first dummy gate 220 includes: etching the first dummy gate 220 using a dry etching process to reduce the height of the first dummy gate 220 to form an intermediate first dummy gate (not shown), and the surface of the intermediate first dummy gate is higher than the top surface of the fin structure 201; etching the intermediate first dummy gate using a wet etching process until the intermediate first dummy gate is removed.

[0065] On the one hand, the dry etching process has a high etching rate. Since the dry etching process is used to etch the first dummy gate 220, the efficiency of the semiconductor structure formation process is improved. On the other hand, the wet etching process can have a greater etching selectivity between the material of the first dummy gate 220 and the material of the fin structure 201. Since the wet etching process is used to etch the middle first dummy gate after the height of the first dummy gate 220 is reduced to form a middle first dummy gate with a top surface higher than the fin structure 201, it can reduce damage and impact on the fin structure 201 after the fin structure 201 is exposed, thereby improving the performance and reliability of the semiconductor structure.

[0066] In this embodiment, in the wet etching process used to etch the middle first dummy gate, the etchant used includes an alkaline solution.

[0067] In this embodiment, the alkaline solution includes at least one alkaline solvent selected from tetramethylammonium hydroxide (TMAH), ammonia water, potassium hydroxide, and the like.

[0068] Please refer to Figure 11 , Figure 11 and Figure 10 A second dummy gate 240 is formed in the gate opening 221 in the same viewing direction.

[0069] In this embodiment, the material of the second dummy gate 240 includes amorphous silicon or polycrystalline silicon.

[0070] In the subsequent process of forming the metal gate structure, the second dummy gate 240 is used to define the pattern of the metal gate structure.

[0071] In this embodiment, the method for forming the second dummy gate 240 includes: forming a second dummy gate material film (not shown) in the gate opening 221 and on the top surface of the dielectric layer 230; flattening the second dummy gate material film until the top surface of the dielectric layer 230 is exposed to form the second dummy gate 240.

[0072] In this embodiment, the process of forming the second dummy gate material film includes a deposition process, such as a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.

[0073] The process of planarizing the second dummy gate material film includes an etch-back process or a chemical mechanical planarization process.

[0074] Next, a gate isolation structure is formed, and the gate isolation structure penetrates at least one second dummy gate 240 in a first direction, and the first direction is perpendicular to the extension direction of the second dummy gate 240. For the specific steps of forming the gate isolation structure, please refer to Figures 12 to 14 .

[0075] Please refer to Figure 12 and Figure 13 , Figure 13 yes Figure 12 Schematic diagram of the cross-sectional structure along the center direction A1-A2, Figure 12 yes Figure 13 In a schematic diagram of a top-down structure along direction B, a first mask layer 250 is formed on the surface of the dielectric layer 230 and the second pseudo gate 240, and the first mask layer 250 exposes part of the surface of the second pseudo gate 240; using the first mask layer 250 as a mask, the second pseudo gate 240 is etched to form a gate isolation opening in the dielectric layer 230.

[0076] The gate isolation opening provides space for subsequently forming a gate isolation structure.

[0077] In this embodiment, the isolation gate opening is also located in the first dielectric layer 210 .

[0078] In the first direction X, the gate isolation opening passes through at least one second dummy gate 240 , and the first direction X is perpendicular to the extension direction of the second dummy gate 240 .

[0079] In this embodiment, the gate isolation opening allows viewing of one second dummy gate 240 .

[0080] In this embodiment, the process of etching the second dummy gate 240 using the first mask layer 250 as a mask includes a wet etching process.

[0081] In this embodiment, in the wet etching process used to etch the second dummy gate 240 using the first mask layer 250 as a mask, the etchant used includes an alkaline solution.

[0082] In this embodiment, the alkaline solution includes at least one alkaline solvent selected from tetramethylammonium hydroxide (TMAH), ammonia water, potassium hydroxide, and the like.

[0083] Please refer to Figure 14 , Figure 14 and Figure 13A gate isolation structure 260 is formed in the gate isolation opening, and the gate isolation structure 260 passes through at least one second dummy gate 240 in the first direction X.

[0084] On the basis of preventing the material of the first dummy gate 220 from remaining and thus improving the performance and reliability of the semiconductor structure, since the second dummy gate 240 is formed in the gate opening 222 after the dielectric layer 230 is formed and before the gate isolation structure 260 is formed, the high-temperature process after the first dummy gate 220 is formed and before the second dummy gate 240 is formed will not affect the material of the second dummy gate 240, so that during the process of forming the gate isolation structure 260, the etching process has a similar or identical etching rate on the second dummy gate 240 in all directions, thereby smoothing the sidewall surface of the gate isolation opening that provides space for forming the gate isolation structure 260, making the sidewall surface of the gate isolation structure 260 smooth, thereby improving the performance and reliability of the semiconductor structure.

[0085] Specifically, on the one hand, the sidewall surface of the gate isolation structure 260 is smooth. Therefore, during the process of removing the second dummy gate 240, it is not easy to block the material of the second dummy gate 240, and at the same time, the impact on the aspect ratio is reduced. Therefore, it is conducive to the removal of the material of the second dummy gate 240, so that the second dummy gate 240 is not likely to remain, and it is conducive to the subsequent filling of the metal gate structure material, thereby improving the performance and reliability of the semiconductor structure. On the other hand, the stress generated by the second dummy gate 240 on the sidewall surface of the gate isolation structure 260 is more uniform. Therefore, the deformation degree of the gate isolation structure 260 during the stress release process after the subsequent removal of the second dummy gate 240 is reduced. Therefore, it is also conducive to the removal of the material of the second dummy gate 240 and the subsequent filling of the metal gate structure material, thereby improving the performance and reliability of the semiconductor structure. Moreover, since the sidewall surface of the gate isolation structure 260 is smooth, the gate isolation structure 260 has a better ability to block the etching solution of other subsequent etching processes, that is, the etching solution is not easy to pass through the gap between the sidewall surface of the gate isolation structure 260 and the dielectric layer 230 and etch into the surrounding fin structure 201, thereby improving the performance and reliability of the semiconductor structure.

[0086] In this embodiment, the method for forming the gate isolation structure 260 in the gate isolation opening includes: forming a gate isolation structure material layer (not shown) in the gate isolation opening, on the dielectric layer 230, and on the second dummy gate 240; and flattening the gate isolation structure material layer until the top surface of the dielectric layer 230 and the top surface of the second dummy gate 240 are exposed to form the gate isolation structure 260.

[0087] In this embodiment, the material of the gate isolation structure 260 includes silicon nitride.

[0088] Please refer to Figure 15 , Figure 15 and Figure 14 In the same viewing direction, after forming the gate isolation structure 260 , the second dummy gate 240 in the gate opening 222 is removed.

[0089] In this embodiment, the method for removing the second dummy gate 240 includes: etching the second dummy gate 240 using a dry etching process to reduce the height of the second dummy gate 240 to form an intermediate second dummy gate (not shown), and the surface of the intermediate second dummy gate is higher than the top surface of the fin structure 201; etching the intermediate second dummy gate using a wet etching process until the intermediate second dummy gate is removed.

[0090] On the one hand, the dry etching process has a high etching rate. Since the dry etching process is used to etch the second dummy gate 240, the efficiency of the semiconductor structure formation process is improved. On the other hand, the wet etching process can have a greater etching selectivity between the material of the second dummy gate 240 and the material of the fin structure 201. After the height of the second dummy gate 240 is reduced to form an intermediate second dummy gate with a top surface higher than the fin structure 201, the intermediate first dummy gate is etched using a wet etching process. Therefore, after the fin structure 201 is exposed, damage and impact to the fin structure 201 can be reduced, thereby improving the performance and reliability of the semiconductor structure.

[0091] In this embodiment, in the wet etching process used to etch the first middle dummy gate, the etchant used includes an alkaline solution, which includes at least one alkaline solvent selected from tetramethylammonium hydroxide (TMAH), ammonia water, and potassium hydroxide.

[0092] Please refer to Figure 16 , Figure 16 and Figure 15 In the same viewing direction, after removing the second dummy gate 240 , a metal gate structure 270 is formed in the gate opening 222 .

[0093] In this embodiment, the metal gate structure 270 includes: a gate dielectric layer (not shown) located on the inner wall of the gate opening 222, a work function layer (not shown) located on the surface of the gate dielectric layer, and a metal gate (not shown) located on the surface of the work function layer, and the metal gate fills the gate opening 222.

[0094] In this embodiment, the method for forming the metal gate structure 270 includes: forming a metal gate structure material layer (not shown) within the gate opening 222 and on the surface of the dielectric layer 230 and the surface of the gate isolation structure 260, wherein the surface of the metal gate structure material layer is higher than the surface of the dielectric layer 230 and the surface of the gate isolation structure 260; and planarizing the metal gate structure material layer until the surface of the dielectric layer 230 and the surface of the gate isolation structure 260 are exposed. In this embodiment, the process for planarizing the metal gate structure material layer includes an etch-back process or a chemical mechanical planarization process.

[0095] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate having a plurality of mutually separated fin structures thereon; forming a plurality of first dummy gates on the substrate and spanning the fin structure; forming a dielectric layer on the substrate, wherein the dielectric layer is also located on the sidewalls of the first dummy gate, and a surface of the dielectric layer exposes a portion of the first dummy gate top surface; After forming the dielectric layer, removing a plurality of the first dummy gates and forming a plurality of gate openings in the dielectric layer; forming a second dummy gate in the gate opening; forming a gate isolation structure, wherein the gate isolation structure penetrates at least one second dummy gate in a first direction, wherein the first direction is perpendicular to an extension direction of the second dummy gate; After forming the gate isolation structure, removing the second dummy gate in the gate opening; After removing the second dummy gate, a metal gate structure is formed in the gate opening.

2. The method for forming a semiconductor structure according to claim 1, wherein: The method for removing the second dummy gate includes: etching the second dummy gate using a dry etching process to reduce the height of the second dummy gate to form an intermediate second dummy gate, and the surface of the intermediate second dummy gate is higher than the top surface of the fin structure; etching the intermediate second dummy gate using a wet etching process until the intermediate second dummy gate is removed.

3. The method for forming a semiconductor structure according to claim 2, wherein: In the wet etching process used to etch the middle second dummy gate, the etchant used includes an alkaline solution.

4. The method for forming a semiconductor structure according to claim 1, wherein: The method for removing the first dummy gate includes: etching the first dummy gate using a dry etching process to reduce the height of the first dummy gate to form an intermediate first dummy gate, and the surface of the intermediate first dummy gate is higher than the top surface of the fin structure; etching the intermediate first dummy gate using a wet etching process until the intermediate first dummy gate is removed.

5. The method for forming a semiconductor structure according to claim 4, wherein: In the wet etching process used to etch the middle first dummy gate, the etchant used includes an alkaline solution.

6. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the gate isolation structure includes: forming a first mask layer on the surface of the dielectric layer and the second dummy gate, the first mask layer exposing a portion of the surface of the second dummy gate; using the first mask layer as a mask, etching the second dummy gate to form a gate isolation opening in the dielectric layer, in the first direction, the gate isolation opening passes through at least one second dummy gate; and forming the gate isolation structure in the gate isolation opening.

7. The method for forming a semiconductor structure according to claim 6, wherein: The process of etching the second dummy gate using the first mask layer as a mask includes a wet etching process.

8. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the gate opening includes: forming a gate opening mask layer on the surface of the dielectric layer, wherein the gate opening mask layer exposes the top surface of the first dummy gate; using the gate opening mask layer as a mask, etching the first dummy gate until the first dummy gate is removed.

9. The method for forming a semiconductor structure according to claim 1, wherein: Before forming the dielectric layer, the method further includes: forming a gate spacer on the sidewall of the first dummy gate.

10. The method for forming a semiconductor structure according to claim 1, wherein: The material of the gate isolation structure includes silicon nitride.

11. The method for forming a semiconductor structure according to claim 1, wherein: The material of the first dummy gate includes amorphous silicon or polysilicon.

12. The method for forming a semiconductor structure according to claim 1, wherein: The material of the second dummy gate includes amorphous silicon or polysilicon.

13. The method for forming a semiconductor structure according to claim 1, wherein: The process of forming the dielectric layer includes a fluid chemical deposition process and an annealing process.

14. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: After forming the first dummy gate and before forming the dielectric layer, source and drain structures are formed in the fin structure on both sides of the first dummy gate.

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