Storage system, and three-dimensional memory and method of making the same

Abstract

Storage system, and three-dimensional memory and method for manufacturing the same. The present disclosure provides a three-dimensional memory and a method for manufacturing the same. The present disclosure also provides a storage system. The three-dimensional memory according to the present disclosure comprises: a stack structure comprising insulating layers and gate layers alternately stacked, the stack structure further comprising a step region, the step region comprising a plurality of sub-regions arranged along a first direction, and a boundary region between any two adjacent sub-regions, each sub-region comprising a plurality of steps arranged along a second direction; in the boundary region, the intersection of adjacent steps forms a boundary structure; the first direction and the second direction are perpendicular to the stacking direction of the insulating layers and the gate layers, respectively; and a gate line slit structure penetrating through the stack structure; wherein part of the gate line slit structure is located in the boundary region and penetrates through at least one boundary structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices, and more specifically, to memory systems, three-dimensional memories, and methods for fabricating the same. Background Technology

[0002] Three-dimensional storage devices, with their high storage density and capacity, have seen continuous development in recent years. For example, 3D NAND flash memory is being used more and more widely.

[0003] Generally, in 3D NAND structures, a stacked structure is formed by alternately stacking multiple gate layers and multiple insulating layers. The stepped region of the stacked structure forms multiple steps, and each gate layer can be led out through a contact (CT) formed on the corresponding step. Usually, to simplify the process, the stepped region is set as a staircase-divide structure (SDS). However, due to its structure and process influences, it is prone to problems such as short circuits between gate layers, thereby affecting device performance and production yield. Summary of the Invention

[0004] One or more embodiments of this application provide a storage system that can at least partially solve the above-mentioned problems existing in the related art, as well as a three-dimensional memory and a method for preparing the same.

[0005] One aspect of this application provides a three-dimensional memory, comprising: a stacked structure including alternately stacked insulating layers and gate layers, the stacked structure further comprising a stepped region, the stepped region comprising a plurality of partitions arranged along a first direction, a boundary region between adjacent partitions, each partition comprising multiple steps arranged along a second direction; within the boundary region, the junction of adjacent steps constitutes a boundary structure; the first direction and the second direction intersect each other and are perpendicular to the stacking directions of the insulating layer and the gate layer, respectively; and a gate line slot structure penetrating the stacked structure; wherein a portion of the gate line slot structure is located in the boundary region and penetrates at least one of the boundary structures.

[0006] In one embodiment of this application, the grid line slot structure located in the boundary region extends along the second direction.

[0007] In one embodiment of this application, the grid line slot structure located in the boundary region is disconnected between two adjacent boundary structures.

[0008] In one embodiment of this application, each of the boundary regions is provided with the grid line slot structure.

[0009] In one embodiment of this application, each of the grid line slot structures located in the boundary region penetrates at least one of the boundary structures.

[0010] In one embodiment of this application, the top surface of the step is the top surface of the gate layer, and the three-dimensional memory further includes a thickened portion located on the top surface of each step, wherein the thickened portion is formed of a conductive material, and there is a gap between the thickened portion and the end face of the upper step adjacent to the step where the thickened portion is located.

[0011] In one embodiment of this application, the three-dimensional memory further includes: a dielectric layer that at least covers the stepped area and spaces the end faces of each thickened portion and adjacent steps apart.

[0012] In one embodiment of this application, the three-dimensional memory further includes: a gate contact formed of a conductive material, extending through the dielectric layer and to the thickened portion.

[0013] Another aspect of this application provides a method for fabricating a three-dimensional memory, the method comprising: forming a dielectric stacked structure on a substrate; forming a plurality of partitions along a first direction in a step region of the dielectric stacked structure, wherein each partition includes multiple steps along a second direction, and a boundary region is formed between two adjacent partitions, wherein the junction of adjacent steps in the boundary region constitutes a boundary structure; the first direction and the second direction intersect each other and are perpendicular to the stacking direction of the dielectric stacked structure; and forming a gate wire slot structure penetrating the dielectric stacked structure; wherein a portion of the gate wire slot structure is located in the boundary region and penetrates at least one of the boundary structures.

[0014] In one embodiment of this application, the dielectric stack structure includes a plurality of alternately stacked gate sacrificial layers and insulating layers, the gate sacrificial layers being exposed on the top surface of the step, and the method further includes, before forming a gate wire gap structure through the dielectric stack structure: forming a buffer layer covering the top surface of the step and having a gap with the end face of an adjacent upper step; and forming a dielectric layer that at least covers the buffer layer and fills the gap.

[0015] In one embodiment of this application, forming a gate line slot structure through the dielectric stack structure includes: forming a mask on the side of the dielectric stack structure away from the substrate; patterning the mask to form a gate line slot arrangement pattern therein including at least one gate line slot pattern, the gate line slot pattern covering at least one of the boundary structures along the length direction; etching the dielectric stack structure via the gate line slot arrangement pattern to remove the portion of the dielectric stack structure including the boundary structure, thereby forming a gate line slot through the dielectric stack structure; and forming the gate line slot structure in the gate line slot.

[0016] In one embodiment of this application, the length of the grid line slot structure located in the boundary region extends along the second direction.

[0017] In one embodiment of this application, the grid line slot structure located in the boundary region is disconnected between two adjacent boundary structures.

[0018] In one embodiment of this application, each of the boundary regions is provided with the grid line slot structure.

[0019] In one embodiment of this application, each of the grid line slot structures located in the boundary region penetrates at least one of the boundary structures.

[0020] In one embodiment of this application, the method further includes: removing the gate sacrificial layer and the buffer layer in the dielectric stack structure via the gate line gap to form a sacrificial gap; filling the sacrificial gap with conductive material to form a gate layer and a thickened portion at the original locations of the gate sacrificial layer and the buffer layer in the dielectric stack structure, respectively; forming a contact hole that penetrates the dielectric layer and extends to the thickened portion; and filling the contact hole with conductive material to form a gate contact portion.

[0021] In one embodiment of this application, the conductive material includes tungsten.

[0022] In one embodiment of this application, forming a buffer layer covering the top surface of the step and having a gap with the end face of an adjacent upper step includes: forming a buffer layer that at least covers the step area; and at least removing a portion of the buffer layer covering the end face of the step, retaining a portion of the buffer layer covering the top surface of the step, and leaving such portion of the buffer layer with a gap from the end face of the adjacent upper step.

[0023] In one embodiment of this application, the material of the buffer layer includes silicon nitride.

[0024] Another aspect of this application provides a storage system that may include at least one three-dimensional memory as described above, and a memory controller electrically connected to at least one of the three-dimensional memories, the memory controller being used to control at least one of the three-dimensional memories.

[0025] This application optimizes the arrangement and position of the gate line slots, removing the boundary structure between at least one of the four adjacent steps of different heights arranged in a "cross" shape during the formation of the gate line slots. This eliminates many defects that are prone to occur at the original boundary structure during deposition and etching, such as voids, end face and / or sidewall residues, and poor accumulation. This avoids the possibility of incorrect connections between different gate layers after the conductive material is replaced with a sacrificial material, which is conducive to improving the quality of subsequent gate contact formation to achieve electrical connection between each gate layer and the external interconnect structure. Attached Figure Description

[0026] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Embodiments of this application are illustrated in the accompanying drawings by way of example rather than limitation, in which the same reference numerals indicate similar elements. Wherein:

[0027] Figure 1 This is a schematic diagram of a contact portion forming a through-gate layer in a stepped region according to one embodiment;

[0028] Figure 2 This is a schematic diagram showing a buffer layer with void defects formed on a step area according to one embodiment;

[0029] Figure 3 This is a schematic diagram showing the etching residue of the buffer layer on the end face of the step and its adjacent area according to one embodiment;

[0030] Figure 4 Is Figure 3 Based on this, after forming the gate layer and the thickened portion, due to Figure 3 The diagram shows how etching residue can cause short circuits between adjacent gate layers.

[0031] Figure 5 This is an electron microscope view of a deposition defect generated on the boundary structure of a partitioned step according to one embodiment;

[0032] Figure 6 This is a flowchart of a method for fabricating a three-dimensional memory according to one embodiment of this application;

[0033] Figure 7 This is a cross-sectional schematic diagram of a step region after a buffer layer is formed above a dielectric stacked structure according to one embodiment;

[0034] Figure 8 This is a cross-sectional schematic diagram of the stepped region of the dielectric laminate structure after removing the buffer layer located at the end face of the stepped structure according to one embodiment;

[0035] Figure 9 This is a cross-sectional schematic diagram of a stepped region after a dielectric layer is formed above a dielectric stack structure according to one embodiment;

[0036] Figure 10 This is a cross-sectional schematic diagram of the stepped region of the stacked structure after the gate layer and the thickened portion are formed according to one embodiment;

[0037] Figure 11 This is a three-dimensional isometric schematic diagram of a partitioned stepped structure according to one implementation method;

[0038] Figure 12 yes Figure 11 The enlarged view shows the boundary structure between four steps of different heights arranged in a "cross" shape along the X and Y directions in the partitioned stepped structure.

[0039] Figure 13 This is a top view of a partitioned stepped structure according to one implementation method;

[0040] Figure 14 This is a schematic diagram of the pattern arrangement of a grid slot mask according to an embodiment of this application;

[0041] Figure 15 This is a schematic diagram of the pattern arrangement of another grid line slot mask according to an embodiment of this application;

[0042] Figure 16 This is a block diagram of an exemplary system having a storage device according to an embodiment of this application;

[0043] Figure 17A This is a schematic diagram of an exemplary memory card having a storage device according to an embodiment of this application; and

[0044] Figure 17B This is a schematic diagram of an exemplary solid-state drive (SSD) with a storage device according to an embodiment of this application. Detailed Implementation

[0045] The present application will now be described in detail with reference to the accompanying drawings. The exemplary embodiments mentioned herein are for illustrative purposes only and are not intended to limit the scope of the application. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0046] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not strictly to scale. As used herein, the terms “approximately,” “about,” and similar terms are used to indicate approximation, not degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art. It should be understood that in this specification, the terms “first,” “second,” etc., are used only to distinguish one feature from another and do not indicate any limitation on the features, and in particular, no order of precedence.

[0047] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to an example or illustration.

[0048] Furthermore, when terms such as “connection,” “covering,” and / or “formed on” are used in this application, they may indicate that the corresponding components are in direct or indirect contact, unless there are other explicit limitations or can be inferred from the context.

[0049] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. Furthermore, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0050] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Additionally, the substrate may comprise a wide variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer.

[0051] As used herein, the term "layer" refers to a portion of material having a certain thickness. A layer can be a region of a uniform or non-uniform continuous structure, wherein the non-uniform continuous structure has a thickness that is smaller or larger than that of the continuous structure.

[0052] As used herein, the term "three-dimensional memory" refers to a semiconductor device having vertically oriented strings of memory cell transistors on a laterally oriented substrate, such that the strings of memory cell transistors extend in a direction perpendicular or substantially perpendicular to the substrate. As used herein, the term "vertical" means perpendicular or substantially perpendicular to the lateral surface of the substrate.

[0053] Many specific details of this application, such as the structure, materials, dimensions, processing techniques, and methods of the devices, are described below to provide a clearer understanding of the application. However, as those skilled in the art will understand, this application may be implemented without adhering to these specific details.

[0054] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be executed in any order or in parallel.

[0055] This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0056] See Figure 1 According to one exemplary embodiment, a three-dimensional memory may include a stacked structure formed by alternating stacks of multiple gate layers 240 and insulating layers 230. The stacked structure is typically divided into a core region (not shown) and a step region. The core region may be used to form a string of memory cells (not shown), with each gate layer 240 serving as a gate line for each memory cell. The step region 300 may include multiple steps 300-1, which expose the stacked gate layers 240 respectively, with each step 300-1 corresponding to one gate layer 240. Gate contacts 600 may be formed on the steps 300-1 to lead out the memory cells corresponding to the gate layer 240. In one embodiment, to achieve electrical connection between the gate contacts 600 and the gate layers 240 in the stacked structure, contact holes are etched in the dielectric layer 500 covering the stacked structure to expose the top surfaces of each step 300-1 of the step region 300, and then the contact holes are filled with conductive material to form the gate contacts 600. However, with the increasing integration level and stacking number of layers in 3D memory, the required etching depth of the contact holes is also increasing. Therefore, during the formation of the contact holes, it is very easy for the gate layer 240 to be penetrated. In this case, the gate contact 600 formed by subsequently filling the contact hole with conductive material will cause short circuits between different gate layers 240, such as... Figure 2 As shown in region A, this could potentially lead to problems such as memory failure.

[0057] See Figures 2 to 5According to an exemplary embodiment, the problem of the gate layer 240 being penetrated during the formation of the contact hole, as described above, can be reduced by thickening the surface of each step 300-1 and forming a thickened portion 410 that is electrically connected to the corresponding gate layer 240.

[0058] Typically, a buffer layer of 400mm can be deposited in the step area at a depth of 300mm, such as... Figure 2 As shown; then the buffer layer 400 covering the end face and side wall of step 300-1 is removed, and the remaining buffer layer 400 on the top surface of step 300-1 is replaced with conductive material to form the required thickening portion 410 on each step 300-1.

[0059] However, since the step region 300 generally adopts a partitioned step structure, this structure forms composite steps in the bidirectional or even three-dimensional direction along the sidewalls of the stacked structure, which can reduce the occupied area of ​​the step region and help improve the device integration density, such as... Figure 11 As shown. Due to its complex structure, the stepped structure has varying heights between the steps. For example, there are boundary structures 310 between four steps that are arbitrarily adjacent to each other along the X and Y directions and located in two adjacent partitions (such as G1 and G2 partitions). Therefore, the stepped area 300 can have multiple boundary structures 310. During the deposition and etching of the buffer layer 400, many uncontrollable factors can easily cause defects at the locations of these boundary structures 310. For example, voids may be generated inside the buffer layer 400 during deposition. Figure 2 As shown, it is understandable that Figure 2 The location of the void is merely illustrative; that is, the void can occur on the partial step end face included in the interface structure 310 or anywhere else. Incomplete etching defects may occur during the removal of the buffer layer 400 covering the step end face, such as... Figure 3 As shown in Figure C, for example, a buffer layer remains on the end face of a portion of the step included in the junction structure 310 and on the top surface of a portion of the adjacent step near that end face; and at the junction structure 310, conditions such as... Figure 5 The defects shown include poor build-up. The presence of these defects can have varying degrees of adverse effects on subsequent process operations, for example, Figure 3 The residual buffer layer 400 shown in Figure C, when replaced with a conductive material in subsequent process operations, can cause short circuits between different gate layers, such as... Figure 4 As shown in D, this will affect device performance and production yield.

[0060] Figure 6 A flowchart of a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application is shown.

[0061] like Figure 6As shown, the method 1000 for fabricating a three-dimensional memory may include the following steps:

[0062] S1: A dielectric stack structure is formed on the substrate;

[0063] S2: Multiple partitions are formed along a first direction in the stepped region of the dielectric stacked structure, wherein each partition along a second direction includes multiple steps, and there is a boundary region between two adjacent partitions. Within the boundary region, the junction of adjacent steps constitutes a boundary structure; and

[0064] S3: Forming a gate wire slot structure that penetrates the dielectric stack structure; wherein part of the gate wire slot structure is located in the boundary region and penetrates at least one boundary structure.

[0065] Before step S1, a substrate is first provided. In various embodiments of this application, the substrate may be, for example, a single-crystal silicon (Si) substrate, a single-crystal germanium (Ge) substrate, a silicon-germanium (GeSi) substrate, a silicon carbide (SiC) substrate, or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or a substrate including other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC. The substrate 100 may also be a stacked structure, such as Si / SiGe, or other epitaxial structures, such as silicon-germanium-on-insulator (SGOI).

[0066] Next, according to step S1, a dielectric stack structure is formed on the substrate. Specifically, gate sacrificial layers 220 and insulating layers 230 can be alternately formed on the substrate to form a dielectric stack structure consisting of multiple gate sacrificial layers 220 and multiple insulating layers 230 stacked alternately. See [link to relevant documentation]. Figure 7In various embodiments of this application, the formation of a dielectric stack structure on the substrate can be achieved through one or more deposition processes. These deposition processes include, but are not limited to, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or any combination thereof. It should be understood that, without departing from the concept of this application, those skilled in the art can create any number and thickness of gate sacrificial layer 220 and insulating layer 230 as needed, and this application does not specifically limit their application. Furthermore, the materials of the gate sacrificial layer 220 and insulating layer 230 can be selected from suitable materials known in the art. For example, the gate sacrificial layer 220 can be a nitride layer (such as silicon nitride), and the insulating layer 230 can be an oxide layer (such as silicon oxide). Furthermore, those skilled in the art should understand that the dielectric stack structure may also include multiple sub-stacks, that is, the dielectric stack structure may be formed by a single sub-stack or by multiple sub-stacks stacked sequentially, and each sub-stack is formed by alternating stacking of multiple gate sacrificial layers 220 and multiple insulating layers 230.

[0067] Generally, a dielectric stack structure may include a core region and a stair step (SS) region. The core region can be used to form multiple memory cell strings arranged in an array. Each memory cell string includes multiple interconnected memory cells formed in a direction perpendicular to the substrate. The stair step region can be used for the contact portion of each gate layer to be led out. The stair step region may be located on the periphery of the core region or between adjacent core regions.

[0068] It should be noted that, in order to simplify the accompanying drawings and highlight the structural parts closely related to the technology of this application, only a portion of the stacked structure of the step region 300 is schematically shown in the drawings; the substrate and other parts of the stacked structure are not shown in the drawings. Figures 7 to 10 The image shows only a portion of the stacked structure of the step region 300.

[0069] Further, as described in step S2 above, a plurality of steps 300-1 are formed in the step region 300 of the dielectric stack structure, arranged in an array along two intersecting directions parallel to the substrate. (Reference) Figure 11 as well as Figure 13 , Figure 11 It is a three-dimensional axonometric view of the partitioned stepped structure. Figure 13This is a top view of the partitioned stepped structure. For ease of description, the three-dimensional directions of the three-dimensional memory are defined as the first axis X, the second axis Y, and the third axis Z, respectively. The first axis X and the second axis Y can be two axes that are parallel to the substrate and intersect each other, for example, perpendicularly. For example, the first axis X can be an axis extending along the core region toward the stepped region 300 for forming the gate contact, and the third axis Z can be an axis perpendicular to the substrate.

[0070] like Figure 11 As shown, according to one embodiment of this application, a staircase partition scheme (SDS) structure is formed in the step region 300, which may include multiple partitions formed along the second axis Y direction, for example... Figure 11 The G1, G2, G3, etc. shown are examples, and each partition may include multiple steps formed along the first axis X direction, such as... Figure 11 The steps shown (1, 2, 3…8, 9…) can reduce the footprint of the steps and improve device integration. As an example, Figure 11 In the partitioned steps shown, partition 1 G1 (including steps such as 3, 6, and 9) is located in the center. Partition 2 G2 (including steps such as 2, 5, and 8) and partition 3 G3 (including steps such as 1, 4, and 7) are arranged sequentially along the positive and negative directions of the second axis Y, and along the negative direction of the first axis X (i.e., towards the core area). The height of each level of steps in each partition increases sequentially along the third axis Z. Along the positive and negative directions of the second axis Y, the steps of each layer start from the edge partition (e.g., ... Figure 11 The partition from the third partition (G3) to the center partition (e.g.) Figure 11 The first partition (G1) also increases by 1 level sequentially. The partitioning method of the partition steps is only an example. In other embodiments, the partitioning method and number are not limited. Depending on different needs, the partition steps can have different partitions, such as 3 partitions, 4 partitions or more partitions.

[0071] Specifically, the aforementioned partitioned steps can be formed, for example, by using different partitioning plates, trimming the photoresist multiple times in the X and Y directions, and etching the exposed stacked layers after each trimming, thereby forming a partitioned step structure comprising multiple steps 300-1 in the step region 300. See [link to relevant documentation] Figure 12 , Figure 12 yes Figure 11 The enlarged view shows the boundary structure 310 in the partitioned stepped structure. A boundary region exists between any two adjacent partitions along the Y-axis, such as... Figure 11 and Figure 12 The N region is enclosed by a dashed line. Within the boundary region, the intersections of adjacent steps 300-1 can form an intersection structure 310. See also... Figure 12Along the Y-axis, steps P1 and P2 are adjacent, and steps P3 and P4 are adjacent. Along the X-axis, steps P1 and P3 are adjacent, and steps P2 and P4 are adjacent. Figure 11 It can be seen that steps P1 and P3 may belong to partition G2, and steps P2 and P4 may belong to partition G3. G2 and G3 are two adjacent partitions, with a boundary region N between them. Step P1 has an end face Q1, and step P2 has an end face Q2. The four steps P1, P2, P3, and P4 share a common edge line L1. In the boundary region N, the intersection of the four adjacent steps P1, P2, P3, and P4 can form a boundary structure 310. That is, the boundary structure 310 includes the partial structure around the common edge line L1 in the boundary region N. It can be understood that the boundary structure 310 includes a portion of the end face Q1 of step P1, and also a portion of the end face Q2 of step P2. It can be understood that a similar boundary structure 310 can exist between any four steps 300-1 arranged in a "cross" or approximately "cross" configuration with different heights along the X and Y axes.

[0072] As can be seen from the above description of the partitioned steps, each step 300-1 has a height difference along the third axis Z. That is, along the first axis X, any step 300-1 and its two adjacent steps 300-1 have a height difference, and along the second axis Y, any step 300-1 and its two adjacent steps 300-1 also have a height difference. Furthermore, any four steps 300-1 arranged in a roughly "cross" shape along the X and Y axes have a boundary structure 310 in the middle. More specifically, any two adjacent steps 300-1 along the second axis Y and the two steps 300-1 adjacent to them along the first axis X can be regarded as any four steps 300-1 arranged in a "cross" or approximately "cross" shape along the X and Y axes, which have a boundary line L1 along the third axis Z located in the middle of these four steps. Figure 12 The four steps 300-1 share the same edge line L1, and the boundary structure 310 can also be understood as a part of the structure of the "boundary" of the four steps 300-1 around the shared edge line L1. Therefore, it can be understood that the step area 300 has multiple similar boundary structures 310.

[0073] Based on the descriptions above, due to the complexity of the structure at junction 310, there are many uncontrollable factors, which can easily lead to defects such as voids, end face etching residues, and poor accumulation in this area. The existence of these defects will have varying degrees of adverse effects on subsequent process operations, such as causing short circuits between different gate layers, which in turn will affect device performance and production yield.

[0074] To address the aforementioned adverse effects of the interface structure 310, according to step S3 of method 1000 above, a gate line slot is formed that penetrates the dielectric stack structure and extends to the substrate. The gate line slot may include the void formed after removing at least one interface structure 310. That is, during the process of forming the gate line slot, at least one interface structure 310 can be removed, thereby at least to some extent reducing the aforementioned adverse effects caused by the presence of the interface structure 310.

[0075] According to one embodiment of this application, a method for forming gate line slots that penetrate a dielectric stack structure and extend to a substrate may include: forming a mask on a side of the dielectric stack structure away from the substrate; patterning the mask to form a gate line slot arrangement pattern therein including at least one gate line slot pattern 210, the gate line slot pattern 210 covering at least one boundary structure 310 along the length direction, i.e., along the first axis X direction (see...). Figure 14 or Figure 15 ); and by etching the dielectric stack structure through the gate line slot arrangement pattern, removing the portion of the dielectric stack structure including the boundary structure 310, forming a gate line slot that penetrates the dielectric stack structure and extends to the substrate.

[0076] In one embodiment, the length of the grid line slot may extend along the direction of the first axis X. Figure 14 and Figure 15 The figures shown are schematic diagrams illustrating the pattern arrangements of two different grid slot mask templates. (See attached diagram.) Figure 14 or Figure 15 The 210 shown is a grid line slot pattern formed on a photomask, and the length of the grid line slot pattern 210 extends along the first axis X. In one embodiment, the break between two adjacent grid line slot patterns 210 along the first axis X can be located between two adjacent boundary structures 310. Figure 15 In this embodiment, the break between the two grid line slot patterns 210-1 and 210-2 can be located between the two boundary structures 310-1 and 310-2. In one implementation, grid line slots can be formed in each boundary region, such as... Figure 15 The middle stepped area 300 includes multiple sub-areas such as G1, G2, and G3, with a boundary area between each pair of adjacent sub-areas. Figure 15 The diagram shows the boundary regions N1, N2, N3, and N4. Figure 15The mask template shown has gate line slot patterns 210 corresponding to each of the N1-N4 boundary regions. In one embodiment, each gate line slot pattern 210 located in the boundary region can cover at least one boundary structure 310 along its length. Therefore, each gate line slot forming a through-dielectric stack structure and extending to the substrate via the gate line slot pattern 210 can include gaps formed after removing at least one of the boundary structures 310. Further, the width of the removed boundary structure 310 along the second axis Y can be equal to the width of the gate line slot pattern 210 along the second axis Y. Furthermore, the centerline of the gate line slot pattern 210 (or gate line slot) parallel to the first axis X can pass through the center point of the boundary structure 310 it covers.

[0077] Figure 14 This is a schematic diagram of the pattern arrangement of a grid slot mask template according to an embodiment of this application. Figure 15 This is a schematic diagram of the pattern arrangement of another grid slot mask according to an embodiment of this application. For example... Figure 14 and Figure 15 As shown, according to the embodiments of this application, the arrangement of each grid line slot pattern 210 is optimized, so that multiple boundary structures 310 can be removed while forming the grid line slots. It is understood that, as needed, the boundary structures 310 can be selectively removed by adjusting the size and arrangement of the aforementioned grid line slot patterns 210. For example, in one embodiment, the grid line slot may include the gap formed after removing all boundary structures 310. In another embodiment, the grid line slot may include the gap formed after removing more than 80% of the boundary structures 310. This application does not specifically limit this.

[0078] As an example, a dielectric stack structure is etched via a gate line slot pattern formed on the photomask to remove a portion of the dielectric stack structure including at least one interface structure 310, forming gate line slots that penetrate the dielectric stack structure and extend to the substrate. Specifically, the formation process includes, but is not limited to, photolithography, etching, and wet cleaning. In some embodiments, an etching process such as deep reactive ion etching (DRIE) can be used to form the gate line slots penetrating the dielectric stack structure and extending to the substrate in a single step. In other embodiments, wet etching, for example using phosphoric acid as an etchant, can be used to etch and form the gate line slots penetrating the dielectric stack structure and extending to the substrate. This application does not specifically limit these methods.

[0079] As mentioned earlier, the structure of the partitioned steps is relatively complex, with varying heights between the step surfaces. In particular, the multiple boundary structures 310 within the partitioned steps negatively impact the aforementioned operations of forming buffer layers on the steps and etching buffer layers on the step end faces and sidewalls. For example, a series of defects, including voids, etching residues, and poor deposition, are more likely to form in the boundary structure 310 area. Some of these defects can lead to short circuits between gate layers in the final 3D memory, affecting device performance. According to the embodiments of this application, without altering the existing process flow, multiple boundary structures 310 can be removed while forming the gate line gaps. This reduces the various risks associated with the fabrication of the 3D memory due to the aforementioned defects easily formed at each boundary structure 310, thus improving and ensuring the device performance of the fabricated 3D memory.

[0080] According to one embodiment of this application, after forming multiple steps 300-1 in the step region 300 of the dielectric stack structure and before forming the grid line gaps penetrating the dielectric stack structure, method 1000 may further include: forming a buffer layer 400 covering the dielectric stack structure including the step region 300; and removing a portion of the buffer layer 400 covering the end face and sidewall of the step 300-1, retaining a portion of the buffer layer 400 covering the top surface of the step 300-1, and making the portion of the buffer layer 400 have a gap with the end face and sidewall of the adjacent upper step 300-1.

[0081] like Figure 7 As shown, the buffer layer 400 can cover the gate sacrificial layer 220 exposed on the top surface of the step 300-1. The portion of the buffer layer 400 formed on the end face and sidewalls of the step 300-1 is removed, leaving the buffer layer 400 at the top of each step, as shown. Figure 8 As shown. Removing the buffer layer 400 formed on the step end face and side wall allows the buffer layers 400 on the top surfaces of two adjacent steps to be spaced apart from each other. Therefore, in subsequent process steps, when the buffer layer 400 on the top surface of the step is replaced with a conductive material to form the thickened portion 410 of the gate end (see the description below), this spacing can effectively prevent incorrect connections between different gate layers.

[0082] As an example, a buffer layer 400 covering the top surface, end face, and sidewalls of each step 300-1, including the step region 300, can be formed by one or more deposition processes, including but not limited to atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or any combination thereof. For example, the buffer layer 400 can be formed by an atomic layer deposition process. As an example, the material used to form the buffer layer 400 may be silicon nitride, and more specifically, TSSIN with a certain proportion may be used. For example, when using phosphoric acid or the like as an etchant to wet-etch the silicon nitride on the end face and sidewalls of the step 300-1, the silicon nitride on the end face and sidewalls of the step 300-1 can have an etching rate about two to three times that of normal SIN due to its lower density. However, this application is not limited to this, and other suitable materials may also be used to form the buffer layer 400.

[0083] As an example, the method of removing the buffer layer 400 formed on the end face and sidewall of step 300-1 may include, but is not limited to, dry etching such as deep reactive ion etching (DRIE), or other methods such as wet etching using phosphoric acid as an etchant.

[0084] According to one embodiment of this application, after forming each level of the partitioned step structure 300-1 and before forming the gate wire gaps that penetrate the dielectric stack structure and extend to the substrate, the method 1000 for fabricating a three-dimensional memory may further include: forming a dielectric layer 500 covering the step region 300 on the dielectric stack structure, such as... Figure 9 As shown. The medium layer 500 can cover the buffer layer 400 on the top surface of each step 300-1, as well as the exposed step end faces and sidewalls of each step 300-1, and can fill the gap between the buffer layer 400 on the top surface of the step 300-1 and the end face of the adjacent upper step 300-1, such as... Figure 9 The E region shown in the diagram provides a flat upper surface for the dielectric stack structure.

[0085] As an example, the dielectric layer 500 can be formed by depositing an oxide, which may be selected from, for example, a silicon oxide-based material. In one embodiment of this application, the dielectric layer 500 may be formed by filling silicon oxide based on TEOS (tetraethyl orthosilicate). The dielectric layer 500 may be a multilayer structure, first forming a first sub-film layer with good step coverage, such as silicon oxide (SiO2) deposited by high-density plasma (HDP) or silicon oxide deposited by atomic layer deposition (ALD); then continuing to form a second sub-film layer with high filling efficiency, such as silicon oxide based on TEOS (TESO-based SiO2). The density of the first sub-film layer is higher than that of the second sub-film layer, thereby the first sub-film layer has good step coverage, while the second sub-film layer has high filling efficiency.

[0086] As an example, the dielectric layer 500 can be further planarized using processes such as chemical mechanical polishing, so that the dielectric layer 500 provides a substantially flat upper surface for dielectric stack structures such as the step region 300 and the core region (not shown).

[0087] According to one embodiment of this application, after forming the gate line gap, method 1000 may further include: removing the gate sacrificial layer 220 and the buffer layer 400 located on the top surface of step 300-1 in the dielectric stack structure via the gate line gap to form a sacrificial gap; filling the formed sacrificial gap with conductive material to form the gate layer 240 and the thickened portion 410 at the gate end, such as... Figure 10 As shown.

[0088] As an example, in this step, the gate line gaps can be used as etchant channels to remove the gate sacrificial layer 220 in the dielectric stack structure using, for example, isotropic etching. Isotropic etching can be performed using selective wet etching or vapor phase etching. In wet etching, an etching solution is used as the etchant, and the semiconductor structure is immersed in the etching solution. In vapor phase etching, an etching gas is used as the etchant, and the semiconductor structure is exposed to the etching gas. The insulating layer 230 and the gate sacrificial layer 220 in the dielectric stack structure are silicon oxide (SiO2). X ) and silicon nitride (SiN) X In the case of wet etching, phosphoric acid solution can be used as the etchant, while in vapor phase etching, one or more of C4F8, C4F6, H2F2, and O2 can be used as the etchant. During the etching step, the etchant fills the gate line gaps and gradually etches the gate sacrificial layer 220 into the dielectric stack structure. Due to the selectivity of the etchant, this etching removes the gate sacrificial layer 220 from the dielectric stack structure, and further removes the buffer layer 400 at the top surface of each step 300-1 at the end of the gate sacrificial layer 220 in the step region 300, while retaining the insulating layer 230.

[0089] After removing the gate sacrificial layer 220 and the buffer layer 400, a gate layer 240 and a thickened portion 410 at the gate end can be formed within the formed sacrificial gap by one or more deposition processes. The conductive material deposited on the gate layer 240 and the thickened portion 410 at the gate end includes, but is not limited to, tungsten (W).

[0090] The thickened portion 410 formed on the top surface of each step 300-1 thickens the ends of each gate layer, which helps to reduce the occurrence of breakdown of the gate layer 240 when forming gate contact holes later.

[0091] According to one embodiment of this application, after replacing the gate sacrificial layer 220 and the buffer layer 400 with the gate layer 240 and the thickened portion 410 at the gate end via the gate line gap, the method 1000 may further include: forming a contact hole (not shown) that penetrates the dielectric layer and extends to the thickened portion 410; and filling the contact hole with a conductive material to form a gate contact portion 600.

[0092] The contact hole may extend only to the top surface of the thickened portion 410. According to another exemplary embodiment of this application, even if etching occurs during the etching process to form the contact hole, the thickened portion 410 has a certain thickness, which can effectively prevent the etching from breaking through the gate layer 240 connected to the thickened portion 410, thereby avoiding short circuits between different gate layers and ensuring the electrical performance of the three-dimensional memory.

[0093] As an example, multiple contact holes extending through the dielectric layer and into the thickened portion 410 can be formed in the stepped region 300 using photolithography and etching processes. Then, conductive materials such as titanium nitride or tungsten alloys are filled into the contact holes to form the gate contact portion 600.

[0094] According to one embodiment of this application, the gate contact 600 may be located on a step 300-1 where all adjacent boundary structures 310 have been removed; that is, all boundary structures 310 adjacent to the step 300-1 where the gate contact 600 is formed may be removed. Referring again... Figure 15 ,Depend on Figure 15 As can be seen from the design scheme shown, for any step 300-1 on which the gate contact portion 600 needs to be formed according to the design scheme, the two or four boundary structures 310 adjacent to the step 300-1 are covered by the gate line slot pattern 210 on the mask shown in the figure. These boundary structures will be removed at the same time as the gate line slot is formed.

[0095] According to one embodiment of this application, after replacing the gate sacrificial layer 220 and the buffer layer 400 with the gate layer 240 and the thickened portion 410 at the gate end via gate line slots, method 1000 may further include: filling the gate line slots with a dielectric material (e.g., silicon oxide) to form a gate line slot structure. Multiple gate line slot structures formed in multiple gate line slots can constitute a gate line slot structure for a three-dimensional memory.

[0096] As mentioned earlier, the presence of multiple boundary structures 310 in the partitioned step structure seriously affects the deposition quality of the buffer layer above the step, as well as the etching quality of the buffer layer on the end face and sidewall of the step. It is easy to generate many defects such as deposition voids, poor accumulation, and etching residues on the end face and sidewall, which can lead to problems such as short circuits between gate layers, affecting device performance.

[0097] The three-dimensional memory fabrication method provided in this application, by optimizing the arrangement of gate line gaps, can remove multiple boundary structures 310 of the aforementioned partitioned step structure while forming the gate line gaps, without changing the original manufacturing process. This can remove many defects generated by the buffer layer 400 during the formation and etching process at these boundary structures 310, thereby effectively avoiding quality problems that may occur in subsequent processes due to these defects, such as poor contact in some gate layer circuits or incorrect connection of different gate layers, which is beneficial to improving device performance and product yield.

[0098] On the other hand, this application also provides a three-dimensional memory. According to one embodiment of this application, the three-dimensional memory may include: a substrate and a stacked structure located on one side of the substrate. The stacked structure may include, for example, a plurality of memory blocks arranged along the Y direction; adjacent memory blocks may be separated by a gate slot structure, and each memory block may include a step region 300, see [link to relevant documentation]. Figure 11 The stepped area 300 may include multiple sections arranged along the Y direction, such as sections G1, G2, and G3. Each section may include multiple steps 300-1 arranged along the X direction. Adjacent sections may have a boundary area, such as... Figure 11 N represents the boundary region between adjacent partitions G2 and G3. (Combined with...) Figure 12 Within the boundary region, the junction of adjacent steps 300-1 can form a junction structure 310. In other words, a junction structure 310 can be formed between any four steps 300-1 arranged in a "cross" or near-cross pattern along two axes (such as the X-axis and Y-axis) that are parallel to the substrate and intersect each other, for example, perpendicularly. Furthermore, the three-dimensional memory may also include a gate line slot structure that penetrates the stacked structure and extends to the substrate. The gate line slot structure may be located in the aforementioned boundary region and may penetrate at least one junction structure 310.

[0099] In some implementations, the length of the grid wire slot structure located in the boundary region can be along, for example... Figure 14 Or it can extend along the X-axis direction as shown in 15. In other words, the length of the gate slot structure can extend in a direction parallel to the stacked structure 200 from the core region (not shown) to the step region 300. The gate slot structure located in the boundary region can be broken between two adjacent boundary structures 310, such as Figure 15 As shown, the grid line slot structure can be interrupted between adjacent boundary structures, such as 310-1 and 310-2. In some embodiments, each boundary region may be provided with a grid line slot structure, see again. Figure 15 The stepped area 300 includes multiple zones such as G1, G2, and G3, with a boundary zone between each pair of adjacent zones. Figure 15 The diagram shows the boundary regions N1, N2, N3, and N4. Figure 15 The mask template shown has corresponding grid line slot patterns 210 within each boundary region N1-N4, and each grid line slot pattern 210 covers at least one boundary structure 310. It can be understood that the area covered by the grid line slot pattern 210 corresponds to the area forming the grid line slot structure in the stacked structure. Therefore, the grid line slot structures located in the boundary regions of the stacked structure can all penetrate at least one boundary structure 310.

[0100] In some embodiments, the stacked structure 200 may include alternately stacked insulating layers 230 and gate layers 240, with thickened portions 410 formed at the ends of the gate layers 240, such as... Figure 10 As shown. The thickened portion 410 may be formed of a conductive material and may be located on the top surface of the step 300-1 and connected to the corresponding gate layer 240.

[0101] In some embodiments, the three-dimensional memory may further include a dielectric layer 500 covering at least the step region 300, see [link to relevant documentation]. Figure 10 The dielectric layer 500 may cover the thickened portion 410 located on the top surface of the step 300-1, as well as the end face and sidewalls of the step 300-1. The dielectric layer 500 may space the thickened portion 410 and the end face and sidewalls of another step 300-1 adjacent to the thickened portion 410. The dielectric layer 500 may also provide a flat upper surface for the stacked structure.

[0102] In some embodiments, the three-dimensional memory may further include a gate contact 600 that penetrates the dielectric layer 500 and extends to the thickened portion 410. The gate contact 600 may be formed of a conductive material.

[0103] In some embodiments, part or all of the boundary structure 310 adjacent to the step 300-1 where the gate contact portion 600 is formed may be removed. The step 300-1 where the gate contact portion 600 is formed may be adjacent to the gate line slot structure.

[0104] Since the content and structure described in the preparation method 1000 above can be fully or partially applied to the three-dimensional memory described here, related or similar content will not be repeated here.

[0105] This application also provides a storage system, see [link to relevant documentation] Figure 16 , Figure 17A as well as Figure 17B The storage system 2200, 2000a, or 2000b shown in the figure may include one or more storage devices 2202 and a memory controller 2201. The storage device 2202 may include one or more three-dimensional memories provided according to any of the exemplary embodiments described above in this application. The memory controller 2201 may be electrically connected to at least one of the three-dimensional memories and may be used to control at least one of the three-dimensional memories.

[0106] Figure 16 This is a block diagram of an exemplary system 2000 with a storage device according to an embodiment of this application. System 2000 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein. Figure 16As shown, system 2000 may include host 2100 and storage system 2200. Storage system 2200 has one or more storage devices 2202 and memory controller 2201. Storage device 2202 may include a three-dimensional memory as described in any of the exemplary embodiments described above. Host 2100 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). Host 2100 may be configured to send data to or receive data from storage device 2202. Storage device 2202 may also include phase-change memory (RRAM), magnetoresistive memory (MRAM), ferroelectric memory (FRAM), NAND flash memory, NOR flash memory, vertical NAND flash memory, spin-transfer torque memory (STT-RAM), etc. In some embodiments, memory controller 2201 may be coupled to storage device 2202 and host 2100 and configured to control storage device 2202. In some embodiments, the memory controller 2201 is designed to operate in low-duty-cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In some embodiments, the memory controller 2201 is designed to operate in high-duty-cycle environments such as SSDs or embedded multimedia cards (eMMCs) used for data storage in mobile devices (such as smartphones, tablets, laptops, etc.) and enterprise storage arrays. The memory controller 2201 can be configured to control the operation of the storage device 2202, such as read operations, erase operations, and programming operations. The memory controller 2201 can also be configured to manage various functions regarding data stored or to be stored in the storage device 2202, including but not limited to bad block management, garbage collection, wear leveling, etc. Any other suitable function, such as formatting the storage device 2202, can also be performed by the memory controller 2201. The memory controller 2201 can communicate with external devices (e.g., host 2100) according to specific communication protocols. For example, the memory controller 2201 can communicate with external devices through at least one of various interface protocols, such as USB protocol, Multimedia Card (MMC) protocol, Peripheral Component Interconnect (PCI) protocol, Serial Bus (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial-ATA protocol, Parallel-ATA20 protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, FireWire protocol, etc.

[0107] Figure 17A This is a schematic diagram of an exemplary memory card having a storage device according to an embodiment of this application.

[0108] The memory controller 2201 and one or more storage devices 2202 can be integrated into various types of storage devices, for example, included in the same package, such as a universal flash memory (UFS) package or an eMMC package. That is, the storage system 2200 ( Figure 16 This can be implemented and packaged into different types of terminal electronic products. For example... Figure 17A In one example shown, the memory controller 2201 and a single storage device 2202 may be integrated into the memory card 2000a. The memory card 2000a may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 2000a may further include a connection between the memory card 2000a and a host (e.g., Figure 16 The memory card connector 2203 is coupled to the host 2100 in the host.

[0109] Figure 17B This is a schematic diagram of an exemplary solid-state drive (SSD) with a storage device according to an embodiment of this application.

[0110] In such Figure 17B In one example shown, the memory controller 2201 and multiple storage devices 2202 can be integrated into the SSD 2000b. The SSD 2000b may also include interfaces for connecting the SSD 2000b to a host computer (e.g., Figure 16 The host 2100 in the SSD is coupled to the SSD connector 2204.

[0111] Although exemplary fabrication methods and structures of three-dimensional memories have been described herein, it is understood that one or more features may be omitted, substituted, or added to the structure of the three-dimensional memory. Furthermore, the layers and materials described are merely exemplary.

[0112] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A three-dimensional memory, characterized in that, include: A stacked structure includes alternating stacked insulating layers and gate layers. The stacked structure also includes a stepped region, which includes multiple partitions arranged along a first direction. There is a boundary region between two adjacent partitions. Each partition includes multiple steps arranged along a second direction. Within the boundary region, the junction of adjacent steps forms a junction structure. The first direction and the second direction intersect each other and are perpendicular to the stacking directions of the insulating layer and the gate layer, respectively. as well as A gate line slot structure that penetrates the stacked structure; wherein a portion of the gate line slot structure is located in the boundary region and penetrates at least one of the boundary structures.

2. The three-dimensional memory according to claim 1, wherein, The grid line slot structure located in the boundary region extends along the second direction.

3. The three-dimensional memory according to claim 2, wherein, The grid line slot structure located in the boundary region is broken between two adjacent boundary structures.

4. The three-dimensional memory according to claim 2 or 3, wherein, Each of the aforementioned boundary zones is provided with the grid line slot structure.

5. The three-dimensional memory according to claim 4, wherein, Each of the grid line slot structures located in the boundary region penetrates at least one of the boundary structures.

6. The three-dimensional memory according to claim 1 or 2, wherein, The top surface of the step is the top surface of the gate layer. The three-dimensional memory also includes a thickened portion located on the top surface of each step, wherein the thickened portion is formed of a conductive material and there is a gap between the thickened portion and the end face of the upper step adjacent to the step where the thickened portion is located.

7. The three-dimensional memory according to claim 6, wherein, The three-dimensional memory also includes: A dielectric layer, at least covering the stepped area, separates the end faces of each thickened portion and adjacent steps.

8. The three-dimensional memory according to claim 7, wherein, The three-dimensional memory also includes: The gate contact, formed of a conductive material, penetrates the dielectric layer and extends to the thickened portion.

9. A method for fabricating a three-dimensional memory, characterized in that, include: A dielectric stack structure is formed on the substrate; In the stepped region of the dielectric stack structure, multiple partitions are formed along a first direction, wherein each partition along a second direction includes multiple steps, and a boundary region exists between adjacent partitions, within which the junction of adjacent steps constitutes a boundary structure; the first direction and the second direction intersect each other and are perpendicular to the stacking direction of the dielectric stack structure; and A gate wire slot structure is formed that penetrates the dielectric stack structure; wherein a portion of the gate wire slot structure is located in the boundary region and penetrates at least one of the boundary structures.

10. The method according to claim 9, wherein, The dielectric stack structure includes multiple alternately stacked gate sacrificial layers and insulating layers, wherein the gate sacrificial layers are exposed on the top surface of the step, and Before forming the gate wire gap structure through the dielectric stack structure, the method further includes: A buffer layer is formed covering the top surface of the step, with a gap between the end face of the adjacent upper step; A medium layer is formed that at least covers the buffer layer and fills the gap.

11. The method according to claim 10, wherein, The gate wire gap structure forming the dielectric stack structure includes: A mask template is formed on the side of the dielectric stack structure away from the substrate; The mask is patterned to form a grid line slot pattern therein, which includes at least one grid line slot pattern covering at least one of the boundary structures along the length direction; The dielectric stack structure is etched via the gate line slot pattern to remove the portion of the dielectric stack structure including the boundary structure, thereby forming gate line slots penetrating the dielectric stack structure; and The grid line slot structure is formed in the grid line slot.

12. The method according to claim 9, wherein, The length of the grid line slot structure located in the boundary region extends along the second direction.

13. The method according to claim 12, wherein, The grid line slot structure located in the boundary region is broken between two adjacent boundary structures.

14. The method according to claim 12 or 13, wherein, Each of the aforementioned boundary zones is provided with the grid line slot structure.

15. The method according to claim 14, wherein, Each of the grid line slot structures located in the boundary region penetrates at least one of the boundary structures.

16. The method according to claim 11, wherein, The method further includes: The gate sacrificial layer and the buffer layer in the dielectric stack structure are removed through the gate line gap to form a sacrificial gap; A conductive material is filled into the sacrificial gap to form a gate layer and a thickened portion at the original locations of the gate sacrificial layer and the buffer layer in the dielectric stack structure, respectively. Forming contact holes that penetrate the dielectric layer and extend to the thickened portion; and A gate contact is formed by filling the contact hole with conductive material.

17. The method according to claim 16, wherein, The conductive material includes tungsten.

18. The method according to claim 10, wherein, The buffer layer forming a gap between the top surface of the step and the end face of the adjacent upper step includes: Form a buffer layer that at least covers the stepped area; and At least a portion of the buffer layer covering the end face of the step is removed, while the portion of the buffer layer covering the top surface of the step is retained, and a gap is created between this portion of the buffer layer and the end face of the adjacent upper step.

19. The method according to claim 10, wherein, The material of the buffer layer includes silicon nitride.

20. A storage system, characterized in that, include: At least one three-dimensional memory as described in any one of claims 1-8; as well as A memory controller, electrically connected to at least one of the three-dimensional memories, is used to control at least one of the three-dimensional memories.

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