Integrated circuit device and method of formation

Abstract

An integrated circuit (IC) device includes: a functional circuit electrically coupled to a first power node and operable by a first power supply voltage on the first power node; and a power control circuit including a first transistor and a second transistor of different types. The first transistor includes a gate terminal configured to receive a control signal, a first terminal electrically coupled to the first power node, and a second terminal electrically coupled to a second power node. The second transistor includes a gate terminal configured to receive a control signal and first and second terminals configured to receive a predetermined voltage. The first transistor is configured to connect or disconnect the first and second power nodes in response to the control signal to provide or disconnect power to the functional circuit. Embodiments of the invention also relate to a method of forming an integrated circuit device.

Description

Technical Field

[0001] Embodiments of the present invention relate to integrated circuit devices and methods of forming them. Background Technology

[0002] Integrated circuit (“IC”) devices or semiconductor devices include one or more devices represented in an IC layout diagram (also known as a “layout diagram”). A layout diagram is hierarchical, comprising modules that perform higher-level functions according to IC design specifications. Modules are typically composed of combinations of cells, each cell representing one or more semiconductor structures configured to perform a specific function. Cells with pre-designed layout diagrams (sometimes called standard cells) are stored in a standard cell library (hereinafter referred to as the “library” or “cell library”) and can be accessed through various tools, such as electronic design automation (EDA) tools, to generate, optimize, and verify IC designs.

[0003] Minimizing the power consumption of semiconductor devices is a design consideration. One approach involves including head circuitry (also known as a "head switch") and / or tail circuitry (also known as a "tail switch") between the power node (or rail) and the functional circuitry. Power consumption is reduced by disconnecting the head switch and / or tail switch when the functional circuitry is inactive. Summary of the Invention

[0004] According to one aspect of an embodiment of the present invention, an integrated circuit device is provided, comprising: a functional circuit electrically coupled to a first power node and operable by a first power supply voltage on the first power node; and a power control circuit including a first transistor of a first type and a second transistor of a second type different from the first type, wherein the first transistor includes: a gate terminal configured to receive a control signal, a first terminal electrically coupled to the first power node, and a second terminal electrically coupled to the second power node; the second transistor includes: a gate terminal configured to receive a control signal, and the first and second terminals configured to receive a predetermined voltage; and the first transistor is configured to connect or disconnect the first and second power nodes in response to the control signal to provide or disconnect power to the functional circuit.

[0005] According to another aspect of the present invention, an integrated circuit device is provided, comprising: a first active region of a first semiconductor type; a second active region of a second semiconductor type, the second semiconductor type being different from the first semiconductor type; a plurality of gate regions extending across the first and second active regions and over the first and second active regions; a plurality of contact structures located over corresponding portions of the first and second active regions and electrically contacting the corresponding portions of the first and second active regions; and a conductive layer located over the plurality of gate regions and the plurality of contact structures. The conductive layer includes: a first conductive pattern electrically coupling a first set of contact structures over the first active region together; a second conductive pattern electrically coupling a second set of contact structures over the first active region together; a third conductive pattern electrically coupling the plurality of gate regions together; and a fourth conductive pattern electrically coupling the contact structures over the second active region together.

[0006] According to another aspect of the present invention, a method for forming an integrated circuit device is provided, comprising: forming a first active region of a first semiconductor type and a second active region of a second semiconductor type different from the first semiconductor type over a substrate, the first active region and the second active region extending along a first axis; forming a gate structure over the first active region and the second active region, the gate structure extending continuously from the first active region to the second active region along a second axis perpendicular to the first axis. The gate structure and the first active region are configured as a first transistor of a first type, and the gate structure and the second active region are configured as a second transistor of a second type different from the first type. A conductive layer is deposited over the gate structure and the first and second active regions, and the conductive layer is patterned into a plurality of conductive patterns extending along the first axis. The plurality of conductive patterns include: a first conductive pattern electrically coupled to a first terminal of the first transistor; a second conductive pattern electrically coupled to a second terminal of the first transistor; a third conductive pattern electrically coupled to the first terminal of the first transistor; and a fourth conductive pattern electrically coupled to the first terminal and the second terminal of the second transistor to form the second transistor as a dummy transistor. Attached Figure Description

[0007] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components can be arbitrarily increased or decreased.

[0008] Figure 1 This is a block diagram of an IC device according to some embodiments.

[0009] Figure 2 This is a block diagram of the circuit region of an IC device according to some embodiments.

[0010] Figures 3A-3E These are schematic circuit diagrams of various head circuits according to some embodiments.

[0011] Figures 4A-4E This is a schematic diagram of the layout of various header units according to some embodiments.

[0012] Figure 5A It is an edge of an IC device according to some embodiments Figure 4A A schematic cross-sectional view of line VV.

[0013] Figure 5B It is an IC device according to some embodiments. Figure 4A A schematic cross-sectional view of the line V'-V'.

[0014] Figure 6A This is a schematic circuit diagram of the head circuit according to some embodiments.

[0015] Figure 6B This is a schematic diagram of the layout of the header unit according to some embodiments.

[0016] Figures 7A-7B This is a table that schematically illustrates various layout configurations with different unit heights according to some embodiments.

[0017] Figures 8A-8E These are schematic circuit diagrams of various tail circuits according to some embodiments.

[0018] Figure 9A This is a schematic diagram of the layout of the tail unit according to some embodiments.

[0019] Figure 9B This is a schematic circuit diagram of the head circuit according to some embodiments.

[0020] Figure 9C This is a schematic diagram of the layout of the tail unit according to some embodiments.

[0021] Figures 10A-10C These are flowcharts of various methods according to some embodiments.

[0022] Figure 11A This is a schematic top view of a planar transistor according to some embodiments. Figure 11B It is the edge of the planar transistor Figure 11A A schematic cross-sectional view of line X1-X1. Figure 11C It is the edge of a planar transistor Figure 11A A schematic cross-sectional view of line Y1-Y1.

[0023] Figure 12AThis is a schematic top view of a fin field-effect transistor (FINFET) according to some embodiments. Figure 12B It is the edge of FINFET Figure 12A A schematic cross-sectional view of line X2-X2. Figure 12C It is the edge of FINFET Figure 12A A schematic cross-sectional view of line Y2-Y2.

[0024] Figure 13A This is a schematic top view of a nanosheet FET according to some embodiments. Figure 13B It is the edge of nanosheet FET Figure 13A A schematic cross-sectional view of line X3-X3. Figure 13C It is the edge of nanosheet FET Figure 13A A schematic cross-sectional view of line Y3-Y3.

[0025] Figure 14A This is a schematic top view of a nanowire FET according to some embodiments. Figure 14B It is along the nanowire FET Figure 14A A schematic cross-sectional view of line X4-X4. Figure 14C It is along the nanowire FET Figure 14A A schematic cross-sectional view of line Y4-Y4.

[0026] Figure 15 This is a block diagram of an electronic design automation (EDA) system according to some embodiments.

[0027] Figure 16 This is a block diagram of an IC device manufacturing system and its associated IC manufacturing process according to some embodiments. Detailed Implementation

[0028] The following disclosure provides numerous different embodiments or examples of various features for carrying out the subject matter of this invention. Specific examples of components, materials, values, steps, arrangements, etc., are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. Other components, materials, values, steps, arrangements, etc., are contemplated. For example, in the following description, forming a first component on or above a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout the various embodiments of the invention. Such repetition is merely for brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0029] Furthermore, for ease of description, spatial relation terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spatial relation terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relation descriptors used herein can be interpreted accordingly.

[0030] The head or tail circuitry includes a first transistor and a second transistor of a different type from the first transistor. For example, when the first transistor is a p-channel metal-oxide-semiconductor (PMOS) transistor, the second transistor is an n-channel metal-oxide-semiconductor (NMOS) transistor, and vice versa. In some embodiments, the first transistor is configured to controllably supply or cut off power to the functional circuitry, and the second transistor is electrically coupled as a dummy transistor. In at least one embodiment, the electrical coupling of the second transistor as a dummy transistor allows the electrical connections of the first transistor to be arranged toward the second dummy transistor, which frees up wiring resources on the first transistor. In one or more embodiments, the freed wiring resources can be used to provide one or more additional electrical connections for the first transistor. As a result, the head or tail circuitry according to some embodiments has one or more advantages compared to other methods in which the second transistor remains unused, such as increased power current density, reduced on-resistance (R0), etc. ON ), reduced area, etc.

[0031] Figure 1 This is a block diagram of an IC device 100 according to some embodiments.

[0032] exist Figure 1In this embodiment, IC device 100 includes macros such as macro 102. In some embodiments, macro 102 includes one or more of a memory, power grid, one or more cells, inverters, latches, buffers, and / or any other type of circuit arrangement that can be digitally represented in a cell library. In some embodiments, macro 102 is understood in the context of an architecture similar to modular programming, where subroutines / procedures are called by a main program (or other subroutines) to perform a given computational function. In this case, IC device 100 uses macro 102 to perform one or more given functions. Therefore, in this context and in terms of architecture, IC device 100 is similar to a main program and macro 102 is similar to a subroutine / procedure. In some embodiments, macro 102 is a soft macro. In some embodiments, macro 102 is a hard macro. In some embodiments, macro 102 is a soft macro digitally described in register-transfer-level (RTL) code. In some embodiments, synthesis, placement, and routing have not yet been performed on macro 102, allowing the soft macro to be synthesized, placed, and routed for various process nodes. In some embodiments, macro 102 is a hard macro digitally described in a binary file format (e.g., Graphical Database System II (GDSII) stream format), wherein the binary file format represents planar geometry, text markers, other information, and one or more layout diagrams of macro 102 in hierarchical form. In some embodiments, synthesis, placement, and routing have been performed on macro 102, making the hard macro specific to a particular process node.

[0033] Macro 102 includes region 104, which includes functional circuitry and power control circuitry as described herein. In some embodiments, region 104 includes a substrate having circuitry formed thereon during front-end process (FEOL) fabrication. Furthermore, above and / or below the substrate, region 104 includes various metal layers stacked above and / or below an insulating layer during back-end process (BEOL) fabrication. BEOL provides wiring for the circuitry of IC device 100, including macro 102 and region 104.

[0034] Figure 2 This is a block diagram of the circuit regions of an IC device 200 according to some embodiments. In at least one embodiment, Figure 2 The circuit region in the middle corresponds to Figure 1 Part of region 104.

[0035] IC device 200 includes power control circuitry comprising head circuitry 210 and tail circuitry 220. In at least one embodiment, head circuitry 210 or tail circuitry 220 is omitted. IC device 200 also includes functional circuitry 230 operable by a power supply voltage from at least one of head circuitry 210 or tail circuitry 220, as described herein.

[0036] The head circuit 210 includes a first transistor P1 and a second transistor N1 of different types. The tail circuit 220 includes a first transistor N2 and a second transistor P2 of different types. Figure 2 In the example configuration, transistors P1 and P2 are P-type transistors, and transistors N1 and N2 are N-type transistors. Examples of transistors in the head circuit 210 and / or tail circuit 220 include, but are not limited to, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, P-channel metal-oxide-semiconductor (PMOS), N-channel metal-oxide-semiconductor (NMOS), bipolar junction transistors (BJTs), high-voltage transistors, high-frequency transistors, P-channel and / or N-channel field-effect transistors (PFETs / NFETs), FinFETs, planar MOS transistors with convex source / drain electrodes, nanosheet FETs, nanowire FETs, etc. In some embodiments, PMOS transistors are referred to as first or second type transistors, while NMOS transistors are referred to as second or first type transistors.

[0037] In the head circuit 210, the first transistor P1 includes a first terminal 211 electrically coupled to a first power node or rail 231, a second terminal 212 electrically coupled to a second power node or rail 232, and a gate terminal 213 configured to receive a control signal CS1. The second transistor N1 includes first and second terminals 215 and 216 configured to receive a predetermined voltage Vp1, and a gate terminal 217 configured to receive the control signal CS1. In some embodiments, the first terminal of the transistor is the source or drain of the transistor, and the second terminal of the transistor is the drain or source of the transistor. The first and second terminals of the transistor are sometimes referred to as the source / drain of the transistor.

[0038] Transistor P1 is configured to connect or disconnect power nodes 231, 232 in response to control signal CS1 to provide or disconnect power to functional circuit 230. Transistor P1 is sometimes referred to as a switching transistor. Power node 232 is configured to receive a power supply voltage True VDD (hereinafter “TVDD”). Power node 232 is referred to herein as the “TVDD power rail”. In some embodiments, TVDD is generated by an external voltage source outside IC device 200. In some embodiments, TVDD is generated by an internal voltage source included in IC device 200. When transistor P1 is turned on by a first logic level (e.g., logic “0”) of control signal CS1, TVDD connected to power node 231 via transistor P1 on the TVDD power rail 232 provides a power supply voltage VDD (hereinafter “VDD”) on power node 231. First power node 231 is referred to herein as the “VDD power rail”. VDD is sometimes also referred to as virtual VDD (VVDD). In some embodiments, TVDD is different from VDD. In some embodiments, TVDD is the same as VDD. When transistor P1 is turned off by the second logic level (e.g., logic "1") of control signal CS1, VDD power rail 231 is disconnected from TVDD power rail 232, and the power supply to functional circuit 230 is cut off. In some embodiments, VDD power rail 231 is floating when transistor P1 is turned off. In some embodiments, control signal CS1 is generated by external circuitry outside of IC device 200. In some embodiments, control signal CS1 is generated by power management circuitry included in IC device 200.

[0039] Because the first and second terminals 215, 216 of transistor N1 are configured to receive the same predetermined voltage Vp1, the terminals 215, 216 of transistor N1 are effectively electrically coupled together and transistor N1 is electrically coupled as a dummy transistor. In some embodiments, as described herein, the predetermined voltage Vp1 applied to the first and second terminals 215, 216 of transistor N1 is a power supply voltage, a control signal, or any predetermined voltage or signal other than a power supply voltage and a control signal.

[0040] In the tail circuit 220, the first transistor N2 includes a first terminal 221 electrically coupled to a first power node or rail 235, a second terminal 222 electrically coupled to a second power node or rail 236, and a gate terminal 223 configured to receive a control signal CS2. The second transistor P2 includes first and second terminals 225 and 226 electrically coupled together and configured to receive a predetermined voltage Vp2, and a gate terminal 227 configured to receive the control signal CS2.

[0041] Transistor N2 is configured to connect or disconnect power nodes 235, 236 in response to control signal CS2 to provide or disconnect power to functional circuitry 230. Transistor N2 is sometimes referred to as a switching transistor. Power node 236 is configured to receive a power supply voltage True VSS (hereinafter “TVSS”). The second power node 236 is referred to herein as the “TVSS power rail”. In some embodiments, TVSS is ground voltage. In some embodiments, TVSS is a reference voltage other than ground voltage. In at least one embodiment, the reference voltage other than ground voltage is generated by external circuitry outside IC device 200 or by an internal voltage source included in IC device 200. When transistor N2 is turned on by a first logic level (e.g., logic “1”) of control signal CS2, TVSS connected to power node 235 via transistor N2 on the TVSS power rail 236 provides a power supply voltage VSS (hereinafter “VSS”) on power node 235. Power node 235 is referred to herein as the “VSS power rail”. VSS is sometimes also referred to as a virtual VSS (VVSS). In some embodiments, TVSS is different from VSS. In some embodiments, TVSS is the same as VSS. When transistor N2 is turned off by the second logic level (e.g., logic "0") of control signal CS2, VSS power rail 235 is disconnected from TVSS power rail 236, and power to functional circuit 230 is cut off. In some embodiments, VSS power rail 235 is floating when transistor N2 is turned off. In some embodiments, control signal CS2 is generated by external circuitry outside of IC device 200. In some embodiments, control signal CS2 is generated by power management circuitry included in IC device 200. In some embodiments, control signal CS2 is the same as control signal CS1. In at least one embodiment, control signal CS2 is different from control signal CS1.

[0042] Because the first and second terminals 225, 226 of transistor P2 are configured to receive the same predetermined voltage Vp2, the terminals 225, 226 of transistor P2 are effectively electrically coupled together, and transistor P2 is electrically coupled as a dummy transistor. In some embodiments, the predetermined voltage Vp2 applied to the first and second terminals 225, 226 of transistor P2 is a power supply voltage, a control signal, or any predetermined voltage or signal other than a power supply voltage and a control signal. In some embodiments, the predetermined voltage Vp2 is the same as the predetermined voltage Vp1. In at least one embodiment, the predetermined voltage Vp2 is different from the predetermined voltage Vp1.

[0043] Functional circuit 230 is configured to operate correspondingly on VDD and VSS on VDD power rail 231 and VSS power rail 235 to perform one or more functions of IC device 200. In at least one embodiment, when VDD or VSS is removed from the corresponding VDD power rail 231 or VSS power rail 235 by turning off the corresponding head circuit 210 or tail circuit 220, functional circuit 230 becomes inactive and stops performing one or more functions. As a result, the power consumption of IC device 200 can be reduced when one or more functions provided by functional circuit 230 are not needed. In some embodiments, functional circuit 230 includes one or more active devices, passive devices, logic circuits, etc., configured to operate on VDD and VSS. Examples of logic circuits include, but are not limited to, AND, OR, NAND, NOR, XOR, INV, AND-OR-Invert (AOI), OR-AND-Invert (OAI), MUX, flip-flops, BUFFs, latches, delays, clocks, memories, etc. Exemplary memory cells include, but are not limited to, Static Random Access Memory (SRAM), Dynamic RAM (DRAM), Resistive RAM (RRAIVI), Magnetoresistive RAM (MRAM), Read-Only Memory (ROM), etc. Examples of active devices or active elements include, but are not limited to, transistors, diodes, etc. Examples of transistors include, but are not limited to, Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs), Complementary Metal-Oxide-Semiconductor (CMOS) transistors, P-channel Metal-Oxide-Semiconductor (PMOS), N-channel Metal-Oxide-Semiconductor (NMOS), Bipolar Junction Transistors (BJTs), High-Voltage Transistors, High-Frequency Transistors, P-channel and / or N-channel Field-Effect Transistors (PFETs / NFETs), FinFETs, Planar MOS Transistors with convex source / drain terminals, Nanosheet FETs, Nanowire FETs, etc. Examples of passive elements include, but are not limited to, capacitors, inductors, fuses, resistors, etc.

[0044] exist Figure 2 In an exemplary configuration, the power control circuit includes a head circuit 210 and a tail circuit 220, and controls, for example, to provide or cut off power to the functional circuit 230 by at least one of the head circuit 210 or the tail circuit 220 according to the corresponding control signal CS1 or control signal CS2.

[0045] In some embodiments, the power control circuitry of IC device 200 includes head circuitry 210, but tail circuitry 220 is omitted. In one example, VSS power rail 235 is omitted, and functional circuitry 230 is electrically coupled to TVSS power rail 236. In another example, VSS power rail 235 is electrically coupled to TVSS power rail 236 via a conductor, instead of a switch or transistor. Power to functional circuitry 230 is controlled (e.g., supplied or cut off) by head circuitry 210 according to control signal CS1.

[0046] In some embodiments, the power control circuitry of IC device 200 includes tail circuitry 220, but omits head circuitry 210. In one example, VDD power rail 231 is omitted, and functional circuitry 230 is electrically coupled to TVDD power rail 232. In another example, VDD power rail 231 is electrically coupled to TVSS power rail 236 via a conductor, instead of a switch or transistor. Power to functional circuitry 230 is controlled (e.g., supplied or cut off) by tail circuitry 220 according to control signal CS2.

[0047] As described herein, by applying the same predetermined voltage Vp1 to terminals 215 and 216 of transistor N1, transistor N1 is electrically coupled as a dummy transistor, and by applying the same predetermined voltage Vp2 to terminals 225 and 226 of transistor P2, transistor P2 is electrically coupled as a dummy transistor. In some embodiments, the predetermined voltage Vp1 or Vp2 is a power supply voltage, a control signal, or a signal or voltage other than a control signal and a power supply voltage, as per [reference to...]. Figures 3A-3E and Figures 8A-8E As stated above.

[0048] Figures 3A-3E These are schematic circuit diagrams of various head circuits 300A-300E according to some embodiments. In at least one embodiment, one or more of the head circuits 300A-300E correspond to... Figure 2 The head circuit 210 in the middle. It has... Figure 2 The corresponding component in Figures 3A-3E The components in are made of Figure 2 The same reference numerals indicate or are represented by Figure 2 The figure reference numerals are indicated by adding 100.

[0049] exist Figures 3A-3E In the head circuits 300A-300E, each includes information about... Figure 2 The first transistor P1 and the second transistor N1 are described. Specifically, the gate terminals of transistors P1 and N1 are electrically coupled to receive signals from the gate terminals of transistors P1 and N1. Figure 2The control signal CS1 corresponds to the control signal Control. Transistor P1 is a switching transistor, including a first terminal 311 electrically coupled to the VDD power rail and a second terminal 322 electrically coupled to the TVDD power rail. Transistor N1 is an electrically coupled dummy transistor, including a first terminal 315 and a second terminal 316 electrically coupled to receive the same predetermined voltage.

[0050] The predetermined voltages on terminals 315 and 316 of transistor N1 differ between the head circuits 300A and 300E. Figure 3A In the head circuit 300A, the predetermined voltage on terminals 315 and 316 of transistor N1 is VSS. Figure 3B In the head circuit 300B, the predetermined voltage on terminals 315 and 316 of transistor N1 is TVDD. Figure 3C In the head circuit 300C, the predetermined voltage on terminals 315 and 316 of transistor N1 is VDD. Figure 3D In the head circuit 300D, the predetermined voltage on terminals 315 and 316 of transistor N1 is the control signal Control. Figure 3E In the head circuit 300E, the predetermined voltage on terminals 315 and 316 of transistor N1 is Vp, which is a voltage or signal other than the power supply voltages VSS, TVDD, and VDD, and the control signal Control. As described herein, examples of the predetermined voltage on terminals 315 and 316 of transistor N1 according to some embodiments include power supply voltages (such as VSS, TVDD, or VDD), control signals (such as Control), or voltages other than VSS, TVDD, VDD, and Control. Other voltage configurations are within the scope of the various embodiments.

[0051] Figure 4A This is a schematic diagram of the layout of a header unit 400A according to some embodiments. In at least one embodiment, the header unit 400A corresponds to a header circuit 300A. In at least one embodiment, the header unit 400A is stored as a standard unit in a standard unit library on a non-transitory computer-readable medium.

[0052] The head unit 400A includes multiple active regions 401, 402. Active regions are sometimes referred to as oxide-defined (OD) regions or source / drain regions, and are schematically shown in the figures using the designation "OD". In at least one embodiment, as described herein, the active regions 401, 402 are located above the front side of the substrate. The active regions 401, 402 extend along a first axis (e.g., the X-axis). The active regions 401, 402 include P-type dopant and / or N-type dopant to form one or more circuit elements or devices. Examples of circuit elements include (but are not limited to) transistors and diodes. Active regions configured to form one or more PMOS devices are sometimes referred to as "PMOS active regions", and active regions configured to form one or more NMOS devices are sometimes referred to as "NMOS active regions". Regarding... Figure 4A In the described exemplary configuration, active region 401 includes a PMOS active region, and active region 402 includes an NMOS active region. Other configurations are within the scope of the various embodiments. In some embodiments, the PMOS active region is referred to as an active region of a first or second semiconductor type, and the NMOS active region is referred to as an active region of a second or first semiconductor type.

[0053] The head unit 400A also includes a plurality of gate regions 411, 412, 413, 414, 415, 418, and 419 located above the active regions 401 and 402. For simplicity, some reference numerals for the gate regions are omitted. Gate regions 411, 412, 413, 414, 415, 418, and 419 extend along a second axis (e.g., a Y-axis perpendicular to the X-axis). Gate regions 411, 412, 413, 414, 415, 418, and 419 extend along the X-axis... Figure 4A The CPP (Contact Polysilicon Pitch) specifies a regular spacing arrangement. CPP refers to two directly adjacent gate regions (e.g., Figure 4A The center-to-center distance along the X-axis between gate regions 414, 415. Two gate regions are considered to be directly adjacent, with no other gate region between them. Gate regions 411, 412, 413, 414, 415, 418, and 419 comprise a conductive material, such as polysilicon, sometimes referred to as "poly". Gate regions 411, 412, 413, 414, 415, 418, and 419 are schematically shown in the figures using the designation "PO". Other conductive materials (such as metals) used for the gate regions are within the scope of various embodiments. Figure 4AIn an exemplary configuration, gate regions 411-415 are functional gate regions that, together with active regions 401, 402, are configured as a plurality of transistors as described herein. In some embodiments, gate regions 418, 419 are non-functional or dummy gate regions. The dummy gate regions are not configured to form transistors together with the underlying active regions, and / or one or more transistors formed by the dummy gate regions together with the underlying active regions are not electrically coupled to other circuitry in the head unit 400A and / or to an IC device including the head unit 400A. In at least one embodiment, the non-functional or dummy gate regions comprise dielectric material in the fabricated IC device.

[0054] The head unit 400A also includes a plurality of active devices configured with gate regions 411-415 and active regions 401, 402. For example, a plurality of PMOS devices are configured together with the PMOS active region 401 and the corresponding gate regions 411-415. Because the PMOS devices are electrically coupled together as described herein, the PMOS devices effectively and jointly form a PMOS transistor. In other words, the gate regions 411-415 and the active region 401 are configured as PMOS transistors, which in at least one embodiment correspond to transistor P1. A plurality of NMOS devices are configured together with the NMOS active region 402 and the corresponding gate regions 411-415. Because the NMOS devices are electrically coupled together as described herein, the NMOS devices effectively and jointly form an NMOS transistor. In other words, the gate regions 411-415 and the active region 402 are configured as NMOS transistors, which in at least one embodiment correspond to transistor N1. A portion of the gate regions 411-415 located above the active region 401 corresponds to the gate terminal of transistor P1. A portion of the gate regions 411-415 located above the active region 402 corresponds to the gate terminal of transistor N1. Since gate regions 411, 412, 413, 414, 415, 418, and 419 extend continuously from the first active region 401 along the Y-axis to the second active region 402, the gate terminals of transistors P1 and N1 are electrically coupled together. One side of each of the gate regions 411-415 (e.g., Figure 4A A portion of the active region 401 (on the left side) corresponds to the source / drain of the corresponding PMOS device, and the other side of each of the gate regions 411-415 (e.g., Figure 4A The other portion of the active region 401 (on the right side) corresponds to the other source / drain of the corresponding PMOS device. One side of each of the gate regions 411-415 (e.g., Figure 4A A portion of the active region 402 (on the left side) corresponds to the source / drain of the corresponding NMOS device, and the other side of each of the gate regions 411-415 (e.g., Figure 4AThe other part of the active region 402 (on the right side of the image) corresponds to the other source / drain of the corresponding NMOS device.

[0055] The configuration in which each of transistors P1 and N1 is configured with a plurality of gate regions is an example. Other configurations are within the scope of the various embodiments. For example, the number of gate regions 411-415 forming each of transistors P1 and N1 is not limited to... Figure 4A The specific configuration is as follows. In some embodiments, the head unit 400A includes a single functional gate region, such as gate region 411, located and directly adjacent to the dummy gate regions 418, 419. In at least one embodiment, the number of gate regions 411-415 forming transistor P1 (i.e., the switching transistor) is selected based on one or more factors, including but not limited to the R of the corresponding head circuit. ON Or drive strength. As the number of gate regions forming the switching transistor P1 increases, R ON The size of the chip or wafer occupied by the head circuitry is reduced, while the driving strength is increased. In at least one embodiment, the number of gate regions selected to form the switching transistor P1 is determined by performance (e.g., reduced RL). ON Design considerations that balance the cost of the area (and / or increased drive strength).

[0056] The head unit 400A also includes a contact structure located above and electrically contacting corresponding portions in the active regions 401 and 402. This contact structure is sometimes referred to as a metal-to-device structure and is schematically shown in the figures as labeled "MD". The MD contact structure includes conductive material formed above corresponding portions (e.g., source / drain) in the corresponding active regions to define an electrical connection from one or more devices formed in the active regions to internal circuitry of the IC device or to external circuitry. Figure 4AIn the exemplary configuration, MD contact structures 421-429 are located above the active region 401, electrically contacting the corresponding portions (i.e., source / drain) of transistor P1, and are alternately arranged along the X-axis with gate regions 418, 411-415, 419. MD contact structures 431-439 are located above the active region 402, electrically contacting the corresponding portions (i.e., source / drain) of transistor N1, and are alternately arranged along the X-axis with gate regions 418, 411-415, 419. MD contact structures 421-429 are aligned with and spaced apart from MD contact structures 431-439 along the Y-axis. In some embodiments, the spacing between MD contact structures 421-429 and their corresponding MD contact structures 431-439 is formed by the natural ends facing the natural ends of MD contact structures 421-429 and 431-439, wherein the natural ends are formed by one or more manufacturing processes used to form the MD structures. In some embodiments, the spacing between MD contact structures 421-429 and their corresponding MD contact structures 431-439 is formed by a mask called a “cut-MD” (not shown). The spacing between directly adjacent MD contact structures, i.e., the center-to-center distance along the X-axis, is the same as the spacing CPP between directly adjacent gate regions, for example, at MD contact structures 436, 437. Two MD contact structures are considered directly adjacent if there are no other MD contact structures between them. Exemplary conductive materials for the MD contact structures include metals. Other configurations are within the scope of the various embodiments.

[0057] The head unit 400A also includes a via structure located above and electrically contacting the corresponding gate region or MD contact structure. The via structure located above and electrically contacting the MD contact structure is sometimes referred to as a via-to-device (VD). The via structure located above and electrically contacting the gate region is sometimes referred to as a via-to-gate (VG). VD via structures are schematically shown in the figures using the designation "VD" or "VD2". VG via structures are schematically shown in the figures using the designation "VG". Figure 4AIn the exemplary configuration, the first row of VD via structures, represented by 450 and 451, is located above and electrically contacts the first group of MD contact structures (i.e., MD contact structures 421, 423, 425, 427, and 429). The second row of VD via structures, represented by 452 and 453, is located above and electrically contacts the second group of MD contact structures (i.e., MD contact structures 422, 424, 426, and 428). The MD contact structures 421, 423, 425, 427, and 429 in the first group are arranged alternately with the MD contact structures 422, 424, 426, and 428 in the second group along the X-axis. The third row of VD via structures, represented by 454 and 455, is located above and electrically contacts the corresponding MD contact structures 421, 423, 425, 427, and 429. The fourth row of VD via structures, indicated by 456, 457, 458, and 459, is located above and electrically contacts the corresponding MD contact structures 431-439. Multiple via structures, indicated by 461 and 462, are located above and electrically contact the corresponding gate regions 411-415. Exemplary materials for the VD and VG via structures include metals. Other configurations are within the scope of the various embodiments.

[0058] The head unit 400A also includes multiple metal layers and via layers arranged sequentially and alternately above the VD and VG via structures. The lowest metal layer immediately above and electrically connected to the VD and VG via structures is the M0 (zero metal) layer, the next metal layer above the M0 layer is the M1 layer, the next metal layer above the M1 layer is the M2 layer, and so on. Via layers VIA0 and V0 are arranged between and electrically coupled to the Mn and Mn+1 layers, where n is an integer from zero upwards. For example, the via zero (VIA0 or V0) layer is the lowest via layer, arranged between and electrically coupled to the M0 and M1 layers. Other via layers are VIA1 (or V1), VIA2 (or V2), etc. As described herein, the M0 layer is the lowest or closest metal layer above the active regions 401 and 402 on the front side of the substrate.

[0059] In the head unit 400A, the M0 layer includes M0 conductive patterns 471, 472, 473, 474, and 475. M0 conductive pattern 471 is above and electrically in contact with the first row of VD via structures including VD via structures 450 and 451. Therefore, MD contact structures 421, 423, 425, 427, and 429 are electrically coupled to the corresponding source / drain electrodes in the active region 401, together forming the first terminal of transistor P1. M0 conductive pattern 472 is above and electrically in contact with the second row of VD via structures including VD via structures 452 and 453. Therefore, MD contact structures 422, 424, 426, and 428 are electrically coupled to the corresponding source / drain electrodes in the active region 401, together forming the second terminal of transistor P1. M0 conductive pattern 473 is above and electrically in contact with the third row of VD via structures including VD via structures 454 and 455. Therefore, MD contact structures 421, 423, 425, 427, and 429 are also electrically coupled to the corresponding source / drain terminals in active region 401 via M0 conductive pattern 473. In other words, M0 conductive patterns 471 and 473 are both electrically coupled to the first terminal of transistor P1. M0 conductive pattern 474 is located above and electrically contacts the VG via structures indicated by 461 and 462. Therefore, gate regions 411-415 are electrically coupled together, corresponding to the gate terminals of transistors P1 and N1. M0 conductive pattern 475 is located above and electrically contacts the fourth row of VD via structures including VD via structures 456-459. Therefore, MD contact structures 431-439 and the corresponding source / drain terminals in active region 402 are electrically coupled together, corresponding to the first and second terminals of transistor N1, making transistor N1 electrically coupled as a pseudo-transistor.

[0060] Figure 4A The markings on the left indicate signals or voltages applicable to M0 conductive patterns 471-475. For example, M0 conductive pattern 471 is configured as a first power rail, such as a VDD power rail, for providing VDD to functional circuitry operable by VDD. As described herein, M0 conductive pattern 472 is configured as a second power rail, such as a TVDD power rail, for receiving TVDD from another circuit. In at least one embodiment, TVDD is applied to M0 conductive pattern 472 from a conductive pattern or power rail located in a metal layer above the M0 layer (e.g., in the M1 layer) through one or more V0 via structures, for example, as referenced. Figure 5AThe M0 conductive pattern 473 is configured as an additional VDD power rail to provide VDD to the functional circuitry. The M0 conductive pattern 474 is configured to apply a control signal Control to gate regions 411-415, i.e., to the gate terminals of transistors P1 and N1. The M0 conductive pattern 475 is configured as a third power rail, such as the VSS power rail, which electrically couples the first and second terminals of transistor N1. This configuration corresponds to a predetermined voltage on the terminals of transistor N1 being the head circuit 300A of VSS. Figure 4A In the exemplary configuration, the M0 layer is an example of a conductive layer with various conductive patterns for electrically coupling transistor N1 as a dummy transistor, or for electrically coupling transistor P1 to various power rails and control signals. Other conductive layers are available in various embodiments.

[0061] The head cell 400A also includes a boundary (or cell boundary) 480, which includes edges 481, 482, 483, and 484. Edges 481 and 482 extend along the X-axis, and edges 483 and 484 extend along the Y-axis. Edges 481, 482, 483, and 484 are joined together to form a closed boundary 480. In the placement and routing operation described herein (also known as “Automatic Place and Routing (APR)”), cells are placed in an IC placement diagram, adjacent to each other at their respective boundaries. Boundary 480 is sometimes referred to as a “place and routing boundary” and is schematically shown in the accompanying drawings with the designation “PR Boundary”. The rectangular shape of boundary 480 is an example. Other boundary shapes for various cells are within the range of various embodiments. In some embodiments, edges 481 and 482 coincide with the center lines of the corresponding MO conductive patterns 471 and 475. In some embodiments, edges 483 and 484 coincide with the center lines of the pseudo or non-functional gate regions 418 and 419. Between edges 481 and 482 and along the Y-axis, head unit 400A contains a PMOS active region (i.e., 401) and an NMOS active region (i.e., 402), and is considered to have a height corresponding to one unit height. (See also: Regarding...) Figure 6B The aforementioned cell or circuit region, comprising two PMOS active regions and two NMOS active regions along the Y-axis, is considered to have a height corresponding to two cell heights or twice the cell height. Regarding Figures 5A-5B Description corresponds to Figure 4A An exemplary cross-sectional view of lines VV and V'-V' in the diagram.

[0062] As described herein, in an IC device including head circuitry corresponding to head unit 400A, in response to a first logic level of the control signal Control on the MO conductive pattern 474, transistor P1 is turned on to connect the TVDD power rail configured by the MO conductive pattern 472 to the VDD power rail configured by the MO conductive patterns 471, 473. Therefore, the functional circuitry electrically coupled to the VDD power rail or the MO conductive patterns 471, 473 receives and operates power from the TVDD power rail or the MO conductive pattern 472. In response to a second logic level of the control signal Control on the MO conductive pattern 474, transistor P1 is turned off to disconnect the TVDD power rail or the MO conductive pattern 472 from the VDD power rail or the MO conductive patterns 471, 473. Therefore, in one or more embodiments, the power supply to the functional circuitry is cut off, and the functional circuitry is in a sleep, standby, or power-off state.

[0063] As described herein, transistor N1 is electrically coupled as a pseudo-transistor. This differs from the header circuitry of other methods, in which NMOS devices or transistors on the NMOS active region are not used, and the gate, drain, and source of the NMOS transistor remain floating, e.g., not electrically coupled to other circuitry. In this header circuitry according to other methods, the VG via structure of the PMOS switching transistor and the corresponding M0 conductive pattern for the control signal electrically coupled to the VG via structure are at least partially arranged above the PMOS active region of the PMOS switching transistor. As a result, the wiring resources of the PMOS switching transistor, such as the available tracks for the M0 conductive pattern, are limited by the presence of the M0 conductive pattern of the control signal.

[0064] In contrast, according to some embodiments, by electrically coupling transistor N2 as a dummy transistor, the VG via structures 461, 462 and the corresponding Mo conductive pattern 474 can be arranged away from the active region 401 and towards the active region 402, for example, above the gap between the active regions 401 and 402, such as... Figure 4A As shown. Therefore, additional wiring resources for switching transistor P1 become available above the corresponding PMOS active region 401. Figure 4A In the exemplary configuration, this additional wiring resource is implemented in the form of additional rows of VD via structures 454, 455 and corresponding additional VDD power rails (i.e., M0 conductive pattern 473), which is not available according to other methods. In at least one embodiment, the additional VD via structures 454, 455 and the additional VDD power rails 473 help reduce R ON And / or increase the current density of the power supplied through the head circuit. With the same cell width (i.e., the number of gate regions in the head circuit), compared to the R of the head circuit according to other methods... ONIn contrast, the R of the head circuit according to some embodiments ON A reduction of approximately 2% to 4%. In the same R... ON (For example, as required for the intended operation of the functional circuitry to be powered) , compared to header circuitry according to other methods, header circuitry according to some embodiments requires less gate region, i.e., a smaller chip or wafer area. One or more of the described advantages, such as increased power supply current density, reduced R..., can be achieved in various embodiments. ON Reduced chip or wafer area, etc.

[0065] Figure 4B This is a schematic diagram of the layout of a header unit 400B according to some embodiments. In at least one embodiment, the header unit 400B corresponds to a header circuit 300B. In at least one embodiment, the header unit 400B is stored as a standard unit in a standard unit library on a non-transitory computer-readable medium. Figure 4A and Figure 4B Corresponding components are indicated by the same reference numerals. For simplicity, Figure 4B The element boundary of head unit 400B, which is similar to boundary 480 of head unit 400A, is omitted. Head unit 400B differs from head unit 400A in terms of the components described herein.

[0066] In the head unit 400B, MD contact structures 422, 424, 426, and 428 extend continuously along the Y-axis to make electrical contact with multiple active regions, specifically with both active regions 401 and 402. In other words, a set of MD contact structures 422, 424, 426, and 428 extends continuously from the first active region 401 to the second active region 402, forming a corresponding set of MD contact structures 432, 434, 436, and 438 located above the second active region 402. The MD contact structures 422, 424, 426, and 428 that make electrical contact with the multiple active regions are referred to herein as extended MD contact structures 422, 424, 426, and 428. A row of VD via structures, represented by 463 and 464, is located above and makes electrical contact with the corresponding extended MD contact structures 422, 424, 426, and 428. VD via structures 463 and 464 will electrically couple the extended MD contact structures 422, 424, 426, and 428 to the M0 conductive pattern 474.

[0067] Compared to head unit 400A, the VG via structures 461, 462 in head unit 400B are arranged further away from the active region 401 and are at least partially located above the active region 402. The MO conductive pattern 476 is located above and electrically contacts the VG via structures 461, 462 to receive the control signal Control from the MO conductive pattern 476.

[0068] Instead of the VD via structures 431-439 electrically coupled to the VSS power rail or MO conductive pattern 475 in the head unit 400A, the head unit 400B includes another row of VD via structures, represented by 465 and 466, which are located above and electrically contacting the MD contact structures 431-439 located above the active region 402. Another MO conductive pattern 477 is located above and electrically contacting another row of VD via structures, including VD via structures 465 and 466.

[0069] Figure 4B The markings on the left indicate signals or voltages applicable to M0 conductive patterns 471-474, 476, and 477. In addition to the M0 conductive pattern 472 configured as a TVDD power rail in a manner similar to that of head unit 400A, head unit 400B also includes M0 conductive patterns 474 and 477 configured as additional TVDD power rails. In at least one embodiment, TVDD is applied from one or more conductive patterns in the overlying metal layer to the M0 conductive patterns 474 and 477 through one or more via structures, as described herein. The TVDD power rail or the M0 conductive patterns 472, 474, and 474 are all electrically coupled to the second terminal of transistor P1 via extended MD contact structures 422, 424, 426, and 428 and corresponding VD via structures. This configuration corresponds to head circuit 300B where a predetermined voltage on the terminal of transistor N1 is TVDD. The additional TVDD power rail helps reduce R... ON And / or increase the current density of the power supplied through the head circuit corresponding to head unit 400B. In at least one embodiment, one or more of the advantages described herein can be achieved in an IC device including such head circuitry.

[0070] Figure 4C This is a schematic diagram of the layout of a header unit 400C according to some embodiments. In at least one embodiment, the header unit 400C corresponds to a header circuit 300C. In at least one embodiment, the header unit 400C is stored as a standard unit in a standard unit library on a non-transitory computer-readable medium. Figure 4A and Figure 4C Corresponding components are indicated by the same reference numerals. For simplicity, Figure 4C The element boundary of head unit 400C, which is similar to boundary 480 of head unit 400A, is omitted. Head unit 400C differs from head unit 400A in terms of the component described herein.

[0071] In the head unit 400C, MD contact structures 421, 423, 425, 427, and 429 extend continuously along the Y-axis to make electrical contact with multiple active regions, specifically with both active regions 401 and 402. In other words, a set of MD contact structures 421, 423, 425, 427, and 429 extends continuously from the first active region 401 to the second active region 402, forming a corresponding set of MD contact structures 431, 433, 435, 437, and 439 located above the second active region 402. MD contact structures 421, 423, 425, 427, and 429 are extended MD contact structures.

[0072] Instead of the VD via structures 431-439 electrically coupled to the VSS power rail or MO conductive pattern 475 in the head unit 400A, the head unit 400C includes a row of VD via structures represented by 465, 466, which are above and electrically contacted with the MD contact structures 431-439 located above the active region 402. Another MO conductive pattern 477 is above and electrically contacted with another row of VD via structures including VD via structures 465-466. Although the MO conductive pattern 476 includes... Figure 4C In the exemplary configuration, however, it is not used and may be omitted in one or more embodiments. In at least one embodiment, the MD contact structures 431-439 above the active region 402 are electrically coupled together via the MO conductive pattern 476 instead of via the MO conductive pattern 477.

[0073] Figure 4C The markings on the left indicate the signals or voltages applicable to M0 conductive patterns 471-474, 477. In addition to the M0 conductive patterns 471, 473 configured as VDD power rails in a manner similar to head unit 400A, head unit 400C also includes an M0 conductive pattern 477 configured as an additional VDD power rail. The VDD power rail or M0 conductive patterns 471, 473, 477 are all electrically coupled to the first terminal of transistor P1 via extended MD contact structures 421, 423, 425, 427, 429 and corresponding VD via structures. This configuration corresponds to head circuit 300C where the predetermined voltage on the terminal of transistor N1 is VDD. The additional VDD power rail helps reduce R... ON And / or increase the current density of the power supplied through the head circuit corresponding to the head unit 400C. In at least one embodiment, one or more of the advantages described herein can be achieved in an IC device including such a head circuit.

[0074] Figure 4DThis is a schematic diagram of the layout of a header unit 400D according to some embodiments. In at least one embodiment, the header unit 400D corresponds to a header circuit 300D. In at least one embodiment, the header unit 400D is stored as a standard unit in a standard unit library on a non-transitory computer-readable medium. Figure 4A and Figure 4D Corresponding components are indicated by the same reference numerals. For simplicity, Figure 4D The element boundary of head unit 400D, which is similar to boundary 480 of head unit 400A, is omitted. Head unit 400D differs from head unit 400A in terms of the component described herein.

[0075] Instead of the VD via structures 431-439 electrically coupled to the VSS power rail or MO conductive pattern 475 in the head unit 400A, the head unit 400D includes a row of VD via structures represented by 465, 466, which are above and electrically contacted with the MD contact structures 431-439 located above the active region 402. Another MO conductive pattern 477 is above and electrically contacted with another row of VD via structures including VD via structures 465-466. Although the MO conductive pattern 476 includes... Figure 4D In the exemplary configuration, however, it is not used and may be omitted in one or more embodiments. In at least one embodiment, the MD contact structures 431-439 above the active region 402 are electrically coupled together via the MO conductive pattern 476 instead of via the MO conductive pattern 477.

[0076] Figure 4D The markings on the left indicate signals or voltages applicable to M0 conductive patterns 471-474, 477. M0 conductive pattern 477 is configured to receive a control signal Control. This configuration corresponds to a header circuit 300D in which a predetermined voltage on the terminal of transistor N1 is the control signal Control. In at least one embodiment, one or more of the advantages described herein can be achieved in the header circuit corresponding to header unit 400D and / or in an ID device including such a header circuit.

[0077] Figure 4E This is a schematic diagram of the layout of a header unit 400E according to some embodiments. In at least one embodiment, the header unit 400E corresponds to a header circuit 300E. In at least one embodiment, the header unit 400E is stored as a standard unit in a standard unit library on a non-transitory computer-readable medium. Figure 4D and Figure 4E Corresponding components are indicated by the same reference numerals. For simplicity, Figure 4E The cell boundaries of the head cell 400E, which are similar to the boundary of the head cell 400A, are omitted.

[0078] Apart from the signal applied to the M0 conductive pattern 477, the head unit 400E is similar to the head unit 400D. Figure 4E The markings on the left indicate signals or voltages applicable to M0 conductive patterns 471-474, 477. Instead of the control signal Control in head unit 400D, the M0 conductive pattern 477 in head unit 400E is configured to receive a signal or voltage Vp in addition to the control signal Control and power supply voltages TVDD, VDD, VSS. This configuration corresponds to head circuit 300E in which the predetermined voltage on the terminal of transistor N1 is the signal Vp. In at least one embodiment, one or more of the advantages described herein can be achieved in the head circuit corresponding to head unit 400E and / or in an IC device including such a head circuit.

[0079] Figure 5A It is an edge of IC device 500 according to some embodiments Figure 4A A schematic cross-sectional view of line VV. IC device 500 includes components corresponding to... Figure 4A The circuit area of ​​the described head unit 400A. It has... Figure 4A The corresponding component in Figure 5A The components in are made of Figure 4A The same reference numerals are used in the accompanying drawings.

[0080] like Figure 5A As shown, the IC device 500 includes a substrate 550 on which a circuit region corresponding to the head unit 400A is formed. The substrate 550 has a thickness direction along the Z-axis. P-type and N-type dopants are added to the substrate 550 to correspondingly form a P-type doped region 551 and an N-type doped region 552 corresponding to the active regions 401, 402, and an N-well 553 is also formed, wherein the P-doped region 551 is formed. In some embodiments, an isolation structure is formed between adjacent P-well / P-doped regions and N-well / N-doped regions. For simplicity, Figure 5A The isolation structure is omitted. The P-doped region 551 defines the source / drain of the PMOS device constituting transistor P1. The N-doped region 552 defines the source / drain of the NMOS device constituting transistor N2.

[0081] IC device 500 also includes MD contact structures for electrically coupling the source / drain of PMOS and NMOS devices to other circuit elements in the circuitry of IC device 500. For example, MD contact structures 421 and 431 are located above and electrically connected to the P-doped region 551 and the N-doped region 552, respectively.

[0082] IC device 500 also includes VD and VG via structures located above and electrically connected to the corresponding MD contact structure and / or gate region. For example, although the VG via structure is in Figure 5A It is not visible in the cross-sectional view, but Figure 5A VD via structures 450 and 454 are shown above and in electrical contact with MD contact structure 421, and VD via structure 456 is shown above and in electrical contact with MD contact structure 431.

[0083] IC device 500 also includes an interconnect structure 560 located above the VD and VG via structures. Interconnect structure 560 includes multiple metal layers M0, M1, ... and multiple via layers V0, V1, ... arranged alternately in the thickness direction (i.e., along the Z-axis) of substrate 550. Interconnect structure 560 also includes various interlayer dielectric (ILD) layers (not shown) in which the metal layers and via layers are embedded. The metal layers and via layers of interconnect structure 560 are configured to electrically couple various components or circuits of IC device 500 to each other and to external circuitry. For simplicity, Figure 5A The metal layer and via layer above layer M1 are omitted.

[0084] The M0 layer includes M0 conductive patterns 471-475, which are correspondingly configured as a VDD power rail, a TVDD power rail, another VDD power rail, a conductor for receiving the control signal Control and applying it to the gates of transistors P1 and N1, and a VSS power rail. The M0 conductive patterns 471, 473, and 475 are located above and electrically in contact with the VD via structures 450, 454, and 456.

[0085] The V0 layer includes a V0 via structure 562 located above and electrically contacting the TVDD power rail or M0 conductive pattern 472 in the M0 layer. The M1 layer includes an M1 conductive pattern 563 located above and electrically contacting the V0 via structure 562. The V0 via structure 562 and the M1 conductive pattern 563 are schematically shown by dashed lines because in at least one embodiment, the V0 via structure 562 and / or the M1 conductive pattern 563 are located above and / or electrically contacting the TVDD power rail or M0 conductive pattern 472 in the M0 layer. Figure 5A The cross-sectional view may not be visible. In some embodiments, the M1 conductive pattern 563 is configured as a TVDD power rail in the M1 layer to apply TVDD to the M0 conductive pattern 472, which serves as the TVDD power rail in the M0 layer, through the V0 via structure 562. In at least one embodiment, the IC device 500 includes more than one V0 via structure between the M1 conductive pattern 563 and the M0 conductive pattern 472 to provide sufficient power current density. In some embodiments, the M0 conductive pattern 474 is configured to receive a control signal Control from a corresponding conductive pattern in the M1 layer through one or more V0 via structures in a similar manner.

[0086] As described in this article, when transistor P1( Figure 5A (Not shown) When the corresponding logic level of the control signal Control applied to the M0 conductive pattern 474 is turned on, the TVDD applied to the M0 conductive pattern 472 is output as VDD by transistor P1 through the MD contact structure 421 and VD via structures 450, 454 to the M0 conductive patterns 471, 473. Then, VDD is applied to the M0 conductive patterns 471, 473 to operate the functional circuits electrically coupled to the M0 conductive patterns 471, 473. In one or more embodiments, the additional VD via structure 454 and the M0 conductive pattern 473 for outputting VDD can reduce the Ro of the head circuit. ON And / or increase the current density of the power supply to the functional circuit.

[0087] Figure 5B It is an edge of IC device 500 according to some embodiments Figure 4A A schematic cross-sectional view taken by line V'-V'. It has... Figure 4A The corresponding component in Figure 5B The components in are made of Figure 4A The accompanying reference numerals indicate this.

[0088] like Figure 5B As shown, the IC device 500 further includes a gate stack corresponding to the gate region 412 and including gate dielectric layers 554, 555 and a gate electrode 512. The IC device 500 also includes another gate stack corresponding to the gate region 413 and including gate dielectric layers 554, 555 and a gate electrode 513. In at least one embodiment, a gate dielectric layer replaces a plurality of gate dielectric layers 554, 555. Exemplary materials for the gate dielectric layers include HfO2, ZrO2, etc. Exemplary materials for the gate electrodes 512, 513 include polysilicon, metal, etc.

[0089] IC device 500 also includes MD contact structures 432, 433, and 434 electrically coupled to the source / drain (not shown) of the NMOS device constituting transistor N1 (not shown). VD via structures 457, 458, and 459 are correspondingly located above and electrically contacting the MD contact structures 432, 433, and 434. MO conductive pattern 475 is located above and electrically contacting the VD via structures 457, 458, and 459. Therefore, the source / drain of the NMOS device constituting transistor N1 is electrically coupled together, i.e., transistor N1 is electrically coupled as a pseudo-transistor, as described herein. In at least one embodiment, one or more of the advantages described herein can be achieved in IC device 500.

[0090] Figure 6A This is a schematic circuit diagram of the head circuit 600A according to some embodiments.

[0091] Head circuit 600A includes sub-circuits 611 and 612 electrically coupled together at VSS power rail 613. Sub-circuit 611 corresponds to head circuit 300A and includes a switching transistor P61 and a dummy transistor N61. Switching transistor P61 and dummy transistor N61 correspond to switching transistor P1 and dummy transistor N1 of head circuit 300A. Transistor P61 has first and second terminals correspondingly electrically coupled to VDD and TVDD. Dummy transistor N61 has first and second terminals electrically coupled to receive VSS. The gates of transistors P61 and N61 are electrically coupled to receive a control signal Control. Sub-circuit 612 corresponds to head circuit 300A and includes a switching transistor P62 and a dummy transistor N62. Switching transistor P62 and dummy transistor N62 correspond to switching transistor P1 and dummy transistor N1 of head circuit 300A. Transistor P62 has first and second terminals correspondingly electrically coupled to VDD and TVDD. Dummy transistor N62 has first and second terminals electrically coupled to receive VSS. The gates of transistors P62 and N62 are electrically coupled to receive the control signal Control. The terminal of transistor N61 is electrically coupled to the terminal of transistor N62 at the VSS power rail 613. Sub-circuits 611 and 612 are configured as described above. Figure 2 and Figure 3A Operate as described above.

[0092] The configuration in which the head circuit 600A includes two sub-circuits corresponding to the head circuit 300A is an example. Other configurations are within the scope of the various embodiments. For example, in some embodiments, the head circuit 600A includes more than two sub-circuits and / or the sub-circuits of the head circuit 600A correspond to any one of the head circuits 300A-300E. In at least one embodiment, one or more of the advantages described herein may be realized in the head circuit 600A and / or the IC device including the head circuit 600A.

[0093] Figure 6B This is a schematic diagram of the layout of header unit 600B according to some embodiments. In at least one embodiment, header unit 600B corresponds to header circuitry 600A. In at least one embodiment, header unit 600B is stored as a standard unit in a standard unit library on a non-transitory computer-readable medium. Figure 6A and Figure 6B Corresponding components in the figures are indicated by the same reference numerals. Figure 4A The corresponding components Figure 6B The components are made of Figure 4AThe reference numerals are increased by 200 to indicate this. For example, the MO conductive patterns 671-675 and the boundary 680 with edges 681-684 in the head unit 600B correspond to the MO conductive patterns 471-475 and the boundary 480 with edges 481-484 in the head unit 400A.

[0094] Head unit 600B includes portion A corresponding to sub-circuit 611 and portion B corresponding to sub-circuit 612. Each of portions A and B of head unit 600B includes a PMOS active region, an NMOS active region, a gate region, an MD contact structure, VD and VG via structures, and an M0 conductive pattern, as described above. Figure 4A The arrangement and electrical coupling are as described above. The head unit 600B also includes a diced polysilicon region 603 that dices a polysilicon mask, extending along the X-axis and indicating the region where the gate region of portion A is disconnected from the gate region of portion B. The diced polysilicon region 603 is schematically shown in the figures with the designation "CPO".

[0095] Figure 6B The markings on the left indicate the signals or voltages applicable to the M0 conductive patterns. For example, M0 conductive patterns 671-674 in part A are correspondingly configured as a first VDD power rail, a first TVDD power rail, a second VDD power rail, and a first conductor for receiving and applying control signals Control to the gates of transistors P61 and N61. M0 conductive patterns 681-684 in part B correspond to M0 conductive patterns 671-674 and are correspondingly configured as a third VDD power rail, a second TVDD power rail, a fourth VDD power rail, and a second conductor for receiving and applying control signals Control to the gates of transistors P62 and N62. M0 conductive pattern 675 is configured as a VSS power rail shared by both parts A and B.

[0096] Each of sections A and B includes a PMOS active region and an NMOS active region along the Y-axis, and corresponds to a head cell of one cell height, as shown in the figure. Figure 4AThe head unit 600B is a combination of two head units of one unit height, and is considered to have a height corresponding to two unit heights or twice the unit height. For simplicity, the unit height of part A is also referred to as "A", and the unit height of part B is also referred to as "B". Unit height A is the dimension along the Y-axis from the edge 681 of boundary 680 to the center line 604 of the cut polysilicon region 603. Unit height B is the dimension along the Y-axis from the edge 682 of boundary 680 to the center line 604 of the cut polysilicon region 603. In some embodiments, unit height A is the same as unit height B. In one or more embodiments, unit height A is different from unit height B. The described configuration of head unit 600B as a head unit having twice the unit height is an example. Other configurations in which head unit 600B has a height greater than twice the unit height are within the scope of various embodiments.

[0097] Besides cell height, sections A and B can differ from each other in terms of active region width (also known as "OD width"). Active region width, or OD width, is the dimension of the active region along the Y-axis. For example, each of the PMOS and NMOS active regions in section A has an OD width D, such as... Figure 6B As shown. Each of the PMOS and NMOS active regions in part B has an OD width E, as... Figure 6B As shown. In some embodiments, the OD width D is the same as the OD width E. In one or more embodiments, the OD width D is different from the OD width E. In at least one embodiment, one or more of the advantages described herein can be achieved in the head circuit corresponding to the head unit 600B or in an IC device including such a head circuit.

[0098] Figure 7A and Figure 7B Tables 700A and 700B schematically illustrate various layout configurations with different unit heights according to some embodiments. Tables 700A and 700B show various cases in which one or more unit head units can be combined to form a larger head unit. In some embodiments, each unit head unit corresponds to Figures 4A-4E One of the head units 400A-400E or Figure 6B Part A or part B in the text.

[0099] Figure 7A Table 700A shows various layout configurations according to some embodiments, where the unit head units have the same or different unit heights.

[0100] As shown in column 710 of Table 700A, a single-cell-height header cell consists of a single header cell with a cell height A. For such a header cell, a configuration is indicated at A.

[0101] As shown in column 720 of Table 700A, a double-height header cell is a combination of two header cells with corresponding cell heights A and B. There are two cases: where A is different from B, and where A is the same as B. For A being different from B, there are two configurations, namely, as follows... Figure 6A The diagram shows AB, and portions A and B of AB interchange positions along the Y-axis. Figure 6B The inverse configuration of BA. For cases where A and B are the same, there exists a BA with the same cell heights A and B. Figure 6B The configuration in the text corresponds to a configuration AA.

[0102] As shown in column 730 of Table 700A, a triple-height header unit is a combination of three header units with corresponding heights A, B, and C. There are three cases: all three heights A, B, and C are different; two of the header units have the same height; and all three of the header units have the same height. For the case where all three heights A, B, and C are different, there are six different configurations where the three header units with corresponding heights A, B, and C can be stacked along the Y-axis: ABC, ACB, BAC, BCA, CAB, and CBA. For the case where two of the header units have the same height, such as A and C being the same, there are three different configurations where the three header units with corresponding heights A, A, and B can be stacked along the Y-axis: AAB, ABA, and BAA. For the case where all the header units have the same height, such as A, B, and C being equal, there is one configuration: AAA.

[0103] As shown in column 740 of Table 700A, according to various embodiments, further configurations in which more than three unit head units can be combined into a larger head unit are possible. In at least one embodiment, in relation to... Figure 7A One or more advantages described herein can be achieved in the head circuit corresponding to the described head unit and / or in the IC device that includes such head circuit.

[0104] Figure 7B Table 700B shows various layout configurations according to some embodiments, where the OD widths of the unit header cells are the same or different.

[0105] As shown in column 712 of Table 700B, a single-unit height header unit consists of a single header unit with an OD width D. For such a header unit, a configuration is indicated at D.

[0106] As shown in column 722 of Table 700B, a double-unit-height header unit is a combination of two unit header units with corresponding OD widths D and E. There are two cases: where D is different from E and where D is the same as E. For D being different from E, there are two configurations, namely, as follows... Figure 6B The diagram shows DE, and the parts A and B within it, whose positions are interchanged along the Y-axis. Figure 6B The inverse configuration of ED. For the case where D and E are the same, there exists a ED where the widths D and E are the same. Figure 6B The configuration in the document corresponds to a configuration DD.

[0107] As shown in column 732 of Table 700B, a triple-height header unit is a combination of three header units with corresponding OD widths D, E, and F. There are three cases: all three OD widths D, E, and F are different; two OD widths are the same; and all three OD widths are the same. For the case where all three OD widths D, E, and F are different, there are six different configurations where the three header units with corresponding OD widths D, E, and F can be stacked along the Y-axis: DEF, DFE, EDF, EFD, FDE, and FED. For the case where two OD widths are the same, such as D and F being identical, there are three different configurations where the three header units with corresponding OD widths D, D, and E can be stacked along the Y-axis: DDE, DED, and EDD. For the case where all OD widths are the same, such as D, E, and F being equal, there is one configuration: DDD.

[0108] As shown in column 742 of Table 700B, according to various embodiments, further configurations in which more than three unit head units can be combined into a larger head unit are possible. In at least one embodiment, in relation to... Figure 7B One or more advantages described herein can be achieved in the head circuit corresponding to the described head unit and / or in the IC device that includes such head circuit.

[0109] In some embodiments, regarding Figures 3A-7B The described configuration and / or advantages of the head unit and head circuitry apply to the tail unit and tail circuitry, wherein the PMOS, NMOS, TVDD, VDD, and VSS in the head unit and head circuitry correspond to the NMOS, PMOS, TVSS, VSS, and VDD in the tail unit and tail circuitry. About Figures 8A-8E and Figures 9A-9C Several examples describing tail units and tail circuits.

[0110] Figures 8A-8E This is a schematic circuit diagram of various tail circuits 800A-800E according to some embodiments. In at least one embodiment, one or more of the tail circuits 800A-800E correspond to Figure 2 The tail circuit 220 in the middle. It has... Figure 2 The corresponding component in Figures 8A-8E The components in are made of Figure 2 The same reference numerals indicate or are represented by Figure 2 The figure reference numerals are indicated by adding 600.

[0111] exist Figures 8A-8E In the middle, each of the tail circuits 800A-800E includes information about Figure 2 The first transistor N2 and the second transistor P2 are described. Specifically, the gate terminals of transistors N2 and P2 are electrically coupled to receive signals from the gate terminals of transistors N2 and P2. Figure 2 The control signal CS2 corresponds to the control signal Control. Transistor N2 is a switching transistor, including a first terminal 821 electrically coupled to the VSS power rail and a second terminal 822 electrically coupled to the TVSS power rail. Transistor P2 is an electrically coupled dummy transistor, including a first terminal 825 and a second terminal 826 electrically coupled to receive the same predetermined voltage.

[0112] The predetermined voltages at terminals 825 and 826 of transistor P2 differ between the tail circuits 800A-800E. Figure 8A In the tail circuit 800A, the predetermined voltage on terminals 825 and 826 of transistor P2 is VDD. Figure 8B In the tail circuit 800B, the predetermined voltage on terminals 825 and 826 of transistor P2 is TVSS. Figure 8C In the tail circuit 800C, the predetermined voltage on terminals 825 and 826 of transistor P2 is VSS. Figure 8D In the tail circuit 800D, the predetermined voltage on terminals 825 and 826 of transistor P2 is the control signal Control. Figure 8E In the tail circuit 800E, a predetermined voltage Vp is present on terminals 825 and 826 of transistor P2, which is a voltage or signal other than the power supply voltages VDD, TVSS, and VSS, and the control signal Control. As described herein, examples of predetermined voltages on terminals 825 and 826 of transistor P2 according to some embodiments include power supply voltages (such as VDD, TVSS, or VSS), control signals (such as Control), or voltages other than VDD, TVSS, VSS, and Control. Other voltage configurations are within the range of various embodiments. In at least one embodiment, one or more advantages described herein may be achieved in one or more of the tail circuits 800A-800E and / or in IC devices including one or more of the tail circuits 800A-800E.

[0113] Figure 9A This is a schematic diagram of the layout of a tail unit 900A according to some embodiments. In at least one embodiment, the tail unit 900A corresponds to a tail circuit 800A. In at least one embodiment, the tail unit 900A is stored as a standard unit in a standard unit library on a non-transitory computer-readable medium.

[0114] exist Figure 9A In the exemplary configuration, the tail unit 900A is Figure 4A A mirror image of the head unit 400A. For example, the tail unit 900A is obtained by flipping the head unit 400A across the X-axis. In some embodiments, an exemplary layout of the tail units corresponding to the tail circuits 800B-800E is obtained by flipping the corresponding head units 400B-400E across the X-axis. Figure 4A The corresponding component in Figure 9A The components in are made of Figure 9A The reference numerals are increased by 500 to indicate this. For example, the MO conductive patterns 971-975 and the boundary 980 with edges 981-984 in the tail unit 900A correspond to the MO conductive patterns 471-475 and the boundary 480 with edges 481-484 in the head unit 400A.

[0115] Figure 9A The markings on the left indicate signals or voltages applicable to M0 conductive patterns 971-975. For example, M0 conductive pattern 971 is configured as a first power rail, such as a VSS power rail, for providing VSS to functional circuitry operable by VSS. As described herein, M0 conductive pattern 972 is configured as a second power rail, such as a TVSS power rail, for receiving TVSS from another circuit. In at least one embodiment, TVSS is applied to M0 conductive pattern 972 from a conductive pattern or power rail located in a metal layer above the M0 layer (e.g., in the M1 layer) through one or more V0 via structures. M0 conductive pattern 973 is configured as an additional VSS power rail for providing VSS to functional circuitry. M0 conductive pattern 974 is configured to apply a control signal Control to the gate terminals of transistors N2 and P2. M0 conductive pattern 975 is configured as a third power rail, such as a VDD power rail, which electrically couples the first and second terminals of transistor P2. This configuration corresponds to a tail circuit 800A in which a predetermined voltage on the terminals of transistor P2 is VDD. In at least one embodiment, the additional VSS power rails 971, 973 and the corresponding VD via structures contribute to achieving one or more of the aforementioned advantages, such as increased power current density and reduced RV. ON Reduced chip or wafer area, etc.

[0116] Figure 9B This is a schematic circuit diagram of the tail circuit 900B according to some embodiments.

[0117] Tail circuit 900B includes sub-circuits 911 and 912 electrically coupled together at VDD power rail 913. Sub-circuit 911 corresponds to tail circuit 800A and includes a switching transistor N91 and a dummy transistor P91. Switching transistor N91 and dummy transistor P91 correspond to switching transistor N2 and dummy transistor P2 of tail circuit 800A. Transistor N91 has first and second terminals correspondingly electrically coupled to VSS and TVSS. Dummy transistor P91 has first and second terminals electrically coupled to receive VDD. The gates of transistors N91 and P91 are electrically coupled to receive a control signal Control. Sub-circuit 912 corresponds to tail circuit 800A and includes a switching transistor N92 and a dummy transistor P92. Switching transistor N92 and dummy transistor P92 correspond to switching transistor N2 and dummy transistor P2 of tail circuit 800A. Transistor N92 has first and second terminals correspondingly electrically coupled to VSS and TVSS. Dummy transistor P92 has first and second terminals electrically coupled to receive VDD. The gates of transistors N92 and P92 are electrically coupled to receive the control signal Control. The terminal of transistor P91 is electrically coupled to the terminal of transistor P92 at the VDD power rail 913. Sub-circuits 911 and 912 are configured as described above. Figure 2 Operate as described above.

[0118] The configuration in which tail circuit 900B includes two sub-circuits corresponding to tail circuit 800A is an example. Other configurations are within the scope of the various embodiments. For example, in some embodiments, tail circuit 900B includes more than two sub-circuits and / or the sub-circuits of tail circuit 900B correspond to any one of tail circuits 800A-800E. In at least one embodiment, one or more of the advantages described herein may be realized in tail circuit 900B and / or in the IC device including tail circuit 900B.

[0119] Figure 9C This is a schematic diagram of the layout of a tail unit 900C according to some embodiments. In at least one embodiment, the tail unit 900C corresponds to a tail circuit 900B. In at least one embodiment, the tail unit 900C is stored as a standard unit in a standard unit library on a non-transitory computer-readable medium. Figure 9B and Figure 9C Corresponding components are indicated by the same reference numerals.

[0120] exist Figure 9CIn the exemplary configuration, when the PMOS, NMOS, TVDD, VDD, and VSS in the head unit 600B are correspondingly replaced with the NMOS, PMOS, TVSS, VSS, and VDD in the tail unit 900C, the layout of the tail unit 900C is the same as that of the head unit 600B. In at least one embodiment, one or more of the advantages described herein can be achieved in the tail circuit corresponding to the tail unit 900C and / or in the IC device including such tail circuit.

[0121] Figure 10A This is a flowchart of a method 1000A for generating a layout diagram and using the layout diagram to manufacture an IC device, according to some embodiments.

[0122] According to some embodiments, method 1000A may, for example, use EDA system 1500 (discussed below). Figure 15 ) and Integrated Circuit (IC) Manufacturing System 1600 (discussed below) Figure 16 This is implemented using [method 1000A]. Examples of layout diagrams for method 1000A include those disclosed herein. Examples of IC devices manufactured according to method 1000A include IC devices having one or more power control circuits, which include one or more head circuits and / or tail circuits as described herein. Figure 10A In the method 1000A, blocks 1005 and 1015 are included.

[0123] At box 1005, a layout diagram is generated, which includes patterns representing one or more circuit regions, circuit systems, circuits, or units, as shown in the diagram. Figures 4A-4E , Figure 6B , Figure 7A , Figure 7B , Figure 9A , Figure 9C As described above. Examples of IC devices corresponding to the layout diagram generated by block 1005 include one or more power control circuits, which include header and / or tail circuits as described herein. References below... Figure 10B Let's discuss box 1005 in more detail. The process proceeds from box 1005 to box 1015.

[0124] At box 1015, based on the layout diagram, at least one of the following is performed: (A) one or more photolithography exposures are performed; (B) one or more semiconductor masks are fabricated; or (C) one or more components in an IC device layer are fabricated. See below for reference. Figure 10C See box 1015 for a more detailed discussion.

[0125] Figure 10B This is a flowchart of a method 1000B for generating a layout diagram according to some embodiments. More specifically, Figure 10B The flowchart illustrates the description of some embodiments. Figure 10A An additional box for an instance of the process implemented in box 1005. Figure 10B In the middle, frame 1005 includes frames 1025 and 1035.

[0126] At box 1025, at least one cell having at least one head circuit and / or tail circuit is generated or retrieved from the cell library. For example, generating or retrieving from the cell library regarding... Figures 4A-4E , Figure 6B , Figure 7A , Figure 7B , Figure 9A , Figure 9C The description refers to head units and / or tail units corresponding to one or more layout diagrams. In at least one embodiment, the required R is based on ensuring the expected operation of the functional circuitry that will be powered by the head units and / or tail units. ON Select head cells and / or tail cells for retrieval or generation. Other considerations for retrieving or generating head cells and / or tail cells include, but are not limited to, the cell height and OD width of one or more other cells that the head cell and / or tail cell will be placed adjacent to.

[0127] At block 1035, at least one unit having at least one head circuit and / or tail circuit is positioned adjacent to one or more other units in the layout diagram. In some embodiments, multiple head or tail units are placed adjacent to each other to form a larger head or tail unit, as per [reference to...]. Figures 7A-7B As described above. In one or more embodiments, at least one unit having at least one head circuit and / or tail circuit is placed adjacent to other units constituting a functional circuit, and the head unit and / or tail unit provides power to the functional circuit. In at least one embodiment, the layout diagram of the generated IC device is stored on a non-transitory computer-readable medium.

[0128] Figure 10C This is a flowchart of a method 1000C for manufacturing one or more components of an IC device based on a layout diagram, according to some embodiments. More specifically, Figure 10C The flowchart illustrates the description of some embodiments. Figure 10A An additional box for an instance of the process implemented in box 1015. Figure 10C In the middle, frame 1015 includes frames 1045, 1055, and 1065.

[0129] At block 1045, an active region and at least one gate region are formed over the substrate to configure first and second transistors of different types. In some embodiments, the active region, gate region, and / or transistor correspond to... Figures 2-9C The active region, gate region, and / or one or more of the transistors described.

[0130] Exemplary manufacturing processes begin with a substrate, such as regarding Figure 5A The substrate 550 is described. In at least one embodiment, the substrate comprises silicon, silicon germanium (SiGe), gallium arsenide, or other suitable semiconductor material. In some embodiments, the substrate comprises an insulating substrate or a silicon-on-insulator (SOI) substrate. Active regions are formed in or over the substrate using one or more masks corresponding to one or more active regions in the layout diagrams described herein. For example, PMOS active region 401 and NMOS active region 402 are as described regarding... Figure 4A It forms as described.

[0131] A gate dielectric material layer is deposited over a substrate. Exemplary materials for the gate dielectric material layer include, but are not limited to, high-k dielectric layers, interface layers, and / or combinations thereof. In some embodiments, the gate dielectric material layer is deposited over the substrate using atomic layer deposition (ALD) or other suitable techniques. A gate electrode layer is deposited over the gate dielectric material layer. Exemplary materials for the gate electrode layer include, but are not limited to, polysilicon, metals, Al, AlTi, Ti, TiN, TaN, Ta, TaC, TaSiN, W, WN, MoN, and / or other suitable conductive materials. In some embodiments, the gate electrode layer is deposited using chemical vapor deposition (CVD), physical vapor deposition (PVD or sputtering), plating, atomic layer deposition (ALD), and / or other suitable processes. A patterning process is then performed using one or more masks corresponding to one or more gate electrodes in the layout diagrams described herein. Thus, the gate dielectric material layer is patterned as one or more gate dielectric layers, such as gate dielectric layers 554, 555, and the gate electrode layer is patterned as at least one gate electrode or gate structure, such as a reference. Figure 5B The gate electrode 511 or 512 is described. At least one gate electrode extends continuously from the first active region to the second active region, for example, as described in... Figure 4A As stated above.

[0132] In at least one embodiment, spacers are formed on opposite sides of each gate electrode by deposition and patterning. Exemplary materials for the spacers include, but are not limited to, silicon nitride, silicon oxynitride, silicon carbide, and other suitable materials. Exemplary deposition processes include, but are not limited to, plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), subatmospheric pressure chemical vapor deposition (SACVD), atomic layer deposition (ALD), etc. Exemplary patterning processes include, but are not limited to, wet etching processes, dry etching processes, or combinations thereof. Drain / source regions (such as those related to...) Figure 5AThe described drain / source regions (551, 552) are formed in the active region of the substrate. In at least one embodiment, the drain / source regions are formed using a gate electrode and spacers as masks. For example, the formation of the drain / source regions is performed by an ion implantation or diffusion process. Depending on the type of device or transistor, the drain / source regions are doped with p-type dopants (such as boron or BF2), n-type dopants (such as phosphorus or arsenic), and / or combinations thereof. Thus, different types of first and second transistors are formed by at least one gate electrode above the corresponding first and second active regions. In some embodiments, transistors of the functional circuitry of the IC device are also formed in the described process.

[0133] At block 1055, an MD contact structure and a via structure are formed above the active region and the gate region. In some embodiments, the MD contact structure and the via structure correspond to... Figures 4A-4E , Figures 5A-5B , Figure 6B , Figure 9A , Figure 9C Describe one or more MD contact structures and through-hole structures.

[0134] In an exemplary manufacturing process, a conductive layer, such as a metal, is deposited over a substrate on which a transistor is formed, thereby creating an electrical connection with the drain / source regions of the transistor. A planarization process is performed to planarize the conductive layer, obtaining a matte contact structure (MD) that is electrically contacted with the underlying drain / source regions, for example, regarding... Figure 5A , Figure 5B The described MD contact structures are 421 and 431-434. Planarization processes include, for example, chemical mechanical polishing (CMP). A dielectric layer is deposited over the substrate, on which drain / source contacts are formed. The dielectric layer is etched, and the etched portions are filled with a conductive material, such as a metal, to form one or more via structures, such as those described above. Figure 5A and Figure 5B The VD via structures 450, 454, and 456-459 are described. A planarization process is then performed. In some embodiments, MD contact structures and VD / VG via structures are also formed above the transistors of the functional circuit in the described process.

[0135] At frame 1065, a conductive layer is deposited and patterned to form first to fourth conductive patterns. The first conductive pattern is electrically coupled to a first terminal of the first transistor, the second conductive pattern is electrically coupled to a second terminal of the first transistor, the third conductive pattern is electrically coupled to a first terminal of the first transistor, and the fourth conductive pattern is electrically coupled to the first and second terminals of the second transistor to form the second transistor as a dummy transistor. In at least one embodiment, the first to fourth conductive patterns extend along the X-axis.

[0136] In an exemplary manufacturing process, an MO layer comprising a conductive material (such as a metal) is deposited over a planarized structure and patterned to form various MO conductive patterns electrically coupled to corresponding terminals of corresponding first and second transistors, as per [reference to...]. Figure 4A The M0 conductive patterns 471-475 are described herein. The M0 conductive patterns 471-475 include at least one VDD power rail and at least one VSS power rail. In the exemplary configuration described herein, the conductive patterns are located within the M0 layer. However, other metal layers are within the scope of various embodiments.

[0137] In some embodiments, another via layer and / or metal layer is sequentially deposited over the MO layer and patterned to obtain an interconnect structure, such as regarding Figure 5A , Figure 5B Interconnection structure 560 is described. Interconnection structure 560 electrically couples VDD and VSS power rails formed by corresponding conductive patterns in the MO layer to functional circuitry, enabling the functional circuitry to operate via power supplied from the VDD and VSS power rails. In at least one embodiment, one or more of the advantages described herein can be realized in an IC device manufactured according to the process described.

[0138] The methods include exemplary operations, but they need not be performed in the order shown. Operations may be added, replaced, rearranged, and / or eliminated as appropriate, within the spirit and scope of embodiments of the invention. Embodiments combining different features and / or different embodiments are within the scope of the invention and will be apparent to those skilled in the art upon reviewing the invention.

[0139] Figure 11A This is a schematic top view of a planar transistor 1100 according to some embodiments. Figure 11B It is the edge of the planar transistor 1100 Figure 11A A schematic cross-sectional view of line X1-X1. Figure 11C It is the edge of the planar transistor 1100 Figure 11A A schematic cross-sectional view of line Y1-Y1.

[0140] like Figure 11A As shown, the planar transistor 1100 includes an active region or source / drain region 1110, 1120 and a gate region 1130 extending along the Y direction across the source / drain regions 1110, 1120. Figure 11B As shown, source / drain regions 1110 and 1120 and gate region 1130 are formed above substrate 1140. Figure 11C As shown, a channel region 1150 is formed below the gate region 1130 and between the source / drain regions 1110 and 1120.

[0141] Figure 12AThis is a schematic top view of a FINFET 1200 according to some embodiments. Figure 12B It is the edge of FINFET 1200 Figure 12A A schematic cross-sectional view of line X2-X2. Figure 12C It is the edge of FINFET1200 Figure 12A A schematic cross-sectional view of line Y2-Y2.

[0142] like Figure 12A As shown, the FINFET 1200 includes an active region or source / drain region 1210, 1220 and a gate region 1230 extending along the Y direction across the source / drain regions 1210, 1220. The source / drain regions 1210, 1220 include a plurality of fins 1260 extending along the X direction (in... Figure 12B (Best visible in the middle). Figure 12B As shown, source / drain regions 1210, 1220 and gate region 1230 are formed above substrate 1240, and fin 1260 is located below gate region 1230. Figures 12B-12C As shown, the channel region 1250 is formed above the fin 1260, below the gate region 1230, and between the source / drain regions 1210 and 1220.

[0143] Figure 13A This is a schematic top view of the nanosheet FET 1300 according to some embodiments. Figure 13B It is the edge of the nanosheet FET1300 Figure 13A A schematic cross-sectional view of line X3-X3. Figure 13C It is the edge of the nanosheet FET 1300 Figure 13A A schematic cross-sectional view of line Y3-Y3.

[0144] like Figure 13A As shown, the nanosheet FET 1300 includes an active region or source / drain region 1310, 1320 and a gate region 1330 extending along the Y direction across the source / drain regions 1310, 1320. The source / drain regions 1310, 1320 include multiple nanosheets 1360 (in... Figure 13B (Best visible in the middle). Figure 13B As shown, source / drain regions 1310 and 1320 and a gate region 1330 are formed above substrate 1340. Nanosheet 1360 is surrounded by gate region 1330. Figures 13B-13C As shown, the channel region 1350 is formed between the nanosheet 1360 and the gate region 1330, and between the source / drain regions 1310 and 1320.

[0145] Figure 14A This is a schematic top view of a nanowire FET 1400 according to some embodiments. Figure 14BIt is the edge of the nanowire FET1400 Figure 14A A schematic cross-sectional view of line X4-X4. Figure 14C It is the edge of the nanowire FET 1400 Figure 14A A schematic cross-sectional view of line Y4-Y4.

[0146] like Figure 14A As shown, the nanowire FET 1400 includes an active region or source / drain region 1410, 1420 and a gate region 1430 extending along the Y direction across the source / drain regions 1410, 1420. The source / drain regions 1410, 1420 include multiple nanowires 1460 (in... Figure 14B (Best visible in the middle). Figure 14B As shown, source / drain regions 1410 and 1420 and a gate region 1430 are formed above a substrate 1440. Nanowires 1460 are surrounded by the gate region 1430. Figures 14B-14C As shown, the channel region 1450 is formed between the nanowire 1460 and the gate region 1430, and between the source / drain regions 1410 and 1420.

[0147] In some embodiments, at least one of the methods discussed above is performed wholly or partially by at least one EDA system. In some embodiments, the EDA system may be used as part of the design room of the IC manufacturing system discussed below.

[0148] Figure 15 This is a block diagram of an electronic design automation (EDA) system 1500 according to some embodiments.

[0149] In some embodiments, EDA system 1500 includes an APR system. According to some embodiments, the design layout methods described herein represent lead routing arrangements according to one or more embodiments, which may be implemented using EDA system 1500, for example.

[0150] In some embodiments, the EDA system 1500 is a general-purpose computing device that includes a hardware processor 1502 and a non-transitory computer-readable storage medium 1504. Among other things, the storage medium 1504 is encoded, i.e., stores, computer program code 1506, i.e., a set of executable instructions. The instructions 1506, executed by the hardware processor 1502, represent (at least partially represent) an EDA tool that implements some or all of the methods described herein according to one or more embodiments (hereinafter, the process and / or method).

[0151] Processor 1502 is electrically coupled to computer-readable storage medium 1504 via bus 1508. Processor 1502 is also electrically coupled to I / O interface 1510 via bus 1508. Network interface 1512 is also electrically coupled to processor 1502 via bus 1508. Network interface 1512 is connected to network 1514, thereby enabling processor 1502 and computer-readable storage medium 1504 to be connected to external components via network 1514. Processor 1502 is configured to execute computer program code 1506 encoded in computer-readable storage medium 1504 to make system 1500 available for performing part or all of the process and / or method. In one or more embodiments, processor 1502 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0152] In one or more embodiments, the computer-readable storage medium 1504 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 1504 includes semiconductor or solid-state memory, magnetic tape, portable computer floppy disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disk, the computer-readable storage medium 1504 includes read-only optical disk storage (CD-ROM), optical disk read / write (CD-R / W), and / or digital video optical disk (DVD).

[0153] In one or more embodiments, storage medium 1504 stores computer program code 1506 configured to enable system 1500 (where such execution (at least partially) represents an EDA tool) to perform part or all of the process and / or method. In one or more embodiments, storage medium 1504 also stores information that facilitates the execution of part or all of the process and / or method. In one or more embodiments, storage medium 1504 stores a standard cell library 1507, including such standard cells disclosed herein.

[0154] EDA system 1500 includes an I / O interface 1510. The I / O interface 1510 is coupled to external circuitry. In one or more embodiments, the I / O interface 1510 includes a keyboard, a numeric keypad, a mouse, a trackball, a touchpad, a touchscreen, and / or cursor arrow keys that transmit information and commands to processor 1502.

[0155] EDA system 1500 also includes a network interface 1512 coupled to processor 1502. Network interface 1512 allows system 1500 to communicate with network 1514, through which one or more other computer systems are connected. Network interface 1512 includes a wireless network interface such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, some or all of the described process and / or method are implemented in two or more systems 1500.

[0156] System 1500 is configured to receive information via I / O interface 1510. The information received via I / O interface 1510 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters for processing by processor 1502. The information is transferred to processor 1502 via bus 1508. EDA system 1500 is configured to receive UI-related information via I / O interface 1510. This information is stored as a user interface (UI) 1542 on computer-readable medium 1504.

[0157] In some embodiments, part or all of the process and / or method is implemented as a standalone software application executed by a processor. In some embodiments, part or all of the process and / or method is implemented as a software application as part of an additional software application. In some embodiments, part or all of the process and / or method is implemented as a plug-in to a software application. In some embodiments, at least one of the process and / or method is implemented as a software application as part of an EDA tool. In some embodiments, part or all of the process and / or method is implemented as a software application used by an EDA system 1500. In some embodiments, a software application such as those available from CADENCE DESIGNSYSTEMS is used. Alternatively, use other suitable layout generation tools to generate layout diagrams that include standard cells.

[0158] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / in-system storage or storage units, such as one or more of optical discs (such as DVDs), magnetic disks (such as hard disks), and semiconductor memories (such as ROMs, RAMs, memory cards, etc.).

[0159] Figure 16This is a block diagram of an integrated circuit (IC) manufacturing system 1600 and its associated IC manufacturing process according to some embodiments. In some embodiments, based on a layout diagram, for example, the manufacturing system 1600 is used to manufacture at least one of (A) one or more semiconductor masks or (B) at least one component of a layer of a semiconductor integrated circuit.

[0160] exist Figure 16 In this IC manufacturing system 1600, entities such as design room 1620, mask room 1630, and IC manufacturer / fab (“fab”) 1650 interact with each other in the design, development, and manufacturing cycle and / or in services related to the manufacture of IC devices 1660. The entities in system 1600 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design room 1620, mask room 1630, and IC fab 1650 are owned by a single, larger company. In some embodiments, two or more of design room 1620, mask room 1630, and IC fab 1650 coexist in a shared facility and use shared resources.

[0161] Design studio (or design team) 1620 generates IC design layout 1622. IC design layout 1622 includes various geometric patterns designed for IC device 1660. These geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that form various components of the IC device 1660 to be manufactured. The various layers combine to form various IC functions. For example, a portion of IC design layout 1622 includes various IC components such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for pads formed in a semiconductor substrate (such as a silicon wafer) and various material layers disposed on the semiconductor substrate. Design studio 1620 implements appropriate design processes to form IC design layout 1622. These design processes include one or more of logic design, physical design, or place-and-route operations. IC design layout 1622 is presented in one or more data files containing geometric pattern information. For example, IC design layout 1622 may be expressed in GDSII or DFII file format.

[0162] Mask chamber 1630 includes data preparation 1632 and mask fabrication 1644. Mask chamber 1630 uses an IC design layout 1622 to fabricate one or more masks 1645 for fabricating various layers of an IC device 1660 according to the IC design layout 1622. Mask chamber 1630 performs mask data preparation 1632, in which the IC design layout 1622 is translated into a representative data file (“RDF”). Mask data preparation 1632 provides the RDF to mask fabrication 1644. Mask fabrication 1644 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (mask) 1645 or a semiconductor wafer 1653. Mask layout data preparation 1632 processes the design layout 1622 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fab 1650. Figure 16 In this embodiment, mask data preparation 1632 and mask manufacturing 1644 are shown as separate elements. In some embodiments, mask data preparation 1632 and mask manufacturing 1644 may be collectively referred to as mask data preparation.

[0163] In some embodiments, mask data preparation 1632 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, or other processing effects. OPC adjustment IC design layout diagram 1622 is shown. In some embodiments, mask data preparation 1632 includes other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assistance, phase-shift masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography (ILT) is also used, which treats OPC as an inverse imaging problem.

[0164] In some embodiments, mask data preparation 1632 includes a mask rule checker (MRC) that uses a set of mask creation rules to check the IC design layout 1622, which has already been processed in the OPC, to ensure sufficient margin to accommodate variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 1622 to compensate for constraints during mask fabrication 1644, which can undo a portion of the modifications performed by the OPC to satisfy the mask creation rules.

[0165] In some embodiments, mask data preparation 1632 includes a lithography process check (LPC), which simulates the process to be implemented by IC fab 1650 to manufacture IC device 1660. The LPC simulates the process based on IC design layout 1622 to create a simulated manufactured device, such as IC device 1660. Processing parameters in the LPC simulation may include parameters related to various processes in the IC manufacturing cycle, parameters related to the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as aerial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and combinations thereof. In some embodiments, after a simulated manufactured device has been created via LPC, if the simulated device is not close enough in shape to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 1622.

[0166] It should be understood that, for clarity, the above description of mask data preparation 1632 has been simplified. In some embodiments, data preparation 1632 includes additional features such as logic operations (LOPs) to modify the IC design layout 1622 according to manufacturing rules. Additionally, the processes applied to the IC design layout 1622 during data preparation 1632 may be performed in various different sequences.

[0167] Following mask data preparation 1632 and during mask fabrication 1644, a mask 1645 or a set of masks 1645 is fabricated based on a modified IC design layout 1622. In some embodiments, mask fabrication 1644 includes performing one or more photolithographic exposures based on the IC design layout 1622. In some embodiments, an electron beam (e-beam) or multi-electron beam mechanism is used to form a pattern on the mask (photomask or photomask slab) 1645 based on the modified IC design layout 1622. The mask 1645 can be formed using various techniques. In some embodiments, the mask 1645 is formed using a binary technique. In some embodiments, the mask pattern includes opaque areas and transparent areas. Radiation beams, such as ultraviolet (UV) beams, used to expose an image-sensitive material layer (e.g., photoresist) already coated on the wafer are blocked by the opaque areas and pass through the transparent areas. In one example, the binary mask version of mask 1645 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated on the opaque regions of the binary mask. In another example, mask 1645 is formed using a phase-shifting technique. In the phase-shifting mask (PSM) version of mask 1645, various features in the pattern formed on the phase-shifting mask are configured to have appropriate phase aberrations to enhance resolution and imaging quality. In various examples, the phase-shifting mask can be a decaying PSM or an alternating PSM. The mask generated by mask fabrication 1644 is used in a variety of processes. For example, such a mask is used in ion implantation processes to form various doped regions in semiconductor wafer 1653, in etching processes to form various etched regions in semiconductor wafer 1653, and / or in other suitable processes.

[0168] IC Fab 1650 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various IC products. In some embodiments, IC Fab 1650 is a semiconductor manufacturing plant. For example, there may be a manufacturing plant for front-end manufacturing (FEOL) of multiple IC products, a second manufacturing plant for providing back-end manufacturing (BEOL) for the interconnection and packaging of IC products, and a third manufacturing plant for providing other services for the manufacturing operations.

[0169] IC fab 1650 includes manufacturing tool 1652 configured to perform various manufacturing operations on semiconductor wafer 1653 to manufacture IC device 1660 according to a mask (e.g., mask 1645). In various embodiments, manufacturing tool 1652 includes one or more of the following: wafer stepper, ion implanter, photoresist coating machine, processing chamber (e.g., CVD chamber or LPCVD furnace), CMP system, plasma etching system, wafer cleaning system, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as discussed herein.

[0170] IC fab 1650 uses mask 1645, manufactured by mask chamber 1630, to fabricate IC device 1660. Therefore, IC fab 1650 fabricates IC device 1660 at least indirectly using IC design layout 1622. In some embodiments, semiconductor wafer 1653 is fabricated from IC device 1660 by IC fab 1650 using mask 1645. In some embodiments, IC fabrication includes one or more photolithographic exposures based at least indirectly on IC design layout 1622. Semiconductor wafer 1653 includes a silicon substrate or other suitable substrate having material layers formed thereon. Semiconductor wafer 1653 also includes one or more of various doped regions, dielectric components, multilayer interconnects, etc. (formed in subsequent fabrication steps).

[0171] Regarding integrated circuit (IC) manufacturing systems (e.g., Figure 16 Details of the system 1600 and the associated IC manufacturing process can be found, for example, in U.S. Patent No. 9,256,709, granted February 9, 2016; U.S. Pre-Publication No. 20150278429, published October 1, 2015; U.S. Pre-Publication No. 20140040838, published February 6, 2014; and U.S. Patent No. 7,260,442, granted August 21, 2007, the entire contents of which are incorporated herein by reference.

[0172] For example, in U.S. Patent No. 9,256,709, an IC design layout is generated in a design room (or design team). The IC design layout includes various geometric patterns designed for an IC device. These geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC device to be manufactured. The various layers combine to form various IC functions. For example, portions of the IC design layout include various IC components such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for forming pads in the semiconductor. These openings will be formed on a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. The design room performs appropriate design processes to form the IC design layout. These design processes may include logic design, physical design, and / or placement and routing. The IC design layout is presented in one or more data files containing geometric pattern information. A mask room uses the IC design layout to fabricate one or more masks, which are used to fabricate the various layers of the IC device according to the IC design layout. The mask room performs mask data preparation, in which the IC design layout is converted into a form that can be physically written by a mask writer. The design layout prepared by mask data preparation is modified to conform to a specific mask manufacturer and / or mask vendor before fabrication. In this embodiment, mask data preparation and mask fabrication are illustrated as separate elements; however, they can be collectively referred to as mask data preparation. Mask data preparation typically includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, or other processing effects. Mask data preparation may include other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-shift masks, other suitable techniques, or combinations thereof. Mask data preparation 132 also includes a mask rule checker (MRC), which uses a set of mask creation rules to check the IC design layout that has already been processed in the OPC. These mask creation rules may include some geometric and connectivity constraints to ensure sufficient margin.

[0173] For example, in U.S. Prelicense Publication No. 20150278429, in one embodiment, the IC manufacturing system may employ maskless lithography techniques, such as electron beam lithography or optical maskless lithography. In such a system, mask fabrication is bypassed, and the IC design layout is modified through data preparation suitable for wafer processing using a specific maskless lithography technique. The data preparation modifies the design layout to suit subsequent operations in the IC manufacturing system. The result of the data preparation is represented by one or more data files, such as files in GDSII or DFII file formats. The one or more data files include information on geometric patterns, such as polygons representing primary design patterns and / or auxiliary components. In this embodiment, the one or more data files also include auxiliary data generated by the data preparation. The auxiliary data will be used to enhance various operations of the IC manufacturing system, such as mask fabrication performed in the mask chamber and wafer exposure performed by the IC manufacturer.

[0174] For example, in U.S. Prelicity License No. 20140040838, an IC design layout is presented in one or more data files containing geometric pattern information. In one example, the IC design layout is represented in the “GDS” format known in the art. In alternative embodiments, the IC design layout may be transferred between components in an IC manufacturing system in alternative file formats such as DFII, CIF, OASIS, or any other suitable file type. IC design layout 300 includes various geometric patterns representing components of an integrated circuit. For example, the IC design layout may include primary IC components such as active regions, gate electrodes, source and drain electrodes, metal lines, interlayer interconnect vias, and openings for forming pads in the semiconductor, the openings being formed on a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate. The IC design layout may also include auxiliary components, such as those for imaging effects, processing enhancement and / or mask recognition information.

[0175] For example, in U.S. Patent No. 7,260,442, a mask manufacturing system includes: a processing tool for processing a mask; a metrology tool connected to the processing tool for inspecting the mask and obtaining inspection results; and a controller coupled to the processing tool and the metrology tool for generating a manufacturing model of the processing tool and calibrating the manufacturing model based on equipment data, material data, and the mask inspection results. The mask manufacturing system may include at least one processing tool, a metrology tool, a controller, a database, and a manufacturing execution system. The processing tool may be an exposure tool, a developer, an etcher, or a photoresist stripper. The metrology tool performs post-etch or post-stripping inspections and obtains post-etch or post-stripping inspection results, respectively. The controller provides operation-to-operation control for the processing tool, including feedforward and feedback control. The controller receives post-etch or post-stripping inspection results from the metrology tool and retrieves device and material data from the database. The controller, connected to the manufacturing execution system, generates a manufacturing model of the processing tool and calibrates the manufacturing model based on equipment data, material data, and the mask inspection results.

[0176] In some embodiments, the integrated circuit (IC) device includes functional circuitry and power control circuitry. The functional circuitry is electrically coupled to a first power node and is operable by a first power supply voltage at the first power node. The power control circuitry includes a first transistor of a first type and a second transistor of a second type different from the first type. The first transistor includes a gate terminal configured to receive a control signal, a first terminal electrically coupled to the first power node, and a second terminal electrically coupled to a second power node. The second transistor includes a gate terminal configured to receive a control signal and first and second terminals configured to receive a predetermined voltage. The first transistor is configured to connect or disconnect the first and second power nodes in response to a control signal to provide or disconnect power to the functional circuitry.

[0177] In the aforementioned integrated circuit device, the predetermined voltage is one of the following: a control signal, a first power supply voltage of a first power node, a second power supply voltage of a second power node, a third power supply voltage different from the first power supply voltage, a functional circuit capable of operating via the first power supply voltage and the third power supply voltage, or a voltage other than the control signal and the first to third power supply voltages.

[0178] In the aforementioned integrated circuit device, the power control circuit is the head circuit, the first transistor is a P-type transistor, and the second transistor is an N-type transistor.

[0179] In the aforementioned integrated circuit device, the power control circuit is the tail circuit, the first transistor is an N-type transistor, and the second transistor is a P-type transistor.

[0180] In the aforementioned integrated circuit device, in response to the first transistor being in the off state, the first power node is disconnected from the second power node and floated.

[0181] In some embodiments, an integrated circuit (IC) device includes a first active region of a first semiconductor type, a second active region of a second semiconductor type different from the first semiconductor type, a plurality of gate regions extending across and above the first and second active regions, a plurality of contact structures located above and electrically contacting corresponding portions of the first and second active regions, and a conductive layer located above the plurality of gate regions and the plurality of contact structures. The conductive layer includes a first conductive pattern electrically coupling a first set of contact structures above the first active region together, a second conductive pattern electrically coupling a second set of contact structures above the first active region together, a third conductive pattern electrically coupling the plurality of gate regions together, and a fourth conductive pattern electrically coupling the contact structures above the second active region together.

[0182] In the aforementioned integrated circuit device, a plurality of gate regions and a first active region are configured as a first transistor of a first type, and a plurality of gate regions and a second active region are configured as a second transistor of a second type different from the first type.

[0183] In the aforementioned integrated circuit device, a first conductive pattern is configured as a first power rail of a functional circuit, which can be operated by a first power supply voltage on the first power rail. A second conductive pattern is configured as a second power rail, and a first transistor is configured to connect or disconnect the first and second power rails in response to a control signal on a third conductive pattern.

[0184] In the aforementioned integrated circuit device, the conductive layer further includes a fifth conductive pattern that electrically couples the first set of contact structures together.

[0185] In the aforementioned integrated circuit device, the contact structures in the first group and the contact structures in the second group are arranged alternately along the first axis, and the second conductive pattern is arranged between the first conductive pattern and the fifth conductive pattern along a second axis perpendicular to the first axis.

[0186] In the aforementioned integrated circuit device, the conductive layer further includes a sixth conductive pattern that electrically couples the second set of contact structures together.

[0187] In the aforementioned integrated circuit device, the contact structures in the first group and the contact structures in the second group are arranged alternately along the first axis, and the second to sixth conductive patterns are arranged alternately with the first conductive pattern and the fifth conductive pattern along the second axis perpendicular to the first axis.

[0188] In the aforementioned integrated circuit device, the second set of contact structures extends continuously from the first active region to the second active region, thereby forming a corresponding set of contact structures above the second active region.

[0189] In the aforementioned integrated circuit device, the first set of contact structures extends continuously from the first active region to the second active region, so as to form a corresponding set of contact structures above the second active region.

[0190] In the aforementioned integrated circuit device, the third conductive pattern and the fourth conductive pattern are electrically coupled together.

[0191] In the aforementioned integrated circuit device, the fourth conductive pattern is configured to receive a predetermined voltage or is configured as a third power rail, and the predetermined voltage is a voltage other than all of the following: a control signal, a first power supply voltage of the first power rail, a second power supply voltage of the second power rail, and a third power supply voltage of the third power rail, wherein the third power supply voltage is different from the first power supply voltage, and the functional circuit can operate by means of the first power supply voltage and the third power supply voltage.

[0192] The aforementioned integrated circuit device further includes: a third active region of a first semiconductor type; a fourth active region of a second semiconductor type, wherein the first active region to the fourth active region extends along a first axis, and the second active region and the fourth active region are arranged between the first active region and the third active region along a second axis perpendicular to the first axis; a plurality of additional gate regions, spanning the third active region and the fourth active region and extending above the third active region and the fourth active region, the plurality of additional gate regions being correspondingly aligned with the plurality of gate regions; and a plurality of additional contact structures located above corresponding portions of the third active region and the fourth active region and electrically contacting the corresponding portions of the third active region and the fourth active region, wherein the conductive layer further includes: a fifth conductive pattern electrically coupling the third set of additional contact structures above the third active region together; a sixth conductive pattern electrically coupling the fourth set of additional contact structures above the third active region together; a seventh conductive pattern electrically coupling the plurality of additional gate regions together; and the fourth conductive pattern also electrically coupling the additional contact structures above the fourth active region together.

[0193] In the aforementioned integrated circuit device, the conductive layer is the M0 layer.

[0194] In some embodiments, a method includes forming a first active region of a first semiconductor type and a second active region of a second semiconductor type different from the first semiconductor type over a substrate. The first and second active regions extend along a first axis. The method further includes forming a gate structure over the first and second active regions. The gate structure extends continuously from the first active region to the second active region along a second axis perpendicular to the first axis. The gate structure and the first active region are configured as a first transistor of a first type. The gate structure and the second active region are configured as a second transistor of a second type different from the first type. The method further includes depositing a conductive layer over the gate structure and the first and second active regions, and patterning the conductive layer into a plurality of conductive patterns extending along the first axis. The plurality of conductive patterns includes a first conductive pattern electrically coupled to a first terminal of the first transistor, a second conductive pattern electrically coupled to a second terminal of the first transistor, a third conductive pattern electrically coupled to the first terminal of the first transistor, and a fourth conductive pattern electrically coupled to the first and second terminals of the second transistor to form the second transistor as a dummy transistor.

[0195] In the above method, the plurality of conductive patterns further includes: a fifth conductive pattern electrically coupled to the gate structure, and the fifth conductive pattern is located above the second active region or above the gap between the first active region and the second active region.

[0196] The foregoing has described components of several embodiments, enabling those skilled in the art to better understand the various embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be readily designed or modified based on the present invention to achieve the same objectives and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the present invention.

Claims

1. An integrated circuit device, comprising: The functional circuit is electrically coupled to the first power node and is operable by the first power supply voltage on the first power node. as well as The power control circuit includes a first transistor of a first type and a second transistor of a second type different from the first type. in, The first transistor includes: The gate terminal is configured to receive control signals. The first terminal is electrically coupled to the first power node, and The second terminal is electrically coupled to the second power supply node. The second transistor includes: The gate terminal is configured to receive the control signal, and The first and second terminals are configured to receive a predetermined voltage, and The first transistor is configured to connect or disconnect the first power node and the second power node in response to the control signal to provide or disconnect power to the functional circuit.

2. The integrated circuit device according to claim 1, wherein, The predetermined voltage is one of the following: The control signal The first power supply voltage of the first power node. The second power supply voltage of the second power node The functional circuit can operate using both the first power supply voltage and the third power supply voltage, which is different from the first power supply voltage. Voltages other than the control signal and the first power supply voltage to the third power supply voltage.

3. The integrated circuit device according to claim 1, wherein, The power control circuit is a head circuit. The first transistor is a P-type transistor, and The second transistor is an N-type transistor.

4. The integrated circuit device according to claim 1, wherein, The power control circuit is a tail circuit. The first transistor is an N-type transistor, and The second transistor is a P-type transistor.

5. The integrated circuit device according to claim 1, wherein, In response to the first transistor being in the off state, the first power node is disconnected from the second power node and floated.

6. An integrated circuit device, comprising: The first active region of the first semiconductor type; A second active region of a second semiconductor type, wherein the second semiconductor type is different from the first semiconductor type; Multiple gate regions, spanning the first active region and the second active region and extending over the first active region and the second active region; Multiple contact structures are located above corresponding portions of the first active region and the second active region and are in electrical contact with corresponding portions of the first active region and the second active region; as well as A conductive layer is located above the plurality of gate regions and the plurality of contact structures, the conductive layer comprising: The first conductive pattern electrically couples together the first set of contact structures above the first active region. The second conductive pattern electrically couples the second set of contact structures above the first active region together. The third conductive pattern electrically couples the plurality of gate regions together, and The fourth conductive pattern electrically couples the contact structures above the second active region together.

7. The integrated circuit device according to claim 6, wherein, The plurality of gate regions and the first active region are configured as a first transistor of a first type, and The plurality of gate regions and the second active region are configured as a second type of transistor, different from the first type.

8. The integrated circuit device according to claim 7, wherein, The first conductive pattern is configured as a first power rail for a functional circuit, which is operable by a first power supply voltage on the first power rail. The second conductive pattern is configured as a second power rail, and The first transistor is configured to connect or disconnect the first power rail and the second power rail in response to a control signal on the third conductive pattern.

9. The integrated circuit device according to claim 8, wherein, The conductive layer further includes: The fifth conductive pattern electrically couples the first set of contact structures together.

10. The integrated circuit device according to claim 9, wherein, The contact structures in the first group of contact structures and the contact structures in the second group of contact structures are arranged alternately along the first axis, and The second conductive pattern is arranged between the first conductive pattern and the fifth conductive pattern along a second axis perpendicular to the first axis.

11. The integrated circuit device according to claim 10, wherein, The conductive layer further includes: The sixth conductive pattern electrically couples the second set of contact structures together.

12. The integrated circuit device according to claim 11, wherein, The contact structures in the first group of contact structures and the contact structures in the second group of contact structures are arranged alternately along the first axis, and The second to the sixth conductive patterns are arranged alternately with the first conductive pattern and the fifth conductive pattern along a second axis perpendicular to the first axis.

13. The integrated circuit device according to claim 11, wherein, The contact structure of the second set of contact structures extends continuously from the first active region to the second active region, so as to form a corresponding set of contact structures above the second active region.

14. The integrated circuit device according to claim 9, wherein, The contact structure of the first set of contact structures extends continuously from the first active region to the second active region, so as to form a corresponding set of contact structures above the second active region.

15. The integrated circuit device according to claim 9, wherein, The third conductive pattern and the fourth conductive pattern are electrically coupled together.

16. The integrated circuit device according to claim 9, wherein, The fourth conductive pattern is configured to receive a predetermined voltage or to be configured as a third power rail, and The predetermined voltage is any voltage other than all of the following: The control signal The first power supply voltage of the first power rail. The second power supply voltage of the second power rail, and The third power supply voltage of the third power rail is different from the first power supply voltage, and the functional circuit can operate using both the first power supply voltage and the third power supply voltage.

17. The integrated circuit device according to claim 6, further comprising: The third active region of the first semiconductor type; The fourth active region of the second semiconductor type, wherein, The first active region to the fourth active region extend along the first axis, and The second active region and the fourth active region are arranged between the first active region and the third active region along a second axis perpendicular to the first axis; A plurality of additional gate regions, extending across and above the third and fourth active regions, are correspondingly aligned with the plurality of gate regions; and Multiple additional contact structures are located above corresponding portions of the third active region and the fourth active region and are in electrical contact with corresponding portions of the third active region and the fourth active region. in, The conductive layer further includes: The fifth conductive pattern electrically couples together the third set of additional contact structures above the third active region. The sixth conductive pattern electrically couples together the fourth set of additional contact structures above the third active region. The seventh conductive pattern electrically couples the plurality of additional gate regions together, and The fourth conductive pattern also electrically couples together the additional contact structures above the fourth active region.

18. The integrated circuit device according to claim 6, wherein, The conductive layer is the M-zero layer.

19. A method for forming an integrated circuit device, comprising: A first active region of a first semiconductor type and a second active region of a second semiconductor type different from the first semiconductor type are formed above a substrate, the first active region and the second active region extending along a first axis; A gate structure is formed above the first active region and the second active region, the gate structure extending continuously from the first active region to the second active region along a second axis perpendicular to the first axis, wherein... The gate structure and the first active region are configured as a first transistor of a first type, and The gate structure and the second active region are configured as a second type of transistor, different from the first type; and A conductive layer is deposited over the gate structure and the first active region and the second active region, and the conductive layer is patterned into a plurality of conductive patterns extending along the first axis, the plurality of conductive patterns including: A first conductive pattern is electrically coupled to a first terminal of the first transistor; The second conductive pattern is electrically coupled to the second terminal of the first transistor; A third conductive pattern is electrically coupled to the first terminal of the first transistor; and A fourth conductive pattern is electrically coupled to the first and second terminals of the second transistor to form the second transistor as a pseudo transistor.

20. The method of claim 19, wherein The plurality of conductive patterns also include: The fifth conductive pattern is electrically coupled to the gate structure, and The fifth conductive pattern: Located above the second active region, or It is located above the gap between the first active region and the second active region.

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