LTPO backplane structure and manufacturing method

Abstract

The application discloses a kind of LTPO backboard structure and manufacturing method, including Poly semiconductor layer, GI layer and metal layer M1 gate are equipped on the Poly semiconductor layer, GI layer and metal layer M1 gate are equipped with insulating layer PV1 outside, metal layer M2 is equipped on the insulating layer PV1, metal layer M2 is equipped with insulating layer PV2 outside, metal layer M3 is equipped on the insulating layer PV2, insulating layer PV3 layer is equipped on the metal layer M3, IGZO semiconductor layer is formed by coating film on the insulating layer PV3 layer, GI layer and metal layer M4 gate are equipped on the IGZO semiconductor layer, insulating layer PV4 is equipped on the metal layer M4 gate and IGZO semiconductor layer, metal layer M5 is equipped on the insulating layer PV4, the application belongs to backboard technical field, specifically refers to a kind of LTPO backboard structure and manufacturing method, low power consumption stability is good.

Description

Technical Field

[0001] This invention belongs to the field of backplane technology, specifically referring to an LTPO backplane structure and manufacturing method. Background Technology

[0002] Currently, the back panels of small and medium-sized OLED panels on the market mainly use two technologies: LTPS (Low Temperature Polycrystalline Silicon) and IGZO (Indium Gallium Zinc Oxide).

[0003] OLED panels using LTPS backplane structures have higher electron mobility and aperture ratio, enabling higher resolution. Although LTPS structures have a larger on-state current, they also have a large leakage current, requiring continuous charging to maintain the capacitor potential, resulting in higher power consumption and inability to drive at low frequencies.

[0004] OLED panels using IGZO backplane structures are similar to those using amorphous silicon substrates, and their production costs are lower than those using LTPS backplane structures. However, IGZO has a lower mobility than LTPS, resulting in larger TFT sizes and lower resolution. Furthermore, IGZO is unstable and easily oxidized in air, leading to a shorter panel lifespan. Summary of the Invention

[0005] To address the aforementioned challenges, this invention provides an LTPO backplane structure that divides the backplane into two layers: the bottom layer consists of a top-gate structure driving TFT using LTPS as the semiconductor; the top layer consists of a top-gate structure switching TFT using IGZO as the semiconductor. This structure combines the advantages of high electron mobility of LTPS and low leakage current of IGZO, resulting in lower power consumption, better stability, and the ability to achieve low-frequency refresh rate display.

[0006] To achieve the above-mentioned functional modules, the technical solution adopted by the present invention is as follows: An LTPO backplane structure includes a Poly semiconductor layer. A Poly semiconductor layer is formed on a substrate using an ELA (excimer laser annealing) process. A GI layer and a metal gate layer M1 are disposed on the Poly semiconductor layer. The GI layer separates the metal gate layer M1 from the Poly semiconductor layer. An insulating layer PV1 is disposed outside the GI layer and the metal gate layer M1. A metal layer M2 is disposed on the insulating layer PV1. The metal layer M2 is connected to the metal gate layer M1. An insulating layer PV2 is disposed outside the metal layer M2. A metal layer M3 is disposed on the insulating layer PV2. The metal layer M3 (OVDD signal) and the metal layer M2 form a storage capacitor Cst for the pixel driving circuit through the insulating layer PV2. An insulating layer PV3 is disposed on the metal layer M3. An IGZO semiconductor layer is deposited on the insulating layer PV3. The IGZO semiconductor layer has a GI layer and a metal layer M4 gate. The GI layer separates the metal layer M4 gate from the IGZO semiconductor layer. The Scan signal is sent through the metal layer M4. An insulating layer PV4 is provided on the metal layer M4 gate and the IGZO semiconductor layer. A metal layer M5 is provided on the insulating layer PV4. The metal layer M5 is connected to the metal layer M2. The metal layer M5 serves as the Source and Drain electrode of the switching TFT and is connected to the metal layer M2. It sends the DATA signal to the metal layer M1 gate of the driving TFT and stores it in the capacitor Cst. An organic planarization layer OC is provided on the metal layer M5. An anode metal layer Anode is provided on the organic planarization layer OC. The anode metal layer Anode is connected to the metal layer M3 and receives the OVDD current signal. A pixel definition layer PDL is provided on the organic planarization layer OC. An opening is provided on the anode metal layer Anode.

[0007] The insulating layer PV1 has a VIA1 hole, and the metal layer M2 is connected to the gate of the metal layer M1 through the VIA1 hole.

[0008] Furthermore, the insulating layer PV2 is provided with a VIA2 hole, and the metal layer M3 is connected to the drain and source electrodes of the driving TFT through the VIA2 hole.

[0009] Preferably, the insulating layer PV4 is provided with a VIA4 hole, and the metal layer M5 is connected to the metal layer M2 through the VIA4 hole.

[0010] The organic flat layer OC has OC holes, and the anode metal layer Anode is connected to the metal layer M3 through the OC holes.

[0011] This invention also includes a method for manufacturing an LTPO backsheet structure, comprising the following steps:

[0012] (1) An amorphous silicon (a-si) film is deposited on a glass substrate. A POLY (LTPS) semiconductor layer is formed in the middle part by ELA (excimer laser annealing) process. P+ ions are then implanted into the left and right ends of the POLY by ion implantation process to form source electrode and drain electrode respectively.

[0013] (2) A GI layer and a metal layer M1 (gate) are deposited on the semiconductor layer Poly, respectively. The GI layer separates the metal layer M1 gate and the semiconductor layer.

[0014] (3) The insulating layer PV1 covers the metal layer M1, the GI film layer, the SOURCE electrode, and the DRAIN electrode;

[0015] (4) Drill a VIA1 hole in the insulation layer PV1;

[0016] (5) A metal layer M2 is deposited on the insulating layer PV1 and connected to the gate of the metal layer M1 through the VIA1 hole;

[0017] (6) Apply an insulating layer PV2 to cover the metal layer M2;

[0018] (7) Drill a VIA2 hole in the insulation layer PV2;

[0019] (8) A metal layer M3 is deposited on the insulating layer PV2. The metal layer M3 (OVDD signal) is connected to the drain and source terminals of the driving TFT through the VIA2 hole, and forms the storage capacitor Cst of the pixel driving circuit with the metal layer M2 through the insulating layer PV2.

[0020] (9) The insulating layer PV3 covers the metal layer M3. An IGZO semiconductor layer is formed by coating the PV3 layer. A GI layer and a metal layer M4 gate are deposited on the IGZO semiconductor layer. The GI layer separates the metal layer M4 gate from the IGZO semiconductor layer. The Scan signal is sent through the metal layer M4.

[0021] (10) The insulating layer PV4 covers the metal layer M4 gate and the IGZO semiconductor layer;

[0022] (11) Drill a VIA4 hole in the PV4 insulation layer;

[0023] (12) A metal layer M5 is deposited on the insulating layer PV4. The metal layer M5 is connected to the source and drain electrodes of the switching TFT and the metal layer M2. The DATA signal is sent to the gate of the metal layer M1 of the driving TFT and stored in the capacitor Cst.

[0024] (13) Organic smoothing layer OC covers metal layer M5;

[0025] (14) Drill OC holes on the organic flat OC layer;

[0026] (15) An anode metal layer is deposited on the organic planar layer OC and connected to the metal layer M3 to receive the OVDD current signal;

[0027] (16) A pixel definition layer (PDL) is deposited on the organic planarization layer (OC) and an opening is made at the anode of the anodic metal layer.

[0028] The beneficial effects of the above-mentioned structure of this invention are as follows: The LTPO backplane structure and manufacturing method provided by this invention are simple to operate, compact in structure, and rationally designed. Compared with the traditional LTPS backplane, it reduces the leakage current of the switching TFT, keeps the opening size of the driving TFT constant during the display time, and reduces the power consumption of the panel. Compared with the traditional IGZO backplane, the size of the driving TFT is reduced and the TFT is distributed in layers, which reduces the area of ​​the driving circuit of a single pixel, increases the PPI, improves the resolution, and makes the picture display clearer. It combines the advantages of both LTPS and IGZO backplane structures, improves the stability of the panel, increases the panel aperture ratio, and realizes low-frequency refresh display of the panel. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the LTPO backsheet structure provided by the present invention;

[0030] Figure 2 This is a schematic diagram of the PEP sequence of the backplane photomask for the LTPO backplane structure provided by the present invention. Detailed Implementation

[0031] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0032] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The invention will be further described in detail below with reference to the accompanying drawings.

[0033] like Figure 1-2As shown, the LTPO backplane structure provided by this invention includes a Poly semiconductor layer. A Poly semiconductor layer is formed on a substrate using an ELA (excimer laser annealing) process. A GI layer and a metal gate layer M1 are disposed on the Poly semiconductor layer. The GI layer separates the metal gate layer M1 from the Poly semiconductor layer. An insulating layer PV1 is disposed outside the GI layer and the metal gate layer M1. A metal layer M2 is disposed on the insulating layer PV1 and connected to the metal gate layer M1. An insulating layer PV2 is disposed outside the metal layer M2. A metal layer M3 is disposed on the insulating layer PV2. The metal layer M3 (OVDD signal) is connected to the drain and source terminals of the driving TFT. The metal layer M3 (OVDD signal) and the metal layer M2 form the storage capacitor Cst of the pixel driving circuit through the insulating layer PV2. An insulating layer PV3 is disposed on the metal layer M3, and an IG layer is formed by deposition on the insulating layer PV3. The ZO semiconductor layer has a GI layer and a metal layer M4 gate. The GI layer separates the metal layer M4 gate from the IGZO semiconductor layer. The Scan signal is sent through the metal layer M4. An insulating layer PV4 is provided on the metal layer M4 gate and the IGZO semiconductor layer. A metal layer M5 is provided on the insulating layer PV4. The metal layer M5 is connected to the metal layer M2. The metal layer M5 serves as the Source and Drain electrode of the switching TFT and is connected to the metal layer M2. It sends the DATA signal to the metal layer M1 gate of the driving TFT and stores it in the capacitor Cst. An organic planarization layer OC is provided on the metal layer M5. An anode metal layer Anode is provided on the organic planarization layer OC. The anode metal layer Anode is connected to the metal layer M3 and receives the OVDD current signal. A pixel definition layer PDL is provided on the organic planarization layer OC. An opening is provided on the anode metal layer Anode.

[0034] The insulating layer PV1 has a VIA1 hole, and the metal layer M2 is connected to the gate of the metal layer M1 through the VIA1 hole; the insulating layer PV2 has a VIA2 hole, and the metal layer M3 is connected to the drain and source electrodes of the driving TFT through the VIA2 hole; the insulating layer PV4 has a VIA4 hole, and the metal layer M5 is connected to the metal layer M2 through the VIA4 hole; the organic planarization layer OC has an OC hole, and the anode metal layer is connected to the metal layer M3 through the OC hole.

[0035] This invention also includes a method for manufacturing an LTPO backsheet structure, comprising the following steps:

[0036] (1) An amorphous silicon (a-si) film is deposited on a glass substrate. A POLY (LTPS) semiconductor layer is formed in the middle part by ELA (excimer laser annealing) process. P+ ions are then implanted into the left and right ends of the POLY by ion implantation process to form source electrode and drain electrode respectively.

[0037] (2) A GI layer and a metal layer M1 (gate) are deposited on the semiconductor layer Poly, respectively. The GI layer separates the metal layer M1 gate and the semiconductor layer.

[0038] (3) The insulating layer PV1 covers the metal layer M1, the GI film layer, the SOURCE electrode, and the DRAIN electrode;

[0039] (4) Drill a VIA1 hole in the insulation layer PV1;

[0040] (5) A metal layer M2 is deposited on the insulating layer PV1 and connected to the gate of the metal layer M1 through the VIA1 hole;

[0041] (6) Apply an insulating layer PV2 to cover the metal layer M2;

[0042] (7) Drill a VIA2 hole in the insulation layer PV2;

[0043] (8) A metal layer M3 is deposited on the insulating layer PV2. The metal layer M3 (OVDD signal) is connected to the drain and source terminals of the driving TFT through the VIA2 hole, and forms the storage capacitor Cst of the pixel driving circuit with the metal layer M2 through the insulating layer PV2.

[0044] (9) The insulating layer PV3 covers the metal layer M3. An IGZO semiconductor layer is formed by coating the PV3 layer. A GI layer and a metal layer M4 gate are deposited on the IGZO semiconductor layer. The GI layer separates the metal layer M4 gate from the IGZO semiconductor layer. The Scan signal is sent through the metal layer M4.

[0045] (10) The insulating layer PV4 covers the metal layer M4 gate and the IGZO semiconductor layer;

[0046] (11) Drill a VIA4 hole in the PV4 insulation layer;

[0047] (12) A metal layer M5 is deposited on the insulating layer PV4. The metal layer M5 is connected to the source and drain electrodes of the switching TFT and the metal layer M2. The DATA signal is sent to the gate of the metal layer M1 of the driving TFT and stored in the capacitor Cst.

[0048] (13) Organic smoothing layer OC covers metal layer M5;

[0049] (14) Drill OC holes on the organic flat OC layer;

[0050] (15) An anode metal layer is deposited on the organic planar layer OC and connected to the metal layer M3 to receive the OVDD current signal;

[0051] (16) A pixel definition layer (PDL) is deposited on the organic planarization layer (OC) and an opening is made at the anode of the anodic metal layer.

[0052] The present invention and its embodiments have been described above. This description is not restrictive, and the accompanying drawings are only one embodiment of the present invention; the actual structure is not limited thereto. In conclusion, if those skilled in the art are inspired by this description and design similar structures and embodiments without departing from the spirit of the invention, such designs should fall within the protection scope of the present invention.

Claims

1. An LTPO backplane structure, characterized by: The Poly semiconductor layer is formed by the ELA process, a GI layer and a metal layer M1 gate electrode are arranged on the Poly semiconductor layer, the GI layer separates the metal layer M1 gate electrode and the Poly semiconductor layer, an insulating layer PV1 is arranged outside the GI layer and the metal layer M1 gate electrode, a metal layer M2 is arranged on the insulating layer PV1, the metal layer M2 is connected with the metal layer M1 gate electrode, an insulating layer PV2 is arranged outside the metal layer M2, a metal layer M3 is arranged on the insulating layer PV2, the metal layer M3 and the metal layer M2 form a storage capacitor Cst of a pixel driving circuit through the insulating layer PV2, an insulating layer PV3 is arranged on the metal layer M3, an IGZO semiconductor layer is formed by plating on the insulating layer PV3, a GI layer and a metal layer M4 gate electrode are arranged on the IGZO semiconductor layer, the GI layer separates the metal layer M4 gate electrode and the IGZO semiconductor layer, an insulating layer PV4 is arranged on the metal layer M4 gate electrode and the IGZO semiconductor layer, a metal layer M5 is arranged on the insulating layer PV4, the metal layer M5 is used as a Source electrode and a Drain electrode of a switching TFT, the metal layer M5 is connected with the metal layer M2, an organic planarization layer OC is arranged on the metal layer M5, an anode metal layer Anode is arranged on the organic planarization layer OC, the anode metal layer Anode is connected with the metal layer M3, a pixel definition layer PDL is arranged on the organic planarization layer OC, an opening is arranged on the anode metal layer Anode, a VIA2 hole is arranged on the insulating layer PV2, and the metal layer M3 is connected with the Drain electrode and the Source electrode of the driving TFT through the VIA2 hole.

2. The LTPO backplane structure of claim 1, wherein: A VIA1 hole is arranged on the insulating layer PV1, and the metal layer M2 is connected with the metal layer M1 gate electrode through the VIA1 hole.

3. The LTPO backplane structure of claim 2, wherein: A VIA4 hole is arranged on the insulating layer PV4, and the metal layer M5 is connected with the metal layer M2 through the VIA4 hole.

4. The LTPO backplane structure of claim 3, wherein: An OC hole is arranged on the organic planarization layer OC, and the anode metal layer Anode is connected with the metal layer M3 through the OC hole.

5. A method of fabricating the LTPO backplane structure of claim 4, wherein: The method comprises the following steps: (1) an amorphous silicon a-si film layer is plated on a glass substrate, a POLY semiconductor layer is formed at the middle part through an ELA process, and P+ ions are injected into the POLY left and right ends through an ion implantation process to form a Source electrode and a Drain electrode, respectively; (2) a GI layer and a metal layer M1 gate electrode are plated on the semiconductor layer Poly, and the GI layer separates the metal layer M1 gate electrode and the semiconductor layer; (3) an insulating layer PV1 covers the metal layer M1 gate electrode, the GI layer, the Source electrode and the Drain electrode; (4) the insulating layer PV1 is punched with a VIA1 hole; (5) a metal layer M2 is plated on the insulating layer PV1 and connected with the metal layer M1 gate electrode through the VIA1 hole; (6) an insulating layer PV2 is plated to cover the metal layer M2; (7) a VIA2 hole is punched on the insulating layer PV2; (8) Metal layer M3 is plated on insulating layer PV2, metal layer M3 is connected with Drain and Source of driving TFT through VIA2 hole, metal layer M3 and metal layer M2 form storage capacitor Cst of pixel driving circuit through insulating layer PV2; (9) Insulating layer PV3 covers metal layer M3, IGZO semiconductor layer is plated on insulating layer PV3, GI layer and metal layer M4 gate are plated on IGZO semiconductor layer respectively, GI layer separates metal layer M4 gate and IGZO semiconductor layer, and scan signal Scan is sent in through metal layer M4; (10) Insulating layer PV4 covers metal layer M4 gate and IGZO semiconductor layer; (11) Insulating layer PV4 is punched VIA4 hole; (12) Metal layer M5 is plated on insulating layer PV4, metal layer M5 is Source and Drain of switch TFT, metal layer M5 is connected with metal layer M2, and DATA signal is sent to metal layer M1 gate of driving TFT and stored in capacitor Cst; (13) Organic flat layer OC covers metal layer M5; (14) OC hole is punched on organic flat layer OC; (15) Anode metal layer Anode is plated on organic flat layer OC, anode metal layer Anode is connected with metal layer M3, and OVDD current signal is received; (16) Pixel definition layer PDL is plated on organic flat layer OC, and anode metal layer Anode is opened.

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