Array substrate and mobile terminal
By setting shielded traces to surround the ends of metal traces on the array substrate, the ESD problem caused by charge accumulation during the manufacturing process of long metal traces is solved, short circuits are prevented, and the reliability of the array substrate is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-04-08
- Publication Date
- 2026-04-03
AI Technical Summary
In the manufacturing process of thin-film transistors, the ends of long metal traces are prone to charge accumulation, leading to electrostatic discharge (ESD) phenomena, which can break down the insulating layer and cause short circuits between unconnected lines.
A shielding trace is placed between the first metal trace and the functional electrode to form a semi-enclosed structure. The shielding trace surrounds the end of the metal trace to prevent charge accumulation and avoid ESD.
It effectively prevents ESD phenomena, avoids insulation layer breakdown, prevents short circuits between unconnected lines, and improves the reliability of the array substrate.
Smart Images
Figure CN114823723B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of display technology, specifically to an array substrate and a mobile terminal. Background Technology
[0002] In the fabrication process of thin-film transistors, some metal traces have a relatively long length. Static electricity is generated in each subsequent process. The static electricity is attracted to the ends or contour edges of the metal traces. Because of their different positions, the state of charge accumulation on two unconnected long traces is also different. Therefore, after the charge accumulates to a certain level, electrostatic discharge (ESD) is likely to occur. The released charge will break down the insulating layer, causing a short circuit between the originally unconnected lines. Summary of the Invention
[0003] This application provides an array substrate and a mobile terminal, which can effectively prevent the accumulation of charge between long traces with opposite ends during the manufacturing process. When the charge accumulates too much, ESD occurs, causing the released charge to break down the insulating layer and cause a short circuit between lines that were not originally connected.
[0004] This application provides an array substrate, including...
[0005] A substrate, wherein a driving circuit is disposed on the substrate near its edge;
[0006] A first metal layer is disposed on the substrate and includes a gate, a first metal trace connected to the gate, and a functional electrode. The end of the first metal trace away from the gate includes a connection portion, and the connection portion and the functional electrode are disposed at a distance.
[0007] An insulating layer is disposed on the substrate and the first metal layer and covers the first metal layer, the insulating layer including a plurality of transition holes located above the connection portion;
[0008] A second metal layer is disposed on the insulating layer. The second metal layer includes a source and drain corresponding to the gate and a second metal trace. One end of the second metal trace is connected to the driving circuit, and the other end of the second metal trace is connected to the first metal trace through the adapter hole.
[0009] The first metal layer further includes shielding traces located between the connection portion and the functional electrode.
[0010] Optionally, the shielding trace includes a first shielding segment extending along a first direction and two second shielding segments respectively connecting the two ends of the first shielding segment and extending along a second direction. The first direction and the second direction have a preset angle. The first shielding segment and the two second shielding segments form a semi-enclosed structure, and the semi-enclosed structure surrounds the end of the first metal trace near the functional electrode.
[0011] Optionally, one end of the second metal trace extends along the first direction, bypasses the second shielding section, and connects to the first metal trace through the adapter hole.
[0012] Optionally, the first metal trace includes at least two first branch traces, the second metal trace includes at least two second branch traces, the two first branch traces are connected to different gates, the connection portion includes at least two connection sub-ports, each first branch trace has a connection sub-port at its end, the end of the first branch trace with the connection sub-port is close to the end of the functional electrode, the insulating layer has a plurality of adapter holes corresponding to the connection sub-region, and the second branch trace is connected to the first branch trace through the adapter holes;
[0013] The shielded trace includes at least two shielded sub-traces, one of which is configured corresponding to one of the first branch traces. Each shielded sub-traces includes a first shielded segment extending along the first direction and a second shielded segment connecting the two ends of the first shielded segment and extending along the second direction. The first shielded segment and the two second shielded segments form a semi-enclosed structure that surrounds the end of the first branch trace near the second metal trace.
[0014] Optionally, the connection between the first shielding segment and the second shielding segment is rounded.
[0015] Optionally, the distance between the shielding trace and the first metal trace is equal to the distance between the shielding trace and the functional electrode.
[0016] Optionally, the width of the shielding trace is greater than or equal to 5µm.
[0017] Optionally, the shielding trace includes a first shielding trace group and a second shielding trace group. The first shielding trace group includes a plurality of first shielding trace sub-sections, and the second shielding trace group includes a plurality of second shielding trace sub-sections. The first shielding trace group and the second shielding trace group are arranged in parallel, and the first shielding trace sub-sections and the second shielding trace sub-sections are arranged alternately.
[0018] Optionally, the shielding traces include one of straight lines, irregular curves, and wavy lines.
[0019] In addition, this application also provides a mobile terminal, including the array substrate and terminal body described in any of the above embodiments, wherein the terminal body and the array substrate are integrated into one unit.
[0020] The beneficial effects of this invention include at least the following:
[0021] This application provides a shielded trace between the ends of the first metal trace and the functional electrode, creating a shielded gap between the end of the functional electrode near the first metal trace and the end of the first metal trace with the connecting portion. This avoids ESD caused by the accumulation of charge at the ends or contour edges of long traces during the manufacturing process, which could break down the insulating layer. This effectively prevents electrostatic short circuits between the functional electrode and the second metal trace caused by ESD. Attached Figure Description
[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0023] Figure 1 This is a schematic diagram of the structure of an array substrate in the prior art;
[0024] Figure 2 This is a schematic diagram of the structure of an array substrate provided in an embodiment of this application;
[0025] Figure 3 This is a schematic diagram of another array substrate structure provided in an embodiment of this application;
[0026] Figure 4 yes Figure 3 Cross-sectional view of line A-A';
[0027] Figure 5 This is a schematic diagram of another array substrate structure provided in an embodiment of this application;
[0028] Figure 6 This is a schematic diagram of another array substrate provided in an embodiment of this application. Detailed Implementation
[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0030] This application provides an array substrate and a mobile terminal. Detailed descriptions are provided below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments. Furthermore, in the description of this application, the term "comprising" means "including but not limited to". The terms first, second, third, etc., are used merely as illustrative and do not impose numerical requirements or establish an order. Various embodiments of the present invention may exist in the form of a range; it should be understood that the description in the form of a range is merely for convenience and brevity and should not be construed as a rigid limitation on the scope of the invention; therefore, it should be considered that the range description has specifically disclosed all possible sub-ranges and single numerical values within that range. For example, it should be considered that the range description from 1 to 6 has specifically disclosed sub-ranges, such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6, etc., and single digits within the range, such as 1, 2, 3, 4, 5, and 6, regardless of the range. Additionally, whenever a numerical range is indicated herein, it means including any referenced number (fraction or integer) within the indicated range.
[0031] To address the aforementioned technical problems, this application provides the following technical solutions, as detailed in the following embodiments.
[0032] This application provides an array substrate, such as... Figure 2 and Figure 4 As shown, it includes:
[0033] A substrate, wherein a driving circuit 70 is disposed on the substrate near its edge;
[0034] A first metal layer M1 is disposed on the substrate and includes a gate, a first metal trace 20 connected to the gate, and a functional electrode 10. The end of the first metal trace 20 away from the gate includes a connection portion, and the connection portion and the functional electrode 10 are disposed at intervals.
[0035] An insulating layer PV is disposed on the substrate and the first metal layer M1 and covers the first metal layer M1. The insulating layer PV includes a plurality of transition holes 401 located above the connection portion.
[0036] The second metal layer M2 is disposed on the insulating layer PV. The second metal layer M2 includes a source / drain electrode 50 corresponding to the gate and a second metal trace 30. One end of the second metal trace 30 is connected to the driving circuit 70, and the other end of the second metal trace 30 is connected to the first metal trace 20 through the adapter hole 401.
[0037] The first metal layer M1 also includes a shielding trace 60 located between the connection portion and the functional electrode 10.
[0038] It should be noted that currently, array substrate structures such as Figure 1 As shown, the array substrate has a structure in which the ends of long traces are arranged opposite each other. An adapter hole 401 is provided on the insulating layer PV above the connection portion of the first metal trace 20 in the array substrate. The end of the first metal trace 20 away from the connection portion is connected to the gate. The second metal trace 30 is connected to the first metal trace 20 through the adapter hole 401. During the manufacturing process, charge accumulation easily occurs at the ends of the long traces (the connection portion of the first metal trace 20) and at the outer contour (the outer contour of the functional electrode 10). Excessive charge accumulation can easily break down the insulating layer PV. The areas prone to breakdown are as follows: Figure 1 As shown in region A1, this causes a short circuit between the functional electrode 10 and the second metal trace 30.
[0039] Specifically, the substrate material may include glass or a highly polymeric material.
[0040] It should be noted that the array substrate may include multiple thin-film transistor devices, and the gate of each thin-film transistor device can be led out through the first metal trace 20 and the second metal trace 30 and connected to the driving circuit 70, which is located on the array substrate near the edge.
[0041] Specifically, one end of the first metal trace 20 is connected to the gate. The first metal trace 20 may also include multiple first branch traces 201, and one first branch trace 201 may be connected to the gate of a thin-film transistor device.
[0042] Specifically, the material of the first metal trace 20 may include one of copper, silver, aluminum, aluminum alloy, nickel, titanium alloy, etc.
[0043] Specifically, the material of the second metal trace 30 may include one of copper, silver, aluminum, aluminum alloy, nickel, titanium alloy, etc.
[0044] Specifically, the functional electrode 10 can be a high-voltage common electrode, and one side of the functional electrode 10 can be as follows: Figure 2 As shown, a C-shape is formed to surround the connection portion of the first metal trace 20.
[0045] Specifically, the second metal layer M2 includes a source and a drain (source-drain 50), the source and drain are disposed corresponding to the gate of the thin film transistor, and the source and drain are connected to the active layer of the thin film transistor.
[0046] Specifically, one end of the second metal trace 30 crosses the functional electrode 10 and is connected to the driving circuit 70, and the other end is connected to the first metal trace 20 through the adapter hole 401 of the corresponding connection part on the insulating layer PV. Charge accumulation is likely to occur at the connection part of the first metal trace 20 during the manufacturing process. Charge accumulation is also likely to occur at the outline of the functional electrode 10 near the first metal trace 20. When too much charge accumulates, the insulating layer PV is likely to be broken down near the adapter hole 401 (at the position between the functional electrode 10 and the first metal trace 20), causing a short circuit between the functional electrode 10 and the second metal trace 30.
[0047] Specifically, the material of the shielding trace 60 is the same as that of the first metal trace 20. Both ends of the shielding trace 60 are free ends. The shielding trace 60 is left empty and is not connected to any trace or electrode.
[0048] Specifically, the shielding trace 60 is extended as far as possible in the first direction F1. When the functional electrode 10 partially surrounds the end of the first metal trace 20, the two ends of the shielding trace 60 are bent to form a C-shape, correspondingly surrounding the end (connection part) of the first metal trace 20, so that the functional electrode 10 and the end of the first metal trace 20 are shielded and isolated, thereby preventing ESD from occurring between the functional electrode 10 and the end of the first metal trace 20, breaking down the insulating layer PV, and causing a short circuit between the second metal trace 30 and the functional electrode 10.
[0049] Specifically, the shape of the shielding trace 60 is not limited; it can be a straight line, an irregular curve, or a wave shape. The specific shape can be set according to the actual production situation. This embodiment will use a straight line as an example for explanation.
[0050] Specifically, the line width of the shielded trace 60 is greater than or equal to 5 μm.
[0051] It is understood that by providing a shielding trace 60 between the ends of the first metal trace 20 and the functional electrode 10, the end of the functional electrode 10 near the first metal trace 20 is shielded from the end of the first metal trace 20 with the connecting portion. This avoids the accumulation of charge at the ends or contour edges of long traces during the manufacturing process, which could cause ESD and break down the insulating layer PV. This effectively avoids the electrostatic short circuit problem between the functional electrode 10 and the second metal trace 30 caused by ESD.
[0052] In one embodiment, such as Figure 2As shown, the shielded trace 60 includes a first shielded segment extending along a first direction F1 and two second shielded segments respectively connecting the two ends of the first shielded segment and extending along a second direction F2. The first direction F1 and the second direction F2 have a preset angle. The first shielded segment and the two second shielded segments form a semi-enclosed structure. The semi-enclosed structure surrounds the end of the first metal trace 20 near the functional electrode 10.
[0053] Specifically, the first shielding segment of the shielding trace 60 is directly opposite the functional electrode 10. The length of the first shielding segment is as long as possible, and the two ends of the first shielding segment extend in the same direction, so that the shielding trace 60 forms a C-shape, which partially surrounds the connecting portion of the first metal trace 20, thereby shielding and isolating the functional electrode 10 and the end of the first metal trace 20, thus preventing ESD from occurring between the functional electrode 10 and the end of the first metal trace 20, breaking down the insulating layer PV, and causing a short circuit between the second metal trace 30 and the functional electrode 10.
[0054] Specifically, the preset angle between the first direction F1 and the second direction F2 can be 90°.
[0055] Specifically, the two bends of the shielded trace 60 are rounded, which can reduce the amount of charge accumulation on the shielded trace 60 during the manufacturing process.
[0056] It is understood that by setting the shielding trace 60 to include a first shielding segment extending along the first direction F1 and two second shielding segments respectively connecting the two ends of the first shielding segment and extending along the second direction F2, the shielding trace 60 forms a C-shape, which can better shield the functional electrode 10 and the first metal trace 20 from each other, preventing ESD from occurring between the ends of the functional electrode 10 and the first metal trace 20, breaking down the insulating layer PV, and thus causing a short circuit between the second metal trace 30 and the functional electrode 10.
[0057] In one embodiment, one end of the second metal trace 30 extends along the first direction F1, bypasses the second shielding section, and is connected to the first metal trace 20 through the adapter hole 401.
[0058] Specifically, in comparison Figure 2 ,like Figure 3 As shown, after setting the shielded trace 60, the second metal trace 30 is moved to both sides. One end of the second metal trace 30 extends along the first direction F1, bypasses the second shielded section, and then connects to the first metal trace 20 through the adapter hole 401.
[0059] It is understandable that by extending one end of the second metal trace 30 along the first direction F1, bypassing the second shielding section, and connecting it to the first metal trace 20 through the adapter hole 401, the A1 area, which is prone to ESD, can be bypassed, thereby further reducing the possibility of a short circuit between the second metal trace 30 and the functional electrode 10.
[0060] In one embodiment, such as Figure 5 As shown, the first metal trace 20 includes at least two first branch traces 201, and the second metal trace 30 includes at least two second branch traces 301. The two first branch traces 201 are connected to different gates. The connection portion includes at least two connection sub-ports. Each end of the first branch trace 201 is provided with a connection sub-port. The end of the first branch trace 201 with the connection sub-port is close to the end of the functional electrode 10. The insulating layer PV is provided with a plurality of transition holes 401 corresponding to the connection sub-region. The second branch trace 301 is connected to the first branch trace 201 through the transition holes 401.
[0061] The shielded trace 60 includes at least two shielded sub-traces 601, each shielded sub-traces 601 corresponding to a first branch trace 201. Each shielded sub-traces 601 includes a first shielded segment extending along the first direction F1 and a second shielded segment connecting the two ends of the first shielded segment and extending along the second direction F2. The first shielded segment and the two second shielded segments form a semi-enclosed structure surrounding the end of the first branch trace 201 near the second metal trace 30.
[0062] It should be noted that the two first branch traces 201 are connected to different gates. The two first branch traces 201 can be shielded from the functional electrode 10 by a shielding trace 60. When the shielding trace 60 fails to provide shielding, the shielding traces 60 corresponding to the two thin film transistors will both fail, and the short circuit risk of the other second branch trace 301 structure that has not been short-circuited will increase significantly. In order to ensure a better shielding effect, a shielding sub-trace 601 is provided for each of the connecting sub-parts.
[0063] Specifically, the shielding sub-trace 601 has a C-shaped structure. The shielding sub-trace 601 surrounds the connecting portion of the first branch trace 201, thereby shielding the connecting portion of the functional electrode 10 and each first branch trace 201, thus preventing ESD from occurring between the functional electrode 10 and the end of the first metal trace 20, breaking down the insulating layer PV, and causing a short circuit between the second branch trace 301 and the functional electrode 10.
[0064] It is understandable that by setting a shielding sub-trace 601 for each connecting sub-part, the ESD risk between the two adjacent first branch traces 201 and the functional electrode 10 is dispersed, further reducing the short circuit risk between the ends of long traces on the array substrate.
[0065] In one embodiment, the connection between the first shielding segment and the second shielding segment is rounded.
[0066] Specifically, the angle of the rounded corner can be 90°, which can be adjusted according to the actual production situation.
[0067] It is understandable that rounding the connection between the first shielding section and the second shielding section can reduce charge accumulation at the bend of the shielding trace 60 during the manufacturing process and prevent excessive charge accumulation at the tip of the outer contour of the shielding trace 60 from causing short circuits in other circuits.
[0068] In one embodiment, the distance between the shielding trace 60 and the first metal trace 20 is equal to the distance between the shielding trace 60 and the functional electrode 10.
[0069] It is understandable that, since the shielding trace 60 is made of metal, placing the shielding trace 60 in the middle position between the first metal trace 20 and the functional electrode 10 can ensure that the shielding effect of the shielding trace 60 on the first metal trace 20 and the functional electrode 10 is the same, thereby improving the ESD protection effect of the shielding trace 60.
[0070] In one embodiment, the width of the shielding trace 60 is greater than or equal to 5 μm.
[0071] Specifically, the width of the shielding trace 60 refers to the line width of the shielding trace 60 projected onto the array substrate. Its width can be 5um, 7um, 12um, etc., and can be selected according to the actual production situation.
[0072] In one embodiment, such as Figure 6 As shown, the shielded trace 60 includes a first shielded trace group and a second shielded trace group. The first shielded trace group includes a plurality of first shielded trace sub-sections 602, and the second shielded trace group includes a plurality of second shielded trace sub-sections 603. The first shielded trace group and the second shielded trace group are arranged in parallel, and the first shielded trace sub-sections 602 and the second shielded trace sub-sections 603 are arranged alternately.
[0073] Specifically, the shielding trace 60 is not limited to a continuous trace. The shielding trace 60 can be a multi-segment line. The multi-segment line can form a continuous metal shielding structure, which can prevent ESD caused by excessive charge accumulation between the functional electrode 10 and the first metal trace 20.
[0074] Specifically, the lengths of the plurality of first shielding trace sub-sections 602 are not limited and can be equal or unequal. The lengths of the plurality of second shielding trace sub-sections 603 are not limited and can be equal or unequal. However, the first shielding trace sub-sections 602 and the second shielding trace sub-sections 603 need to be staggered, that is, at least one shielding trace sub-section is needed to isolate and disconnect the functional electrode 10 and the first metal trace 20.
[0075] In one embodiment, the shielding trace 60 includes one of a straight line, an irregular curve, and a wavy line.
[0076] Specifically, the shielding trace 60 is preferably a straight line. Straight lines have fewer ends (protrusions) compared to curved or wavy lines, resulting in less static charge accumulation during the manufacturing process and thus providing a better shielding effect.
[0077] It is understood that the function of the shielding trace 60 is to prevent excessive charge accumulation on the first metal trace 20 and the functional electrode 10 from breaking down the insulating layer PV. Therefore, the shape of the shielding trace 60 is not required. Any line structure that can shield and isolate the functional electrode 10 and the first metal trace 20 is within the protection scope of this application.
[0078] In addition, this application also provides a mobile terminal, including the array substrate and terminal body described in any of the above embodiments, wherein the terminal body and the array substrate are integrated into one unit.
[0079] In summary, this application provides a shielding trace 60 between the ends of the first metal trace 20 and the functional electrode 10 that are opposite to each other, so that the end of the functional electrode 10 near the first metal trace 20 and the end of the first metal trace 20 with the connecting part shield each other, avoiding ESD caused by the accumulation of charge at the ends or contour edges of long traces during the manufacturing process, which could break down the insulating layer PV. This effectively avoids the problem of electrostatic short circuit between the functional electrode 10 and the second metal trace 30 caused by ESD.
[0080] The above provides a detailed description of an array substrate and a mobile terminal provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. An array substrate, characterized in that, include A substrate, wherein a driving circuit is disposed on the substrate near its edge; A first metal layer is disposed on the substrate and includes a gate, a first metal trace connected to the gate, and a functional electrode. The end of the first metal trace away from the gate includes a connection portion, and the connection portion and the functional electrode are disposed at a distance. An insulating layer is disposed on the substrate and the first metal layer and covers the first metal layer, the insulating layer including a plurality of transition holes located above the connection portion; A second metal layer is disposed on the insulating layer. The second metal layer includes a source and drain corresponding to the gate and a second metal trace. One end of the second metal trace is connected to the driving circuit, and the other end of the second metal trace is connected to the first metal trace through the adapter hole. The first metal layer further includes shielding traces located between the connection portion and the functional electrode; The shielded trace includes a first shielding segment extending along a first direction and two second shielding segments respectively connecting the two ends of the first shielding segment and extending along a second direction. The first shielding segment and the two second shielding segments form a semi-enclosed structure, which surrounds the end of the first metal trace near the functional electrode.
2. The array substrate as described in claim 1, characterized in that, The first direction and the second direction have a preset angle.
3. The array substrate as described in claim 1, characterized in that, One end of the second metal trace extends along the first direction, bypasses the second shielding section, and connects to the first metal trace through the adapter hole.
4. The array substrate as described in claim 1, characterized in that, The first metal trace includes at least two first branch traces, the second metal trace includes at least two second branch traces, the two first branch traces are connected to different gates, the connection portion includes at least two connection sub-ports, each first branch trace has a connection sub-port at its end, the end of the first branch trace with the connection sub-port is close to the end of the functional electrode, the insulating layer has a plurality of adapter holes corresponding to the connection sub-region, and the second branch trace is connected to the first branch trace through the adapter holes; The shielded trace includes at least two shielded sub-traces, one of which is configured corresponding to one of the first branch traces. Each shielded sub-traces includes a first shielded segment extending along the first direction and a second shielded segment connecting the two ends of the first shielded segment and extending along the second direction. The first shielded segment and the two second shielded segments form a semi-enclosed structure that surrounds the end of the first branch trace near the second metal trace.
5. The array substrate as described in claim 1, characterized in that, The connection between the first shielding section and the second shielding section is rounded.
6. The array substrate as claimed in claim 1, characterized in that, The distance between the shielding trace and the first metal trace is equal to the distance between the shielding trace and the functional electrode.
7. The array substrate as claimed in claim 1, characterized in that, The width of the shielding trace is greater than or equal to 5µm.
8. The array substrate as claimed in claim 1, characterized in that, The shielding traces include a first shielding trace group and a second shielding trace group. The first shielding trace group includes multiple first shielding trace sub-sections, and the second shielding trace group includes multiple second shielding trace sub-sections. The first shielding trace group and the second shielding trace group are arranged in parallel, and the first shielding trace sub-sections and the second shielding trace sub-sections are arranged alternately.
9. The array substrate as claimed in claim 1, characterized in that, The shielded traces include one of the following: straight lines, irregular curves, and wavy lines.
10. A mobile terminal, characterized in that, It includes the array substrate and terminal body as described in any one of claims 1 to 9, wherein the terminal body and the array substrate are integrated into one unit.
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