Ferroelectric transistor structure and method of making the same

Abstract

The application provides a ferroelectric transistor structure and a preparation method thereof. The ferroelectric transistor structure comprises a bottom substrate, a ferroelectric layer, an insulating dielectric layer and a top substrate which are sequentially arranged on the surface of the bottom substrate in a direction away from the bottom substrate, a field effect transistor on the top substrate, and a control electrode penetrating through the top substrate and electrically connected with the ferroelectric layer, wherein the control electrode is used for controlling the ferroelectric layer. The application can improve the integration of the ferroelectric transistor, and reduce the structural complexity and the preparation difficulty of the ferroelectric transistor.

Description

Technical Field

[0001] This invention relates to the field of memory technology, and in particular to a ferroelectric transistor structure and its fabrication method. Background Technology

[0002] Ferroelectric memories utilize the ferroelectric effect of ferroelectric materials under an external electric field to store information. A ferroelectric memory contains multiple ferroelectric transistors (FeFETs), and each FeFET can store information. This promises to enable information storage in smaller cells.

[0003] However, for existing ferroelectric memories, one type of ferroelectric memory structure places the ferroelectric layer between the gate and gate oxide layers in the gate structure. However, because the gate oxide layer in the gate structure is relatively thin, it is prone to ferroelectric polarization breakdown, thereby reducing the lifetime of the ferroelectric transistor. Another type of ferroelectric memory structure places the ferroelectric layer on the outside of the gate structure and forms a ferroelectric capacitor by placing electrode layers on opposite sides. Although this can avoid ferroelectric polarization breakdown of the ferroelectric transistor, it not only reduces the integration density of the ferroelectric transistor, but also increases the structural complexity of the ferroelectric transistor and the complexity of its fabrication. Summary of the Invention

[0004] To address the aforementioned problems, the ferroelectric transistor structure and its fabrication method provided by this invention, by placing the ferroelectric layer on the side of the insulating layer away from the gate structure, not only can the polarization breakdown of the ferroelectric layer be avoided from breaking through the field-effect transistor above, but the integration density of the gate structure can also be improved.

[0005] In a first aspect, the present invention provides a ferroelectric transistor structure, comprising: a bottom substrate;

[0006] A ferroelectric layer, an insulating dielectric layer, and a top substrate are sequentially disposed on the surface of the bottom substrate in a direction away from the bottom substrate.

[0007] Field-effect transistors located on the top substrate;

[0008] In addition, a control electrode that penetrates the top substrate and is electrically connected to the ferroelectric layer, the control electrode being used to control the ferroelectric layer.

[0009] Optionally, the thickness of the insulating dielectric layer ranges from 10 nm to 100 nm.

[0010] Optionally, the thickness of the top substrate ranges from 5 nm to 100 nm.

[0011] Optionally, the material of the underlying substrate includes at least one of silicon, germanium, gallium arsenide, and silicon carbide.

[0012] Optionally, the material of the top layer substrate includes at least one of silicon, germanium, gallium arsenide, and silicon carbide.

[0013] Optionally, the field-effect transistor includes at least one of the following: silicon-on-insulator planar field-effect transistor, silicon-on-insulator fin field-effect transistor, and silicon-on-insulator all-around gate transistor.

[0014] Optionally, the ferroelectric transistor structure further includes: a first shallow trench isolation;

[0015] The first shallow trench isolation penetrates the top substrate, the insulating dielectric layer and the ferroelectric layer, and the first shallow trench isolation is in contact with the bottom substrate;

[0016] The first shallow trench isolation is located on the side of the control electrode away from the field-effect transistor and on the side of the field-effect transistor away from the control electrode.

[0017] Optionally, the ferroelectric transistor structure further includes: a second shallow trench isolation;

[0018] The second shallow trench isolation penetrates the top substrate;

[0019] The second shallow trench isolation is used to isolate the control electrode from the field-effect transistor.

[0020] In a second aspect, the present invention provides a method for fabricating a ferroelectric transistor structure, comprising:

[0021] Provide a pre-prepared substrate;

[0022] Ions are implanted on the surface of the pre-substrate to form a release layer within the pre-substrate, with the pre-substrate on opposite sides of the release layer being the top substrate and the sacrificial substrate, respectively.

[0023] Provide the underlying substrate;

[0024] On the surface of the bottom substrate, a ferroelectric layer and an insulating dielectric layer are formed sequentially in a direction away from the bottom substrate;

[0025] Bond the top substrate to the insulating dielectric layer;

[0026] By processing the release layer, the sacrificial substrate is removed while the top layer substrate is retained;

[0027] A control electrode is formed within the top substrate, and a field-effect transistor is formed on the top substrate.

[0028] Optionally, after the step of removing the sacrificial substrate and retaining the top substrate by processing the release layer, the fabrication method further includes:

[0029] A first shallow trench isolation and a second shallow trench isolation are formed on the top substrate;

[0030] The first shallow trench isolation is located on the side of the control electrode away from the field-effect transistor and on the side of the field-effect transistor away from the control electrode, respectively.

[0031] The second shallow trench isolation extends through the top substrate and is located on the side of the control electrode facing the source. The second shallow trench isolation is used to isolate the control electrode from the field-effect transistor.

[0032] The ferroelectric transistor structure and its fabrication method provided in this invention, by placing the ferroelectric layer on the side of the insulating layer away from the gate structure, not only avoids the ferroelectric layer polarization breakdown that breaks down the field-effect transistor above, but also improves the integration of the ferroelectric transistor structure. At the same time, it facilitates the formation of the ferroelectric layer, reduces the structural complexity and fabrication difficulty of the ferroelectric transistor. In addition, by providing an insulating dielectric layer, it is possible to effectively prevent the ferroelectric layer from breaking down the ferroelectric transistor structure during polarization. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a schematic structural diagram of a ferroelectric transistor structure according to an embodiment of this application;

[0035] Figure 2 This is a schematic flowchart illustrating a method for fabricating a ferroelectric transistor structure according to an embodiment of this application;

[0036] Figures 3 to 7 These are schematic structural diagrams illustrating the various stages in the fabrication of a ferroelectric transistor structure according to an embodiment of this application.

[0037] Figure Labels

[0038] 1. Bottom substrate; 2. Ferroelectric layer; 3. Insulating dielectric layer; 4. Preparatory substrate; 41. Release layer; 42. Top substrate; 43. Sacrificial substrate; 5. Field-effect transistor; 51. Gate structure; 52. Source; 53. Drain; 6. Control electrode; 71. First shallow trench isolation; 72. Second shallow trench isolation. Detailed Implementation

[0039] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0040] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0041] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.

[0042] It should be noted that when an element is referred to as "fixedly connected" to another element, it can be directly on the other element or there may be an intervening element. When an element is considered to be "connected" to another element, it can be directly connected to the other element or there may be an intervening element. Conversely, when an element is referred to as being "directly on" another element, there is no intervening element. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0043] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising,” “including,” or “having,” etc., specify the presence of the stated feature, whole, step, operation, component, part, or combination thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0044] In a first aspect, the present invention provides a ferroelectric transistor structure, see [link to previous document]. Figure 1 The ferroelectric transistor structure includes: a bottom substrate 1;

[0045] Located on the surface of the bottom substrate 1, and arranged sequentially along the direction away from the bottom substrate 1 are the ferroelectric layer 2, the insulating dielectric layer 3, and the top substrate 42;

[0046] Field-effect transistor 5 is located on the top substrate 42;

[0047] And a control electrode 6 that penetrates the top substrate 42 and is electrically connected to the ferroelectric layer 2, the control electrode 6 being used to control the ferroelectric layer 2.

[0048] The field-effect transistor 5 includes: a gate structure 51 located on the side of the bottom substrate 1 facing away from the bottom substrate 1, and a source 52 and a drain 53 located within the top substrate 42; a control electrode 6 penetrating the top substrate 42 and contacting the upper surface of the bottom substrate 1, or inserted into the bottom substrate, or contacting the ferroelectric layer 2; the thickness of the insulating dielectric layer 3 ranges from 20nm to 100nm, such as 30nm, 50nm, 60nm, or 80nm; the thickness of the top substrate 42 ranges from 5nm to 150nm, such as 60nm, 70nm, 80nm, 100nm, 120nm, or 130nm. The insulating dielectric layer 3 further prevents the ferroelectric layer 2 from penetrating the field-effect transistor 5 when polarized.

[0049] Furthermore, the thickness of the ferroelectric layer 2 is determined by the material used in the ferroelectric layer 2. Specifically, the ferroelectric layer 2 can be a mixed material layer composed of hafnium dioxide (HfO2) and zirconium dioxide (ZrO2), or it can be hafnium dioxide, etc. In this embodiment, the ferroelectric layer 2 is composed of hafnium dioxide and zirconium dioxide, and the ratio of hafnium dioxide to zirconium dioxide is 1:1, but it is not limited to this; the thickness of the ferroelectric layer 2 is 9nm to 11nm, such as 10nm, and this embodiment does not specifically limit it.

[0050] The material of the bottom substrate 1 includes at least one of silicon, germanium, gallium arsenide and silicon carbide; the material of the top substrate includes at least one of silicon, germanium, gallium arsenide and silicon carbide.

[0051] When both the bottom substrate 1 and the top substrate 42 are germanium substrates, the bottom substrate 1, the ferroelectric layer 2, the insulating dielectric layer 3 and the top substrate 42 constitute a GOI (germanium on insulator) ferroelectric substrate.

[0052] In this embodiment, the stacked structure formed by the ferroelectric layer 2, the insulating dielectric layer 3, and the top substrate 42 is located above the bottom substrate 1; the bottom substrate 1, the ferroelectric layer 2, the insulating dielectric layer 3, and the top substrate 42 constitute a composite ferroelectric substrate; the insulating dielectric layer 3 is a BOX (buried oxide) layer, that is, an insulating oxide, such as silicon oxide; the gate structure 51 includes: a gate, a protective layer, and a gate oxide layer; the gate is located on the side of the gate oxide layer away from the top substrate 42, and the protective layer is located outside the gate and the gate oxide layer, wherein the protective layer is an insulating material; the gate can be an HKMG (high dielectric constant metal gate), but is not limited to this, in this embodiment The embodiment does not limit the specific material of the gate oxide layer; the control electrode 6 penetrates the top substrate 42 and contacts the upper surface of the bottom substrate 1; both the bottom substrate 1 and the top substrate 42 are silicon substrates; the bottom substrate 1, the ferroelectric layer 2, the insulating dielectric layer 3 and the top substrate 42 constitute an SOI (silicon-on-insulator) ferroelectric substrate; the thickness of the insulating dielectric layer 3 is 40 nm; the thickness of the top substrate 42 is 65 nm; the control electrode 6 contacts the upper surface of the bottom substrate 1, and the control electrode 6 is electrically connected to the ferroelectric layer 2 through the bottom substrate 1; the control electrode 6, the source electrode 52 and the drain electrode 53 are all exposed on the upper surface of the top substrate 42.

[0053] The field-effect transistor 5 includes at least one of the following: silicon-on-insulator planar field-effect transistor, silicon-on-insulator fin field-effect transistor (SOI FinFET), and silicon-on-insulator gate-all-around transistor (SOI GAAFET). That is, the structure of the gate structure 51, source 52, and drain 53 above the insulating dielectric layer 3 may be the same as the structure of the gate structure 51, source 52, and drain 53 on the silicon-on-insulator planar transistor 5, the silicon-on-insulator fin field-effect transistor, or the silicon-on-insulator gate-all-around transistor, but is not limited thereto.

[0054] The ferroelectric transistor structure further includes a first shallow trench isolation 71 and a second shallow trench isolation 72. The first shallow trench isolation 71 penetrates the top substrate 42, the insulating dielectric layer 3, and the ferroelectric layer 2, and is in contact with the bottom substrate 1. The first shallow trench isolation 71 is located on the side of the control electrode 6 away from the gate structure 51 and on the side of the gate structure 51 away from the control electrode 6, respectively. By setting the first shallow trench isolation 71, adjacent field-effect transistors 5 can be effectively isolated. The bottom end of the first shallow trench isolation 71 can contact the upper surface of the bottom substrate 1 or be inserted into the interior of the bottom substrate 1. In this embodiment, the bottom end of the first shallow trench isolation 71 is inserted into the interior of the bottom substrate 1.

[0055] The second shallow trench isolation 72 penetrates the top substrate 42. The second shallow trench isolation 72 is located on the side of the control electrode 6 facing the source 52 or drain 53. In this embodiment, the drain 53 is located on the left side of the gate structure 51, the source 52 is located on the right side of the gate structure 51, and the control electrode 6 is located on the right side of the gate structure 51. The second shallow trench isolation 72 penetrates the top substrate 42 and contacts the insulating dielectric layer 3. The second shallow trench isolation 72 is used to isolate the control electrode 6 from the source 52.

[0056] It should be noted that the ferroelectric layer 2 is the ferroelectric storage cell, which is used to store the corresponding information. At the same time, after the information is stored in the ferroelectric layer 2, it will affect the opening of the field-effect transistor 5 above. The external system can read the relevant information from the field-effect transistor 5. The control electrode 6 can complete the writing and erasing of information in the form of a back gate.

[0057] In addition, the control electrode 6 can also turn on the field-effect transistor 5 together with the gate.

[0058] The ferroelectric transistor structure provided in this embodiment is simple, by placing the ferroelectric layer 2 in the insulating layer.

[0059] The side facing away from the gate structure 51 not only reduces the space occupied by the ferroelectric layer 2 above the top substrate 42, but also improves the integration density of the ferroelectric transistor structure, allowing for more space above the top substrate 42.

[0060] By placing other devices, the polarization breakdown of the ferroelectric layer 2 is avoided, which breaks down the field-effect transistor 5 above it. At the same time, it facilitates the formation of the ferroelectric layer 2, reduces the structural complexity and fabrication difficulty of the ferroelectric transistor. In addition, by placing the insulating dielectric layer 3, the ferroelectric layer 2 is effectively prevented from breaking down the ferroelectric transistor structure during polarization, thus extending the service life of the ferroelectric transistor structure.

[0061] 0. In a second aspect, this embodiment provides a method for fabricating a ferroelectric transistor structure, which, in conjunction with the ferroelectric transistor provided in the first aspect, is described in [reference needed]. Figure 2 The preparation method includes steps S101 to S107:

[0062] Step S101: Provide a pre-substrate 4.

[0063] Step S102: Combining Figure 3 Ions are implanted into the surface of the pre-substrate 4 to form a release layer 41 within the pre-substrate 4.

[0064] The pre-substrate 4 located on opposite sides of the release layer 41 is the top substrate 42 and the sacrificial substrate 43, respectively.

[0065] In this embodiment, the implanted ions are low-energy hydrogen ions, but are not limited to this. Any ion that can divide the prepared substrate 4 into two parts and requires other conditions to separate the two parts can be used.

[0066] This embodiment does not further limit the method of hydrogen ion injection.

[0067] It should be noted that when injecting low-energy hydrogen ions, the injection is performed from above and downwards on the preparatory substrate 4. The preparatory substrate 4 is located above the release layer 41, and the sacrificial substrate 43 is located below the release layer 41.

[0068] Step S103: Provide the bottom substrate 1.

[0069] Step S104: Combining Figure 4 On the surface of the bottom substrate 1, a ferroelectric layer 2 and an insulating dielectric layer 3 are formed sequentially in a direction away from the bottom substrate 1.

[0070] 5. The methods for forming the ferroelectric layer 2 and the insulating dielectric layer 3 include, but are not limited to, atomic layer deposition.

[0071] Step S105: Combining Figure 5 The top substrate 42 is bonded to the insulating dielectric layer 3 so that the upper surface of the top substrate 42 is attached to the upper surface of the insulating dielectric layer 3.

[0072] Step S106: Combining Figure 6 By processing the stripping layer 41, the sacrificial substrate 43 is removed and the top substrate 42 is retained.

[0073] In this embodiment, hydrogen ions are condensed into bubbles by heating and annealing the release layer 41, so as to separate the top substrate 42 and the sacrificial substrate 43 while removing the release layer 41.

[0074] Step S107: Combining Figure 1 and Figure 7 A control electrode 6 is formed in the top substrate 42, and a field-effect transistor 5 is formed on the top substrate 42.

[0075] The execution order of steps S101 to S102 and steps S103 to S104 can be interchanged, or steps S101 and S103 can be performed simultaneously.

[0076] The method of forming the control electrode 6 includes, but is not limited to: etching a groove through the top substrate 42, the insulating dielectric layer 3 and the ferroelectric layer 2 on the top substrate 42, the groove being located between the first shallow trench isolation 71 and the second shallow trench isolation 72; filling the two sides of the groove with a material of the same material as the bottom substrate 1 to form a filling layer; and filling the remaining space in the groove with the material of the control electrode 6 to form the control electrode 6.

[0077] In an alternative embodiment, after the step of removing the sacrificial substrate 43 and retaining the top substrate 42 by processing the release layer 41, the fabrication method further includes forming a first shallow trench isolation 71 and a second shallow trench isolation 72 on the top substrate 42.

[0078] The first shallow trench isolation 71 and the second shallow trench isolation 72 can be formed using STI (shallow trench isolation) technology, but are not limited to this. The first shallow trench isolation 71 is located on the side of the control electrode 6 away from the field-effect transistor 5 and the side of the field-effect transistor 5 away from the control electrode 6, respectively. The second shallow trench isolation 72 penetrates the top substrate 42 and the insulating dielectric layer 3, and is located on the side of the control electrode 6 facing the field-effect transistor 5. The second shallow trench isolation 72 is used to isolate the control electrode 6 from the field-effect transistor 5.

[0079] In an optional embodiment, after step S107, the fabrication method further includes: performing metal interconnection on the drain 53, source 52, gate and control electrode 6.

[0080] In an optional embodiment, before step S105, the preparation method further includes: planarizing the surface of the top layer facing away from the sacrificial substrate 43, and planarizing the surface of the insulating dielectric layer 3 facing away from the ferroelectric layer 2, which can improve the stability of the composite ferroelectric substrate structure after bonding.

[0081] The fabrication method is simple to operate. By placing the ferroelectric layer 2 on the side of the insulating layer away from the gate structure 51, it not only reduces the space occupied by the ferroelectric layer 2 above the top substrate 42 and improves the integration of the ferroelectric transistor structure, but also allows more space above the top substrate 42 to arrange other devices. At the same time, it facilitates the formation of the ferroelectric layer 2, reduces the structural complexity and fabrication difficulty of the ferroelectric transistor. In addition, by placing the insulating dielectric layer 3, it effectively prevents the ferroelectric layer 2 from breaking down the ferroelectric transistor structure during polarization, thus extending the service life of the ferroelectric transistor structure.

[0082] In the description of this specification, the references to terms such as "some embodiments," "other embodiments," "ideal embodiments," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example that are included in at least one embodiment or example of this application. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0083] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0084] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A ferroelectric transistor structure, characterized in that, include: The underlying substrate; the material of the underlying substrate includes at least one of silicon and silicon carbide, and at least one of germanium and gallium arsenide; A ferroelectric layer, an insulating dielectric layer, and a top substrate are sequentially disposed on the surface of the bottom substrate and in a direction away from the bottom substrate, wherein the ferroelectric layer is directly bonded to the bottom substrate; A field-effect transistor located on the top substrate, the field-effect transistor being located on the side of the insulating dielectric layer away from the ferroelectric layer; the field-effect transistor includes: a gate structure located on the side of the bottom substrate away from the bottom substrate, and a source and drain located within the top substrate; the gate structure, source, and drain are all located above the insulating dielectric layer; Additionally, a control electrode is provided that penetrates the top substrate and is electrically connected to the ferroelectric layer through the bottom substrate, the control electrode being used to control the ferroelectric layer.

2. The ferroelectric transistor structure according to claim 1, characterized in that, The thickness of the insulating dielectric layer ranges from 10 nm to 100 nm.

3. The ferroelectric transistor structure according to claim 1, characterized in that, The thickness of the top substrate ranges from 5 nm to 100 nm.

4. The ferroelectric transistor structure according to claim 1, characterized in that, The material of the top substrate includes at least one of silicon, germanium, gallium arsenide, and silicon carbide.

5. The ferroelectric transistor structure according to claim 1, characterized in that, The field-effect transistor includes at least one of the following: silicon-on-insulator planar field-effect transistor, silicon-on-insulator fin field-effect transistor, and silicon-on-insulator all-around gate transistor.

6. The ferroelectric transistor structure according to claim 1, characterized in that, Also includes: First shallow trench isolation; The first shallow trench isolation penetrates the top substrate, the insulating dielectric layer and the ferroelectric layer, and the first shallow trench isolation is in contact with the bottom substrate; The first shallow trench isolation is located on the side of the control electrode away from the field-effect transistor and on the side of the field-effect transistor away from the control electrode.

7. The ferroelectric transistor structure according to any one of claims 1 to 6, characterized in that, Also includes: Second shallow trench isolation; The second shallow trench isolation penetrates the top substrate; The second shallow trench isolation is used to isolate the control electrode from the field-effect transistor.

8. A method for fabricating a ferroelectric transistor structure as described in any one of claims 1 to 7, characterized in that, include: Provide a pre-prepared substrate; Ions are implanted into the surface of the pre-substrate to form a release layer within the pre-substrate, wherein the pre-substrate located on opposite sides of the release layer is the top substrate and the sacrificial substrate, respectively. Provide the underlying substrate; A ferroelectric layer and an insulating dielectric layer are sequentially formed on the surface of the bottom substrate, in a direction away from the bottom substrate; The top substrate is bonded to the insulating dielectric layer; By processing the release layer, the sacrificial substrate is removed while the top layer substrate is retained; A control electrode is formed within the top substrate, and a field-effect transistor is formed on the top substrate.

9. The preparation method according to claim 8, characterized in that, Following the step of removing the sacrificial substrate and retaining the top substrate by processing the release layer, the fabrication method further includes: A first shallow trench isolation and a second shallow trench isolation are formed on the top layer substrate; The first shallow trench isolation is located on the side of the control electrode away from the field-effect transistor and on the side of the field-effect transistor away from the control electrode, respectively; The second shallow trench isolation extends through the top substrate and is used to isolate the control electrode from the field-effect transistor.

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