Semiconductor device and display device

Abstract

The present disclosure provides a semiconductor device and a display device, wherein the semiconductor device comprises a buffer layer, a first sub-chip, a second sub-chip, and a connector. The first sub-chip and the second sub-chip are separately arranged on the buffer layer. Each of the first sub-chip and the second sub-chip comprises a first diffusion layer, an active layer, and a second diffusion layer. The first diffusion layer, the active layer, and the second diffusion layer are sequentially arranged on the buffer layer from top to bottom. The first diffusion layer and the buffer layer are first type epitaxial layers, and the second diffusion layer is a second type epitaxial layer. The connector is used to electrically couple the second diffusion layer of the first sub-chip to the first diffusion layer of the second sub-chip.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a display device, and more particularly to a semiconductor device and a display device including light emitting diodes coupled in series. Background Art

[0002] Regarding micro light emitting diode (micro LED) displays, the main thing is to miniaturize the LED structure design, and its size is only about 1 to 10μm level; then the micro LED is transferred to the circuit substrate in batches, and then the substrate is packaged using a physical deposition process to complete the simple micro LED display. Micro LED displays have high brightness and are suitable for outdoor applications, but their power is mostly provided by batteries, so if you want to extend the use time of micro LED displays, you need to reduce their power consumption. Summary of the invention

[0003] One embodiment of the present disclosure provides a semiconductor device, comprising a buffer layer, a first sub-chip, a second sub-chip, and a connector. The first sub-chip and the second sub-chip are separately disposed on the buffer layer. Each of the first sub-chip and the second sub-chip comprises a first diffusion layer, an active layer, and a second diffusion layer. The first diffusion layer, the active layer, and the second diffusion layer are sequentially disposed on the buffer layer from top to bottom, the first diffusion layer and the buffer layer are first type epitaxial layers, and the second diffusion layer is a second type epitaxial layer. The connector is used to electrically couple the second diffusion layer of the first sub-chip to the first diffusion layer of the second sub-chip.

[0004] Another embodiment of the present disclosure provides a display device, comprising a plurality of pixels, a first reference voltage terminal, a second reference voltage terminal, and a third reference voltage terminal. Each of the pixels comprises a plurality of groups of sub-pixels. The first group of sub-pixels in the plurality of groups of sub-pixels comprises at least two first light-emitting elements. At least two first light-emitting elements are coupled in series with each other. The first reference voltage terminal is used to provide a first reference voltage to the pixel. The second reference voltage terminal is used to provide a second reference voltage to the pixel. The third reference voltage terminal is used to provide a third reference voltage to the pixel. The first reference voltage, the second reference voltage, and the third reference voltage are different from each other. The first light-emitting elements coupled in series with each other in the first group of sub-pixels are coupled between the first reference voltage terminal and the second reference voltage terminal, and the second group of sub-pixels in the plurality of groups of sub-pixels are coupled to the third reference voltage terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 It is a partial schematic diagram of a display device according to some embodiments of the present disclosure.

[0006] Figure 2Ais a circuit diagram of a sub-pixel display circuit according to some embodiments of the present disclosure.

[0007] Figure 2B is a circuit diagram of a sub-pixel display circuit according to some embodiments of the present disclosure.

[0008] Figure 3 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0009] Figure 4 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure.

[0010] Figure 5A is a schematic diagram of a pixel according to some embodiments of the present disclosure.

[0011] Figure 5B is a schematic diagram of a pixel according to some embodiments of the present disclosure.

[0012] Fig. 6A is a schematic diagram of a pixel according to some embodiments of the present disclosure.

[0013] Figure 6B is a schematic diagram of a pixel according to some embodiments of the present disclosure.

[0014] Description of reference numerals:

[0015] 100: Display device

[0016] 110: Pixels

[0017] 120R, 120G, 120B: drive circuit

[0018] DR1, DR2, DG, DB: Light Emitting Diode

[0019] VDD: voltage

[0020] VSS: voltage

[0021] T1: Transistor

[0022] N1: Node

[0023] D1: Light Emitting Diode

[0024] I1: Current

[0025] I2: Current

[0026] D2: Light Emitting Diode

[0027] 300: Semiconductor devices

[0028] 310: Sub-chip

[0029] 312: First diffusion layer

[0030] 314: Active layer

[0031] 316: Second diffusion layer

[0032] 320: Sub-chip

[0033] 322: First diffusion layer

[0034] 324: Active layer

[0035] 326: Second diffusion layer

[0036] 330: Buffer layer

[0037] 340: Electrode

[0038] 350: Electrode

[0039] I31, I32, I33: current

[0040] INS: Isolation layer

[0041] CON: Connectors

[0042] 400: Semiconductor devices

[0043] 410: Sub-chip

[0044] 412: First diffusion layer

[0045] 414: Active layer

[0046] 416: Second diffusion layer

[0047] 420: Sub-chip

[0048] 422: First diffusion layer

[0049] 424: Active layer

[0050] 426: Second diffusion layer

[0051] 430: Buffer layer

[0052] 440: Electrode

[0053] 450: Electrode

[0054] I41, I42, I43: current

[0055] 510A: Pixel

[0056] VDD2: voltage

[0057] VDD1: voltage

[0058] 510B: Pixel

[0059] VSS1: Voltage

[0060] VSS2: Voltage

[0061] 610A: Pixel

[0062] VDD3: voltage

[0063] 610B: Pixel

[0064] VSS3: Voltage

[0065] DB2: Light Emitting Diode DETAILED DESCRIPTION

[0066] The following is a detailed description of the embodiments with the accompanying drawings, but the embodiments provided are not intended to limit the scope of the present disclosure, and the description of the structure operation is not intended to limit its execution order. Any device with equal technical effects produced by the re-combination of components is within the scope of the present disclosure. In addition, the illustrations are for illustrative purposes only and are not drawn according to the original size. For ease of understanding, the same or similar components in the following description will be described with the same symbols.

[0067] In this article, unless the context specifically limits the article, "a", "an" and "the" may refer to one or more. In addition, "comprising", "including", "having" and similar words used in this article are used to specify the recorded features, regions, integers, steps, operations, elements and / or components.

[0068] In this document, when an element is described as being "connected", "coupled" or "electrically connected" to another element, the element may be directly connected, directly coupled or directly electrically connected to the other element, or there may be an additional element between the two elements, and the element may be indirectly connected, indirectly coupled or indirectly electrically connected to the other element. In addition, although the terms "first", "second", etc. are used in this document to describe different elements, the terms are only used to distinguish elements or operations described with the same technical terms.

[0069] One embodiment of the present disclosure relates to a display device. Figure 1 . Figure 1 FIG. 1 is a partial schematic diagram of a display device 100 according to some embodiments of the present disclosure. The display device 100 includes a plurality of pixels 110, and the pixels 110 are arranged in an array manner in the display device 100. In other words, the pixels 110 are arranged in a plurality of rows and columns. Figure 1In the embodiment of the present invention, the pixels 110 in the same column are coupled to the same voltages VDD and VSS through wiring, and the voltage VDD has a relatively high voltage level, and the voltage VSS has a relatively low voltage level. This embodiment is only exemplary, and in different embodiments, different wiring designs (such as the following) may be used. FIG. 5A to FIG. 6B ) to provide voltage to pixel 110. Figure 1 The size and number of the pixels 110 in the embodiment are also for illustration purposes only and do not represent the actual size and number of the pixels 110 .

[0070] like Figure 1 As shown in the pixel 110 in the upper left corner, each pixel 110 includes a driving circuit 120R, 120G, 120B and a light emitting diode (LED) DR1, DR2, DG, DB. The driving circuits 120R, 120G, 120B are used to receive a voltage VDD to drive the corresponding light emitting diode to emit light. Specifically, the first end of the driving circuits 120R, 120G, 120B is used to receive the voltage VDD, the second end of the driving circuit 120R is coupled to the light emitting diodes DR1, DR2, the second end of the driving circuit 120G is coupled to the light emitting diode DG, and the second end of the driving circuit 120B is coupled to the light emitting diode DB. The second ends of the light emitting diodes DR2, DG, DB are used to receive a voltage VSS.

[0071] like Figure 1 As shown, the LEDs DR1 and DR2 coupled to the driving circuit 120R can be regarded as the first group of sub-pixels, the LED DG coupled to the driving circuit 120G can be regarded as the second group of sub-pixels, and the LED DB coupled to the driving circuit 120B can be regarded as the third group of sub-pixels. In other words, each pixel 110 includes three groups of sub-pixels, and each group of sub-pixels is driven by a corresponding driving circuit to emit light. In some embodiments, the first group of sub-pixels includes a red LED to emit red light, the second group of sub-pixels includes a green LED to emit green light, and the third group of sub-pixels includes a blue LED to emit blue light.

[0072] In some embodiments, the display device 100 includes a gate driving circuit and a source driving circuit (not shown in the figure), the gate driving circuit is used to enable and turn on the driving circuits 120R, 120G, and 120B, and the source driving circuit is used to provide a voltage VDD to the driving circuits 120R, 120G, and 120B. The display device 100 can therefore determine the time point when each pixel 110 emits light through the gate driving circuit, and determine the brightness of the light emitted by each pixel 110 through the source driving circuit.

[0073] It is worth noting that one group of sub-pixels in pixel 110 includes two LEDs coupled in series. Figure 1 In the embodiment shown, the first group of sub-pixels includes LEDs DR1 and DR2 coupled in series, but the embodiments of the present disclosure are not limited thereto. In different embodiments, multiple groups of sub-pixels may include LEDs coupled in series, and the number of LEDs coupled in series may be more than two. The design of the LEDs coupled in series in the above sub-pixels is to reduce the power consumption of the display device 100. Figure 2A and Figure 2B Further explanation.

[0074] Figure 2A and Figure 2B is a circuit diagram of a sub-pixel display circuit according to some embodiments of the present disclosure. Figure 2A The display circuit does not use series-coupled light-emitting diodes (the display circuit includes only one light-emitting diode D1). Figure 2B The display circuit uses serially coupled light emitting diodes (the display circuit includes serially coupled light emitting diodes D1 and D2). In both embodiments, a group of sub-pixels is driven by a transistor T1, and the transistor T1 and the sub-pixels are coupled between a voltage VDD and a voltage VSS.

[0075] exist Figure 2A In the display circuit, the first end of the transistor T1 receives the voltage VDD, the second end of the transistor T1 is coupled to the light emitting diode D1, the second end of the light emitting diode D1 is coupled to the voltage VDD, and the current flowing through the transistor T1 and the light emitting diode D1 is the current I1. Figure 2B In the display circuit, it is assumed that the light emitting diode D2 and the light emitting diode D1 are the same type of light emitting diodes and have the same resistance and forward bias voltage. Since the two light emitting diodes D1 and D2 are connected in series, Figure 2B The sub-pixel has approximately Figure 2A The resistance of the sub-pixel is twice that of the sub-pixel. Therefore, the current I2 flowing through the transistor T1, the light-emitting diode D1 and the light-emitting diode D2 is about half of the current I1 (the resistance of the transistor T1 is temporarily ignored).

[0076] Regarding the power consumption of the sub-pixel (ie, the light-emitting diode), although the current I2 is half of the current I1, Figure 2B The voltage difference between the two ends of the series-coupled light-emitting diodes D1 and D2 is Figure 2A The LED D1 in the display circuit has twice the voltage difference between its two ends, so the power consumption of the LED in the two circuits is the same (power consumption is current multiplied by voltage). However, regarding the power consumption of transistor T1, since current I2 is half of current I1, Figure 2B The power consumption of transistor T1 in the display circuit will be less than Figure 2A The power consumption of transistor T1 in the circuit is shown. Figure 2A and Figure 2B Both circuits require additional circuits (not shown in the figure) to provide voltage to node N1. The voltage of node N1 will determine the current in the two circuits. Since current I2 is half of current I1, Figure 2B The power consumption of the circuit used to provide the voltage of node N1 in the display circuit will also be relatively high. Figure 2A These circuits show the circuits to be low.

[0077] Based on the above Figure 2A and Figure 2B Compared with the embodiments, using a plurality of light emitting diodes coupled in series will help reduce the power consumption of the circuit, so the embodiments of the present disclosure (such as the aforementioned Figure 1 In the display circuit 100 , at least one group of sub-pixels in each pixel is a plurality of light-emitting diodes coupled in series, thereby improving the power efficiency of the display circuit.

[0078] One embodiment of the present disclosure also provides a semiconductor structure to manufacture a plurality of light emitting diodes coupled in series on the same semiconductor structure. Figure 3 . Figure 3 FIG. 3 is a cross-sectional view of a semiconductor device 300 according to some embodiments of the present disclosure. The semiconductor device 300 includes a buffer layer 330 and two sub-chips 310 and 320 formed on the buffer layer 330. The two sub-chips 310 and 320 may correspond to Figure 1 The light emitting diode DR1 and the light emitting diode DR2 are coupled in series in the embodiment. The sub-chip 310 and the sub-chip 320 are separately and independently disposed on the buffer layer 330. The sub-chip 310 includes a first diffusion layer 312, an active layer 314 and a second diffusion layer 316 from top to bottom, and the sub-chip 320 includes a first diffusion layer 322, an active layer 324 and a second diffusion layer 326 from top to bottom.

[0079] In some embodiments, the first diffusion layer 312 of the sub-chip 310, the first diffusion layer 322 of the sub-chip 320, and the buffer layer 330 are epitaxial layers of the same type, and the second diffusion layer 316 of the sub-chip 310 and the second diffusion layer 326 of the sub-chip 320 are epitaxial layers of another type. Figure 3 In the embodiment of the present invention, the first diffusion layer 312, the first diffusion layer 322 and the buffer layer 330 are P-type epitaxial layers including P-type dopants, and the second diffusion layer 316 and the second diffusion layer 326 are N-type epitaxial layers including N-type dopants.

[0080] In some embodiments, the active layer 314 of the sub-chip 310 and the active layer 324 of the sub-chip 320 have a multiple quantum well (MQW) structure for emitting light when current flows through them.

[0081] exist Figure 3 In an embodiment of the present invention, the semiconductor device 300 may further include an electrode 340, an electrode 350 and a connector CON, wherein the electrode 340, the electrode 350 and the connector CON are conductors (e.g., metals) and can be used to transmit current. The electrode 340 is disposed on the first diffusion layer 312 of the first sub-chip 310, and the electrode 340 is used to receive a relatively high voltage and serve as an anode of the semiconductor device 300. The connector CON is used to electrically couple the second diffusion layer 316 of the first sub-chip 310 to the first diffusion layer 322 of the second sub-chip 320. The electrode 350 is used to couple the second diffusion layer 326 of the second sub-chip 320 to the buffer layer 330, and the electrode 350 is used to receive a relatively low voltage and serve as a cathode of the semiconductor device 300. In an embodiment, the semiconductor device 300 has an isolation layer INS at multiple locations to ensure that the electrode 340, the electrode 350 and the connector CON are correctly coupled to the corresponding structures and to avoid erroneous electrical connections between components.

[0082] In operation, when the electrode 340 receives a relatively high voltage (e.g. Figure 1 voltage VDD in the embodiment) while electrode 350 receives a relatively low voltage (e.g. Figure 1 When the voltage VSS in the embodiment is increased, a current I31 will be generated in the sub-chip 310, flowing from the P-type first diffusion layer 312 through the active layer 314 and then to the N-type second diffusion layer 316. Then, the current I32 will flow from the second diffusion layer 316 of the sub-chip 310 to the first diffusion layer 322 of the sub-chip 320 through the connector CON. Finally, a current I33 will be generated in the sub-chip 320, flowing from the P-type first diffusion layer 322 through the active layer 324 and then to the N-type second diffusion layer 326. Since the currents I31 and I33 flow through the active layer 314 of the sub-chip 310 and the active layer 324 of the sub-chip 320 respectively, the sub-chip 310 and the sub-chip 320 will emit light. Figure 1 The light emitting diodes DR1 and DR2 coupled in series in the embodiment may adopt a structure such as the semiconductor structure 300 , the sub-chips 310 and 320 correspond to the light emitting diodes DR1 and DR2 respectively, and the sub-chips 310 and 320 are coupled in series via the connection element CON.

[0083] It is worth noting that the doped buffer layer 330 (in Figure 3In the embodiment, the buffer layer 330 includes a P-type dopant to prevent leakage current from flowing from the second diffusion layer 316 of the sub-chip 310 to the electrode 350 through the buffer layer 330, or leakage current is formed between the second diffusion layer 326 of the sub-chip 320 and the buffer layer 330. As mentioned above, the second diffusion layer 316 and the second diffusion layer 326 are N-type epitaxial layers, and the buffer layer 330 is a P-type epitaxial layer, so the contact surface between the second diffusion layer 316 and the buffer layer 330 and the contact surface between the second diffusion layer 326 and the buffer layer 330 will form a PN junction. Based on the characteristic that the PN junction will be disconnected when receiving a reverse bias, the contact surface between the second diffusion layer 316 and the buffer layer 330 and the contact surface between the second diffusion layer 326 and the buffer layer 330 can be used as a diode. In detail, since the sub-chip 310 receives a relatively high voltage through the electrode 340, and the buffer layer 330 receives a relatively low voltage through the electrode 350, the N-type second diffusion layer 316 will have a higher voltage than the P-type buffer layer 330, so that a reverse bias of the PN junction will be formed. At this time, the area near the contact surface of the second diffusion layer 316 and the buffer layer 330 will form a depletion region and only a few carriers will drift. Therefore, a short circuit will be formed between the second diffusion layer 316 and the buffer layer 330, and it can be ensured that no current will flow from the second diffusion layer 316 to the buffer layer 330. In addition, the PN junction formed by the second diffusion layer 326 and the buffer layer 330 receives the same voltage through the electrode 350, so no current will be generated between the two. In different examples, the buffer layer may be undoped or only lightly doped, and leakage current may occur in the buffer layer, which affects the luminous efficiency of the sub-chip.

[0084] exist Figure 3 In the embodiment of the present invention, the electrode 350 is extended to the first diffusion layer 322 of the second sub-chip 320 and has substantially the same height as the electrode 340 disposed on the first diffusion layer 312 of the first sub-chip 310. This embodiment is conducive to mass transfer of the semiconductor device 300. In some embodiments, the interval between the sub-chip 310 and the sub-chip 320 is greater than or equal to about 1 micron, and the lengths of the sub-chip 310 and the sub-chip 320 are both less than or equal to about 100 microns.

[0085] In some embodiments, more than two sub-chips may be formed on the same semiconductor device, and two corresponding sub-chips may be coupled in series through a plurality of connectors, for example, Figure 3 In the semiconductor structure 300, a sub-chip having a similar diffusion layer and active layer structure is further arranged to the right of the sub-chip 320 and connected through another connection member CON, and the electrode 350 is changed to be arranged at the rightmost part of the semiconductor structure 300.

[0086] Please refer to Figure 4 . Figure 4 4 is a cross-sectional view of a semiconductor device 400 according to some embodiments of the present disclosure. The semiconductor device 400 has a structure similar to that of the semiconductor device 300, but the structure in the semiconductor device 400 includes different dopants and its electrodes receive the same Figure 3 Embodiments of different voltages. Figure 4 As shown, the semiconductor device 400 includes a buffer layer 430 and two sub-chips 410 and 420 formed on the buffer layer 430. The sub-chip 410 includes a first diffusion layer 412, an active layer 414 and a second diffusion layer 416, and the sub-chip 420 includes a first diffusion layer 422, an active layer 424 and a second diffusion layer 426. The electrode 440 is disposed on the first diffusion layer 412 of the sub-chip 410, and the connection member CON is used to couple the second diffusion layer 416 of the sub-chip 410 and the first diffusion layer 422 of the sub-chip 420.

[0087] and Figure 3 Different from the semiconductor device 300 of the embodiment, in the semiconductor device 400, the first diffusion layer 412 of the sub-chip 410, the first diffusion layer 422 of the sub-chip 420 and the buffer layer 430 are N-type epitaxial layers containing N-type dopants, and the second diffusion layer 416 of the sub-chip 410 and the second diffusion layer 426 of the sub-chip 420 are P-type epitaxial layers containing P-type dopants.

[0088] In addition, the electrode 440 is used to receive a relatively low voltage (eg Figure 1 The electrode 450 is used to receive a relatively high voltage (eg, Figure 1 In operation, since the second diffusion layer 426 of the sub-chip 420 receives a relatively high voltage through the electrode 450, a current I41 will flow from the second diffusion layer 426 through the active layer 424 to the first diffusion layer 422. Then, a current I42 will flow from the first diffusion layer 422 of the sub-chip 420 to the second diffusion layer 416 of the sub-chip 410 through the connector CON. Finally, a current I43 will flow from the second diffusion layer 416 through the active layer 414 to the first diffusion layer 412. The sub-chip 420 and the sub-chip 410 will therefore emit light.

[0089] The doped buffer layer 430 (in Figure 4In the embodiment, the buffer layer 430 includes N-type dopants to prevent leakage current from being generated in the semiconductor device 400. The contact surface between the P-type second diffusion layer 416 and the N-type buffer layer 430 and the contact surface between the P-type second diffusion layer 426 and the N-type buffer layer 430 will form a PN junction. Therefore, when the buffer layer 430 has a higher voltage than the second diffusion layer 416 or the second diffusion layer 426, the PN junction is reverse biased, so an open circuit will be formed. In other words, since the buffer layer 430 receives a relatively high voltage through the electrode 450, and the sub-chip 410 receives a relatively low voltage through the electrode 440, the PN junction formed by the second diffusion layer 416 and the buffer layer 430 is reverse biased at this time, so that it can be ensured that no current flows from the buffer layer 430 to the second diffusion layer 416. In addition, since the PN junction formed by the buffer layer 430 and the second diffusion layer 426 receives the same voltage through the electrode 450, no leakage current will be generated between the two.

[0090] In some embodiments, more than two sub-chips may be formed on the same semiconductor device, and two corresponding sub-chips may be coupled in series through a plurality of connectors, for example, Figure 4 In the semiconductor structure 400, a sub-chip with a similar structure is further arranged to the left of the sub-chip 410 and connected to it through another connection member CON, and the electrode 440 is changed to be arranged at the leftmost part of the semiconductor structure 400.

[0091] In summary, through Figure 3 and Figure 4 The semiconductor structure shown will enable Figure 1 The LEDs in the display circuit 100 are coupled in series, and such a structure can avoid leakage current generation to ensure the light emitting efficiency of the LED sub-chip.

[0092] Please refer to Figure 1 .because Figure 1The LEDs DR1 and DR2 of the first group of sub-pixels in the pixel 110 are coupled in series, and require a larger voltage to turn on and emit light than the LED DG or the LED DB. Therefore, if the same voltage VDD is provided to all three groups of sub-pixels, additional power consumption may be caused. For example, assuming that the LEDs DR1 and DR2 are both red LEDs and their forward bias voltage is 2.5 volts (V), and the LEDs DG and DB are respectively green LEDs and blue LEDs and their forward bias voltages are both 3V. If the voltage required by the driving circuits 120R, 120G, and 120B is not considered for the time being, and the three groups of sub-pixels are driven by a voltage VDD of 5V, although it can ensure that the LEDs in the three groups of sub-pixels can emit light, the LEDs DG and DB actually only need a voltage of 3V to emit light, thereby generating unnecessary power consumption. Based on this, an embodiment of the present disclosure also proposes a display circuit including more than three groups of voltages to further improve the power efficiency of the display circuit.

[0093] Please refer to Figure 5A , Figure 5A is a schematic diagram of a pixel 510A according to some embodiments of the present disclosure. Figure 1 The pixel 110 in FIG. 5 can be changed to adopt the design of the pixel 510A. Figure 5A As shown, the pixel 510A includes driving circuits 120R, 120G, 120B and three groups of sub-pixels (i.e., a first group of sub-pixels formed by light-emitting diodes DR1 and DR2, a second group of sub-pixels formed by light-emitting diodes DG, and a third group of sub-pixels formed by light-emitting diodes DB). Figure 1 In different embodiments, the first terminal of the driving circuit 120R receives a voltage VDD2 , and the first terminals of the driving circuits 120G and 120B receive a voltage VDD1 , and the voltage VDD2 is different from the voltage VDD1 .

[0094] In one embodiment, the LEDs DR1 and DR2 are both red LEDs and their respective forward bias voltages are both 2.5V, the LEDs DG and DB are respectively green LEDs and blue LEDs and their forward bias voltages are both 3V, so the voltage VDD1 can have a voltage smaller than the voltage VDD2 (for example, the voltage VDD2 is 5V, the voltage VSS is 0V, and the voltage VDD1 is 3V), thereby enabling all the LEDs to emit light and saving power consumption.

[0095] In some embodiments, voltage VDD2 is provided by a first reference voltage terminal in the display circuit, voltage VSS is provided by a second reference voltage terminal in the display circuit, voltage VDD1 is provided by a third reference voltage terminal in the display circuit, and voltages VDD2, VDD1, and VSS are different from each other. Figure 5AIn the embodiment, voltages VDD2 and VDD1 are both greater than voltage VSS, and voltage VDD2 is greater than voltage VDD1. In addition, the series-coupled light-emitting diodes DR1 and DR2 are coupled between the first reference voltage terminal and the second reference voltage terminal, and the light-emitting diode DG is coupled between the third reference voltage terminal and the second reference voltage terminal.

[0096] In some embodiments, the first group of sub-pixels may include more LEDs in addition to LEDs DR1 and DR2. In different embodiments, the first group of sub-pixels of pixel 510A may include only one red LED, while the second group of sub-pixels or the third group of sub-pixels include multiple green LEDs or blue LEDs coupled in series.

[0097] Please refer to Figure 5B , Figure 5B is a schematic diagram of a pixel 510B according to some embodiments of the present disclosure. Figure 1 The pixel 110 in the embodiment may be changed to adopt the design of the pixel 510B. The pixel 510B has the same Figure 1 The structure of the pixel 110 is similar to that of the pixel 110, but Figure 1 In a different embodiment, the second end of the light emitting diode DR2 receives the voltage VSS2 , and the second ends of the light emitting diode DG and the light emitting diode DB receive the voltage VSS1 , and the voltage VSS2 is different from the voltage VSS1 .

[0098] In one embodiment, the LEDs DR1 and DR2 are both red LEDs and their respective forward bias voltages are both 2.5V, the LEDs DG and DB are respectively green LEDs and blue LEDs and their forward bias voltages are both 3V, the voltage VDD is 5V, the voltage VSS2 is 0V, and the voltage VSS1 is 2V.

[0099] In some embodiments, the voltage VDD is provided by a first reference voltage terminal in the display circuit, the voltage VSS2 is provided by a second reference voltage terminal in the display circuit, and the voltage VSS1 is provided by a third reference voltage terminal in the display circuit. The voltages VDD, VSS2, and VSS1 are different from each other. Figure 5B In the embodiment, voltages VSS2 and VSS1 are both lower than voltage VDD, and voltage VSS2 is lower than voltage VSS1. In addition, light emitting diodes DR1 and DR2 coupled in series are coupled between a first reference voltage terminal and a second reference voltage terminal, and light emitting diodes DG and DB are coupled between a first reference voltage terminal and a third reference voltage terminal.

[0100] In some embodiments, when Figure 5A Pixel 510A and Figure 5BWhen the light emitting diode in the pixel 510B is operating in the light emitting period and emits light, the current density of the light emitting diode is greater than 500 mA / cm 2 (mA / cm 2 ) to ensure operation in a high luminous efficiency range.

[0101] In some embodiments, a pixel may include multiple groups of sub-pixels having light-emitting diodes coupled in series to better save power consumption of the display circuit. Fig. 6A , Fig. 6A FIG. 6 is a schematic diagram of a pixel 610A according to some embodiments of the present disclosure. The pixel 610A has Figure 5A The structure of the pixel 510A is similar to that of the pixel 510A, and also includes driving circuits 120R, 120G, and 120B to drive corresponding different groups of sub-pixels. Figure 5A Different from the pixel 510A, the third group of sub-pixels in the pixel 610A includes light-emitting diodes DB1 and DB2 coupled in series, and the first terminal of the driving circuit 120B receives the voltage VDD3 instead.

[0102] In one embodiment, the LEDs DR1 and DR2 are both red LEDs and their respective forward bias voltages are both 2.5 V, the LEDs DG and DB are respectively green LEDs and blue LEDs and their forward bias voltages are both 3 V, the voltage VDD2 is 5 V, the voltage VDD1 is 3 V, the voltage VDD3 is 6 V, and the voltage VSS is 0 V. In other words, different voltages are provided for different groups of sub-pixels to avoid extra power consumption.

[0103] In some embodiments, voltage VDD2 is provided by a first reference voltage terminal in the display circuit, voltage VSS is provided by a second reference voltage terminal in the display circuit, voltage VDD1 is provided by a third reference voltage terminal in the display circuit, voltage VDD3 is provided by a fourth reference voltage terminal in the display circuit, and voltages VDD2, VDD1, VSS, and VDD3 are different from each other.

[0104] Please refer to Figure 6B , Figure 6B FIG. 6 is a schematic diagram of a pixel 610B according to some embodiments of the present disclosure. The pixel 610B has Figure 5B The structure of the pixel 510B is similar to that of the pixel 510B, and also includes driving circuits 120R, 120G, and 120B to drive corresponding different groups of sub-pixels. Figure 5B Different from the pixel 510B, the third group of sub-pixels in the pixel 610B includes LEDs DB1 and DB2 coupled in series, and the second end of the LED DB2 receives the voltage VSS3.

[0105] In one embodiment, the LEDs DR1 and DR2 are both red LEDs and their respective forward bias voltages are both 2.5V, the LEDs DG and DB are respectively green LEDs and blue LEDs and their forward bias voltages are both 3V, the voltage VDD is 6V, the voltage VSS2 is 1V, the voltage VSS1 is 3V, and the voltage VSS3 is 0V.

[0106] In some embodiments, voltage VDD is provided by a first reference voltage terminal in the display circuit, voltage VSS2 is provided by a second reference voltage terminal in the display circuit, voltage VSS1 is provided by a third reference voltage terminal in the display circuit, and voltage VSS3 is provided by a fourth reference voltage terminal in the display circuit, and voltages VDD, VSS2, VSS1, and VSS3 are different from each other.

[0107] In some embodiments, Figure 5A , Figure 5B , Fig. 6A and Figure 6B In the embodiment, the sub-pixel having series-coupled light emitting diodes may have the following configuration: Figure 3 or Figure 4 In the structure of the embodiment, a plurality of sub-chips are coupled in series through connectors to form a same structure, and leakage current is avoided by doping in a specific layer to ensure power efficiency.

[0108] In summary, Figure 5A , Figure 5B , Fig. 6A and Figure 6B The embodiment provides multiple sets of voltages to provide different voltages for different sub-pixels, so as to further reduce the Figure 1 Displays the power consumption of the circuit.

[0109] Although the present disclosure has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make various changes and modifications without departing from the concept and scope of the present disclosure. The scope of protection of the present disclosure shall be determined by the claims.

Claims

1. A semiconductor device comprising: a buffer layer; A first sub-chip and a second sub-chip are separately disposed on the buffer layer, and each of the first sub-chip and the second sub-chip comprises: a first diffusion layer; an active layer; and a second diffusion layer; in, The first diffusion layer, the active layer and the second diffusion layer are sequentially disposed on the buffer layer from top to bottom, the first diffusion layer and the buffer layer are a first type epitaxial layer, and the second diffusion layer is a second type epitaxial layer; and a connecting member, for electrically coupling the second diffusion layer of the first sub-chip to the first diffusion layer of the second sub-chip, The semiconductor device further comprises: a first electrode, disposed on the first diffusion layer of the first sub-chip and used for receiving a first reference voltage; and A second electrode is used to couple the second diffusion layer of the second sub-chip to the buffer layer and receive a second reference voltage.

2. The semiconductor device according to claim 1, wherein: The second electrode is extended to the first diffusion layer of the second sub-chip and has substantially the same height as the first electrode disposed on the first sub-chip.

3. The semiconductor device according to claim 1, wherein: The first type epitaxial layer is a P-type epitaxial layer, the second type epitaxial layer is an N-type epitaxial layer, and the first reference voltage is greater than the second reference voltage; or The first type epitaxial layer is an N-type epitaxial layer, the second type epitaxial layer is a P-type epitaxial layer, and the second reference voltage is greater than the first reference voltage.

4. The semiconductor device according to claim 1, wherein: The spacing between the first sub-chip and the second sub-chip is greater than or equal to about 1 micron, and the length of each of the first sub-chip and the second sub-chip is less than or equal to about 100 microns.

5. A display device, comprising: A plurality of pixels, each of the pixels comprises a plurality of groups of sub-pixels, a first group of sub-pixels in the plurality of groups of sub-pixels comprises: At least two first light-emitting elements, the at least two first light-emitting elements are coupled to each other in series; A first reference voltage terminal, used for providing a first reference voltage to the pixels; A second reference voltage terminal, used for providing a second reference voltage to the pixels; as well as a third reference voltage terminal, used for providing a third reference voltage to the pixels; Wherein, the first reference voltage, the second reference voltage and the third reference voltage are different from each other; The first light-emitting elements in the first group of sub-pixels coupled in series are coupled between the first reference voltage terminal and the second reference voltage terminal, and a second group of sub-pixels in the plurality of groups of sub-pixels is coupled to the third reference voltage terminal. in: The first light-emitting elements coupled in series include: a buffer layer; A first sub-chip and a second sub-chip are separately disposed on the buffer layer, and each of the first sub-chip and the second sub-chip comprises: a first diffusion layer; an active layer; and a second diffusion layer; The first diffusion layer, the active layer and the second diffusion layer are sequentially arranged on the buffer layer from top to bottom, the first diffusion layer and the buffer layer are a first type epitaxial layer, and the second diffusion layer is a second type epitaxial layer; and a connecting member, for electrically coupling the second diffusion layer of the first sub-chip to the first diffusion layer of the second sub-chip, The first light emitting element further comprises: a first electrode, disposed on the first diffusion layer of the first sub-chip and used for receiving a first reference voltage; and A second electrode is used to couple the second diffusion layer of the second sub-chip to the buffer layer and receive a second reference voltage.

6. The display device according to claim 5, wherein: The first reference voltage and the third reference voltage are both greater than the second reference voltage; or The second reference voltage and the third reference voltage are both lower than the first reference voltage.

7. The display device according to claim 5, wherein: When the light emitting elements are operated in a light emitting period, the current density of the light emitting elements is greater than 500 mA / cm 2 .

8. The display device according to claim 5, further comprising: a fourth reference voltage terminal, for providing a fourth reference voltage to the pixels, the fourth reference voltage being different from the first reference voltage, the second reference voltage and the third reference voltage; in, A third group of sub-pixels in the plurality of groups of sub-pixels comprises: Two second light-emitting elements, the second light-emitting elements are coupled to each other in series; The third group of sub-pixels is coupled to the fourth reference voltage terminal.

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