Bipolar transistor and high frequency power amplifier module

Abstract

A bipolar transistor having a structure capable of thinning a base layer to achieve high speed is provided. A collector layer, a base layer, and an emitter layer are formed on a substrate composed of a compound semiconductor. The emitter layer is disposed inside compared with the edge of the base layer in plan view. A base electrode is disposed on a region of a part of the emitter layer and the base layer to form a path from the inside of the emitter layer to the outside of the base layer in plan view. An insulating film is disposed between a part of the base layer not overlapping the emitter layer and the base electrode. An alloy layer penetrates the emitter layer from the base electrode in the thickness direction and reaches the base layer. The alloy layer contains a part of the constituent elements of the base electrode and the constituent elements of the emitter layer and the above base layer.

Description

[0001] This application is a divisional application of the application with the application number 201811024684.3, the application date of September 4, 2018, and the invention patent application name of "Bipolar Transistor and High Frequency Power Amplifier Module". TECHNICAL FIELD

[0002] The present application relates to a bipolar transistor and a high frequency power amplifier module. BACKGROUND

[0003] Now, a mobile communication system typified by a mobile phone terminal is moving from the fourth generation (4G) to the fifth generation (5G). A higher frequency band is used in the fifth generation mobile communication system compared to the fourth generation mobile communication system. Therefore, further high speed of semiconductor devices is desired.

[0004] One of the main components of a mobile phone terminal is a high frequency power amplifier module, which generally uses a compound semiconductor device. And, as a compound semiconductor device, a heterojunction bipolar transistor (HBT) having excellent characteristics such as high linearity operation, high efficiency operation, high current density operation, etc. is generally used.

[0005] A HBT capable of high speed operation with excellent process controllability is disclosed in the following patent document 1. The HBT has a sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter cap layer formed in this order on one side of a semi-insulating GaAs substrate in a prescribed shape. The inner end portion of the base electrode is overlapped on the periphery of the emitter layer, and the base electrode is electrically connected to the base layer through an alloy layer based on alloying of the emitter layer under the base electrode. The emitter layer is selectively formed on the base layer, the base electrode extends from the periphery portion of the emitter layer to the base layer, and the alloy layer extends to the middle depth of the base layer. The edge of the base layer is located inside compared to the outer edge of the base electrode.

[0006] By locating the edge of the base layer inside compared to the outer edge of the base electrode, the junction area between the base and collector is smaller compared to the structure in which the edge of the base layer is located outside the outer edge of the base electrode. As a result, the high frequency feedback capacitance (base-collector capacitance) is reduced. As a result, high speed of the HBT can be achieved.

[0007] Patent Document 1: Japanese Patent Application Publication No. 2000-260783

[0008] In order to achieve further high speed of the bipolar transistor such as HBT, it is effective to shorten the travel time of electrons within the base layer by thinning the base layer. However, in the structure disclosed in the patent document 1, it is known that it is difficult to make the base layer thinner than a certain lower limit value. SUMMARY

[0009] The present application has an object to provide a bipolar transistor having a structure capable of thinning a base layer to achieve high speed. The present application has another object to provide a high-frequency power amplifier module having the bipolar transistor.

[0010] The bipolar transistor of the first aspect of the present application has:

[0011] a collector layer formed on a substrate composed of a compound semiconductor;

[0012] a base layer formed on the collector layer;

[0013] an emitter layer formed on the base layer and disposed inside compared with an edge of the base layer in plan view;

[0014] a base electrode disposed on a region of the emitter layer and a part of the base layer and formed to reach from inside of the emitter layer to outside of the base layer in plan view;

[0015] an insulating film disposed between the base electrode and a part of the base layer not overlapping with the emitter layer in the base layer; and

[0016] an alloy layer penetrating the emitter layer from the base electrode in a thickness direction and reaching the base layer and containing a constituent element of the base electrode and constituent elements of the emitter layer and the base layer.

[0017] The insulating film disposed between the base layer and the base electrode prevents alloying based on a reaction of the base electrode and the base layer. Therefore, a constituent element of the base electrode is prevented from directly diffusing to the base layer and diffusing to the base layer via the emitter layer. As a result, an invasion depth of the alloy layer to the base layer becomes shallow, so the base layer can be thinned. By thinning the base layer, high speed can be achieved.

[0018] The bipolar transistor of the second aspect of the present application has, in addition to the constitution of the bipolar transistor of the first aspect, a feature that a side surface of a part of an upper side of the collector layer is continuous with a side surface of the base layer, and a side surface of a remaining part of a lower side is located outside compared with the side surface of the base layer.

[0019] The structure described in the first aspect that the base electrode reaches outside compared with the edge of the base layer in plan view can be achieved, for example, by side etching the base layer with the base electrode as an etching mask. When the base layer is side etched, a part of the upper side of the collector layer is etched and removed. The remaining part of the lower side of the collector layer can be etched independently of the process of side etching. Thereby, the amount of side etching can be set without depending on the thickness of the collector layer.

[0020] The bipolar transistor of the third aspect of the present application has the feature that the collector layer contains, at an intermediate position in the thickness direction, an intermediate collector layer composed of a semiconductor material different in etching characteristics from the other semiconductor materials, and the side surface of the collector layer on the upper side is continuous with the side surface of the base layer, and the side surface of the collector layer on the lower side is located outward of the side surface of the base layer, compared with the intermediate collector layer.

[0021] When the base electrode is used as an etching mask to etch the base layer and the collector layer, etching in the depth direction can be stopped at the intermediate collector layer. Thereafter, by side surface etching the base layer and the collector layer on the upper side compared with the intermediate collector layer, the amount of side surface etching can be controlled independently of the amount of etching in the depth direction.

[0022] The bipolar transistor of the fourth aspect of the present application has the feature that a sub-collector layer is arranged between the substrate and the collector layer and becomes a path of current flowing into and out of the collector layer, in addition to the constitution of the bipolar transistor of the first to third aspects.

[0023] The sub-collector layer contains a first sub-collector layer arranged on the substrate, and a second sub-collector layer arranged on the first sub-collector layer, and the etching characteristics of the second sub-collector layer are different from the etching characteristics of the portion of the collector layer in contact with the second sub-collector layer.

[0024] When the collector layer is etched, the second sub-collector layer can be used as an etching stopper. Thus, process controllability is improved.

[0025] The bipolar transistor of the fifth aspect of the present application has the feature that a contact layer is arranged on a portion of the area of the emitter layer and becomes a path of current flowing into and out of the emitter layer, in addition to the constitution of the bipolar transistor of the first to fourth aspects.

[0026] The contact layer is arranged on a portion of the area of the emitter layer and becomes a path of current flowing into and out of the emitter layer, in addition to the constitution of the bipolar transistor of the first to fourth aspects.

[0027] The emitter electrode is arranged on the contact layer and protrudes outward of the edge of the contact layer,

[0028] The tip of the protruding portion of the emitter electrode coincides with the edge of the base electrode when viewed from above.

[0029] For example, when the base electrode is vapor-deposited, the emitter electrode can be formed self-matching with the base layer.

[0030] The bipolar transistor of the sixth aspect of the present application has the feature that the emitter electrode is arranged on the contact layer and protrudes outward of the edge of the contact layer, in addition to the constitution of the bipolar transistor of the fifth aspect.

[0031] The contact layer is composed of a plurality of semiconductor layers arranged side by side along the in-plane direction on the upper surface of the emitter layer,

[0032] The base electrode includes a portion arranged between the plurality of semiconductor layers constituting the emitter layer.

[0033] The plurality of semiconductor layers constituting the contact layer and the base electrodes on both sides thereof function as one bipolar transistor (basic bipolar transistor). By arranging the plurality of semiconductor layers constituting the contact layer and arranging the base electrode between the semiconductor layers, a circuit in which a plurality of basic bipolar transistors are connected in parallel can be virtually obtained.

[0034] The bipolar transistor of the seventh aspect of the present application has the following feature in addition to the configuration of the bipolar transistor of the first to fourth aspects, i.e., a plurality of emitter electrodes connected to the emitter layer and arranged side by side along the in-plane direction,

[0035] The base electrode includes a portion arranged between the emitter electrodes.

[0036] Each of the emitter electrodes and the base electrodes on both sides thereof functions as one bipolar transistor (basic bipolar transistor). By arranging the base electrode between each of the plurality of emitter electrodes, a circuit in which a plurality of basic bipolar transistors are connected in parallel can be virtually obtained.

[0037] The bipolar transistor of the eighth aspect of the present application has the following feature in addition to the configuration of the bipolar transistor of the first to seventh aspects, i.e., the substrate, the collector layer, and the base layer include a layer composed of GaAs,

[0038] The emitter layer is formed of InGaP,

[0039] The insulating film includes a layer composed of SiN,

[0040] A constituent element of a portion of the base electrode included in the alloy layer is Pt.

[0041] Pt reacts with InGaP and Pt reacts with GaAs, thereby forming the alloy layer. The insulating film composed of SiN prevents the base electrode from reacting with the base layer to form the alloy layer in a region in which the emitter layer is not arranged.

[0042] The high-frequency power amplifier module of the ninth aspect of the present application has:

[0043] An IC for amplification including a bipolar transistor; and

[0044] A control IC that controls the operation of the bipolar transistor,

[0045] The above-mentioned IC for amplification has:

[0046] a collector layer formed on a substrate composed of a compound semiconductor;

[0047] a base layer formed on the collector layer;

[0048] an emitter layer formed on the base layer and disposed inside compared with an edge of the base layer in plan view;

[0049] a base electrode disposed on a region of the emitter layer and a part of the base layer and formed to reach from inside of the emitter layer to outside of the base layer in plan view;

[0050] an insulating film disposed between the base electrode and a part of the base layer not overlapping with the emitter layer; and

[0051] an alloy layer penetrating the emitter layer from the base electrode in a thickness direction and reaching the base layer and containing a constituent element of the base electrode and constituent elements of the emitter layer and the base layer.

[0052] Like the bipolar transistor of the first viewpoint, the high speed of the bipolar transistor can be achieved. As a result, the high speed of the high frequency power amplifier module can be achieved.

[0053] The insulating film disposed between the base layer and the base electrode prevents alloying based on the reaction of the base electrode and the base layer. Therefore, the constituent element of the base electrode is prevented from directly diffusing to the base layer and diffusing to the base layer via the emitter layer. As a result, the invasion depth of the alloy layer to the base layer becomes shallow, so the base layer can be thinned. By thinning the base layer, the high speed of the bipolar transistor can be achieved. By using the bipolar transistor, the high speed of the high frequency power amplifier module can be achieved. BRIEF DESCRIPTION OF DRAWINGS

[0054] FIG. 1A is a plan view of an electrode to which a collector, a base, and an emitter of an HBT of the first embodiment are connected, and a wiring disposed thereon, FIG. 1B is FIG. 1A is a sectional view of the HBT at a dot-dash line 1B-1B of

[0055] FIG. 2A and FIG. 2B are respectively FIG. 1A are respectively sectional views of the HBT at a dot-dash line 2A-2A and a dot-dash line 2B-2B of

[0056] FIG. 3A and FIG. 3B are respectively partial sectional views of the HBT of the first embodiment and the reference example.

[0057] FIG. 4A , FIG. 4B and FIG. 4C is a cross-sectional view of the HBT of the first embodiment at a manufacturing intermediate stage.

[0058] FIG. 5A , FIG. 5B and FIG. 5C is a cross-sectional view of the HBT of the first embodiment at a manufacturing intermediate stage.

[0059] FIG. 6A , FIG. 6B and FIG. 6C is a cross-sectional view of the HBT of the first embodiment at a manufacturing intermediate stage.

[0060] FIG. 7A , FIG. 7B and FIG. 7C is a cross-sectional view of the HBT of the first embodiment at a manufacturing intermediate stage.

[0061] FIG. 8A , FIG. 8B and FIG. 8C is a cross-sectional view of the HBT of the first embodiment at a manufacturing intermediate stage.

[0062] FIG. 9A , FIG. 9B and FIG. 9C is a cross-sectional view of the HBT of the first embodiment at a manufacturing intermediate stage.

[0063] FIG. 10A and FIG. 10B is a cross-sectional view of the HBT of the second embodiment, FIG. 10C is a cross-sectional view of the base electrode of the HBT of the second embodiment and its vicinity.

[0064] FIG. 11A and FIG. 11B is a cross-sectional view of the HBT of the second embodiment at a manufacturing intermediate stage.

[0065] FIG. 12 is a cross-sectional view of the HBT of the third embodiment.

[0066] FIG. 13A , FIG. 13B and FIG. 13C is a cross-sectional view of the HBT of the third embodiment at a manufacturing intermediate stage.

[0067] FIG. 14A is a cross-sectional view of the HBT of the fourth embodiment, FIG. 14B is a cross-sectional view of the HBT of the fourth embodiment at a manufacturing intermediate stage.

[0068] FIG. 15is a cross-sectional view of the HBT of the fifth embodiment.

[0069] FIG. 16A , FIG. 16B and FIG. 16C are cross-sectional views of the HBT of the fifth embodiment at an intermediate stage of manufacture.

[0070] FIG. 17A is a plan view of the electrodes to which the collector, the base and the emitter of the HBT of the sixth embodiment are connected, and the wiring provided thereon, FIG. 17B is FIG. 17A a cross-sectional view at the dotted line 17B-17B of

[0071] FIG. 18A and FIG. 18B are cross-sectional views of the HBT at the dotted line 18A-18A and the dotted line 18B-18B, respectively, of FIG. 17A

[0072] FIG. 19A , FIG. 19B and FIG. 19C are cross-sectional views of the HBT of the sixth embodiment at an intermediate stage of manufacture.

[0073] FIG. 20A , FIG. 20B and FIG. 20C are cross-sectional views of the HBT of the sixth embodiment at an intermediate stage of manufacture.

[0074] FIG. 21A , FIG. 21B and FIG. 21C are cross-sectional views of the HBT of the sixth embodiment at an intermediate stage of manufacture.

[0075] FIG. 22 is a cross-sectional view of the HBT of the seventh embodiment.

[0076] FIG. 23 is a cross-sectional view of the HBT of the eighth embodiment.

[0077] FIG. 24 is a cross-sectional view of the HBT of the ninth embodiment.

[0078] FIG. 25 is a plan view of the electrodes to which the collector, the base and the emitter of the HBT of the tenth embodiment are connected, and the wiring provided thereon.

[0079] FIG. 26 is FIG. 25 a cross-sectional view at the dotted line 26-26 of

[0080] FIG. 27 is an equivalent circuit diagram of the HBT of the tenth embodiment.

[0081] ​FIG. 28 is a plan view of the collector, base and emitter electrodes of the HBT of the eleventh embodiment, and the wiring provided thereon.

[0082] FIG. 29 is a sectional view taken along the dotted line 29-29 of FIG. 28

[0083] FIG. 30A is a block diagram of a high-frequency power amplifier module of the twelfth embodiment, FIG. 30B is an equivalent circuit diagram of the output stage HBT.

[0084] Reference Signs List

[0085] 50...substrate, 51...sub-collector layer, 51A...first sub-collector layer, 51B...second sub-collector layer, 52...collector layer, 52A...lower collector layer, 52B...upper collector layer, 52C...intermediate collector layer, 53...base layer, 54...emitter layer, 55...first contact layer, 56...second contact layer, 57...high platform structure, 61...collector electrode alloy layer, 62...insulating film, 62a...opening portion, 65...base electrode alloy layer, 71, 72...interlayer insulating film, 72a, 72b...opening portion, 73...interlayer insulating film, 73a...opening portion, 74...interlayer insulating film, 74a...opening portion, 76...planarization insulating film, 76a...opening portion, 80...HBT, 81...elementary HBT, 90, 91, 92...photoresist film, 100...high-frequency power amplifier module, 101...high-frequency input terminal, 102...high-frequency output terminal, 103...control terminal, 104, 105...power supply terminal, 110...elementary HBT, 112...bias terminal, 114...collector terminal, 120...output stage HBT, 122...bias terminal, 124...collector terminal, 125...elementary HBT, 126...ballast resistor, 127...DC cut capacitor, 130...amplification IC, 131, 132, 133...matching circuit, 135, 136...inductor, 140...control IC, 150...mounting substrate, B0...base electrode, Bl...base wiring of the first layer, C0...collector electrode, Cl...collector wiring of the first layer, C2...collector wiring of the second layer, E0...emitter electrode, E0a...lower layer of the emitter electrode, E0b...upper layer of the emitter electrode, El...emitter wiring of the first layer, E2...emitter wiring of the second layer. DETAILED DESCRIPTION

[0086] [First Embodiment]

[0087] With reference to the drawings, FIGS. 1A-3B a heterojunction bipolar transistor (HBT) of the first embodiment will be described. ​

[0088] FIG. 1A This is a top view of the collector, base, and emitter electrodes of the HBT of the first embodiment, and the wiring disposed thereon. The base electrode B0 is disposed on both sides of the emitter electrode E0, and the base electrodes B0 on ​​both sides of the emitter electrode E0 are located to the side of the emitter electrode E0 (in...). FIG. 1A The base electrode B0 is continuous with each other from three directions (in the middle and above). That is, the base electrode B0 has three directions (in the middle and above). FIG. 1A The emitter electrode E0 is a U-shaped (horseshoe-shaped) planar shape that surrounds it from the left, right, and top. Collector electrodes C0 are disposed on both sides of the emitter electrode E0 via the base electrode B0. That is, the base electrode B0 is disposed between the emitter electrode E0 and the collector electrode C0.

[0089] The emitter wiring E1 of the first layer overlaps with and is connected to the emitter electrode E0. The emitter wiring E2 of the second layer extends in a direction in which the emitter electrode E0, the base electrode B0, and the collector electrode C0 are arranged side by side (hereinafter referred to as the electrode arrangement direction), and partially overlaps with the base electrode B0 and the collector electrode C0. The emitter wiring E2 of the second layer is connected to the emitter wiring E1 of the first layer at the position where it overlaps with the emitter wiring E1 of the first layer. The emitter electrode E0 and the pair of collector electrodes C0 are each rectangular in shape, with their long sides orthogonal to the electrode arrangement direction.

[0090] A pair of first-layer collector wirings C1 partially overlap with a pair of collector electrodes C0, and are led out in a direction orthogonal to the electrode arrangement direction to a region that does not overlap with the second-layer emitter wiring E2. The first-layer collector wirings C1 are connected to the collector electrodes C0 at the locations where they overlap. To the side of the second-layer emitter wiring E2 (in...) FIG. 1A The lower side (in the middle) is provided with a second layer of collector wiring C2, which is connected to a pair of first layer collector wiring C1.

[0091] The base wiring B1 of the first layer is positioned on the opposite side of the collector wiring C2 of the second layer when viewed from the emitter wiring E2 of the second layer, and extends along the electrode arrangement direction. The base wiring B1 of the first layer partially overlaps with the base electrode B0, and is connected to the base electrode B0 at the overlapping position.

[0092] FIG. 1B yes FIG. 1AA cross-sectional view of the HBT at the dot-dash line 1B-1B. A sub-collector layer 51 is provided on a substrate 50. A collector layer 52 and a base layer 53 are sequentially stacked on a region of a part of the sub-collector layer 51. An emitter layer 54 is provided on the base layer 53. The emitter layer 54 is provided inside compared with an edge of the base layer 53 in plan view. Thus, there is a region where the emitter layer 54 is not provided from the edge of the base layer 53 toward the inside.

[0093] A first contact layer 55 and a second contact layer 56 are sequentially stacked on a region of a part of the emitter layer 54. The first contact layer 55 and the second contact layer 56 are provided inside compared with an edge of the emitter layer 54 in plan view.

[0094] As the substrate 50, for example, semi-insulating GaAs is used. The sub-collector layer 51 is formed of n-type GaAs having a doping concentration of 5 x 1018cm-3 of Si, for example, and has a film thickness of 600 nm. The collector layer 52 is formed of n-type GaAs having a doping concentration of 1 x 1018cm-3 of Si, for example, and has a film thickness of 1000 nm. The base layer 53 is formed of p-type GaAs having a doping concentration of 5 x 1018cm-3 of C, for example, and has a film thickness of 50 nm. The emitter layer 54 is formed of n-type InGaP having a mole ratio of 0.48 of InP and a doping concentration of 4 x 1018cm-3 of Si, for example, and has a film thickness of 35 nm. The first contact layer 55 is formed of n-type GaAs having a doping concentration of 5 x 1018cm-3 of Si, for example, and has a film thickness of 50 nm. The second contact layer 56 is formed of n-type InGaAs having a mole ratio of 0.5 of InAs and a doping concentration of 1 x 1018cm-3 of Si, for example, and has a film thickness of 50 nm. 18 cm －3 16 cm －3 19 cm －3 17 cm －3 18 cm －3 19 cm －3

[0095] Collector electrodes CO are provided on the sub-collector layers 51 on both sides of the collector layer 52, respectively. The collector electrodes CO have a multilayer metal structure in which an AuGe film having a thickness of 60 nm, a Ni film having a thickness of 10 nm, and an Au film having a thickness of 200 nm are sequentially stacked. The lowermost AuGe film is in contact with the sub-collector layer 51, and a collector electrode alloy layer 61 is formed at the interface between the collector electrode CO and the sub-collector layer 51 by reaction of the AuGe with the sub-collector layer 51. By the collector electrode alloy layer 61, an ohmic electrical connection is obtained between the collector electrode CO and the sub-collector layer 51. The sub-collector layer 51 becomes a path of current flowing into and out of the collector layer 52. ​​​​​​

[0096] The base electrode B0 is disposed on the emitter layer 54 on both sides of the first contact layer 55. The base electrode B0 extends from the emitter layer 54 to the outside through a region between the edge of the emitter layer 54 and the edge of the base layer 53 and beyond the edge of the base layer 53. Thus, the base electrode B0 includes a portion protruding to the outside beyond the edge of the base layer 53. A portion of the base layer 53 not overlapping the emitter layer 54 is disposed between the base electrode B0 and the insulating film 62.

[0097] The base electrode B0 has a multilayer metal structure in which a Pt film with a thickness of 20 nm, a Ti film with a thickness of 50 nm, a Pt film with a thickness of 50 nm, and an Au film with a thickness of 200 nm are sequentially stacked. The lowermost Pt film is in contact with the emitter layer 54, and a base electrode alloy layer 65 is formed by the reaction of Pt with the emitter layer 54 and Pt with the base layer 53. The base electrode alloy layer 65 penetrates the emitter layer 54 in the thickness direction and reaches the base layer 53. An ohmic electrical connection is obtained between the base electrode B0 and the base layer 53 through the base electrode alloy layer 65. The base electrode alloy layer 65 contains constituent elements of a portion of the base electrode B0 and constituent elements of the emitter layer 54 and the base layer 53. The emitter layer 54 in a region between the edge (inner edge) of the inside of the base electrode B0 and the edge of the first contact layer 55 is depleted.

[0098] The emitter electrode E0 is disposed on a region of a portion of the second contact layer 56. The emitter electrode E0 has a multilayer metal structure in which a Mo film with a thickness of 10 nm, a Ti film with a thickness of 5 nm, a Pt film with a thickness of 30 nm, and an Au film with a thickness of 200 nm are sequentially stacked. The lowermost Mo film is in contact with the second contact layer 56. The emitter electrode E0 is electrically connected to the emitter layer 54 via the second contact layer 56 and the first contact layer 55.

[0099] The insulating film 62 disposed between the base layer 53 and the base electrode B0 covers the stacked structure from the emitter layer 54 to the emitter electrode E0. The base electrode B0 is in contact with the emitter layer 54 via an opening portion formed in the insulating film 62.

[0100] The interlayer insulating film 71 covers a region other than a region in which the collector electrode C0 is disposed in the upper surface of the collector layer 51. The interlayer insulating film 71 covers the stacked structure from the collector layer 52 to the second contact layer 56, the base electrode B0, and the emitter electrode E0. The interlayer insulating film 72 is disposed so as to cover the interlayer insulating film 71 and the collector electrode C0.

[0101] The first layer's collector wiring C1 is arranged on the collector electrode C0. The first layer's collector wiring C1 is connected to the collector electrode C0 via an opening portion provided in the interlayer insulating film 72. The first layer's emitter wiring E1 is arranged on the emitter electrode E0. The first layer's emitter wiring E1 is connected to the emitter electrode E0 via an opening portion provided in the insulating film 62, the interlayer insulating film 71, and the interlayer insulating film 72. The interlayer insulating film 73 is arranged so as to cover the interlayer insulating film 72, the first layer's collector wiring C1, and the first layer's emitter wiring E1.

[0102] The first layer's collector wiring C1, the first layer's emitter wiring E1, and the first layer's base wiring B1 FIG. 1A are, for example, composed of an Au film having a thickness of 1 μm. The insulating film 62 and the interlayer insulating films 71, 72, and 73 are, for example, formed of SiN. Further, the insulating film 62 can be formed of an insulating material such as SiON, SiO, or the like. The thickness of the insulating film 62 is, for example, 50 nm, and the thickness of each of the interlayer insulating films 71, 72, and 73 is, for example, 200 nm.

[0103] The planarization insulating film 76 is formed on the interlayer insulating film 73. The planarization insulating film 76 is, for example, formed of polyimide, and the thickness of the thickest portion is, for example, 4 μm. The upper surface of the planarization insulating film 76 is substantially flat.

[0104] The second layer's emitter wiring E2 and the second layer's collector wiring C2 FIG. 1A are arranged on the planarization insulating film 76. The second layer's emitter wiring E2 is connected to the first layer's emitter wiring E1 via an opening portion provided in the planarization insulating film 76 and the interlayer insulating film 73. The second layer's emitter wiring E2 and the second layer's collector wiring C2 FIG. 1A are, for example, formed of Au, and the thickness thereof is, for example, 4 μm.

[0105] FIG. 2A is a cross-sectional view of the HBT at the dot-dash line 2A-2A of FIG. 1A . In the cross section shown in FIG. 2A , the cross section of the portion of the base electrode B0 having a U-shaped planar shape, which is located on the side opposite to the opening portion, is shown. In the cross section shown in FIG. 2A , the base electrode B0 is also connected to the base layer 53 via the base electrode alloy layer 65. The insulating film 62 is arranged between the base electrode B0 and the base layer 53 in the same manner as in the cross section shown in FIG. 1B . Further, the edge (outer edge) of the base electrode B0 on the outer side protrudes to the outer side as compared with the edges of the collector layer 52 and the base layer 53 in the same manner as in the cross section shown in FIG. 1B . Further, the edge (outer edge) of the base electrode B0 on the outer side protrudes to the outer side as compared with the edges of the collector layer 52 and the base layer 53 in the same manner as in the cross section shown in

[0106] A first layer of base wiring B1 is disposed on the base electrode B0 via interlayer insulating films 71 and 72. Base wiring B1 is connected to the base electrode B0 via openings in the interlayer insulating films 71 and 72. The first layer of base wiring B1, like the first layer of emitter wiring E1, is covered by an interlayer insulating film 73. A second layer of collector wiring C2 is disposed on a planarized insulating film 76 covering the interlayer insulating film 73.

[0107] FIG. 2B yes FIG. 1A A cross-sectional view of the HBT at the dotted line 2B-2B. A first layer of collector wiring C1 is disposed on the collector electrode C0 via interlayer insulating films 71 and 72. The first layer of collector wiring C1 is connected to the collector electrode C0 through openings provided in the interlayer insulating films 71 and 72. The first layer of collector wiring C1 extends to the area where the collector electrode C0 is not disposed.

[0108] A second layer of collector wiring C2 and emitter wiring E2 are disposed on the planarization insulating film 76. The second layer of collector wiring C2 is connected to the first layer of collector wiring C1 at a position where no collector electrode C0 is disposed through an opening disposed in the planarization insulating film 76 and the interlayer insulating film 73.

[0109] Next, refer to FIG. 3A as well as FIG. 3B The superior performance of the HBT of the first embodiment is explained by comparing it with a reference example.

[0110] FIG. 3A This is a partial cross-sectional view of the HBT of the first embodiment. An emitter layer 54 is disposed on a portion of the base layer 53. The edge of the emitter layer 54 is located inside the edge of the base layer 53. An insulating film 62 is disposed on the base layer 53 and the emitter layer 54 between the edges of the base layer 53 and the emitter layer 54. A base electrode B0 is disposed on the insulating film 62. The inner edge of the base electrode B0 (in...) FIG. 3A The middle edge (the right edge) is located inside the emitter layer 54 compared to the edge of the right edge, while the outer edge (in) FIG. 3A The middle (left edge) is located on the outer side compared to the edge of the base layer 53. Similarly, the insulating film 62 protrudes outwards compared to the edge of the base layer 53, covering the lower surface of the base electrode B0. The position of the front end of the protruding portion of the insulating film 62 roughly coincides with the position of the outer edge of the base electrode B0.

[0111] An opening portion is provided in the insulating film 62 disposed between the emitter layer 54 and the base electrode B0. The base electrode B0 contacts the emitter layer 54 via the opening portion. A base electrode alloy layer 65 is formed in a region where the base electrode B0 contacts the emitter layer 54. The base electrode alloy layer 65 penetrates the emitter layer 54 in the thickness direction and reaches the base layer 53, but does not reach the collector layer 52. The insulating film 62 is disposed in a region between the edge of the emitter layer 54 and the edge of the base layer 53, so the base electrode alloy layer 65 is not formed in this region. The insulating film 62 has a function of preventing alloying.

[0112] FIG. 3B A partial cross-sectional view of an HBT of a reference example. In this reference example, the insulating film 62 is not disposed between the emitter layer 54 and the base electrode B0. Therefore, the base electrode B0 directly contacts the base layer 53. As a result, the base electrode alloy layer 65 is formed in the base layer 53 even in a region where the emitter layer 54 is not disposed. FIG. 3A

[0113] In order for the base electrode alloy layer 65 to penetrate the emitter layer 54 and reach the base layer 53, the base electrode alloy layer 65 must be thicker than the emitter layer 54. This condition must be satisfied in the first embodiment shown in FIG. 6 and in either of the reference examples shown in FIG. 7 and FIG. 8. FIG. 3A FIG. 3B In the reference example shown in FIG. 8, in addition to the above condition, in order for the base electrode alloy layer 65 not to reach the collector layer 52, the base layer 53 must be thicker than the base electrode alloy layer 65. The thickness of the base electrode alloy layer 65 (the depth of alloying) depends on the thickness of the Pt film of the base electrode B0. Generally, the thickness of the base electrode alloy layer 65 is about 2.5 times the thickness of the Pt film. Therefore, the base layer 53 must be thicker than 2.5 times the thickness of the Pt film of the base electrode B0.

[0114] On the contrary, in the first embodiment shown in FIG. 6, it is only necessary to make the total thickness of the emitter layer 54 and the base layer 53 thicker than 2.5 times the thickness of the Pt film of the base electrode B0. FIG. 3B

[0115] If the Pt film is too thin, a covering film cannot be formed on the entire substrate surface, and the deposited Pt becomes island-shaped. Therefore, there is a lower limit value in the appropriate range of the thickness of the Pt film. There is also a lower limit value in the range in which the thickness of the base electrode alloy layer 65 can be obtained. In the reference example shown in FIG. 8, it is not preferable to make the base layer 53 thinner than the lower limit value of the thickness of the base electrode alloy layer 65. FIG. 3A On the contrary, in the first embodiment shown in FIG. 6, it is only necessary to make the total thickness of the emitter layer 54 and the base layer 53 thicker than 2.5 times the thickness of the Pt film of the base electrode B0.

[0116] FIG. 3B

[0117] On the contrary, in the first embodiment shown in FIG. 6, it is only necessary to make the total thickness of the emitter layer 54 and the base layer 53 thicker than 2.5 times the thickness of the Pt film of the base electrode B0. FIG. 3A ​​​​​In the first embodiment shown, the total thickness of the emitter layer 54 and the base layer 53 is only required to be greater than the lower limit of the thickness of the base electrode alloy layer 65. Therefore, it is also possible to make the base layer 53 thinner than the base electrode alloy layer 65.

[0118] As described above, in the first embodiment, with FIG. 3B Compared to the reference example shown, the base layer 53 can be made thinner. If the base layer 53 is made thinner, the electron travel time within the base layer 53 is shortened, thus enabling high-speed operation of the HBT.

[0119] Furthermore, in the first embodiment, the edge of the interface between the base layer 53 and the collector layer 52 extends inward compared to the outer edge of the base electrode B0. Therefore, compared to the edge of the base-collector interface, the outer edge of the base electrode B0 can be extended outward and patterned. This also improves process controllability. By reducing the area of ​​the base-collector interface, the high-frequency feedback capacitance (base-collector inter-capacitor capacitance) is reduced, resulting in the ability to achieve high speeds.

[0120] Next, refer to FIGS. 4A-9C The accompanying drawings illustrate the manufacturing method of the HBT according to the first embodiment. FIGS. 4A-9C The attached diagram shows the HBT during the manufacturing process. FIG. 1B Corresponding to the cross-section.

[0121] like FIG. 4A As shown, a semiconductor layer from a sub-collector layer 51 to a second contact layer 56 is grown on a substrate 50 made of semi-insulating GaAs with a thickness of approximately 650 μm. The growth of these semiconductor layers can be performed, for example, using metal-organic vapor phase epitaxy (MO-VPE). The crystal orientation of the surface of the substrate 50 is, for example, in the range of (001) ± 4°.

[0122] An emitter electrode E0 is formed on a portion of the second contact layer 56. The emitter electrode E0 can be formed, for example, by vacuum evaporation or a stripping method.

[0123] like FIG. 4B As shown, unwanted areas of the second contact layer 56 and the first contact layer 55 are removed by etching. This etching can be performed, for example, by using a wet etching solution containing an etchant of 85% (by weight) phosphoric acid, 35% (by weight) hydrogen peroxide solution, and water in a volume ratio of 1:2:40. Hereinafter, this etchant solution with this mixing ratio will be referred to simply as the phosphoric acid-hydrogen peroxide mixture. This etchant solution exhibits etch selectivity, stopping etching at the moment the emitter layer 54, composed of InGaP, is exposed.

[0124] like FIG. 4CAs shown, the unnecessary region of the emitter layer 54 is etched and removed. This etching can apply, for example, a wet etching using hydrochloric acid. The hydrochloric acid has an etching selectivity of stopping etching at the moment of exposing the base layer 53 composed of GaAs.

[0125] As shown, the insulating film 62 composed of SiN is deposited on the entire region of the exposed surface by a chemical vapor deposition (CVD) method. FIG. 5A As shown, the insulating film 62 is formed with an opening portion 62a exposing a part of the upper surface of the emitter layer 54.

[0126] FIG. 5B As shown, the base electrode B0 is formed using a vacuum evaporation method and a lift-off method. The base electrode B0 has a planar shape as shown.

[0127] As shown, the base electrode B0 is in contact with the emitter layer 54 via the opening portion 62a ( ). In the region where the opening portion 62a ( ) is not formed, the base electrode B0 is not in contact with the emitter layer 54 and the base layer 53. FIG. 5C FIG. 1A As shown, the photoresist film 90 is formed. The edge of the photoresist film 90 is located outside compared to the inner edge of the base electrode B0, and is located inside compared to the outer edge. FIG. 5B FIG. 5B As shown, the exposed part of the insulating film 62 is etched and removed using the photoresist film 90 and the base electrode B0 as etching masks. The insulating film 62 remains between the base electrode B0 and the base layer 53.

[0128] As shown, the base layer 53 and the collector layer 52 are etched using a hydrogen peroxide-phosphoric acid mixed solution until the sub-collector layer 51 is exposed, using the photoresist film 90, the base electrode B0, and the insulating film 62 as etching masks. The etching amount is controlled by the etching time. By side etching the base layer 53 and the collector layer 52, the side surfaces (the edges of the joint interfaces) of the base layer 53 and the collector layer 52 retreat from the outer edge of the base electrode B0 toward the inside. FIG. 6A As shown, the photoresist film 90 ( ) used as an etching mask is removed. Thereby, the entire region of the upper surface of the base electrode B0 and the insulating film 62 are exposed.

[0129] FIG. 6B As shown, the photoresist film 90 ( ) used as an etching mask is removed. Thereby, the entire region of the upper surface of the base electrode B0 and the insulating film 62 are exposed.

[0130] As shown, the photoresist film 90 ( ) used as an etching mask is removed. Thereby, the entire region of the upper surface of the base electrode B0 and the insulating film 62 are exposed. FIG. 6C As shown, the photoresist film 90 ( ) used as an etching mask is removed. Thereby, the entire region of the upper surface of the base electrode B0 and the insulating film 62 are exposed.

[0131] FIG. 7A As shown, the photoresist film 90 ( ) used as an etching mask is removed. Thereby, the entire region of the upper surface of the base electrode B0 and the insulating film 62 are exposed. FIG. 6C As shown, the photoresist film 90 ( ) used as an etching mask is removed. Thereby, the entire region of the upper surface of the base electrode B0 and the insulating film 62 are exposed.

[0132] FIG. 7B ​​​​​​As shown, the interlayer insulating film 71 is deposited on the entire region of the exposed surface by a CVD method. The interlayer insulating film 71 has a function of protecting the edge of the pn junction interface of the collector layer 52 and the base layer 53 from being exposed.

[0133] As shown, a prescribed region of the interlayer insulating film 71 is etched to form an opening portion, and a collector electrode CO is formed on the sub-collector layer 51 in the opening portion. A photoresist film for peeling is used as an etching mask for the formation of the opening portion of the interlayer insulating film 71. The collector electrode CO is formed by a vacuum evaporation method and a peeling method. FIG. 7C

[0134] As shown, the interlayer insulating film 72 is deposited on the entire region of the exposed surface by a CVD method. Thereafter, heat treatment is performed at 350°C for 30 minutes in a nitrogen atmosphere to form the base electrode alloy layer 65 and the collector electrode alloy layer 61. FIG. 8A As shown, the interlayer insulating film 72 is deposited on the entire region of the exposed surface by a CVD method. Thereafter, heat treatment is performed at 350°C for 30 minutes in a nitrogen atmosphere to form the base electrode alloy layer 65 and the collector electrode alloy layer 61.

[0135] FIG. 8B As shown, the interlayer insulating film 72 is deposited on the entire region of the exposed surface by a CVD method. Thereafter, heat treatment is performed at 350°C for 30 minutes in a nitrogen atmosphere to form the base electrode alloy layer 65 and the collector electrode alloy layer 61.

[0136] As shown, the interlayer insulating film 72 is deposited on the entire region of the exposed surface by a CVD method. Thereafter, heat treatment is performed at 350°C for 30 minutes in a nitrogen atmosphere to form the base electrode alloy layer 65 and the collector electrode alloy layer 61. FIG. 8C As shown, the interlayer insulating film 72 is deposited on the entire region of the exposed surface by a CVD method. Thereafter, heat treatment is performed at 350°C for 30 minutes in a nitrogen atmosphere to form the base electrode alloy layer 65 and the collector electrode alloy layer 61.

[0137] FIG. 9A As shown, the interlayer insulating film 72 is deposited on the entire region of the exposed surface by a CVD method. Thereafter, heat treatment is performed at 350°C for 30 minutes in a nitrogen atmosphere to form the base electrode alloy layer 65 and the collector electrode alloy layer 61.

[0138] As shown, the interlayer insulating film 72 is deposited on the entire region of the exposed surface by a CVD method. Thereafter, heat treatment is performed at 350°C for 30 minutes in a nitrogen atmosphere to form the base electrode alloy layer 65 and the collector electrode alloy layer 61. FIG. 9B As shown, the interlayer insulating film 72 is deposited on the entire region of the exposed surface by a CVD method. Thereafter, heat treatment is performed at 350°C for 30 minutes in a nitrogen atmosphere to form the base electrode alloy layer 65 and the collector electrode alloy layer 61.

[0139] FIG. 9C As shown, the interlayer insulating film 72 is deposited on the entire region of the exposed surface by a CVD method. Thereafter, heat treatment is performed at 350°C for 30 minutes in a nitrogen atmosphere to form the base electrode alloy layer 65 and the collector electrode alloy layer 61.

[0140] Thereafter, the second layer of the emitter wire E2 ( ) and the collector wire C2 ( ) are formed on the planarization insulating film 76 using a vacuum evaporation method and a peeling method. FIG. 1B FIG. 1A ​​​​​). A Cu stud bump or a solder bump or the like can also be formed on the emitter wiring E2 and the collector wiring C2 of the second layer.

[0141] [Modified example of the first embodiment]

[0142] In the HBT of the first embodiment, GaAs is used for the base layer 53, but another compound semiconductor can also be used. For example, AlGaAs, InGaAs, GaAsSb, GaAsPBi, GaInNAs, GaAsBi, GaAsN, GaAsBiN, or the like can also be used for the base layer 53. Alternatively, a multilayer base structure including a plurality of layers made of these compound semiconductors can also be adopted for the base layer 53. In addition, a compositionally graded base structure, a doping concentration graded base structure can also be adopted.

[0143] In the HBT of the first embodiment, GaAs is used for the collector layer 52, but another compound semiconductor can also be used. For example, AlGaAs, InGaAs, InP, or the like can also be used for the collector layer 52. In addition, a multilayer collector structure including a plurality of layers made of these compound semiconductors can also be adopted for the collector layer 52. In addition, a compositionally graded collector structure, a doping concentration graded collector structure can also be adopted.

[0144] In the HBT of the first embodiment, GaAs is used for the substrate 50, but another compound semiconductor can also be used. For example, an InP substrate can also be used.

[0145] In the first embodiment, an npn type HBT is exemplified, but the feature structure of the HBT of the first embodiment can also be applied to a pnp type HBT. In the first embodiment, a bipolar transistor having a heterojunction is exemplified, but the feature structure of the first embodiment can also be applied to a general bipolar transistor.

[0146] [Second embodiment]

[0147] Next, the HBT of the second embodiment will be described with reference to the drawings. FIGS. 10A-11B Here, the same configuration as the HBT of the first embodiment will be omitted from the description below.

[0148] FIG. 10A and FIG. 10B are cross-sectional views of the HBT of the second embodiment, respectively, and correspond to the cross sections of the base electrode B0 and its vicinity of the HBT of the first embodiment FIG. 1B and FIG. 2A , respectively. FIG. 10C is a cross-sectional view of the base electrode B0 and its vicinity of the HBT of the second embodiment. In the first embodiment, the lower surface of the portion of the base electrode B0 that protrudes outwardly compared to the edge of the base layer 53 is covered with the insulating film 62 FIG. 1B ,FIG. 2A )cover.

[0149] In the second embodiment, the lower surface of the portion of the base electrode B0 that protrudes outward compared to the edge of the base layer 53 is not covered by the insulating film 62. When viewed from above, the edge of the insulating film 62 is approximately aligned with the edge of the base layer 53.

[0150] Furthermore, in the first embodiment, the insulating film 62 and FIG. 2A The left edge of the base layer 53 shown protrudes outwards. In the second embodiment, the edge of the insulating film 62 in this portion also roughly coincides with the edge of the base layer 53.

[0151] Next, refer to FIG. 11A as well as FIG. 11B The manufacturing method of the HBT according to the second embodiment will be described.

[0152] FIG. 11A Compared with the HBT of the first embodiment FIG. 6C The cross-sectional view shown is the same as that of the intermediate manufacturing stage. In this stage, the lower surface of the portion of the base electrode B0 that protrudes outward compared to the edge of the base layer 53 is covered by an insulating film 62.

[0153] like FIG. 11B As shown, for example, buffered hydrofluoric acid etching is used to remove the insulating film 62 on the outer side compared to the edge of the base layer 53. Subsequent processes are the same as the manufacturing process of the HBT in the first embodiment. The insulating film 62 on the inner side compared to the inner edge of the base electrode B0 is covered by a photoresist film 90 and therefore is not etched.

[0154] Next, the superior effects of the HBT of the second embodiment will be explained. In the second embodiment, similar to the first embodiment, the ability to perform high-speed operation is achieved. If, as in the first embodiment, an insulating film 62 remains on the lower surface of the protruding portion of the base electrode B0, the possibility of process defects such as peeling in subsequent processes increases. In the second embodiment, since the insulating film 62 in this portion is removed, the occurrence of process defects can be suppressed.

[0155] [Third Embodiment]

[0156] Next, refer to FIGS. 12-13C The accompanying drawings illustrate the HBT of the third embodiment. Hereinafter, descriptions of configurations identical to those of the HBT of the first embodiment will be omitted.

[0157] FIG. 12 This is a cross-sectional view of the HBT of the third embodiment, compared to the HBT of the first embodiment. FIG. 1B The cross-sectional view shown corresponds to this. In the first embodiment, the collector layer 52 ( FIG. 4AThe side surface of the base layer 53, from its lower surface to its upper surface, aligns with the edge of the base layer 53. In the third embodiment, as shown... FIG. 12 As shown, the edge of the upper collector layer 52B, which is part of the upper side of the collector layer 52, coincides with the edge of the base layer 53 when viewed from above, while the edge of the lower collector layer 52A, which is the remaining lower side, is located outside the edge of the base layer 53. Alternatively, the side surface of the upper collector layer 52B is smoothly (without forming a step difference) continuous to the side surface of the base layer 53.

[0158] Next, refer to FIGS. 13A-13C The accompanying drawings illustrate the manufacturing method of the HBT according to the third embodiment.

[0159] FIG. 13A It is the same as the first embodiment FIG. 6C The cross-sectional view shown corresponds to an intermediate stage of manufacturing. In the first embodiment, etching is performed to the subset electrode layer 51 ( FIG. 6C The upper surface of the collector layer 52 is etched, but in the third embodiment, it is etched to the middle of the thickness direction of the collector layer 52.

[0160] like FIG. 13B As shown, after etching halfway to the collector layer 52, an interlayer insulating film 74 is deposited over the entire exposed surface area, for example by CVD. The interlayer insulating film 74 is formed, for example, of SiN, and has a thickness of, for example, 50 nm.

[0161] like FIG. 13C As shown, in the case where the collector electrode C0 should be formed ( FIG. 1B An opening 74a is formed in the region ( ) that penetrates the interlayer insulating film 74 and the collector layer 52. The sub-collector layer 51 is exposed within the opening 74a. Subsequent processes are the same as in the first embodiment. FIG. 7C The subsequent steps are the same as those shown. Furthermore, in the third embodiment, the edge of the pn junction interface between the collector layer 52 and the base layer 53 is protected by the interlayer insulating film 74, so the interlayer insulating film 71 of the first embodiment is not required. FIG. 7C ).

[0162] Next, the superior effects of the HBT in the third embodiment will be explained. In the third embodiment, similar to the first embodiment, the ability to perform high-speed operation is achieved. In the first embodiment, in... FIG. 6C The process shown determines the lateral etching depth based on the etching time in the thickness direction of the base layer 53 and the collector layer 52. In contrast, in the third embodiment, a portion of the upper side of the base layer 53 and the collector layer 52 can be etched laterally to the target depth. FIG. 13A After that, the remaining portion of the collector layer 52 is etched in the thickness direction. FIG. 13C). Thus, the freedom of the depth of the etching of the base layer 53 and the upper side of the collector layer 52 in the lateral direction is increased. Also, the depth of the etching of the base layer 53 and the upper side of the collector layer 52 in the lateral direction is shallower than that of the first embodiment. Thus, the process controllability can be increased.

[0163] [Variation of the Third Embodiment]

[0164] In the third embodiment, the insulating film 62 covering the lower surface of the protruding portion of the base electrode B0 can be removed as in the second embodiment ( FIG. 10A , FIG. 10B , FIG. 10C ).

[0165] In the third embodiment, the doping concentration of the collector layer 52 is made uniform, but the doping concentration of the upper collector layer 52B ( FIG. 12 ) can be lower than that of the lower collector layer 52A ( FIG. 12 ). By being such a distribution of the doping concentration, the high frequency linearity can be increased. Also, the position where the doping concentration of the collector layer 52 is changed and the boundary of the upper collector layer 52B and the lower collector layer 52A do not need to be coincident.

[0166] It is preferable that the thickness of the upper collector layer 52B ( FIG. 12 ) is thinner than that of the lower collector layer 52A. By being such a configuration, the controllability of the etching in the lateral direction can be increased. As a result, the positional relationship of the outer edge of the base electrode B0 and the edge of the base layer 53 can be controlled with high precision.

[0167] [Fourth Embodiment]

[0168] Next, the HBT of the fourth embodiment will be described with reference to FIG. 14A and FIG. 14B . Hereinafter, the description of the configuration common to the HBT of the first embodiment will be omitted.

[0169] FIG. 14A is a cross-sectional view of the HBT of the fourth embodiment, and corresponds to the cross-sectional view of the HBT of the first embodiment FIG. 1B . In the first embodiment, the sub-collector layer 51 is configured of a single compound semiconductor layer. In the fourth embodiment, the sub-collector layer 51 includes a first sub-collector layer 51A disposed on the substrate 50, and a second sub-collector layer 51B disposed on the first sub-collector layer 51A.

[0170] The etching characteristics of the second sub-collector layer 51B are different from those of the portion of the collector layer 52 in contact with the second sub-collector layer 51B. For example, the first sub-collector layer 51A is configured of Si whose doping concentration is 5 x 1018cm-3, and the second sub-collector layer 51B is configured of GaAs whose doping concentration is 1 x 1018cm-3.18 cm －3 of n-type GaAs is formed, and has a thickness of 600 nm. The second sub-collector layer 51B is formed of n-type InGaP having a molar ratio of 0.48 of In and a doping concentration of 5 x 1018cm"3of Si, and has a thickness of 20 nm. The collector layer 52 is formed of n-type GaAs, like the first embodiment. 18 cm －3 of n-type InGaP is formed, and has a thickness of 20 nm. The collector layer 52 is formed of n-type GaAs, like the first embodiment.

[0171] FIG. 14B is a cross-sectional view of the HBT at an intermediate stage of manufacture, corresponding to the cross-sectional view at the intermediate stage of manufacture shown in Fig. 1 of the first embodiment. The photoresist film 90, the base electrode B0, and the insulating film 62 are used as etching masks, and the base layer 53 and the collector layer 52 are etched. The etching conditions are the same as in the case of the first embodiment. Under the etching conditions, the second sub-collector layer 51B composed of n-type InGaP is not actually etched, and the base layer 53 and the collector layer 52 can be selectively etched. The subsequent processes are the same as the manufacturing processes of the HBT of the first embodiment. FIG. 6C Next, the excellent effects possessed by the HBT of the fourth embodiment will be described. In the fourth embodiment, like the first embodiment, the effect that high-speed operation can be achieved is obtained. Also, in the fourth embodiment, in the etching process shown in Fig. 1, the second sub-collector layer 51B functions as an etching stopper layer, so the side etching of the base layer 53 and the collector layer 52 can be continued even after the sub-collector layer 51 is exposed. Therefore, the etching amount of the base layer 53 and the collector layer 52 in the lateral direction can be controlled independently of the etching amount in the thickness direction.

[0172] FIG. 14B [Modified Example of the Fourth Embodiment]

[0173] In the fourth embodiment, like the second embodiment (Figs. 2 to 4), the insulating film 62 covering the lower surface of the protruding portion of the base electrode B0may be removed.

[0174] [Modified Example of the Fourth Embodiment] FIG. 10A 、 FIG. 10B 、 FIG. 10C In the fourth embodiment, like the second embodiment (Figs. 2 to 4), the insulating film 62 covering the lower surface of the protruding portion of the base electrode B0may be removed.

[0175] [Modified Example of the Fourth Embodiment]

[0176] Next, the HBT of the fifth embodiment will be described with reference to the drawings of Fig. 1. Hereinafter, the description of the same configuration as the HBT of the third embodiment (Figs. 5 to 7) will be omitted. FIGS. 15-16C FIG. 12

[0177] FIG. 15 is a cross-sectional view of the HBT at an intermediate stage of manufacture, corresponding to the cross-sectional view at the intermediate stage of manufacture shown in Fig. 1 of the first embodiment. The photoresist film 90, the base electrode B0, and the insulating film 62 are used as etching masks, and the base layer 53 and the collector layer 52 are etched. The etching conditions are the same as in the case of the first embodiment. Under the etching conditions, the second sub-collector layer 51B composed of n-type InGaP is not actually etched, and the base layer 53 and the collector layer 52 can be selectively etched. The subsequent processes are the same as the manufacturing processes of the HBT of the first embodiment. FIG. 12 ​​​The cross-sectional views shown correspond. In the third embodiment, the collector layer 52 is divided into an upper collector layer 52B and a lower collector layer 52A, but the boundary between the two is not clear. In the fifth embodiment, the collector layer 52 contains, at an intermediate position in the thickness direction, an intermediate collector layer 52C composed of a semiconductor material different in etching characteristics from the other portions of the semiconductor material. By the intermediate collector layer 52C, the collector layer 52 is divided into the upper collector layer 52B and the lower collector layer 52A.

[0178] For example, the lower collector layer 52A and the upper collector layer 52B are formed of n-type GaAs of 1 x 10 16 cm －3 -2. The thickness of the lower collector layer 52A and the upper collector layer 52B is, for example, 700 nm and 300 nm, respectively. The intermediate collector layer 52C is formed of, for example, undoped InGaP of 0.48 in molar ratio of InP. The thickness of the intermediate collector layer 52C is, for example, 10 nm. The thickness of the intermediate collector layer 52C is set to be as thin as not to hinder the movement of carriers.

[0179] The sub-collector layer 51 is composed of the same as in the fourth embodiment FIG. 14A ) and contains the first sub-collector layer 51A and the second sub-collector layer 51B.

[0180] Next, the manufacturing method of the HBT of the fifth embodiment will be described with reference to FIG. 16A , FIG. 16B , and FIG. 16C . FIG. 16A , FIG. 16B , and FIG. 16C correspond to the cross-sectional views of the HBT at the manufacturing intermediate stage shown in FIG. 13A , FIG. 13B , and FIG. 13C of the third embodiment, respectively.

[0181] As shown in FIG. 16A , the base layer 53 and the upper collector layer 52B are etched with the photoresist film 90, the base electrode B0, and the insulating film 62 as etching masks. The etching conditions are the same as those of the etching process shown in FIG. 13A . Under the etching conditions, the intermediate collector layer 52C composed of InGaP is not actually etched. Thus, the base layer 53 and the upper collector layer 52B can be etched selectively with respect to the intermediate collector layer 52C.

[0182] By this, a structure in which the edge of the base layer 53 and the edge of the upper collector layer 52B coincide when viewed from above can be obtained. Also, the side surface of the base layer 53 is smoothly continuous to the side surface of the upper collector layer 52B without a step difference.

[0183] As shown in FIG. 16B , the interlayer insulating film 74 is stacked so as to cover the entire region of the exposed surface. The interlayer insulating film 74 protects the exposed end portion of the pn junction interface of the base layer 53 and the upper collector layer 52B.

[0184] As shown in FIG. 16C , the opening portion 74a is formed through the interlayer insulating film 74, the intermediate collector layer 52C, and the lower collector layer 52A. The etching of the interlayer insulating film 74 can use buffered hydrofluoric acid, the etching of the intermediate collector layer 52C can use hydrochloric acid, and the etching of the lower collector layer 52A can use a phosphoric acid hydrogen peroxide mixture. The upper collector layer 52B is disposed inside the intermediate collector layer 52C and the lower collector layer 52A in plan view. The subsequent processes are the same as the manufacturing processes of the HBT of the third embodiment.

[0185] Next, the excellent effects that the HBT of the fifth embodiment has will be described. In the fifth embodiment, as with the first embodiment, the effect that high-speed operation can be performed can be obtained. Also, in the fifth embodiment, in the etching process shown in FIG. 16A , the intermediate collector layer 52C functions as an etching stopper layer. Therefore, compared with the etching process of the third embodiment shown in FIG. 13A , the time of etching in the lateral direction of the base layer 53 and the upper collector layer 52B can be set independently from the etching in the depth direction. Thereby, the degree of freedom of the depth of etching in the lateral direction is increased.

[0186] In order to improve the controllability of etching in the lateral direction, it is preferable that the upper collector layer 52B be thinner than the lower collector layer 52A.

[0187] The intermediate collector layer 52C is preferably a thickness that embodies the tunnel effect of quantum mechanics, such as a thickness of 20 nm or less. By setting the thickness of the intermediate collector layer 52C like this, the travel of electrons within the collector layer 52 can be inhibited from being hindered by the intermediate collector layer 52C.

[0188] [Modified example of the fifth embodiment]

[0189] In the fifth embodiment, the insulating film 62 that covers the lower surface of the protruding portion of the base electrode B0 can be removed, as with the configuration of the second embodiment FIG. 10A , FIG. 10B , FIG. 10C .

[0190] [Sixth embodiment]

[0191] Next, the HBT of the sixth embodiment will be described with reference to the drawings. FIGS. 17A-21C . Hereinafter, the description will be made with reference to the first embodiment FIGS. 1A-9CThe same configuration as the HBT of the first embodiment is omitted from explanation.

[0192] FIG. 17A is a plan view of electrodes to which the collector, the base, and the emitter of the HBT of the sixth embodiment are connected, and a wiring disposed thereon. In FIG. 17A the base electrode B0 and the emitter electrode E0 are respectively attached with a relatively thick hatching and a relatively thin hatching.

[0193] In the first embodiment, as shown in FIG. 1A , the emitter electrode E0 is disposed separately from the inner edge of the base electrode B0 when viewed in plan from three directions by the horse-shoe shaped base electrode B0. In the sixth embodiment, as shown in FIG. 17A , the emitter electrode E0 is surrounded from four directions by the base electrode B0, and the edge of the emitter electrode E0 coincides with the inner edge of the base electrode B0.

[0194] FIG. 17B is a sectional view at the dotted line 17B-17B of FIG. 17A . The emitter electrode E0 has a double layer structure of a lower layer E0a and an upper layer E0b disposed thereon. The lower layer E0a of the emitter electrode E0 is formed of, for example, WSi with a molar ratio of Si of 0.3, and has a thickness of, for example, 300 nm. The upper layer E0b of the emitter electrode E0 has the same layer structure as the base electrode B0.

[0195] The edge of the emitter electrode E0 is disposed on the outside when viewed in plan compared with the edges of the first contact layer 55 and the second contact layer 56 thereunder. That is, the emitter electrode E0 protrudes to the outside compared with the edges of the first contact layer 55 and the second contact layer 56, and has a structure like a visor. The inner edge of the base electrode B0 is disposed directly under the edge of the emitter electrode E0.

[0196] In the first embodiment, as shown in FIG. 1B and FIG. 7A , the insulating film 62 is disposed in the area on the inside compared with the inner edge of the base electrode B0. In the sixth embodiment, the insulating film 62 is disposed on the lower surface of the base electrode B0, but is not disposed in the area on the inside compared with the inner edge of the base electrode B0.

[0197] FIG. 18A is a sectional view at the dotted line 18A-18A of FIG. 17A . In this sectional view, the emitter electrode E0 protrudes to the outside compared with the edges of the first contact layer 55 and the second contact layer 56, and has a structure like a visor, as in the sectional view shown in FIG. 17B . Also, the inner edge of the base electrode B0 is disposed directly under the edge of the emitter electrode E0.

[0198] FIG. 18B isFIG. 17A cross-sectional view at the dotted line 18B-18B. FIG. 18B the cross-sectional structure of the first embodiment. FIG. 2B the cross-sectional structure of the first embodiment.

[0199] Next, a manufacturing method of the HBT of the sixth embodiment will be described with reference to the drawings. FIGS. 19A-21C the cross-sectional view of the HBT at the manufacturing intermediate stage. FIGS. 19A-21C the cross-sectional view of the HBT at the manufacturing intermediate stage.

[0200] As shown in FIG. 19A , the semiconductor layers from the sub-collector layer 51 to the second contact layer 56 are formed on the substrate 50. This process is the same as the process up to the formation of the second contact layer 56 shown in FIG. 4A the first embodiment. The lower layer E0a of the emitter electrode E0 is stacked on the second contact layer 56, for example, by a high-frequency sputtering method.

[0201] As shown in FIG. 19B , the unnecessary portion of the lower layer E0a of the emitter electrode E0 is removed. Thereby, the second contact layer 56 is exposed. The etching of the lower layer E0a of the emitter electrode E0 can apply a dry etching using CF4.

[0202] As shown in FIG. 19C , the unnecessary portions of the second contact layer 56 and the first contact layer 55 are removed as the etching mask using the lower layer E0a of the emitter electrode E0. The etching can apply the same conditions as the etching shown in FIG. 4B the first embodiment. In this etching, the emitter layer 54 functions as an etching stopper layer. By also etching the second contact layer 56 and the first contact layer 55 in the lateral direction, the edges of the second contact layer 56 and the first contact layer 55 are located inside compared with the edges of the lower layer E0a of the emitter electrode E0 in plan view.

[0203] As shown in FIG. 20A , the unnecessary portion of the emitter layer 54 is removed. The etching of the emitter layer 54 can apply the same conditions as the etching shown in FIG. 4C the first embodiment. The emitter layer 54 after the etching contains the lower layer E0a of the emitter electrode E0 inside in plan view. In this etching, the base layer 53 functions as an etching stopper layer.

[0204] As shown in FIG. 20B , the insulating film 62 is stacked on the entire region of the exposed surface.

[0205] As shown in FIG. 20CThe unnecessary portion of the insulating film 62 is removed. Specifically, the insulating film 62 of the region stacked on the inner side compared with the edge of the emitter layer 54 is removed. Further, considering the alignment accuracy of the photoresist film used as the etching mask, in fact, the edge of the insulating film 62 is slightly located on the inner side compared with the edge of the emitter electrode E0. When viewed from the top, the edge of the insulating film 62 is located on the outer side compared with the edge of the lower layer E0a of the emitter electrode E0.

[0206] As shown in FIG. 9A, the photoresist film 91 is formed on the outer side compared with the outer edge of the base electrode B0 to be formed. In this state, vacuum evaporation is performed on the base electrode B0. The upper layer E0b of the emitter electrode E0 having the same stacked structure as the base electrode B0 is evaporated on the lower layer E0a. The inner edge of the base electrode B0 and the edge of the emitter electrode E0 are self-matched in position. FIG. 21A As shown in FIG. 9B, the photoresist film 91 is removed together with the metal film stacked thereon. Thereby, the insulating film 62 is exposed in the region on the outer side compared with the outer edge of the base electrode B0.

[0207] As shown in FIG. 9C, the photoresist film 92 having an edge between the outer edge and the inner edge of the base electrode B0 is formed. The photoresist film 92 and the base electrode B0 are used as etching masks to etch the insulating film 62. By this etching, the insulating film 62 on the outer side compared with the outer edge of the base electrode B0 is removed, and the insulating film 62 remains under the base electrode B0. FIG. 21B As shown in FIG. 9D, the photoresist film 92 is removed together with the metal film stacked thereon. Thereby, the insulating film 62 is exposed in the region on the outer side compared with the outer edge of the base electrode B0. FIG. 21A As shown in FIG. 9E, the photoresist film 92 is removed together with the metal film stacked thereon. Thereby, the insulating film 62 is exposed in the region on the outer side compared with the outer edge of the base electrode B0.

[0208] As shown in FIG. 9F, the photoresist film 92 having an edge between the outer edge and the inner edge of the base electrode B0 is formed. The photoresist film 92 and the base electrode B0 are used as etching masks to etch the insulating film 62. By this etching, the insulating film 62 on the outer side compared with the outer edge of the base electrode B0 is removed, and the insulating film 62 remains under the base electrode B0. FIG. 21C As shown in FIG. 9G, the photoresist film 92 is removed together with the metal film stacked thereon. Thereby, the insulating film 62 is exposed in the region on the outer side compared with the outer edge of the base electrode B0. FIG. 21B As shown in FIG. 9H, the photoresist film 92 is removed together with the metal film stacked thereon. Thereby, the insulating film 62 is exposed in the region on the outer side compared with the outer edge of the base electrode B0. FIG. 6C As shown in FIG. 91, the photoresist film 92 having an edge between the outer edge and the inner edge of the base electrode B0 is formed. The photoresist film 92 and the base electrode B0 are used as etching masks to etch the insulating film 62. By this etching, the insulating film 62 on the outer side compared with the outer edge of the base electrode B0 is removed, and the insulating film 62 remains under the base electrode B0.

[0209] Next, the excellent effects of the HBT of the sixth embodiment are described. In the sixth embodiment, as in the first embodiment, the effect that high-speed operation can be performed can be obtained. In the first embodiment, as shown in FIG. 1A, the interval between the inner edge of the base electrode B0 and the edge of the first contact layer 55 must be designed considering the alignment accuracy of photolithography. In contrast, in the sixth embodiment, the interval between the inner edge of the base electrode B0 and the edge of the first contact layer 55 is almost the same as the depth at which the second contact layer 56 and the first contact layer 55 are etched in the process of FIG. 5. Therefore, the base electrode B0 can be brought close to the first contact layer 55 without being affected by the alignment accuracy of photolithography. By bringing the base electrode B0 close to the first contact layer 55, the base resistance can be reduced. FIG. 5C FIG. 19C [Modified Example of the Sixth Embodiment]

[0210] [Modified Example of the Sixth Embodiment]

[0211] ​In the sixth embodiment, the insulating film 62 covering the lower surface of the protruding portion of the base electrode B0 can also be removed, as in the configuration of the second embodiment ( FIG. 10A , FIG. 10B , FIG. 10C ).

[0212] [Seventh Embodiment]

[0213] Next, the HBT of the seventh embodiment will be described with reference to FIG. 22 . Hereinafter, the description of the configuration common to the HBT of the sixth embodiment ( FIGS. 17A-21C ) will be omitted.

[0214] FIG. 22 is a cross-sectional view of the HBT of the seventh embodiment, corresponding to the cross-sectional view shown in FIG. 17B of the sixth embodiment. In the sixth embodiment, the side surface of the collector layer 52 ( FIG. 17B ) from the lower surface to the upper surface coincides with the edge of the base layer 53 in plan view. In the seventh embodiment, as in the third embodiment ( FIG. 12 ), the edge of the upper collector layer 52B, which is a part of the upper side of the collector layer 52, coincides with the edge of the base layer 53 in plan view, and the edge of the lower collector layer 52A, which is the remaining part of the lower side, is located outside compared to the edge of the base layer 53.

[0215] In the seventh embodiment, by becoming such a configuration, in addition to the excellent effects possessed by the HBT of the sixth embodiment, the excellent effects possessed by the HBT of the third embodiment can also be obtained.

[0216] [Variation of the Seventh Embodiment]

[0217] In the seventh embodiment, the insulating film 62 covering the lower surface of the protruding portion of the base electrode B0 can also be removed, as in the configuration of the second embodiment ( FIG. 10A , FIG. 10B , FIG. 10C ).

[0218] [Eighth Embodiment]

[0219] Next, the HBT of the eighth embodiment will be described with reference to FIG. 23 . Hereinafter, the description of the configuration common to the HBT of the sixth embodiment ( FIGS. 17A-21C ) will be omitted.

[0220] FIG. 23 is a cross-sectional view of the HBT of the eighth embodiment, corresponding to the cross-sectional view shown in FIG. 17B of the sixth embodiment. In the sixth embodiment, the sub-collector layer 51 ( FIG. 17B) is composed of a single compound semiconductor layer. In contrast, in the eighth embodiment, like the fourth embodiment ( FIG. 14A ), the sub-collector layer 51 includes a first sub-collector layer 51A disposed on the substrate 50, and a second sub-collector layer 51B disposed on the first sub-collector layer 51A.

[0221] In the eighth embodiment, by being configured in this way, in addition to the excellent effects that the HBT of the sixth embodiment has, the excellent effects that the HBT of the fourth embodiment has can also be obtained.

[0222] [Modified Example of the Eighth Embodiment]

[0223] In the eighth embodiment, like the second embodiment ( FIG. 10A , FIG. 10B , FIG. 10C ), the insulating film 62 covering the lower surface of the protruding portion of the base electrode B0 can be removed.

[0224] [Ninth Embodiment]

[0225] Next, the HBT of the ninth embodiment will be described with reference to FIG. 24 . Hereinafter, the configuration common to the HBT of the sixth embodiment ( FIGS. 17A-21C ) will be omitted.

[0226] FIG. 24 is a cross-sectional view of the HBT of the ninth embodiment, and corresponds to the cross-sectional view illustrated in FIG. 17B of the sixth embodiment. In the ninth embodiment, like the fifth embodiment ( FIG. 15 ), the collector layer 52 includes the lower collector layer 52A, the intermediate collector layer 52C, and the upper collector layer 52B, and like the eighth embodiment ( FIG. 14A ), the sub-collector layer 51 includes the first sub-collector layer 51A and the second sub-collector layer 51B.

[0227] In the ninth embodiment, by being configured in this way, in addition to the excellent effects that the HBT of the sixth embodiment has, the excellent effects that the HBT of the fifth embodiment has and the excellent effects that the HBT of the eighth embodiment has can also be obtained.

[0228] [Modified Example of the Ninth Embodiment]

[0229] In the ninth embodiment, like the second embodiment ( FIG. 10A , FIG. 10B , FIG. 10C ), the insulating film 62 covering the lower surface of the protruding portion of the base electrode B0 can be removed.

[0230] [Tenth Embodiment]

[0231] Next, refer to FIG. 25 , FIG. 26 ,as well as FIG. 27 The HBT of the tenth embodiment will be described below. Hereinafter, it will be compared with the HBT of the first embodiment (…). FIGS. 1A-9C The same configuration as the HBT in the attached diagram is omitted.

[0232] FIG. 25 This is a top view of the collector, base, and emitter electrodes of the HBT according to the tenth embodiment, and the wiring disposed thereon. First embodiment ( FIG. 1A The HBT of the tenth embodiment includes one emitter electrode E0. In contrast, the HBT of the tenth embodiment includes multiple emitter electrodes E0, for example, three emitter electrodes E0. The three emitter electrodes E0 are arranged in a row (in... Figure 25 The emitter wirings are arranged horizontally. A first-layer emitter wiring E1 is arranged corresponding to each emitter electrode E0. Multiple first-layer emitter wirings E1 are connected to a shared second-layer emitter wiring E2.

[0233] The base electrode B0 has a comb-like planar shape. Multiple comb-like portions of the base electrode B0 are respectively disposed between and on the outer sides of the emitter electrodes E0 at both ends. Connecting these multiple comb-like portions constitutes the base electrode B0. The base wiring B1 of the first layer is configured to partially overlap with the portion connecting the multiple comb-like portions.

[0234] Collector electrodes C0 are respectively disposed on the outer side of the comb-like portion at both ends of the base electrode B0. A first layer of collector wiring C1 is disposed corresponding to each collector electrode C0. The first layer of collector wiring C1 extends in a direction orthogonal to the electrode arrangement direction and is connected to the second layer of collector wiring C2.

[0235] Figure 26 yes Figure 25 The cross-sectional view at the dotted line 26-26. Three raised structures 57, consisting of a first contact layer 55 and a second contact layer 56, are arranged side by side along the in-plane direction on an emitter layer 54. An emitter electrode E0 is disposed on each of the three raised structures 57.

[0236] Base electrodes B0 are disposed between adjacent raised structures 57, and base electrodes B0 are also disposed on the outer sides of the raised structures 57 at both ends. Base electrode alloy layers 65 are formed corresponding to the base electrodes B0. The base electrodes B0 disposed on the outer sides of the raised structures 57 at both ends are similar to those in the first embodiment (…). Figure 1B Similar to the base electrode 53, it has a structure that protrudes outward compared to the edge of the base layer 53. An insulating film 62 is disposed between the base electrode B0 and the base layer 53.

[0237] Figure 26 the sectional structure of the point-and-line 2A-2A and the point-and-line 2B-2B is the same as that shown in the sectional view of the first embodiment. Figure 2A and Figure 2B .

[0238] Figure 27 is an equivalent circuit diagram of the HBT of the tenth embodiment. The HBT 80 of the tenth embodiment is configured by connecting three basic HBTs 81 in parallel, which are the HBT of the first embodiment. Figure 1A , Figure 1B , Figure 2A , Figure 2B ) as the basic HBT 81.

[0239] In the tenth embodiment, as in the first embodiment, by thinning the base layer 53, the excellent effect that the high-speed operation of the HBT can be achieved can be obtained.

[0240] [Modified Example of the Tenth Embodiment]

[0241] In the tenth embodiment, three basic HBTs 81 are connected in parallel Figure 27 ), but two or more than four basic HBTs 81 can be connected in parallel. In the tenth embodiment, the HBT of the first embodiment is used as the basic HBT 81, and a plurality of basic HBTs 81 on the same substrate are connected in parallel. The HBT of each of the second to fifth embodiments can be used as the basic HBT 81, and a plurality of basic HBTs 81 can be connected in parallel as in the tenth embodiment.

[0242] In the tenth embodiment, as in the second embodiment Figure 10A , Figure 10B , Figure 10C ), the insulating film 62 covering the lower surface of the protruding portion of the base electrode B0 is removed.

[0243] [Eleventh Embodiment]

[0244] Next, the HBT of the eleventh embodiment will be described with reference to Figure 28 and Figure 29 . Hereinafter, the description of the configuration common to the HBT of the tenth embodiment Figure 25 , Figure 26 , Figure 27 ) will be omitted.

[0245] Figure 28 is a plan view of the electrodes to which the collector, the base, and the emitter of the HBT of the eleventh embodiment are connected, and the wiring provided thereon. In the tenth embodiment, the HBT of the first embodiment Figure 1A , Figure 1B , Figure 2A ,Figure 2B ) as the basic HBT81 ( Figure 27 ), and multiple basic HBT81s are connected in parallel. In the eleventh embodiment, the HBT of the sixth embodiment ( Figure 17A , Figure 17B , Figure 18A , Figure 18B (As a basic HBT81)

[0246] In the tenth embodiment, the base electrode B0 ( Figure 25 It has a comb-like planar shape. In the eleventh embodiment, it has a ladder-like planar shape with the front ends of a plurality of comb-like portions that are interconnected with each other, forming a base electrode B0. Emitter electrodes E0 are respectively disposed in a plurality of regions enclosed by adjacent comb-like portions, portions connecting the bases of the comb-like portions to each other, and portions connecting the front ends of the comb-like portions to each other. Figure 28 In the diagram, a denser shadow is applied to the base electrode B0, and a lighter shadow is applied to the emitter electrode E0. The configuration of the collector electrode C0, the first-layer collector wiring C1, the emitter wiring E1, the base wiring B1, the second-layer collector wiring C2, and the second-layer emitter wiring E2 is consistent with the tenth embodiment. Figure 25 The electrodes and wiring configurations are the same.

[0247] Figure 29 yes Figure 28 A cross-sectional view at the dotted line 29-29. In the tenth embodiment, the emitter electrode E0 is positioned inside the platform structure 57 when viewed from above. In contrast, in the eleventh embodiment, the HBT (in the sixth embodiment) Figure 17B Similar to the 57, the emitter electrode E0 protrudes outwards from the edge of the platform structure 57. A base electrode B0 is disposed between adjacent emitter electrodes E0. The edges of the base electrode B0 on ​​both sides coincide with the edges of the emitter electrodes E0 on either side of the base electrode B0 when viewed from above.

[0248] The structure of the base electrode B0, which is respectively disposed on the outside of the emitter electrode E0 at both ends, is similar to that of the HBT in the sixth embodiment. Figure 17B The structure of the base electrode B0 is the same as that of the base electrode B0. An insulating film 62 is disposed between the base electrode B0 and the base layer 53. The insulating film 62 is not disposed in the region inside the base electrode B0 compared to the inner edge at both ends.

[0249] In the eleventh embodiment, as in the sixth embodiment, by thinning the base layer 53, an excellent effect such as enabling high-speed operation of the HBT can be obtained.

[0250] [Modifications of the eleventh embodiment]

[0251] In the eleventh embodiment, three basic HBT81s are connected in parallel.Figure 27 ), but two or more basic HBTs 81 (n = 2, 3, 4,...) can be connected in parallel. In the eleventh embodiment, the HBT of the sixth embodiment is used as the basic HBT 81, and a plurality of basic HBTs 81 on the same substrate are connected in parallel. The HBT of each of the seventh to ninth embodiments can be used as the basic HBT 81, and a plurality of basic HBTs 81 can be connected in parallel in the same manner as in the eleventh embodiment. Figure 27

[0252] In the eleventh embodiment, the insulating film 62 covering the lower surface of the protruding portion of the base electrode B0 can be omitted, as in the configuration of the second embodiment (n = 1) ( Figure 10A Figure 10B Figure 10C

[0253] [Twelfth Embodiment]

[0254] Next, the high-frequency power amplifier module of the twelfth embodiment will be described with reference to FIG. 12 and FIG. 13. The high-frequency power amplifier module of the twelfth embodiment uses the HBT of any one of the first to eleventh embodiments. Figure 30A Figure 30B FIG. 12 is a block diagram of a high-frequency power amplifier module 100 of the twelfth embodiment. The high-frequency power amplifier module 100 of the twelfth embodiment includes an amplification IC 130, a control IC 140, inductors 135, 136, and matching circuits 131, 133. These elements are mounted on a mounting substrate 150.

[0255] Figure 30A The amplification IC includes a primary HBT 110, an output stage HBT 120, and a matching circuit 132 interposed therebetween. A high-frequency signal input from a high-frequency input terminal 101 is output to a high-frequency output terminal 102 via the matching circuit 131, the primary HBT 110, the matching circuit 132, the output stage HBT 120, and the matching circuit 133. A power supply voltage Vcc is applied to a collector terminal 114 of the primary HBT 110 and a collector terminal 124 of the output stage HBT 120 from a power supply terminal 104 and a power supply terminal 105 via the inductor 135 and the inductor 136, respectively.

[0256] A control signal is input from a plurality of control terminals 103 to the control IC 140. The control IC 140 applies a bias signal to a bias terminal 112 of the primary HBT 110 and a bias terminal 122 of the output stage HBT 120.

[0257] A control signal is input from a plurality of control terminals 103 to the control IC 140. The control IC 140 applies a bias signal to a bias terminal 112 of the primary HBT 110 and a bias terminal 122 of the output stage HBT 120.

[0258] Figure 30B ​​​​​is an equivalent circuit diagram of the output stage HBT 120. A plurality of elementary HBTs 125 are connected in parallel. The elementary HBTs 125 use the HBT of any one of the first embodiment to the eleventh embodiment.

[0259] The bases of the plurality of elementary HBTs 125 are respectively connected to the bias terminal 122 via ballast resistors 126. The ballast resistors 126 prevent thermal runaway and protect the elementary HBTs 125 from being destroyed. Also, the bases of the plurality of elementary HBTs 125 are respectively connected to the matching circuit 132 via DC cut capacitors 127. The DC cut capacitors 127 are provided for each elementary HBT 125 in order to make the ballast resistors 126 function effectively. Figure 30A

[0260] The collectors of the plurality of elementary HBTs 125 are connected to the matching circuit 133 and the collector terminal 124. Figure 30A Figure 30A

[0261] The primary HBT 110 also has a similar circuit configuration to the output stage HBT 120. Generally, the number of elementary HBTs connected in parallel in the primary HBT 110 is less than the number of elementary HBTs 125 of the output stage HBT 120.

[0262] The high frequency power amplifier module of the twelfth embodiment uses the HBT of any one of the first embodiment to the eleventh embodiment, so high speed operation can be performed by thinning the base layer of each HBT.

[0263] The above-described embodiments are examples, and of course, substitution or combination of parts of the configurations shown in different embodiments can be performed. The same effects resulting from the same configurations of a plurality of embodiments are not mentioned in order for each embodiment. Also, the present application is not limited to the above-described embodiments. For example, various changes, improvements, combinations, and the like can be performed by those skilled in the art.​​​

Claims

1. A bipolar transistor, wherein, have: Collector layer, which is formed on a substrate made of compound semiconductor; A base layer is formed on the aforementioned current collector layer; An emitter layer is formed on the aforementioned base layer; The base electrode has a portion disposed on a portion of the emitter layer, and another portion extending in a plan view toward the edge of the base layer above the emitter layer and the base layer. as well as An insulating film is disposed between the other portion of the base electrode and a portion of the emitter layer, and between the other portion of the base electrode and a portion of the base layer.

2. The bipolar transistor according to claim 1, wherein, The aforementioned base electrode protrudes outward from the edge of the aforementioned collector layer.

3. The bipolar transistor according to claim 1, wherein, The aforementioned base electrode protrudes outward from the edge of the aforementioned base layer.

4. The bipolar transistor according to claim 1, wherein, It also has: An alloy layer that extends from a portion of the base electrode along the thickness direction through the emitter layer and reaches the base layer.

5. The bipolar transistor according to claim 4, wherein, The alloy contains at least one element constituting the base electrode and an element constituting the emitter layer and the base layer.

6. The bipolar transistor according to claim 1, wherein, A portion of the aforementioned base layer does not overlap with the aforementioned emitter layer.

7. The bipolar transistor according to claim 1, wherein, The upper side surface of the aforementioned current collector layer is continuous with the side surface of the aforementioned base layer, and The remaining lower side of the aforementioned collector layer is located outside the side of the aforementioned base layer.

8. The bipolar transistor according to claim 1, wherein, The aforementioned collector layer has an intermediate collector layer, which is disposed at the middle position in the thickness direction and is made of a semiconductor material having etching characteristics different from those of the semiconductor material of the other part of the aforementioned collector layer. The side surface of the aforementioned current collector layer disposed on the upper part of the aforementioned intermediate current collector layer is continuous with the side surface of the aforementioned base layer, and The lower side of the aforementioned collector layer, located below the intermediate collector layer, is situated outside the side of the aforementioned base layer.

9. The bipolar transistor according to claim 1, wherein, It also has: A sub-collector layer disposed between the substrate and the collector layer. The aforementioned sub-collector electrode layer has a first sub-collector electrode layer disposed on the aforementioned substrate and a second sub-collector electrode layer disposed on the aforementioned first sub-collector electrode layer, and The second sub-collector layer has etching characteristics that are different from those of a portion of the collector layer, and the portion is in contact with the second sub-collector layer.

10. The bipolar transistor according to claim 1, wherein, It also has: A contact layer, which is disposed on a portion of the aforementioned emitter layer; and An emitter electrode is disposed on the contact layer and protrudes outward from the edge of the contact layer. The front end of the protruding portion of the aforementioned emitter electrode coincides with the edge of the aforementioned base electrode in the plan view.

11. The bipolar transistor according to claim 1, wherein, It also has: A contact layer is disposed on a portion of the aforementioned emitter layer; The aforementioned contact layer has multiple semiconductor layers, which are arranged in an in-plane direction on the upper surface of the aforementioned emitter layer, and The base electrode described above has a portion disposed between the plurality of semiconductor layers forming the contact layer described above.

12. The bipolar transistor according to claim 11, wherein, The base electrode is disposed between the plurality of semiconductor layers, and a portion thereof is disposed on a portion of the emitter layer. Another portion of the aforementioned base electrode, disposed between the plurality of semiconductor layers, extends in a plan view towards the edge of the plurality of semiconductor layers above the aforementioned emitter layer and the aforementioned base layer; and The bipolar transistor also has an insulating film disposed between the other portion of the base electrode disposed between the plurality of semiconductor layers and the emitter layer, and between the other portion of the base electrode disposed between the plurality of semiconductor layers and a portion of the base layer.

13. The bipolar transistor according to claim 1, wherein, It also has: Multiple emitter electrodes are connected to the aforementioned emitter layer and arranged in an in-plane direction. The base electrode described above has a portion disposed between the emitter electrodes described above.

14. The bipolar transistor according to claim 13, wherein, The base electrode is disposed between the emitter electrodes, and a portion thereof is disposed on a portion of the emitter layer. Another portion of the base electrode, disposed between the emitter electrodes, extends toward the edge of the emitter electrodes in the plan view above the emitter layer and the base layer. as well as The bipolar transistor also has an insulating film disposed between another portion of the base electrode and the emitter layer and a portion of the base layer.

15. The bipolar transistor according to claim 1, wherein, The base layer has a length extending in the longitudinal direction and a width extending in the transverse direction perpendicular to the longitudinal direction, and The base electrode extends in a plan view toward the edge of the base layer above the emitter layer and the base layer, extending substantially to the entire length of the base layer.

16. A radio frequency power amplifier module, wherein, have: An amplifier IC having a bipolar transistor, wherein the bipolar transistor has: Collector layer, which is formed on a substrate made of compound semiconductor; A base layer is formed on the aforementioned current collector layer; An emitter layer is formed on the aforementioned base layer; The base electrode has a portion disposed on a portion of the emitter layer, and another portion extending in a plan view toward the edge of the base layer above the emitter layer and the base layer. as well as An insulating film is disposed between another portion of the base electrode and the emitter layer and a portion of the base layer; and The control IC controls the operation of the aforementioned bipolar transistor.

17. The RF power amplifier module according to claim 16, wherein, The aforementioned base layer has a length extending in the longitudinal direction and a width extending in a transverse direction perpendicular to the aforementioned longitudinal direction, and The base electrode extends in a plan view toward the edge of the base layer above the emitter layer and the base layer, extending substantially to the entire length of the base layer.

18. The RF power amplifier module according to claim 16, wherein, The aforementioned base electrode protrudes outward from the edge of the aforementioned collector layer.

19. The RF power amplifier module according to claim 16, wherein, The aforementioned base electrode protrudes outward from the edge of the aforementioned base layer.

20. The RF power amplifier module according to claim 16, wherein, The bipolar transistor described above also has: An alloy layer extends from a portion of the base electrode along the thickness direction through the emitter layer and reaches the base layer.

21. A bipolar transistor, wherein, have: Collector layer, which is on the substrate; A base layer, which is located on the aforementioned collector layer; An emitter layer, which is situated on the aforementioned base layer; and An insulating film is disposed above the aforementioned emitter layer and the aforementioned base layer; The aforementioned insulating film has an opening. A base electrode is disposed on the insulating film and in the opening, and the base electrode is arranged asymmetrically with respect to the opening. The bipolar transistor also has a second insulating film, which is formed in the shape of the edge exposed at the pn junction interface between the collector layer and the base layer to protect the edge exposed at the pn junction interface between the collector layer and the base layer, and the second insulating film is disposed below a portion of the base electrode that protrudes outward from the edge of the base layer.

22. The bipolar transistor of claim 21, wherein, The opening is farther from the outer edge of the base electrode than from the inner edge of the base electrode.

23. The bipolar transistor according to claim 21, wherein, The aforementioned base electrode protrudes outward from the edge of the aforementioned collector layer.

24. The bipolar transistor of claim 21, wherein, The aforementioned base electrode protrudes outward from the edge of the aforementioned base layer.

25. The bipolar transistor according to claim 21, wherein, The second insulating film is made of the same material as the insulating film.

26. The bipolar transistor of claim 21, wherein, The edge of the insulating film is substantially the same as the edge of the base layer.

27. The bipolar transistor of claim 21, wherein, It also has: An alloy layer that extends from the base electrode in the opening along the thickness direction through the emitter layer and reaches the base layer.

28. The bipolar transistor of claim 27, wherein, The alloy layer contains at least one element constituting the base electrode and an element constituting the emitter layer and the base layer.

29. The bipolar transistor of claim 21, wherein, A portion of the aforementioned base layer does not overlap with the aforementioned emitter layer.

30. The bipolar transistor according to claim 21, wherein, The aforementioned base layer has a length extending in the longitudinal direction and a width extending in a transverse direction perpendicular to the longitudinal direction, and The base electrode extends in a plan view toward the edge of the base layer above the emitter layer and the base layer, extending substantially to the entire length of the base layer.

31. The bipolar transistor according to claim 21, wherein, The upper side surface of the aforementioned current collector layer is continuous with the side surface of the aforementioned base layer, and The remaining lower side of the aforementioned collector layer is located outside the side of the aforementioned base layer.

32. The bipolar transistor according to claim 21, wherein, It also has: A sub-collector layer disposed between the substrate and the collector layer. in, The aforementioned sub-collector electrode layer has a first sub-collector electrode layer disposed on the aforementioned substrate and a second sub-collector electrode layer disposed on the aforementioned first sub-collector electrode layer, and The second sub-collector layer has etching characteristics that are different from those of a portion of the collector layer, and the portion is in contact with the second sub-collector layer.

33. A bipolar transistor, wherein, have: Collector layer, which is on the substrate; A base layer, which is located on the aforementioned collector layer; An emitter layer, which is located on the aforementioned base layer; An insulating film disposed on the aforementioned emitter layer and the aforementioned base layer; and The base electrode is disposed on the insulating film and protrudes outward from the edge of the base layer or the current collector layer. The bipolar transistor also has a second insulating film, which is formed in the shape of the edge exposed at the pn junction interface between the collector layer and the base layer to protect the edge exposed at the pn junction interface between the collector layer and the base layer, and the second insulating film is disposed below a portion of the base electrode that protrudes outward from the edge of the base layer.

34. The bipolar transistor according to claim 33, wherein, The second insulating film is made of the same material as the insulating film.

35. The bipolar transistor according to claim 33, wherein, The edge of the insulating film is substantially the same as the edge of the base layer.

36. The bipolar transistor according to claim 33, wherein, A portion of the aforementioned base layer does not overlap with the aforementioned emitter layer.

37. The bipolar transistor according to claim 33, wherein, The upper side surface of the aforementioned current collector layer is continuous with the side surface of the aforementioned base layer, and The remaining lower side of the aforementioned collector layer is located outside the side of the aforementioned base layer.

38. The bipolar transistor according to claim 33, wherein, It also has: A sub-collector layer disposed between the substrate and the collector layer. The aforementioned sub-collector electrode layer has a first sub-collector electrode layer disposed on the aforementioned substrate and a second sub-collector electrode layer disposed on the aforementioned first sub-collector electrode layer, and The second sub-collector layer has etching characteristics that are different from those of a portion of the collector layer, and the portion is in contact with the second sub-collector layer.

39. The bipolar transistor according to claim 33, wherein, It also has: An alloy layer extends from a portion of the base electrode along the thickness direction through the emitter layer and reaches the base layer.

Images