High voltage semiconductor components

Abstract

The present invention discloses a high-voltage semiconductor element, wherein the high-voltage element comprises: a semiconductor substrate of a first conductivity type. A deep well layer of a second conductivity type, opposite to the first conductivity type. The deep well layer is formed on the semiconductor substrate and has a surface. A field isolation layer is formed on the surface, separating a source active region and a drain active region. A source metal internal connection contacts the surface in the source active region to form an ohmic contact, serving as a source of the high-voltage element. A drain metal internal connection contacts the surface in the drain active region, serving as a drain of the high-voltage element. A first well layer of the first conductivity type is formed on the surface and is located between the source active region and the field isolation layer. A bottom layer of the first conductivity type is formed at a bottom of the deep well layer. A control gate is formed on the field isolation layer, serving as a gate of the high-voltage element. A gate voltage of the control gate can control a conductive channel provided by the deep well layer, which electrically connects the drain to the source.

Description

Technical Field

[0001] The present invention relates to a high voltage semiconductor element, and in particular to a semiconductor element whose drain can withstand a high voltage. Background Art

[0002] In order to achieve fast computing and lightweight products, semiconductor products are often made more and more precise and fragile. However, semiconductor products often need to target different application systems, and their input and output ports must face special environments and have some special requirements. For example, in high-power applications, some electronic products operate in a connection network with switches, inductors and capacitors, which requires the input and output ports of electronic products to be able to withstand large instantaneous changes in voltage and current. These specifications will bring new challenges to semiconductor component designers. Summary of the invention

[0003] An embodiment of the present invention provides a high-voltage element. A semiconductor substrate is of a first conductivity type. A deep well layer is of a second conductivity type, opposite to the first conductivity type. The deep well layer is formed on the semiconductor substrate and has a surface. A field isolation layer is formed on the surface, separating a source active region and a drain active region. A source metal internal connection contacts the surface in the source active region to form an ohmic contact, serving as a source of the high-voltage element. A drain metal internal connection contacts the surface in the drain active region, serving as a drain of the high-voltage element. A first well layer is of the first conductivity type, formed on the surface, and located between the source active region and the field isolation layer. A bottom layer is of the first conductivity type, formed at a bottom of the deep well layer. A control gate is formed on the field isolation layer, serving as a gate of the high-voltage element. A gate voltage of the control gate can control a conductive channel provided by the deep well layer, which electrically connects the drain to the source. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1 is a schematic diagram of a high voltage component 100;

[0005] Figure 2A A schematic diagram of a high voltage component 200a implemented in the present invention;

[0006] Figure 2B Schematic diagram of a conductive channel PTH provided by the N-type deep well layer 206 between the N-type heavily doped layer 213 b and the N-type well layer 210 in the high voltage device 200 a ;

[0007] Figure 2C is a symbolic diagram of a high voltage component 200a;

[0008] Figure 3 and Figure 4 A schematic diagram of two high voltage components implemented by the present invention;

[0009] Figure 5A A schematic diagram of a high voltage component 200d implemented in the present invention;

[0010] Figure 5B is a symbolic diagram of a high voltage component 200d;

[0011] Figure 6 It is a schematic diagram of a high voltage component 200e implemented in the present invention.

[0012] Explanation of symbols

[0013] 100 High voltage components

[0014] 102 P-type substrate

[0015] 104 P-type epitaxial layer

[0016] 106, 206N type deep well layer

[0017] 108a, 108b P-type well layer

[0018] 110N type well layer

[0019] 111a, 111b P-type heavily doped layer

[0020] 112a, 112b, 112c field isolation layer

[0021] 113a, 113b N-type heavily doped layer

[0022] 114 Gate Oxide

[0023] 116 Polysilicon layer

[0024] 118 Contact embolism

[0025] 120a, 120b, 120c, 120d metal wires

[0026] 200a, 200b, 200c, 200d, 200e high voltage components

[0027] 202 P-type substrate

[0028] 204 P-type epitaxial layer

[0029] 206 N-type deep well layer

[0030] 208a, 208b P-type well layer

[0031] 210N type well layer

[0032] 211a, 211b P-type heavily doped layer

[0033] 212a, 212b, 212c field isolation layer

[0034] 213a, 213b N-type heavily doped layer

[0035] 218 Contact Embolism

[0036] 220a, 220b, 220c, 220d metal wire

[0037] 222, 222a, 222b, 222c P-type bottom layer

[0038] 226a, 226b P-type lightly doped layer

[0039] BTP, BBT edge

[0040] CR distance

[0041] DRAIN

[0042] DS Schottky contact

[0043] FS Surface

[0044] GATE

[0045] OD1, OD2, OD3, OD4 active areas

[0046] PTH conductive channel

[0047] SOURCE

[0048] SUB substrate electrode DETAILED DESCRIPTION

[0049] In this specification, there are some identical symbols, which represent components with the same or similar structure, function, and principle, and those with general knowledge in the industry can infer based on the teachings of this specification. For the sake of brevity of the specification, components with the same symbols will not be repeated.

[0050] Figure 1 The high voltage device 100 is equivalent to an N-type junction field effect transistor (JFET) formed on a P-type substrate 102. The high voltage device 100 has a drain DRAIN, a source SOURCE, and a gate GATE. The drain DRAIN of the high voltage device 100 can withstand a high voltage input.

[0051] A P-type epitaxial layer 104 is formed on the P-type substrate 102. A plurality of field isolation layers 112a, 112b, and 112c are formed on the surface of the P-type epitaxial layer 104. Each field isolation layer is used to separate different active regions. The gate structure and source-drain heavily doped layer of the metal oxide semiconductor transistor can be formed in the active region. The field isolation layer 112a isolates the P-type heavily doped layer 111a from the N-type heavily doped layer 113a, and the two serve as ohmic contacts between the P-type well layer 108b and the N-type well layer 110, respectively. The field isolation layer 112b is between the P-type heavily doped layer 111b and the N-type heavily doped layer 113a. The field isolation layer 112c is between the gate oxide layer 114 and the N-type heavily doped layer 113b. The P-type heavily doped layer 111b serves as an ohmic contact of the P-type well layer 108a, and the N-type heavily doped layer 113b serves as an ohmic contact of the N-type deep well layer (deep N well) 106. The N-type deep well layer 106 can be formed by lightly doping a local P-type epitaxial layer 104, and the bottom of the N-type deep well layer 106 can selectively contact the P-type substrate 102.

[0052] A polysilicon layer 116 is formed on the gate oxide layer 114 and the isolation layer 112c, and is connected to the patterned metal line 120c and the P-type heavily doped layer 111b through a contact plug 118. The metal line 120c and the contact plug 118 serve as the gate GATE of the high-voltage component 100, and also as a metal interconnection, which can be electrically connected to other electronic circuits. Similarly, the metal line 120b and the related contact plug 118 serve as the source SOURCE of the high-voltage component 100, and the metal line 120d and the related contact plug 118 serve as the drain DRAIN of the high-voltage component 100. The metal line 120a and the related contact plug 118 serve as the substrate electrode SUB, providing electrical contact with the substrate 102. In one embodiment, the substrate electrode SUB is electrically connected to a ground power supply.

[0053] The gate-to-source voltage of the gate GATE to the source SOURCE can control the width of the depletion region on the PN junction between the P-type well layer 108a and the N-type deep well layer 106, thereby controlling the conductive path provided by the N-type deep well layer 106 from the N-type heavily doped layer 113b to the N-type well layer 110. The polysilicon layer 116 located on the gate oxide layer 114 and the isolation layer 112c can serve as a field plate to fine-tune the electric field distribution in the N-type deep well layer 106, thereby enhancing the drain-to-source breakdown voltage.

[0054] Figure 1 The high voltage element 100 in the circuit has a problem: gate leakage. When the source SOURCE is lower than the gate GATE voltage momentarily during circuit operation, the PN junction between the P-type well layer 108a and the N-type deep well layer 106 presents a forward bias, resulting in a momentary large current flowing from the gate GATE to the source SOURCE, which is called gate leakage. Gate leakage is not allowed in some circuit applications.

[0055] Figure 2A The high voltage device 200a is implemented according to the present invention. The high voltage device 200a has a drain DRAIN, a source SOURCE, and a gate GATE. Figure 1 The high-voltage component 100 of the present invention has the same or similar features as those of the high-voltage component 100 , which can be understood by referring to the description of the high-voltage component 100 and will not be described in detail.

[0056] Field isolation layers 212a, 212b, and 212c are formed on the surface FS of the N-type deep well layer 206. The field isolation layer 212a separates the active regions OD4 and OD3, the field isolation layer 212b separates the active regions OD3 and OD2, and the field isolation layer 212c separates the active regions OD2 and OD1. Figure 2A In the embodiment, only one heavily doped layer is formed in each active region, but the present invention is not limited thereto. In other embodiments, several heavily doped layers and / or gate oxide layers may be formed in the active region.

[0057] A P-type heavily doped layer 211b is formed in the active region OD4 and is located in the P-type well layer 208b, which is used to provide electrical connection between the P-type well layer 208b, the P-type epitaxial layer 204 and the P-type substrate 202, and the metal line 220a. The metal line 220a and the related contact plug 218 serve as the substrate electrode SUB, providing electrical contact with the substrate 202, and can be electrically connected to a ground power supply.

[0058] An N-type heavily doped layer 213a is formed in the active region OD3 as an ohmic contact between the N-type well layer 210 and the contact plug 218; a P-type heavily doped layer 211a is formed in the active region OD2 as an ohmic contact between the P-type well layer 208a and the contact plug 218. The P-type well layer 208a partially overlaps with the field isolation layer 212c, and is partially located between the field isolation layer 212c and the N-type heavily doped layer 213a (ohmic contact of the N-type well layer 210). The N-type heavily doped layer 213a and the P-type heavily doped layer 211a are short-circuited to each other through the related contact plug 218 and are electrically connected to the metal line 220b. The metal line 220b and the related contact plug 218 can be regarded as a source metal interconnection, which serves as the source SOURCE of the high-voltage element 200a. The source metal interconnection is equivalent to contacting the surface of the P-type well layer 208a. The active region OD3 can be regarded as a source active region. In one embodiment, the field isolation layer 212b can be omitted, and the P-type heavily doped layer 211a and the N-type heavily doped layer 213a are located in the same source active region.

[0059] An N-type heavily doped layer 213b is formed in the active region OD1, serving as an ohmic contact of the N-type deep well layer 206, and is electrically connected to a metal line 220d through a related contact plug 218. The metal line 220d can be regarded as a drain metal internal connection, contacting the surface of the N-type heavily doped layer 213b in the active region OD1, serving as the drain DRAIN of the high-voltage element 200a. The active region OD1 can be regarded as a drain active region.

[0060] The polysilicon layer 216 is formed as a control gate on the field isolation layer 212c and is electrically connected to the metal line 220c through the related contact plug 218, which can be regarded as a gate metal inner connection and serves as the gate GATE of the high voltage element 200a. In one embodiment, there is no polysilicon layer 216 below. Figure 1 The gate oxide layer 114 is thin. In this way, the field isolation layer 212c can withstand a relatively large gate-source voltage of the gate GATE to the source SOURCE.

[0061] A P-type bottom layer 222 is formed by burying the bottom of the N-type deep well layer 206. Figure 2A As shown in the cross-sectional view of , the P-type bottom layer 222 may be partially located in the N-type deep well layer 206 and partially located in the P-type substrate 202. Figure 2AAs shown, the P-type bottom layer 222 at least partially overlaps with the field isolation layer 212c, and maintains a distance CR with the active area OD1. In other words, the P-type bottom layer 222 does not overlap with the active area OD1. The P-type bottom layer 222 also partially overlaps with the P-type well layer 208a. In terms of manufacturing, for example, before the P-type epitaxial layer 204 is formed, a P-type dopant can be doped in a predetermined area on the P-type substrate 202, and then after the P-type epitaxial layer 204 is formed, the previous P-type dopant is diffused through heat treatment to form the P-type bottom layer 222.

[0062] Figure 2B The high voltage device 200 a is shown in which a conductive channel PTH provided by the N-type deep well layer 206 between the N-type heavily doped layer 213 b and the N-type well layer 210 electrically connects the drain DRAIN to the source SOURCE. Figure 2B The edges BTP and BBT of the two depletion regions are also shown, which roughly determine the width of the conductive channel PTH. When the edge BTP contacts the BBT, it indicates that the channel is pinched off or the current is cut off. The voltage on the gate GATE can control the position of the edge BTP. For example, when the gate-source voltage of the gate GATE to the source SOURCE is more negative, the depletion region under the field isolation layer 212c is wider, and the edge BTP is closer to the edge BBT. The P-type well layer 208a can reduce the surface field of the N-type deep well layer 206 and increase the drain-source breakdown voltage. The position, range, and concentration of the P-type bottom layer 222 can also be used to determine the position of the edge BBT and adjust the channel pinch off voltage. In other words, the P-type bottom layer 222 can also increase the drain-source breakdown voltage of the high-voltage component 200a.

[0063] Figure 2C A symbolic diagram showing a high-voltage device 200a is shown, which is represented as a depletion mode metal-oxide-semiconductor (MOS) transistor. The gate GATE is located on the field isolation layer 212c, and can control the conductive channel PTH located in the N-type deep well layer 206. When the gate-source voltage is 0V, the conductive channel PTH can conduct current, so the high-voltage device 200a is a depletion mode metal-oxide-semiconductor transistor, but the high-voltage device 200a uses a thick field isolation layer 212c as a gate oxide layer.

[0064] High voltage component 200a will not have Figure 1The gate leakage current problem of the high-voltage component 100 is solved. The P-type well layer 208a is electrically connected to the N-type well layer 210 through the metal line 220b and the related contact plug 218. The P-type well layer 208a and the N-type well layer 210 are both electrically connected to the source SOURCE. Therefore, the P-type well layer 208a and the N-type well layer 210 are at the same potential. The gate GATE of the high-voltage component 200a is located on the field isolation layer 212c, and is not short-circuited to the P-type well layer 208a, that is, it is not electrically connected to the P-type well layer 208a. Therefore, even if the voltage of the gate GATE of the high-voltage component 200a is higher than the source SOURCE of the high-voltage component 200a, as long as the field isolation layer 212c is not broken down, there will be no leakage current from the gate GATE to the source SOURCE.

[0065] Figure 3 The high voltage component 200b implemented according to the present invention has the same or similar features as the high voltage components 100 and 200a, which can be understood by referring to the previous description and will not be described in detail. Figure 2A Unlike the single P-type bottom layer 222 in the high-voltage component 200a, the high-voltage component 200b has a plurality of P-type bottom layers 222a, 222b, and 222c, each of which at least partially overlaps with the field isolation layer 212c and does not overlap with the active area OD1. As long as the number and position of the P-type bottom layers are properly designed, the drain-source breakdown voltage of the high-voltage component 200b can be increased.

[0066] Figure 4 The high voltage component 200c implemented according to the present invention has the same or similar features as the high voltage components 100, 200a and 200b, which can be understood by referring to the previous description and will not be described in detail. Figure 2A The P-type well layer 208a short-circuited to the N-type well layer 210 in the high voltage element 200a is different. Figure 4 The P-type well layer 208a in the circuit is electrically floating. The P-type well layer 208a is not electrically in contact with any metal interconnection. Even if it is electrically in contact with a metal interconnection, the metal interconnection does not provide a fixed voltage to the P-type well layer 208a. Figure 4 The P-type well layer 208 a is electrically floating. The P-type well layer 208 a may be stabilized at approximately the same voltage as the N-type deep well layer 206 due to very little PN junction leakage current between the P-type well layer 208 a and the N-type deep well layer 206 . Figure 4 The electrically floating P-type well layer 208 a can also reduce the surface electric field of the N-type deep well layer 206 .

[0067] Figure 5A The high voltage component 200d implemented according to the present invention has the same or similar features as the high voltage components 100, 200a, 200b and 200c, which can be understood by referring to the previous description and will not be described in detail. Figure 2AThe drain electrode DRAIN in the high voltage element 200a is electrically short-circuited to the N-type deep well layer 206 through the N-type heavily doped layer 213b. Figure 2A Different, Figure 5A In the high voltage element 200d in FIG. 1 , the contact plug 218 (i.e., a part of the drain metal interconnect) under the metal line 220d directly contacts the surface of the N-type deep well layer 206 in the active region OD1 to form a Schottky contact DS. The Schottky contact DS is surrounded by the P-type lightly doped layers 226a and 226b, and the P-type lightly doped layers 226a and 226b are also electrically shorted to the drain DRAIN. In an unshown top view, the P-type lightly doped layers 226a and 226b may be located in the same P-type lightly doped region. Figure 5B A symbolic diagram showing a high voltage device 200d includes a depletion metal oxide semiconductor transistor and a Schottky diode formed by a Schottky junction DS. The Schottky junction DS can prevent reverse current from flowing from the source SOURCE to the drain DRAIN and provide a relatively low forward voltage. The P-type lightly doped layers 226a and 226b can increase the breakdown voltage of the Schottky diode.

[0068] Figure 6 The high voltage device 200e implemented according to the present invention has a plurality of P-type bottom layers 222a, 222b, 222c, an electrically floating P-type well layer 208a, and a Schottky junction DS. The high voltage device 200e is the same or similar to the high voltage devices 100, 200a, 200b, 200c, and 200d, which can be known by referring to the previous description and will not be described in detail.

[0069] The above descriptions are only preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A high voltage component, characterized in that: Contains: A semiconductor substrate of a first conductivity type; A deep well layer, which is of a second conductivity type and opposite to the first conductivity type, is formed on the semiconductor substrate and has a surface; A field isolation layer is formed on the surface to separate the source active region and the drain active region; A source metal interconnect contacts the surface in the source active region to form an ohmic contact, serving as a source of the high voltage element; A drain metal interconnect contacts the surface in the drain active region and serves as a drain of the high voltage element; A first well layer, of the first conductivity type, formed on the surface and located between the ohmic contact and the field isolation layer; A bottom layer, of the first conductivity type, formed at the bottom of the deep well layer; as well as A control gate, formed on the field isolation layer and contacting the field isolation layer, serving as a gate of the high voltage element; The gate voltage of the control gate can control the conductive channel provided by the deep well layer, which electrically connects the drain to the source. The bottom layer at least partially overlaps with the field isolation layer and does not overlap with the drain active region. The bottom layer at least partially overlaps with the first well layer. The source metal interconnect contacts the first well layer or the first well layer is electrically floating.

2. The high voltage component according to claim 1, wherein: The high voltage element comprises a plurality of bottom layers, each of which at least partially overlaps with the field isolation layer and does not overlap with the drain active region.

3. The high voltage component according to claim 1, wherein: The drain metal inner connection contacts the surface of the deep well layer to form a Schottky contact.

4. The high voltage component according to claim 3, further comprising: At least two first doped layers of the first conductivity type are formed on the surface and surround the Schottky contact.

5. The high voltage component according to claim 1, further comprising: The drain doping layer is of the second conductivity type, located in the drain active region, formed on the surface, and used to provide an ohmic contact between the drain metal inner connection and the deep well layer.

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