High-brightness light-emitting diode chip and method for preparing same

Abstract

The present disclosure provides a high-brightness light-emitting diode chip and a method for manufacturing the same. The high-brightness light-emitting diode chip includes: a substrate, a first semiconductor layer, a light-emitting layer, a second semiconductor layer, a current blocking layer, a transparent conductive layer, a first electrode, and a second electrode; the substrate, the first semiconductor layer, the light-emitting layer, the second semiconductor layer, and the current blocking layer are stacked in sequence, the transparent conductive layer is located on the surface of the current blocking layer and extends to the surface of the second semiconductor layer, the second electrode is located on the surface of the transparent conductive layer, the orthographic projection of the second electrode on the substrate is located within the orthographic projection of the current blocking layer on the substrate, and the first electrode is connected to the first semiconductor layer; the second electrode includes a pad and finger bars, one end of a finger bar is connected to the pad, and in the direction from the pad to the finger bar, the thickness of the current blocking layer gradually decreases in the direction perpendicular to the bearing surface of the substrate. The present disclosure can improve the problem that the pad connected to the external circuit on the electrode is easily damaged and enhance the reliability of the chip.

Description

Technical Field

[0001] The present disclosure relates to the field of optoelectronic manufacturing technologies, and particularly to a high-brightness light-emitting diode chip and a method for preparing the same. Background Art

[0002] As a highly influential new product in the optoelectronic industry, a light-emitting diode (LED for short) has the characteristics of small volume, long service life, rich and colorful colors, low energy consumption, etc., and is widely used in fields such as lighting, display screens, signal lights, backlights, toys, etc. The core structure of an LED is a light-emitting diode chip, and the production of the light-emitting diode chip has a great influence on the optoelectronic characteristics of the LED.

[0003] In related technologies, a light-emitting diode chip generally includes a substrate, an n-type semiconductor layer, an active layer, and a p-type semiconductor layer that are stacked in sequence. Usually, a p electrode is further provided on the surface of the p-type semiconductor layer, and a current blocking layer is also provided between the p-type semiconductor layer and the p electrode. The current blocking layer blocks the current from directly flowing to the position below the p electrode, so that the current diffuses to various positions of the p-type semiconductor layer.

[0004] However, during the use of the chip, the pad connecting the external circuit on the p electrode is easily damaged by the impact of a large current, such as being burned or damaged. Summary of the Invention

[0005] Embodiments of the present disclosure provide a high-brightness light-emitting diode chip and a method for preparing the same, which can improve the problem that the pad connected to the external circuit on the electrode is easily damaged and enhance the reliability of the chip. The technical solution is as follows:

[0006] Embodiments of the present disclosure provide a high-brightness light-emitting diode chip, which includes: a substrate, a first semiconductor layer, a light-emitting layer, a second semiconductor layer, a current blocking layer, a transparent conductive layer, a first electrode, and a second electrode; the substrate, the first semiconductor layer, the light-emitting layer, the second semiconductor layer, and the current blocking layer are stacked in sequence, the transparent conductive layer is located on the surface of the current blocking layer and extends to the surface of the second semiconductor layer, the second electrode is located on the surface of the transparent conductive layer, a positive projection of the second electrode on the substrate is located within a positive projection of the current blocking layer on the substrate, and the first electrode is connected to the first semiconductor layer; the second electrode includes a pad and finger bars, one end of the finger bar is connected to the pad, and in the direction from the pad to the finger bar, the thickness of the current blocking layer gradually decreases in a direction perpendicular to the bearing surface of the substrate.

[0007] In one implementation manner of the embodiment of the present disclosure, the current blocking layer includes a block region and a strip region connected to each other. The orthographic projection of the pad of the second electrode on the substrate is located within the orthographic projection of the block region on the substrate, and the orthographic projection of the finger strip of the second electrode on the substrate is located within the orthographic projection of the strip region on the substrate.

[0008] In another implementation manner of the embodiment of the present disclosure, the surface of the current blocking layer away from the substrate is a plane.

[0009] In another implementation manner of the embodiment of the present disclosure, the included angle between the surface of the current blocking layer away from the substrate and the surface of the current blocking layer close to the substrate is 0° to 45°.

[0010] In another implementation manner of the embodiment of the present disclosure, the surface of the current blocking layer away from the substrate is a concave surface.

[0011] In another implementation manner of the embodiment of the present disclosure, the surface of the current blocking layer away from the substrate is stepped.

[0012] In another implementation manner of the embodiment of the present disclosure, the block region is annular.

[0013] In another implementation manner of the embodiment of the present disclosure, in the direction perpendicular to the bearing surface of the substrate, the thickness of the position where the current blocking layer has the maximum thickness is not greater than 5 μm.

[0014] In another implementation manner of the embodiment of the present disclosure, the current blocking layer has a via exposing the second semiconductor layer, and the second electrode is connected to the second semiconductor layer through the via.

[0015] The embodiment of the present disclosure provides a method for manufacturing a high-brightness light-emitting diode chip. The manufacturing method includes: providing a substrate; sequentially forming a first semiconductor layer, a light-emitting layer, a second semiconductor layer, and a current blocking layer on the substrate; fabricating a transparent conductive layer on the current blocking layer, where the transparent conductive layer is located on the surface of the current blocking layer and extends to the surface of the second semiconductor layer; fabricating a first electrode and a second electrode, where the first electrode is connected to the first semiconductor layer, the second electrode is located on the surface of the transparent conductive layer, the orthographic projection of the second electrode on the substrate is located within the orthographic projection of the current blocking layer on the substrate, the second electrode includes a pad and a finger strip, one end of the finger strip is connected to the pad, and in the direction from the pad to the finger strip, the thickness of the current blocking layer in the direction perpendicular to the bearing surface of the substrate gradually decreases.

[0016] The beneficial effects brought by the technical solution provided by the embodiment of the present disclosure at least include:

[0017] In the high-brightness light-emitting diode chip provided by an embodiment of the present disclosure, a current blocking layer is disposed between the second semiconductor layer and the second electrode, which can block the current from directly flowing downward to the second semiconductor layer. A transparent conductive layer is further disposed between the current blocking layer and the second electrode, and the transparent conductive layer extends to the second semiconductor layer, so that the current can be extended to various positions of the second semiconductor layer through the transparent conductive layer.

[0018] Wherein, in the direction from the pad of the second electrode to the finger strip of the second electrode, the thickness of the current blocking layer gradually decreases in the direction perpendicular to the bearing surface of the substrate. Since the pad on the second electrode is the contact point where the second electrode connects to the external circuit, the current at this contact point is the most crowded. By setting the thickness of the current blocking layer to gradually decrease in the direction away from the pad, the blocking effect of the current blocking layer on the current can be gradually weakened, so as to guide the current to move from the area of the pad to the area of the finger strip. Compared with the current blocking layer with no change in thickness, the current blocking layer with a gradually decreasing thickness in the direction from the pad of the second electrode to the finger strip of the second electrode can make more current flow to the finger strip of the second electrode, enabling the current to be evenly distributed in various areas of the second electrode, thereby effectively avoiding the problems of burning or damage of the pad on the second electrode due to large current impact and improving the reliability of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0020] Figure 1 is a schematic structural diagram of a high-brightness light-emitting diode chip provided by an embodiment of the present disclosure;

[0021] Figure 2 is a top view of a current blocking layer provided by an embodiment of the present disclosure;

[0022] Figure 3 is a cross-sectional view of a current blocking layer provided by an embodiment of the present disclosure;

[0023] Figure 4 is a cross-sectional view of a current blocking layer provided by an embodiment of the present disclosure;

[0024] Figure 5 is a cross-sectional view of a current blocking layer provided by an embodiment of the present disclosure;

[0025] Figure 6It is a flowchart of a method for manufacturing a high-brightness light-emitting diode chip provided by an embodiment of the present disclosure.

[0026] The descriptions of each label in the figure are as follows:

[0027] 10. Substrate;

[0028] 21. First semiconductor layer; 22. Light-emitting layer; 23. Second semiconductor layer;

[0029] 30. Current blocking layer; 31. Block region; 32. Strip region;

[0030] 40. Transparent conductive layer;

[0031] 51. First electrode; 52. Second electrode; 521. Pad; 522. Finger strip;

[0032] 60. Groove; 61. Passivation layer. Detailed implementation manners

[0033] To make the objectives, technical solutions and advantages of the present disclosure clearer, the following will further describe the embodiments of the present disclosure in detail with reference to the accompanying drawings.

[0034] Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings understood by those of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", "third" and similar terms used in the specification and claims of the present patent application do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, terms such as "a" or "one" do not denote a quantity limitation, but mean that there is at least one. The terms "comprising" or "including" and similar terms mean that the elements or items appearing before "comprising" or "including" cover the elements or items listed after "comprising" or "including" and their equivalents, and do not exclude other elements or items. The terms "connected" or "coupled" and similar terms are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", "top", "bottom" etc. are only used to represent relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationships may also change accordingly.

[0035] Figure 1 It is a schematic structural diagram of a high-brightness light-emitting diode chip provided by an embodiment of the present disclosure. As Figure 1 shown, the high-brightness light-emitting diode chip includes: a substrate 10, a first semiconductor layer 21, a light-emitting layer 22, a second semiconductor layer 23, a current blocking layer 30, a transparent conductive layer 40, a first electrode 51 and a second electrode 52.

[0036] As shown Figure 1 in FIG. 1, a substrate 10, a first semiconductor layer 21, a light-emitting layer 22, a second semiconductor layer 23, and a current blocking layer 30 are stacked in sequence. A transparent conductive layer 40 is located on the surface of the current blocking layer 30 and extends to the surface of the second semiconductor layer 23. A second electrode 52 is located on the surface of the transparent conductive layer 40. The orthographic projection of the second electrode 52 on the substrate 10 is located within the orthographic projection of the current blocking layer 30 on the substrate 10. A first electrode 51 is used to connect to the first semiconductor layer 21.

[0037] As shown Figure 1 in FIG. 2, the second electrode 52 includes a pad 521 and finger bars 522. One end of the finger bars 522 is connected to the pad 521. In the direction from the pad 521 to the finger bars 522, the thickness of the current blocking layer 30 gradually decreases in the direction perpendicular to the bearing surface of the substrate 10.

[0038] Wherein, the bearing surface of the substrate 10 is the surface on which the epitaxial layer of the substrate 10 grows.

[0039] In the high-brightness light-emitting diode chip provided by the embodiments of the present disclosure, a current blocking layer 30 is provided between the second semiconductor layer 23 and the second electrode 52, which can block the current from directly flowing downward to the second semiconductor layer 23. A transparent conductive layer 40 is further provided between the current blocking layer 30 and the second electrode 52. The transparent conductive layer 40 extends to the second semiconductor layer 23. In this way, the current can be extended to various positions of the second semiconductor layer 23 through the transparent conductive layer 40.

[0040] Wherein, in the direction from the pad 521 of the second electrode 52 to the finger bars 522 of the second electrode 52, the thickness of the current blocking layer 30 gradually decreases in the direction perpendicular to the bearing surface of the substrate 10. Since the pad 521 on the second electrode 52 is the contact point where the second electrode 52 connects to the external circuit, the current at this contact point is the most crowded. By setting the thickness of the current blocking layer 30 to gradually decrease in the direction away from the pad 521, the blocking effect of the current blocking layer 30 on the current can be gradually weakened, so as to guide the current to move from the area of the pad 521 towards the area of the finger bars 522. Compared with the current blocking layer 30 with no change in thickness, the current blocking layer 30 whose thickness gradually decreases in the direction from the pad 521 of the second electrode 52 to the finger bars 522 of the second electrode 52 can make more current flow to the finger bars 522 of the second electrode 52, so that the current can be evenly distributed in each area of the second electrode 52, thereby effectively avoiding the problem of burning or damage of the pad 521 on the second electrode 52 due to large current impact and improving the reliability of the chip.

[0041] Optionally, the material of the substrate 10 can be one of sapphire, silicon, gallium nitride, silicon nitride, silicon carbide, and glass, such as a flat sapphire substrate 10 or a patterned sapphire substrate 10 (Patterned Sapphire Substrate, abbreviated as: PSS).

[0042] In an embodiment of the present disclosure, one of the first semiconductor layer 21 and the second semiconductor layer 23 can be an n-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer.

[0043] As an example, the first semiconductor layer 21 is an n-type layer, and the second semiconductor layer 23 is a p-type layer.

[0044] Correspondingly, the first electrode 51 is connected to the first semiconductor layer 21, and the first electrode 51 is an n-electrode; the second electrode 52 is connected to the second semiconductor layer 23, and the second electrode 52 is a p-electrode.

[0045] Optionally, both the n-electrode and the p-electrode include one or more of the metals gold (Au), aluminum (Al), nickel (Ni), platinum (Pt), chromium (Cr), and titanium (Ti).

[0046] Optionally, the material of the n-type layer can be gallium nitride (GaN) doped with an n-type dopant (such as silicon).

[0047] Exemplarily, the thickness of the n-type layer can be 1 μm to 5 μm. For example, the thickness of the n-type layer is 3 μm.

[0048] Exemplarily, the doping concentration of the n-type dopant in the n-type layer can be 10 18 / cm 3 to 10 19 / cm 3 , for example, the doping concentration is 5 × 10 18 / cm 3 .

[0049] Optionally, the light-emitting layer 22 can include a plurality of quantum wells and a plurality of quantum barriers, and the plurality of quantum wells and the plurality of quantum barriers are alternately stacked; the material of the quantum wells can be indium gallium nitride (InGaN), and the material of the quantum barriers can be gallium nitride.

[0050] Exemplarily, the thickness of the quantum wells can be 2.5 nm to 3.5 nm. For example, the thickness of the quantum wells is 3 nm; the thickness of the quantum barriers can be 9 nm to 20 nm. For example, the thickness of the quantum barriers is 15 nm.

[0051] Among them, the number of quantum wells is the same as the number of quantum barriers, and the number of quantum barriers can be 5 to 15. For example, the number of quantum barriers is 10.

[0052] Optionally, the material of the p-type layer may be p-type doped (such as magnesium) gallium nitride.

[0053] Exemplarily, the thickness of the p-type layer may be from 100 nm to 800 nm. For example, the thickness of the p-type layer is 450 nm.

[0054] Exemplarily, the doping concentration of the p-type dopant in the p-type layer may be 10 18 / cm 3 to 10 20 / cm 3 For example, the doping concentration is 10 19 / cm 3 .

[0055] Optionally, the transparent conductive layer 40 is an indium tin oxide (ITO) film layer.

[0056] Among them, the indium tin oxide film layer has good transmittance and low resistivity, which is convenient for carrier conduction and improves the injection efficiency.

[0057] Exemplarily, the thickness of the transparent conductive layer 40 is from 6 μm to 10 μm. For example, the thickness of the transparent conductive layer 40 is 8 μm.

[0058] As Figure 1 shown, the transparent conductive layer 40 is located on the surface of the current blocking layer 30, and the thickness of the transparent conductive layer 40 is not less than the maximum thickness of the current blocking layer 30, so that the transparent conductive layer 40 can completely cover the current blocking layer 30 and form a flat surface on the current blocking layer 30, facilitating subsequent processing to form the second electrode 52.

[0059] Optionally, as Figure 1 shown, the surface of the second semiconductor layer 23 has a groove 60 exposing the first semiconductor layer 21, the first electrode 51 is located in the groove 60, and the first electrode 51 is connected to the surface of the first semiconductor layer 21.

[0060] Optionally, as Figure 1 shown, the surface of the second semiconductor layer 23 further has a passivation layer 61, and the passivation layer 61 extends to the groove 60. And the passivation layer 61 has through holes exposing the first electrode 51 and the second electrode 52.

[0061] Exemplarily, the passivation layer 61 may be a SiO 2 layer or a SiN layer. Among them, the thickness of the passivation layer 61 may be from 1 μm to 5 μm.

[0062] Figure 2 is a top view of a current blocking layer 30 provided by an embodiment of the present disclosure. As Figure 2As shown, the current blocking layer 30 includes a connected block region 31 and a strip region 32. The orthographic projection of the pad 521 of the second electrode 52 on the substrate 10 is located within the orthographic projection of the block region 31 on the substrate 10, and the orthographic projection of the finger strip 522 of the second electrode 52 on the substrate 10 is located within the orthographic projection of the strip region 32 on the substrate 10.

[0063] By also configuring the current blocking layer 30 to have a structure of a connected block region 31 and a strip region 32, and making the block region 31 face the pad 521 and the strip region 32 face the finger strip 522. In this way, regions of the same shape are arranged opposite to each other, which not only fully realizes current blocking but also avoids affecting the current spreading effect due to an overly large area of the current blocking layer 30.

[0064] Exemplarily, as Figure 2 shown, the block region 31 is annular, and correspondingly, the pad 521 of the second electrode 52 is also annular.

[0065] As an example, in the embodiments of the present disclosure, the block region 31 can be circularly annular or square annular.

[0066] Exemplarily, the block region 31 is a solid plate, and correspondingly, the pad 521 of the second electrode 52 is also a solid plate.

[0067] As an example, in the embodiments of the present disclosure, the block region 31 can be disk-shaped.

[0068] In the embodiments of the present disclosure, the first electrode 51 has the same structure as the second electrode 52. The first electrode can also include a connected pad and finger strips, with one end of the finger strips connected to the pad.

[0069] Optionally, the current blocking layer 30 is a SiO 2 layer, a SiN layer, or a DBR (Distributed Bragg Reflection) layer. Among them, the DBR layer is a stacked structure of SiO 2 and TI 3 O 5 .

[0070] Exemplarily, the current blocking layer 30 can be a SiO 2 layer.

[0071] Optionally, the maximum thickness of the current blocking layer 30 in the direction perpendicular to the bearing surface of the substrate 10 is not greater than 5 μm. Since the thickness of the current blocking layer 30 gradually changes, in the embodiments of the present disclosure, the maximum thickness of the current blocking layer 30 is 5 μm, and the minimum thickness of the current blocking layer 30 is 0 μm.

[0072] Optionally, the current blocking layer 30 has vias exposing the second semiconductor layer 23. The vias are located in the current blocking layer 30, and the second electrode 52 is connected to the second semiconductor layer 23 through the vias. By providing the vias passing through the current blocking layer 30, the second electrode 52 can be connected to the second semiconductor layer 23 through the vias, so that part of the current can also directly flow through the vias to the second semiconductor layer 23 under the current blocking layer 30.

[0073] In some implementations of the present disclosure, Figure 3 is a cross-sectional view of a current blocking layer 30 provided by an embodiment of the present disclosure. As Figure 3 shown, the surface of the current blocking layer 30 away from the substrate 10 is a plane.

[0074] In the above implementation, in the direction from the block region 31 to the strip region 32, the thickness of the current blocking layer 30 linearly decreases in the direction perpendicular to the substrate 10.

[0075] By setting the thickness of the current blocking layer 30 to gradually linearly decrease in the direction away from the block region 31, so as to gradually weaken the blocking effect of the current blocking layer 30 on the current, the current can be guided to move from the region of the pad 521 towards the region of the finger strip 522, enabling more current to flow to the finger strip 522 of the second electrode 52, and allowing the current to be evenly distributed in each region of the second electrode 52, thereby effectively improving the problem that the pad 521 on the second electrode 52 is burned or damaged due to large current impact, and enhancing the reliability of the chip.

[0076] Optionally, the thickness of the current blocking layer 30 is determined by the following formula:

[0077] h = (L - d) × H / L (1)

[0078] Taking Figure 3 the lower left corner endpoint O of the block region in the schematic cross-sectional view as the origin to establish a rectangular coordinate system, with the extension direction of the strip region as the X-axis and the thickness direction of the current blocking layer as the Y-axis.

[0079] In this rectangular coordinate system, in formula (1), h is the thickness (length in the Y-axis direction) of the current blocking layer 30 at any point A on the X-axis, with the unit of μm; L is the maximum length of the current blocking layer 30 in the X-axis direction, with the unit of μm; d is the distance between any point A on the X-axis of the current blocking layer 30 and point O, with the unit of μm; H is the maximum length of the current blocking layer 30 in the Y-axis direction, with the unit of μm.

[0080] Optionally, the angle α between the surface of the current blocking layer 30 away from the substrate 10 and the surface of the current blocking layer 30 close to the substrate 10 is 0° to 45°.

[0081] In some other implementations of the present disclosure,Figure 4 This is a cross-sectional view of a current blocking layer 30 provided by an embodiment of the present disclosure. As Figure 4 shown, the surface of the current blocking layer 30 away from the substrate 10 is concave.

[0082] In the above implementation, in the direction from the block area 31 to the strip area 32, the rate of decrease in the thickness of the current blocking layer 30 gradually becomes smaller to form a concave surface.

[0083] Among them, since the rate of decrease in the thickness of the current blocking layer 30 gradually becomes smaller, at the beginning stage, the amplitude of decrease in the thickness of the current blocking layer 30 is relatively large. As the rate of decrease gradually decreases, the amplitude of decrease in the thickness of the current blocking layer 30 gradually decreases. That is to say, the change in the thickness of the current blocking layer 30 gradually becomes gentle.

[0084] In this way, since the amplitude of decrease in the thickness of the current blocking layer 30 in the area closer to the block area 31 is relatively large, it can more easily attract the current to move towards the finger area. After the current is drained from the pad 521 of the electrode to the finger strip 522, the demand for drainage decreases. At this time, the change in the thickness of the current blocking layer 30 can be relatively gentle to ensure that the current blocking layer 30 has a certain effect of blocking the current.

[0085] By making the amplitude of decrease in the thickness of the current blocking layer 30 in the area closer to the block area 31 relatively large, the current can be quickly attracted to move towards the finger strip 522, avoiding excessive concentration of the current on the pad 521, and enabling the current to be evenly distributed in various areas of the second electrode 52, thereby effectively improving the problem of burning or damage of the pad 521 on the second electrode 52 due to large current impact.

[0086] In some other implementations of the present disclosure, Figure 5 This is a cross-sectional view of a current blocking layer 30 provided by an embodiment of the present disclosure. As Figure 5 shown, the surface of the current blocking layer 30 away from the substrate 10 is stepped.

[0087] By setting the thickness of the current blocking layer 30 to decrease step by step, the blocking effect of the current blocking layer 30 on the current can be gradually weakened, guiding the current to move from the area of the pad 521 towards the area of the finger strip 522, enabling more current to flow to the finger strip 522 of the second electrode 52, and allowing the current to be evenly distributed in various areas of the second electrode 52, thereby effectively improving the problem of burning or damage of the pad 521 on the second electrode 52 due to large current impact and enhancing the reliability of the chip.

[0088] The embodiment of the present disclosure provides a method for manufacturing a high-brightness light-emitting diode chip, which is applicable to manufacturing Figure 1 the high-brightness light-emitting diode chip shown. Figure 6It is a flowchart of a method for manufacturing a high-brightness light-emitting diode chip provided by an embodiment of the present disclosure. As Figure 6 shown, the manufacturing method includes:

[0089] Step S11: Provide a substrate 10.

[0090] Among them, the substrate 10 can be a sapphire substrate 10.

[0091] Step S12: Sequentially form a first semiconductor layer 21, a light-emitting layer 22, a second semiconductor layer 23, and a current blocking layer 30 on the substrate 10.

[0092] Among them, the first semiconductor layer 21 is an n-type layer, and the second semiconductor layer 23 is a p-type layer.

[0093] Optionally, the material of the n-type layer can be gallium nitride (GaN) doped with an n-type dopant (such as silicon).

[0094] Exemplarily, the thickness of the n-type layer can be 1 μm to 5 μm. For example, the thickness of the n-type layer is 3 μm.

[0095] Exemplarily, the doping concentration of the n-type dopant in the n-type layer can be 10 18 / cm 3 to 10 19 / cm 3 , for example, the doping concentration is 5×10 18 / cm 3 .

[0096] Optionally, the light-emitting layer 22 can include a plurality of quantum wells and a plurality of quantum barriers, and the plurality of quantum wells and the plurality of quantum barriers are alternately stacked; the material of the quantum wells can be indium gallium nitride (InGaN), and the material of the quantum barriers can be gallium nitride.

[0097] Exemplarily, the thickness of the quantum wells can be 2.5 nm to 3.5 nm. For example, the thickness of the quantum wells is 3 nm; the thickness of the quantum barriers can be 9 nm to 20 nm. For example, the thickness of the quantum barriers is 15 nm.

[0098] Among them, the number of quantum wells is the same as the number of quantum barriers, and the number of quantum barriers can be 5 to 15. For example, the number of quantum barriers is 10.

[0099] Optionally, the material of the p-type layer can be gallium nitride doped with a p-type dopant (such as magnesium).

[0100] Exemplarily, the thickness of the p-type layer can be 100 nm to 800 nm. For example, the thickness of the p-type layer is 450 nm.

[0101] Exemplarily, the doping concentration of the p-type dopant in the p-type layer can be 1018 / cm 3 to 10 20 / cm 3 , for example, the doping concentration is 10 19 / cm 3 .

[0102] Exemplarily, step S12 may include:

[0103] Using metal organic chemical vapor deposition (abbreviation: MOCVD) technology to grow an n-type layer, a light-emitting layer, and a p-type layer on a substrate in sequence.

[0104] When preparing the current blocking layer 30 in step S12, it may include: first laying the current blocking layer 30, and then patterning the current blocking layer 30 using photolithography technology and etching technology to form a current blocking layer 30 with a gradually changing thickness.

[0105] Wherein, in the direction from the pad 521 of the second electrode 52 to the finger bar 522 of the second electrode 52, the thickness of the current blocking layer 30 gradually decreases in the direction perpendicular to the substrate 10.

[0106] Step S13: Fabricate a transparent conductive layer 40 on the current blocking layer 30, and the transparent conductive layer 40 is located on the surface of the current blocking layer 30 and extends to the surface of the second semiconductor layer 23.

[0107] Preparing the transparent conductive layer 40 may include: first laying an indium tin oxide film, and then patterning the indium tin oxide film using photolithography technology and etching technology to obtain the transparent conductive layer 40.

[0108] Step S14: Fabricate a first electrode 51 and a second electrode 52.

[0109] Wherein, the first electrode 51 is electrically connected to the first semiconductor layer 21, the second electrode 52 is located on the surface of the transparent conductive layer 40, the orthographic projection of the second electrode 52 on the substrate 10 is located within the orthographic projection of the current blocking layer 30 on the substrate 10, the second electrode 52 includes a pad 521 and a finger bar 522, one end of the finger bar 522 is connected to the pad 521, and in the direction from the pad 521 to the finger bar 522, the thickness of the current blocking layer 30 gradually decreases in the direction perpendicular to the bearing surface of the substrate 10.

[0110] Before fabricating the first electrode 51 and the second electrode 52, a groove 60 also needs to be formed on the p-type layer, which may specifically include:

[0111] First, a photoresist with a certain pattern is formed on the p-type layer using photolithography technology. Second, the p-type layer and the light-emitting layer 22 not covered by the photoresist are dry-etched to form a groove 60 exposing the n-type layer. Third, the photoresist is removed.

[0112] After the groove 60 is formed, a p-electrode is fabricated on the surface of the p-type layer, and an n-electrode is fabricated within the groove 60.

[0113] Optionally, both the n-electrode and the p-electrode include one or more of the metals such as gold (Au), aluminum (Al), nickel (Ni), platinum (Pt), chromium (Cr), and titanium (Ti).

[0114] After the electrodes are formed, it further includes: forming a passivation layer 61 on the area of the p-type layer except the area where the p-electrode is disposed, and on the area within the groove 60 except the area where the n-type layer is disposed.

[0115] Exemplarily, the formation process of the passivation layer 61 may include: first depositing a SiO 2 layer, and then patterning the SiO 2 layer using photolithography technology and etching technology to obtain the passivation layer 61.

[0116] In the high-brightness light-emitting diode chip prepared according to the embodiments of the present disclosure, a current blocking layer 30 is disposed between the second semiconductor layer 23 and the second electrode 52, which can block the current from directly flowing downward to the second semiconductor layer 23. A transparent conductive layer 40 is further disposed between the current blocking layer 30 and the second electrode 52, and the transparent conductive layer 40 extends to the second semiconductor layer 23, so that the current can be extended to various positions of the second semiconductor layer 23 through the transparent conductive layer 40.

[0117] Wherein, in the direction from the pad 521 of the second electrode 52 to the finger bar 522 of the second electrode 52, the thickness of the current blocking layer 30 in the direction perpendicular to the bearing surface of the substrate 10 gradually decreases. Since the pad 521 on the second electrode 52 is the contact point where the second electrode 52 connects to the external circuit, the current at this contact point position is the most crowded. By setting the thickness of the current blocking layer 30 to gradually decrease in the direction away from the pad 521, the blocking effect of the current blocking layer 30 on the current is gradually weakened, so that the current can be guided to move from the area of the pad 521 towards the area of the finger bar 522. Compared with the current blocking layer 30 with a constant thickness, the current blocking layer 30 with a gradually decreasing thickness in the direction from the pad 521 of the second electrode 52 to the finger bar 522 of the second electrode 52 can make more current flow to the finger bar 522 of the second electrode 52, enabling the current to be evenly distributed in various areas of the second electrode 52, thereby effectively avoiding the problems of burning or damage of the pad 521 on the second electrode 52 due to large current impact and improving the reliability of the chip.

[0118] The above is not any form of limitation to the present disclosure. Although the present disclosure has been disclosed as above through embodiments, it is not intended to limit the present disclosure. Any person skilled in the art can make some changes or modifications to equivalent embodiments with equivalent changes by using the technical content disclosed above within the scope of the technical solution of the present disclosure. However, as long as it does not depart from the content of the technical solution of the present disclosure, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present disclosure still fall within the scope of the technical solution of the present disclosure.

Claims

1. A high-brightness light-emitting diode chip, characterized in that, the high-brightness light-emitting diode chip includes: a substrate (10), a first semiconductor layer (21), a light-emitting layer (22), a second semiconductor layer (23), a current blocking layer (30), a transparent conductive layer (40), a first electrode (51) and a second electrode (52); the substrate (10), the first semiconductor layer (21), the light-emitting layer (22), the second semiconductor layer (23) and the current blocking layer (30) are stacked in sequence, the transparent conductive layer (40) is located on the surface of the current blocking layer (30) and extends to the surface of the second semiconductor layer (23), the second electrode (52) is located on the surface of the transparent conductive layer (40), the orthographic projection of the second electrode (52) on the substrate (10) is located within the orthographic projection of the current blocking layer (30) on the substrate (10), and the first electrode (51) is connected to the first semiconductor layer (21); the second electrode (52) includes a pad (521) and finger bars (522), one end of the finger bars (522) is connected to the pad (521), and in the direction from the pad (521) to the finger bars (522), the thickness of the current blocking layer (30) in the direction perpendicular to the bearing surface of the substrate (10) gradually decreases; the current blocking layer (30) includes a connected block area (31) and strip area (32), the orthographic projection of the pad (521) of the second electrode (52) on the substrate (10) is located within the orthographic projection of the block area (31) on the substrate (10), and the orthographic projection of the finger bars (522) of the second electrode (52) on the substrate (10) is located within the orthographic projection of the strip area (32) on the substrate (10); the surface of the current blocking layer (30) away from the substrate (10) is a plane, and the surface of the current blocking layer (30) away from the substrate (10) is inclined to the side wall of the current blocking layer (30), and in the direction from the block area (31) to the strip area (32), the thickness of the current blocking layer (30) in the direction perpendicular to the substrate (10) linearly decreases; In a rectangular coordinate system with the end point O of the block area (31) away from the strip area (32) as the origin, the extension direction of the strip area (32) as the X-axis, and the thickness direction of the current blocking layer (30) as the Y-axis, the thickness of the current blocking layer (30) at any point on the X-axis is determined by the following formula: h = (L - d) × H / L (1) In formula (1), h is the thickness of the current blocking layer (30) at any point on the X-axis, in μm; L is the maximum length of the current blocking layer (30) in the X-axis direction, in μm; d is the distance of any point on the X-axis of the current blocking layer (30) from point O, in μm; H is the maximum length of the current blocking layer (30) in the Y-axis direction, in μm.

2. The high-brightness light-emitting diode chip according to claim 1, It is characterized in that the included angle between the surface of the current blocking layer (30) far from the substrate (10) and the surface of the current blocking layer (30) close to the substrate (10) is 0° to 45°.

3. The high-brightness light-emitting diode chip according to claim 1, It is characterized in that the block region (31) is annular.

4. The high-brightness light-emitting diode chip according to any one of claims 1 to 3, It is characterized in that in the direction perpendicular to the bearing surface of the substrate (10), the thickness of the position where the current blocking layer (30) has the maximum thickness is not greater than 5 μm.

5. The high-brightness light-emitting diode chip according to any one of claims 1 to 3, It is characterized in that the current blocking layer (30) has a via exposing the second semiconductor layer (23), and the second electrode (52) is connected to the second semiconductor layer (23) through the via.

6. A method for manufacturing a high-brightness light-emitting diode chip, It is characterized in that the manufacturing method includes: providing a substrate; successively forming a first semiconductor layer, a light-emitting layer, a second semiconductor layer and a current blocking layer on the substrate, the current blocking layer including a connected block region and a strip region; fabricating a transparent conductive layer on the current blocking layer, the transparent conductive layer being located on the surface of the current blocking layer and extending to the surface of the second semiconductor layer; fabricating a first electrode and a second electrode, the first electrode being connected to the first semiconductor layer, the second electrode being located on the surface of the transparent conductive layer, the orthographic projection of the second electrode on the substrate being located within the orthographic projection of the current blocking layer on the substrate, the second electrode including a pad and finger bars, one end of the finger bars being connected to the pad, in the direction from the pad to the finger bars, the thickness of the current blocking layer in the direction perpendicular to the bearing surface of the substrate gradually decreases, the orthographic projection of the pad of the second electrode on the substrate being located within the orthographic projection of the block region on the substrate, the orthographic projection of the finger bars of the second electrode on the substrate being located within the orthographic projection of the strip region on the substrate, the surface of the current blocking layer far from the substrate is a plane, and the surface of the current blocking layer far from the substrate is inclined to the side wall of the current blocking layer, in the direction from the block region to the strip region, the thickness of the current blocking layer in the direction perpendicular to the substrate linearly decreases; In a rectangular coordinate system with the end point O of the block region far from the strip region as the origin, the extension direction of the strip region as the X axis, and the thickness direction of the current blocking layer as the Y axis, the thickness of the current blocking layer at any point on the X axis is determined by the following formula: h = (L - d) × H / L (1) In formula (1), h is the thickness of the current blocking layer at any point on the X axis, in μm; L is the maximum length of the current blocking layer in the X axis direction, in μm; d is the distance of any point on the X axis of the current blocking layer from point O, in μm; H is the maximum length of the current blocking layer in the Y axis direction, in μm.

Images