A method for manufacturing a high-speed low-voltage conductive bridge-type resistive memory device

Abstract

The present invention discloses a method for manufacturing a high-speed, low-voltage conductive bridge-type resistive memory device. The manufacturing method of the present invention comprises: preparing a lower electrode on a substrate having silicon oxide or silicon nitride on the surface, preparing a relatively thick isolation layer of silicon oxide or silicon nitride by plasma enhanced chemical vapor deposition or other processes, then etching the isolation layer of silicon oxide or silicon nitride to form a well region, then depositing a resistive layer oxide by magnetron sputtering, electron beam evaporation or other processes, depositing an upper electrode and patterning it by wet etching, and finally removing part of the isolation layer by wet or dry etching to expose the lower electrode. The present invention reduces the process complexity by using a planar micro-nano processing technology. At the same time, the presence of the well region enables the upper and lower electrodes to form good electrical isolation outside the resistive functional area, and can also accurately control the thickness of the resistive layer. This makes it possible to achieve extremely low operating voltage and fast switching speed, and is widely applicable to the processing and manufacturing of new non-volatile memory CBRAM.

Description

Technical Field

[0001] The invention relates to a method for manufacturing a high-speed, low-voltage conductive bridge-type resistive memory device, and belongs to the technical field of information storage. Background Art

[0002] Due to the continuous reduction of microelectronic process nodes, traditional non-volatile memories are beginning to face huge challenges. Conductive Bridge Resistive RAM (CBRAM), as a new type of non-volatile memory, stands out among a number of new non-volatile memories due to its relatively simple functional structure, high compatibility with CMOS processes, and low read-write crosstalk. It has become one of the strong candidates for the next generation of non-volatile memory. However, current CBRAM faces two major problems: First, the operating voltage of current CBRAM devices is relatively high, usually above 1V. However, the threshold voltage of transistors processed in current advanced microelectronic process nodes is generally less than 0.4V, which makes CBRAM difficult to integrate with advanced microelectronic processes. Summary of the Invention

[0003] The technical problem to be solved by the present invention is that the CBRAM devices currently manufactured have the following technical problems: the operating voltage is relatively high and it is difficult to integrate them with advanced microelectronic processes.

[0004] In order to solve the above technical problems, the present invention provides a method for manufacturing a high-speed, low-voltage conductive bridge-type resistive memory device, which is manufactured using planar micro-nano processing and specifically includes the following steps:

[0005] Step 1: Form an insulating layer on the silicon wafer substrate; the function of the insulating layer is to electrically isolate the lower electrode of the device to prevent short circuits between independent devices on the single chip;

[0006] Step 2: fabricating a lower electrode on the silicon wafer substrate with the insulating layer obtained in step 1;

[0007] Step 3: Depositing an insulating layer on the lower electrode;

[0008] Step 4: Applying resist, photolithography and development to expose the etched area, and etching the insulating layer by wet etching or dry etching to completely etch the bottom electrode to form a well area;

[0009] Step 5: After removing the photoresist in step 4, a nanometer-thick silicon oxide, aluminum oxide or hafnium oxide layer is deposited as a resistive switching layer;

[0010] Step 6: Fabricate an upper electrode on the sample obtained in step 5;

[0011] Step 7: coating, photolithography and development to expose the etched area, and etching the insulating layer in step 3 by wet etching or dry etching to completely etch the lower electrode so that the lower electrode is exposed, thereby obtaining a conductive bridge type resistive memory device;

[0012] Step 8: Connect a current limiting bias circuit to the fabricated conductive bridge resistive random access memory device to limit the current flowing through the conductive bridge resistive random access memory device; the current limiting bias circuit is a current limiting circuit composed of a single field effect transistor or a current limiting circuit composed of multiple field effect transistors.

[0013] Preferably, the insulating layer in step 1 is a silicon oxide layer or a silicon nitride layer; the silicon oxide layer is grown by a thermal oxidation process; and the silicon nitride layer is prepared by a chemical vapor deposition method.

[0014] Preferably, the method for manufacturing the lower electrode in step 2 includes any one of the following two methods:

[0015] Method 1: Depositing and patterning the lower electrode by a lift-off process based on a stripping photoresist, wherein the spin-coated thickness of the stripping photoresist should be greater than the thickness of the lower electrode;

[0016] Method 2: Deposit the lower electrode and perform photolithography, and then perform wet etching, dry etching or chemical mechanical polishing to pattern the lower electrode.

[0017] Preferably, the material for making the lower electrode is an inert metal, and the inert metal is at least one of platinum, tungsten and gold. The deposition method of the lower electrode includes thermal evaporation, electron beam evaporation, magnetron sputtering, electroplating, plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition.

[0018] Preferably, in the first method, a layer of metal titanium is first deposited as an adhesion layer before depositing the lower electrode.

[0019] Preferably, the deposition method of the metal titanium adhesion layer includes thermal evaporation, electron beam evaporation, magnetron sputtering, electroplating, plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition; the thickness of the metal titanium adhesion layer is 10 to 20 nm.

[0020] Preferably, the insulating layer in step 3 is a silicon oxide layer or a silicon nitride layer; the deposition method is plasma-enhanced chemical vapor deposition, low-pressure chemical vapor deposition, magnetron sputtering, electron beam evaporation, or thermal evaporation, and the thickness of the insulating layer is 0.1 to 2 microns. The function of this insulating layer (silicon oxide or silicon nitride layer) is to provide good electrical isolation between the upper and lower electrodes in the area outside the well region.

[0021] Preferably, the specific steps of making the upper electrode in step 6 include: depositing the upper electrode by magnetron sputtering, electron beam evaporation, thermal evaporation, electroplating, plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition, coating the upper electrode with glue, photolithography and development, and patterning the upper electrode by dry etching, wet etching and chemical mechanical polishing; the deposition thickness of the upper electrode should be adjusted according to the thickness of the insulating layer in step 3 to ensure that the upper electrode will not break on the side wall of the well area to avoid causing an open circuit.

[0022] Preferably, the upper electrode is made of an active metal, and the active metal is at least one of copper and silver.

[0023] Preferably, the conductive bridge-type resistive memory device produced in step 7 includes an upper electrode and a lower electrode; the two electrodes are isolated from each other by a silicon oxide or silicon nitride insulating layer outside the well area; and are connected by a silicon oxide, aluminum oxide or hafnium oxide resistive layer in the well area; and the lower electrode is isolated from the silicon wafer substrate by a silicon oxide or silicon nitride insulating layer.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] (1) The present invention uses a planar micro-nano processing technology to manufacture a well region to realize the core function of the CBRAM device. The existence of the well region not only forms a good electrical isolation between the upper and lower electrodes outside the resistive switching functional region, but also can limit the area where the conductive metal wire is formed. At the same time, the existence of the well region can effectively protect the resistive switching functional region during the patterning process of the upper electrode;

[0026] (2) The present invention accurately controls the thickness of the resistive switching layer through processes such as chemical vapor deposition, magnetron sputtering, electron beam evaporation, and thermal evaporation. The thickness of the resistive switching layer can be accurately controlled by depositing the resistive switching layer twice at the nanometer level, while forming good isolation. Ultimately, the operating voltage and low-resistance resistance of the CBRAM can be effectively reduced, thereby improving the performance of the CBRAM. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a process flow chart of the method of the present invention;

[0028] Figure 2 This is a three-dimensional schematic diagram of forming a thermally oxidized silicon dioxide layer on a silicon wafer substrate in an embodiment;

[0029] Figure 3 For Figure 2 Schematic diagram of the bottom electrode patterned on the substrate by a lift-off process based on lift-off photoresist (LOR);

[0030] Figure 4 For Figure 3On the basis of the above, a thick layer of silicon oxide is deposited by plasma chemical vapor deposition (PECVD);

[0031] Figure 5 Schematic diagram of wet etching of a silicon oxide layer using a buffered silicon oxide etchant (BOE) solution to etch out a well structure in an embodiment;

[0032] Figure 6 For Figure 5 Schematic diagram of the structure after a nanometer-thick silicon oxide layer is deposited on the surface of the sample after etching by magnetron sputtering;

[0033] Figure 7 Schematic diagram of the structure of an unpatterned upper electrode prepared by magnetron sputtering in an embodiment;

[0034] Figure 8 Schematic diagram of the structure after the active metal of the upper electrode is patterned using a metal etching solution in the embodiment;

[0035] Figure 9 Schematic diagram of etching a portion of the silicon oxide layer to expose the lower electrode using a buffered silicon oxide etchant (BOE) solution in an embodiment;

[0036] Figure 10 3D cross-sectional view of a CBRAM device with a well structure prepared in an embodiment;

[0037] Figure 11 Schematic diagrams of two CBRAM array architectures, where a is a 1T1R architecture and b is a cross-point array architecture;

[0038] Figure 12 The IV test curve of the CBRAM device prepared by the process of the present invention is shown in FIG. 1 , wherein the set voltage (SET) is 0.35V and the reset voltage (RESET) is -0.09V;

[0039] Figure 13 This is a test curve diagram of the resistance switching time of the CBRAM device prepared by the process method of the present invention. The short dotted line represents the external bias voltage curve, and the solid line is the test device voltage divider curve. The figure shows a high-speed resistance switching with a switching time of only 7 nanoseconds.

[0040] Figure numerals: (1) to (8) represent steps 1 to 8 of the manufacturing method respectively; 1. lower electrode; 2. upper electrode; 3. well region; 4. resistive layer; 5. insulating layer; 6. substrate insulating layer. DETAILED DESCRIPTION

[0041] To make the present invention more clearly understood, preferred embodiments are described in detail below with reference to the accompanying drawings.

[0042] Example

[0043] This embodiment provides a method for manufacturing a high-speed, low-voltage conductive bridge resistive random access memory (CBRAM) device. The process flow is as follows: Figure 1 As shown, the specific steps include:

[0044] 1. Using a P-type silicon wafer as the substrate, a silicon oxide insulating layer is grown using a thermal oxidation process, such as Figure 2 shown.

[0045] 2. Spin-coat lift-off photoresist (LOR) and ordinary photoresist in sequence and pre-bake them separately. Use the first mask to prepare the sacrificial layer of the lift-off process according to the standard photolithography process. Then, deposit 20 nanometers thick titanium and 80 nanometers thick platinum in sequence by magnetron sputtering. Finally, remove the photoresist with PG Remover organic solution to complete the patterning of the bottom electrode. Figure 3 shown.

[0046] 3. Deposit a 0.5 μm thick silicon oxide isolation layer by plasma enhanced chemical vapor deposition (PECVD), such as Figure 4 shown.

[0047] 4. Use the second mask to perform photolithography and completely etch the 0.5 micron thick PECVD silicon oxide layer using a buffered silicon oxide etchant (BOE) solution, such as Figure 5 shown.

[0048] 5. Deposit a 20 nm thick silicon oxide layer on the entire sample surface as a resistive switching layer by magnetron sputtering. Figure 6 As shown;

[0049] 6. Deposit a layer of 250 nm thick silver as the top electrode on the entire sample surface by magnetron sputtering. Figure 7 shown.

[0050] 7. Use the third mask to perform photolithography and wet-etch part of the upper electrode with a silver etching solution to complete the patterning of the upper electrode, such as Figure 8 As shown;

[0051] 8. Following the same idea as step (4), use the fourth mask to perform photolithography and use buffered silicon oxide etchant (BOE) solution to etch the silicon oxide layer above the lower electrode, eventually exposing the lower electrode. Figure 9 As shown. Thus, a CBRAM device is prepared, and its 3D cross-sectional view is shown as follows Figure 10As shown, it includes a lower electrode 1 and an upper electrode 2; the two electrodes are isolated by an insulating layer (silicon oxide or silicon nitride insulating layer) 5 outside the well area 3; they are connected by a silicon oxide, aluminum oxide or hafnium oxide resistive layer 4 in the well area; the lower electrode and the silicon wafer substrate are isolated by a substrate insulating layer (silicon oxide or silicon nitride insulating layer) 6.

[0052] 9. Connect the current limiting bias circuit to the fabricated conductive bridge resistive memory device to limit the current flowing through the conductive bridge resistive memory. The current limiting bias circuit can be a current limiting circuit composed of a single field effect transistor ( Figure 11 a), or a current limiting circuit composed of multiple field effect transistors ( Figure 11 b). In practical applications, whether it is a 1-transistor-1 resistive memory (1T1R) architecture ( Figure 11 a) or cross-point array architecture ( Figure 11 b) The current flowing through the conductive bridge type resistive random access memory must be provided by an additional bias current source.

[0053] The IV test curve of the CBRAM device prepared by the process of the present invention is as follows: Figure 12 As shown in FIG, the set (SET) voltage is 0.35V and the reset (RESET) voltage is -0.09V. The resistance switching time test curve of the CBRAM device prepared by the process of the present invention is shown in FIG. Figure 13 As shown in the figure, it can be seen that the device achieves high-speed resistive switching with a switching time of only 7 nanoseconds.

[0054] The above embodiments are only preferred embodiments of the present invention and are not intended to limit the present invention in any form or substance. It should be noted that ordinary technicians in this technical field can make several improvements and supplements without departing from the present invention, and these improvements and supplements should also be regarded as the scope of protection of the present invention.

Claims

1. A method for manufacturing a high-speed, low-voltage conductive bridge-type resistive memory device, characterized in that: The fabrication process is planar micro-nano processing, which includes the following steps: Step 1: Create an insulating layer on the silicon wafer substrate; Step 2: fabricating a lower electrode on the silicon wafer substrate with the insulating layer obtained in step 1; Step 3: Depositing an insulating layer on the lower electrode; Step 4: Applying resist, photolithography and development to expose the etched area, and etching the insulating layer by wet etching or dry etching to completely etch the bottom electrode to form a well area; Step 5: After removing the photoresist in step 4, a nanometer-thick silicon oxide, aluminum oxide or hafnium oxide layer is deposited as a resistive switching layer; Step 6: Fabricate an upper electrode on the sample obtained in step 5; Step 7: coating, photolithography and development to expose the etched area, and etching the insulating layer in step 3 by wet etching or dry etching to completely etch the lower electrode so that the lower electrode is exposed, thereby obtaining a conductive bridge type resistive memory device; Step 8: Connect a current limiting bias circuit to the fabricated conductive bridge resistive random access memory device to limit the current flowing through the conductive bridge resistive random access memory; the current limiting bias circuit is a current limiting circuit composed of a single field effect transistor or a current limiting circuit composed of multiple field effect transistors.

2. The method for manufacturing a high-speed, low-voltage conductive bridge-type resistive memory device according to claim 1, wherein: The insulating layer in step 1 is a silicon oxide layer or a silicon nitride layer; the silicon oxide layer is grown by a thermal oxidation process; and the silicon nitride layer is prepared by a chemical vapor deposition method.

3. The method for manufacturing a high-speed, low-voltage conductive bridge-type resistive memory device according to claim 2, wherein: The method for manufacturing the lower electrode in step 2 includes any one of the following two methods: Method 1: Depositing and patterning the lower electrode by a lift-off process based on a stripping photoresist, wherein the spin-coated thickness of the stripping photoresist should be greater than the thickness of the lower electrode; Method 2: Deposit the lower electrode and perform photolithography, and then perform wet etching, dry etching or chemical mechanical polishing to pattern the lower electrode.

4. The method for manufacturing a high-speed, low-voltage conductive bridge-type resistive memory device according to claim 3, wherein: The lower electrode is made of an inert metal, which is at least one of platinum, tungsten and gold. The deposition method of the lower electrode includes thermal evaporation, electron beam evaporation, magnetron sputtering, electroplating, plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition.

5. The method for manufacturing a high-speed, low-voltage conductive bridge-type resistive memory device according to claim 3, wherein: In the first method, a layer of metal titanium is first deposited as an adhesion layer before depositing the lower electrode.

6. The method for manufacturing a high-speed, low-voltage conductive bridge-type resistive random access memory according to claim 5, wherein: The deposition method of the adhesion layer includes thermal evaporation, electron beam evaporation, magnetron sputtering, electroplating, plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition; the thickness of the adhesion layer is 10 to 20 nm.

7. The method for manufacturing a high-speed, low-voltage conductive bridge-type resistive memory device according to claim 1, wherein: The insulating layer in step 3 is a silicon oxide layer or a silicon nitride layer; the deposition method is plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, magnetron sputtering, electron beam evaporation or thermal evaporation, and the thickness of the insulating layer is 0.1 to 2 microns.

8. The method for manufacturing a high-speed, low-voltage conductive bridge-type resistive memory device according to claim 1, wherein: The specific steps of making the upper electrode in step 6 include: depositing the upper electrode by magnetron sputtering, electron beam evaporation, thermal evaporation, electroplating, plasma enhanced chemical vapor deposition or low pressure chemical vapor deposition, coating the upper electrode with glue, photolithography and development, and patterning the upper electrode by dry etching, wet etching and chemical mechanical polishing; the deposition thickness of the upper electrode should be adjusted according to the thickness of the insulating layer in step 3 to ensure that the upper electrode will not break on the side wall of the well area to avoid causing an open circuit.

9. The method for manufacturing a high-speed, low-voltage conductive bridge-type resistive memory device according to claim 6, wherein: The upper electrode is made of an active metal, which is at least one of copper and silver.

10. The method for manufacturing a high-speed, low-voltage conductive bridge-type resistive memory device according to any one of claims 1 to 9, wherein: The conductive bridge resistive memory device produced in step 7 includes an upper electrode and a lower electrode; the two electrodes are isolated from each other by a silicon oxide or silicon nitride insulating layer outside the well area; and are connected by a silicon oxide, aluminum oxide or hafnium oxide resistive layer in the well area; and the lower electrode is isolated from the silicon wafer substrate by a silicon oxide or silicon nitride insulating layer.

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