A broadband low-loss limiter chip based on a hybrid π-type topology

Abstract

A broadband low insertion loss limiter chip based on a hybrid π-type topology, belonging to the technical field of microwave passive devices, solves the problems of high small-signal insertion loss, narrow operating bandwidth and large size of existing microwave limiters; by replacing the quarter-wavelength transmission line between the limiter circuits with a capacitive-loaded hybrid π-type structure, the electrical lengths of the first and second tapered U-shaped transmission lines in the two hybrid π-type structures are much less than 90° and are bent, reducing the area of the limiter chip; the first-stage limiter circuit reduces the total equivalent capacitance, thereby reducing the insertion loss; the electrical length of the transmission line is shortened, and its physical length is correspondingly shortened, reducing the insertion loss; in the two hybrid π-type structures, the total turn-off capacitance of each stage of the limiter circuit is absorbed into the hybrid π-type structure, making the limiter equivalent to a quasi-50-ohm transmission line model at small signals, thereby eliminating the influence of the turn-off capacitance reactance loaded on the transmission channel on impedance matching and expanding the operating bandwidth of the limiter.

Description

Technical Field

[0001] The present invention belongs to the technical field of microwave passive devices, and relates to a broadband low-loss limiter chip based on a hybrid π-type topology. Background Art

[0002] In recent years, with the rapid development of wireless communication technologies, high-density, high-integration, and high-sensitivity functional units have been widely used in radar and communication systems. Sensitive components such as low-noise amplifier chips in the radio frequency (RF) front-end are extremely vulnerable to high-power interference signals from transmitter leakage and antenna reception. The high-power electromagnetic signals entering the receiving link generate electrical, thermal, and biological effects during the interaction of system components, leading to the paralysis or permanent damage of the RF communication system.

[0003] As an important RF control device, the impedance of a microwave limiter changes with the incident microwave power, so it is widely used as a protection device for sensitive components in the RF front-end. When the input power is lower than the threshold power for limiting, the microwave limiter allows the signal to pass through with low loss; when the input power is higher than the threshold power for limiting, the signal is reflected or absorbed due to impedance mismatch, and the output power remains constant, which is called the flat leakage power. According to the limiting element, limiters can be divided into plasma limiters, ferrite limiters, high (low) temperature superconducting limiters, and solid-state limiters. The first three types of limiters are not suitable for current RF front-end systems due to strict usage environments, complex processing technologies, and high costs. Solid-state limiters commonly use field-effect transistors, Schottky diodes, and PIN diodes as limiting units. Field-effect transistors require additional bias circuits, and Schottky diodes cannot withstand high power due to their thin depletion layers resulting in low breakdown voltages and large reverse leakage currents. Therefore, PIN diodes are more commonly used in current limiter designs.

[0004] The working principle of a PIN diode limiter is as follows: Based on the non-linear limiting mechanism of a microwave semiconductor diode, the equivalent impedance of a PIN diode is controlled by the microwave power applied to it. Under the action of high-power microwave signals, a unique radio frequency conductance modulation effect will occur, realizing effective attenuation of the input signal. Small-power signals are not sufficient to turn on the PIN diode and pass through with low loss, thereby protecting sensitive devices in the RF front-end from being damaged by high-power radiation energy.

[0005] For limiters based on printed circuit board (PCB) technology, in order to obtain a high power capacity, large-size discrete PIN diodes are used, and severe parasitic effects at high frequencies lead to high insertion loss, thus affecting the overall noise figure and gain of the receiving link; in addition, the inherent large size of board-level circuits does not conform to the trend of high density and high integration of current RF front-end systems.

[0006] The prior art multi-stage limiter based on chip technology can only operate within a narrow band due to the diode turn-off capacitance of different-stage limiter circuits affecting impedance matching. Additionally, the quarter-wavelength transmission line serving as the inter-stage matching network causes the chip size to increase significantly as the number of limiter circuit stages increases.

[0007] Therefore, in the design of microwave limiters, how to reduce insertion loss, broaden the operating frequency band, and simultaneously achieve circuit miniaturization is an urgent problem to be solved currently. Summary of the Invention

[0008] The object of the present invention is to design a broadband low-insertion-loss limiter chip based on a hybrid π-type topology to solve the problems of high small-signal insertion loss, narrow operating bandwidth, and large size of existing microwave limiters.

[0009] The present invention solves the above technical problems through the following technical solutions:

[0010] A broadband low-insertion-loss limiter chip based on a hybrid π-type topology includes: a first-stage limiter circuit (11), a second-stage limiter circuit (12), and a third-stage limiter circuit (13) attached to a microwave dielectric substrate (10), an input main transmission line (14), a first tapered U-shaped transmission line (15), a second tapered U-shaped transmission line (16), a first capacitive stub (17), a second capacitive stub (18), and an output transmission line (19) etched on the microwave dielectric substrate (10);

[0011] The input main transmission line (14), the first tapered U-shaped transmission line (15), the second tapered U-shaped transmission line (16), and the output transmission line (19) are connected end to end in sequence to form a transmission channel for radio frequency signals; the first-stage limiter circuit (11), the second-stage limiter circuit (12), the third-stage limiter circuit (13), the first capacitive stub (17), and the second capacitive stub (18) are all loaded on the transmission channel;

[0012] The first-stage limiter circuit (11), the first tapered U-shaped transmission line (15), the second-stage limiter circuit (12), and the first capacitive stub (17) form a first π-type structure, and the second-stage limiter circuit (12), the first capacitive stub (17), the second tapered U-shaped transmission line (16), the second capacitive stub (18), and the third-stage limiter circuit (13) form a second π-type structure. The first π-type structure and the second π-type structure share the second-stage limiter circuit (12) and the first capacitive stub (17) to form a hybrid π-type structure;

[0013] The first capacitive stub (17) is used to adjust the total equivalent capacitance C of the second-stage limiter circuit (12) L2such that the equivalent capacitance of the first capacitive stub (17) and the total equivalent capacitance C of the second limiter circuit (12) L2 add up to 2C L1 The second capacitive stub (18) is used to adjust the total equivalent capacitance C of the third limiter circuit (13) L3 such that the equivalent capacitance of the second capacitive stub (18) and the total equivalent capacitance C of the third limiter circuit (13) L3 add up to C L1 .

[0014] The technical solution of the present invention designs a hybrid π-type structure with capacitive loading to replace the traditional quarter-wavelength transmission line between adjacent-stage limiter circuits. The electrical lengths of the first tapered U-shaped transmission line (15) and the second tapered U-shaped transmission line (16) included in the two hybrid π-type structures are much less than 90° and are bent, thereby reducing the area of the limiter chip; the total cut-off capacitance of the first-stage limiter circuit (11) is small, reducing the small-signal insertion loss of the limiter circuit; and since the electrical length of the transmission line is shortened, its physical length is also correspondingly shortened. Therefore, the small-signal insertion loss of the limiter chip is reduced; in the two hybrid π-type structures, the total turn-off capacitance of each stage of the limiter circuit is absorbed into the hybrid π-type structure, making the limiter equivalent to a quasi-50-ohm transmission line model at small signals, thereby eliminating the influence of the turn-off capacitance reactance loaded on the transmission channel on impedance matching and expanding the operating bandwidth of the limiter.

[0015] Further, the input port and the output port of the chip both adopt the GSG form and the wafer-level GaAs PIN AB process. The material of the microwave dielectric substrate (10) is GaAs, with a dielectric constant of 12.9, a loss tangent of 0.001, and a thickness of 0.1 mm.

[0016] Further, the first - stage limiting circuit (11) includes two sets of series - parallel limiting units. The two sets of series - parallel limiting units are symmetrically loaded on the main input transmission line (14) in a form of reverse parallel connection; each set of series - parallel limiting units includes a parallel PIN diode pair (111) and a first series PIN diode pair (112); the anodes of the two PIN diodes in the parallel PIN diode pair (111) in the first set of series - parallel limiting units are respectively grounded, the cathodes of the parallel PIN diode pair (111) in the first set of series - parallel limiting units and the anodes of the first series PIN diode pair (112) in the first set of series - parallel limiting units are connected by a microstrip line, the cathodes of the first series PIN diode pair (112) in the first set of series - parallel limiting units and the anodes of the first series PIN diode pair (112) in the second set of series - parallel limiting units are both connected to the main input transmission line (14) by a microstrip line; the cathodes of the first series PIN diode pair (112) in the second set of series - parallel limiting units and the anodes of the two PIN diodes in the parallel PIN diode pair (111) in the second set of series - parallel limiting units are connected by a microstrip line, and the cathodes of the two PIN diodes in the parallel PIN diode pair (111) in the second set of series - parallel limiting units are respectively grounded.

[0017] Further, the second - stage limiting circuit (12) includes two sets of series limiting units. The two sets of series limiting units are loaded on the output end of the first tapered U - shaped transmission line (15) in a form of reverse parallel connection; each set of series limiting units includes a second series PIN diode pair (121); the anode of the second series PIN diode pair (121) in the first set of series limiting units is grounded, the cathodes of the second series PIN diode pair (121) in the first set of series limiting units and the anodes of the second series PIN diode pair (121) in the second set of series limiting units are both connected to the output end of the first tapered U - shaped transmission line (15) by a microstrip line, and the cathode of the second series PIN diode pair (121) in the second set of series limiting units is grounded.

[0018] Further, the third - stage limiting circuit (13) includes two sets of single - transistor limiting units. The two sets of single - transistor limiting units are loaded on the output end of the second tapered U - shaped transmission line (16) in a form of reverse parallel connection; each set of single - transistor limiting units includes a PIN diode single - transistor (131), the anode of the first PIN diode single - transistor (131) is grounded, the cathodes of the first PIN diode single - transistor (131) and the anodes of the second PIN diode single - transistor (131) are both connected to the output end of the second tapered U - shaped transmission line (16) by a microstrip line, and the cathode of the second PIN diode single - transistor (131) is grounded.

[0019] Further, the main transmission line (14) at the input end is a rectangular microstrip line. One end of the main transmission line (14) at the input end is loaded with a radio frequency incident signal, and the other end of the main transmission line (14) at the input end is connected to the connection common point of two groups of first series PIN diode pairs (112) of the first-stage limiting circuit (11); the transmission line (19) at the output end is a tapered microstrip line. One end of the transmission line (19) at the output end is connected to the connection common point of two PIN diode single tubes (131) of the third-stage limiting circuit (13), and the other end of the transmission line (19) at the output end serves as the emission end of the radio frequency signal.

[0020] Further, both the input end and the output end of the first tapered U-shaped transmission line (15) are tapered microstrip lines, and the middle section is a microstrip line bent into a U shape; the input end of the first tapered U-shaped transmission line (15) is connected to the connection common point of two groups of first series PIN diode pairs (112) of the first-stage limiting circuit (11), and the output end of the first tapered U-shaped transmission line (15) is connected to the connection common point of two groups of second series PIN diode pairs (121) of the second-stage limiting circuit (12); both the input end and the output end of the second tapered U-shaped transmission line (16) are tapered microstrip lines, and the middle section is a microstrip line bent into a U shape; the input end of the second tapered U-shaped transmission line (16) is connected to the connection common point of two groups of second series PIN diode pairs (121) of the second-stage limiting circuit (12), and the output end of the second tapered U-shaped transmission line (16) is connected to the connection common point of two PIN diode single tubes (131) of the third-stage limiting circuit (13).

[0021] Further, the calculation formula for the electrical length θ1 of the first tapered U-shaped transmission line (15) and the second tapered U-shaped transmission line (16) is as follows:

[0022] θ1 = arccos(C L1 ω0Z0) (1)

[0023]

[0024] Where C L1 is the total equivalent capacitance of the first-stage limiting circuit (11), C D1 is the equivalent capacitance of the PIN diode in the first series PIN diode pair (112), C' D1 is the equivalent capacitance of the PIN diode in the parallel PIN diode pair (111), Z0 is the characteristic impedance of the main transmission line (14) at the input end, and ω0 is the operating angular frequency.

[0025] Further, the first capacitive stub (17) is an open - circuited microstrip line. One end of the first capacitive stub (17) is connected to the input end of the second tapered U - shaped transmission line (16), and the other end of the first capacitive stub (17) is open - circuited. A parallel - plate capacitor is formed between the first capacitive stub (17) and the ground plane on the back of the microwave dielectric substrate (10); the second capacitive stub (18) is an open - circuited microstrip line. One end of the second capacitive stub (18) is connected to the output end of the second tapered U - shaped transmission line (16), and the other end of the second capacitive stub (18) is open - circuited. A parallel - plate capacitor is formed between the second capacitive stub (18) and the ground plane on the back of the microwave dielectric substrate (10).

[0026] Further, the calculation formulas for the electrical lengths θ2 and θ3 of the first capacitive stub (17) and the second capacitive stub (18) are as follows:

[0027]

[0028] θ2 = arctan[ω0Z1(2C L1 - C L2 )] (4)

[0029] θ3 = arctan[ω0Z1(C L1 - C L3 )] (5)

[0030] Wherein, Z0 is the characteristic impedance of the main transmission line (14) at the input end, θ1 is the electrical length of the first tapered U - shaped transmission line (15) and the second tapered U - shaped transmission line (16), ω0 is the operating angular frequency, C L2 is the total equivalent capacitance of the second - stage limiter circuit (12), and C L3 is the total equivalent capacitance of the third - stage limiter circuit (13).

[0031] The advantages of the present invention are as follows:

[0032] (1) The technical solution of the present invention designs a hybrid π - type structure with capacitive loading to replace the traditional quarter - wavelength transmission line between adjacent - stage limiter circuits. The electrical lengths of the first tapered U - shaped transmission line (15) and the second tapered U - shaped transmission line (16) included in the two hybrid π - type structures are much less than 90° and are bent, thereby reducing the area of the limiter chip; since the electrical length of the transmission line is shortened, its physical length is also correspondingly shortened. Therefore, the small - signal insertion loss of the limiter chip is reduced; in the two hybrid π - type structures, the turn - off capacitance of the PIN diode in each stage of the limiter circuit is absorbed into the parallel - grounded capacitance of the π - type structure, making the overall limiter circuit equivalent to a quasi - 50 - ohm transmission - line model at small signals, eliminating the influence of the turn - off capacitance reactance loaded on the main transmission path on impedance matching, and expanding the operating frequency band of the limiter.

[0033] (2) The first - stage limiter circuit (11), the second - stage limiter circuit (12), and the third - stage limiter circuit (13) are used to reflect high - power input signals and reduce the limiter output level. They have a capacitive - loaded hybrid - π structure, which is used to reduce the circuit size and improve impedance matching to enhance the working bandwidth. In the first - stage limiter circuit (11), the series structure of three - order PIN diodes reduces the total cut - off capacitance of the first - stage limiter circuit (11), reduces the small - signal insertion loss of the limiter circuit, and the series structure increases the total breakdown voltage of the first - stage limiter circuit (11), improving the steady - state power capacity of the limiter circuit. The parallel structure in the parallel PIN diode pair (111) reduces the total on - resistance of the first - stage limiter circuit (11), reduces the power dissipated by the PIN diodes themselves, and increases the power reflected due to impedance mismatch of the limiter circuit, thus enhancing the transient power capacity of the limiter circuit. Compared with traditional series - type and parallel - type topologies, the series - parallel limiter circuit can further reduce the small - signal insertion loss while maintaining sufficient power capacity.

[0034] (3) The open - circuit capacitive stub used to adjust the equivalent capacitance of the limiter circuit, whose equivalent grounded capacitance is a parallel - plate capacitance formed by the microstrip line on the dielectric substrate and the ground plane on the other side of the dielectric substrate. Compared with the structure using MIM capacitors and grounding vias, it can reduce the circuit complexity and reduce the circuit processing error. Description of the Drawings

[0035] Figure 1 It is the three - dimensional structure diagram of the broadband low - insertion - loss limiter chip based on the hybrid - π topology according to the embodiment of the present invention;

[0036] Figure 2 It is the equivalent circuit schematic diagram of the broadband low - insertion - loss limiter chip based on the hybrid - π topology according to the embodiment of the present invention;

[0037] Figure 3 It is the small - signal equivalent circuit diagram of the traditional limiter using a quarter - wavelength transmission line;

[0038] Figure 4 (a) is the traditional quarter - wavelength transmission line model diagram, Figure 4 (b) is the π - type structure model diagram equivalent to the quarter - wavelength transmission line;

[0039] Figure 5 It is the small - signal equivalent circuit diagram of the limiter with a capacitive - loaded hybrid - π structure according to the embodiment of the present invention;

[0040] Figure 6 It is the small - signal equivalent circuit diagram of the broadband low - insertion - loss limiter chip based on the hybrid - π topology according to the embodiment of the present invention;

[0041] Figure 7Comparison display diagram of insertion loss results of different - structure limiting circuits of the broadband low - insertion - loss limiter chip based on the hybrid π - type topology according to the embodiments of the present invention;

[0042] Figure 8 Comparison display diagram of power - capacity results of different - structure limiting circuits of the broadband low - insertion - loss limiter chip based on the hybrid π - type topology according to the embodiments of the present invention;

[0043] Figure 9 Comparison display diagram of insertion loss results of limiting circuits with different numbers of stages of the broadband low - insertion - loss limiter chip based on the hybrid π - type topology according to the embodiments of the present invention;

[0044] Figure 10 Comparison display diagram of limiting - level results of limiting circuits with different numbers of stages of the broadband low - insertion - loss limiter chip based on the hybrid π - type topology according to the embodiments of the present invention;

[0045] Figure 11 Comparison display diagram of insertion loss results of the structure substituting the traditional quarter - wavelength transmission line of the broadband low - insertion - loss limiter chip based on the hybrid π - type topology according to the embodiments of the present invention;

[0046] Figure 12 Comparison display diagram of voltage - standing - wave - ratio results of the structure substituting the traditional quarter - wavelength transmission line and the hybrid π - type structure of the broadband low - insertion - loss limiter chip based on the hybrid π - type topology according to the embodiments of the present invention. Detailed implementation manners

[0047] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art without making creative efforts based on the embodiments of the present invention belong to the scope of protection of the present invention.

[0048] The technical solutions of the present invention will be further described below in conjunction with the accompanying drawings of the specification and specific embodiments:

[0049] Embodiment 1

[0050] 1. Structure of the broadband low - insertion - loss limiter chip based on the hybrid π - type topology of the present invention

[0051] As Figure 1 and Figure 2As shown in the figure, a broadband low-loss limiter chip based on a hybrid π-type topology includes a first-stage limiter circuit 11, a second-stage limiter circuit 12, and a third-stage limiter circuit 13 attached to a microwave dielectric substrate 10, an input main transmission line 14, a first tapered U-shaped transmission line 15, a second tapered U-shaped transmission line 16, a first capacitive stub 17, a second capacitive stub 18, an output transmission line 19, six pads 20 etched on the microwave dielectric substrate 10, and twelve ground vias 21 opened on the microwave dielectric substrate 10.

[0052] The first-stage limiter circuit 11 includes two sets of series-parallel limiter units. The two sets of series-parallel limiter units are symmetrically loaded on the input main transmission line 14 in a reverse-parallel form. The specific connection relationship is as follows:

[0053] Each set of series-parallel limiter units includes a parallel PIN diode pair 111 and a first series PIN diode pair 112. The anodes of the two PIN diodes in the parallel PIN diode pair 111 in the first set of series-parallel limiter units are respectively connected to the ground vias 21. The cathode of the parallel PIN diode pair 111 in the first set of series-parallel limiter units is connected to the anode of the first series PIN diode pair 112 in the first set of series-parallel limiter units through a microstrip line. The cathodes of the first series PIN diode pair 112 in the first set of series-parallel limiter units and the anode of the first series PIN diode pair 112 in the second set of series-parallel limiter units are both connected to the input main transmission line 14 through microstrip lines. The cathode of the first series PIN diode pair 112 in the second set of series-parallel limiter units is connected to the anodes of the two PIN diodes in the parallel PIN diode pair 111 in the second set of series-parallel limiter units through a microstrip line. The cathodes of the two PIN diodes in the parallel PIN diode pair 111 in the second set of series-parallel limiter units are respectively connected to the ground vias 21.

[0054] The second-stage limiter circuit 12 includes two sets of series limiter units. The two sets of series limiter units are loaded on the output end of the first tapered U-shaped transmission line 15 in a reverse-parallel form. The specific connection relationship is as follows:

[0055] Each set of series limiter units includes a second series PIN diode pair 121. The anode of the second series PIN diode pair 121 in the first set of series limiter units is connected to the ground vias 21. The cathodes of the second series PIN diode pair 121 in the first set of series limiter units and the anode of the second series PIN diode pair 121 in the second set of series limiter units are both connected to the output end of the first tapered U-shaped transmission line 15 through microstrip lines. The cathode of the second series PIN diode pair 121 in the second set of series limiter units is connected to the ground vias 21.

[0056] The described third-stage limiting circuit 13 includes two sets of single-tube limiting units, and the two sets of single-tube limiting units are loaded at the output end of the second tapered U-shaped transmission line 16 in a reverse-parallel form. The specific connection relationship is as follows:

[0057] Each set of single-tube limiting units includes a PIN diode single tube 131. The anode of the first PIN diode single tube 131 is connected to the ground via hole 21. The cathode of the first PIN diode single tube 131 and the anode of the second PIN diode single tube 131 are both connected to the output end of the second tapered U-shaped transmission line 16 through microstrip lines. The cathode of the second PIN diode single tube 131 is connected to the ground via hole 21.

[0058] The described input main transmission line 14 is a rectangular microstrip line. The input and output ports of the chip both adopt the GSG form and use the wafer-level GaAs PINAB process. The material of the microwave dielectric substrate 10 is GaAs, with a dielectric constant of 12.9, a loss tangent of 0.001, and a thickness of 0.1 mm. One end of the microwave dielectric substrate 10 is provided with a row of 3 pads 20. One end of the input main transmission line 14 is connected to the middle pad 20 and loads the radio frequency incident signal. The other two pads 20 are respectively connected to the ground via holes 21 and load the ground signal. The other end of the input main transmission line 14 is connected to the connection common point of the two sets of first series PIN diode pairs 112 of the first-stage limiting circuit 11;

[0059] The input end and the output end of the described first tapered U-shaped transmission line 15 are both a section of tapered microstrip line, and the middle section is a microstrip line bent into a U shape. The input end of the first tapered U-shaped transmission line 15 is connected to the connection common point of the two sets of first series PIN diode pairs 112 of the first-stage limiting circuit 11, and the output end of the first tapered U-shaped transmission line 15 is connected to the connection common point of the two sets of second series PIN diode pairs 121 of the second-stage limiting circuit 12;

[0060] The input end and the output end of the described second tapered U-shaped transmission line 16 are both a section of tapered microstrip line, and the middle section is a microstrip line bent into a U shape. The input end of the second tapered U-shaped transmission line 16 is connected to the connection common point of the two sets of second series PIN diode pairs 121 of the second-stage limiting circuit 12, and the output end of the second tapered U-shaped transmission line 16 is connected to the connection common point of the two PIN diode single tubes 131 of the third-stage limiting circuit 13;

[0061] The described first capacitive stub 17 is a section of open-circuit microstrip line. One end of the first capacitive stub 17 is connected to the input end of the second tapered U-shaped transmission line 16, and the other end of the first capacitive stub 17 is open-circuited. A parallel-plate capacitor is formed between the first capacitive stub 17 and the ground plane on the back of the microwave dielectric substrate 10;

[0062] The second capacitive stub 18 is an open - circuited microstrip line. One end of the second capacitive stub 18 is connected to the output end of the second tapered U - shaped transmission line 16, and the other end of the second capacitive stub 18 is open - circuited. A parallel - plate capacitor is formed between the second capacitive stub 18 and the ground plane on the back of the microwave dielectric substrate 10;

[0063] The output - end transmission line 19 is a tapered microstrip line. One end of the output - end transmission line 19 is connected to the common connection point of two PIN diode transistors 131 in the third - stage limiting circuit 13. Three pads 20 are arranged in a row at the other end of the microwave dielectric substrate 10. The other end of the output - end transmission line 19 is connected to the middle pad 20 as the RF signal output end, and the other two pads 20 are respectively connected to the ground vias 21 and loaded with ground signals.

[0064] The first - stage limiting circuit 11, the first tapered U - shaped transmission line 15, the second - stage limiting circuit 12, and the first capacitive stub 17 form the first π - type structure with capacitive loading. The second - stage limiting circuit 12, the second tapered U - shaped transmission line 16, the first capacitive stub 17, the second capacitive stub 18, and the third - stage limiting circuit 13 form the second π - type structure with capacitive loading. The first π - type structure with capacitive loading and the second π - type structure with capacitive loading share the second - stage limiting circuit 12 and the first capacitive stub 17, thus forming a hybrid π - type structure.

[0065] 2. Principle of the hybrid π - type structure with capacitive loading proposed by the present invention

[0066] As Figure 3 shown, it is the small - signal equivalent circuit diagram of a traditional limiter using a quarter - wavelength transmission line. The quarter - wavelength transmission line TL0 is used as a matching network and loaded between each stage of the limiting circuit. There is a disadvantage that as the number of stages of the limiting circuit increases, the circuit area of the limiter will also increase accordingly, which cannot miniaturize the chip and seriously restricts the application scenarios of the chip.

[0067] As Figure 4 (a) shown, it is a traditional quarter - wavelength transmission line model, Figure 4 (b) shown, it is a π - type structure model equivalent to the quarter - wavelength transmission line, where the values of the two shunt - grounded capacitors C1 are the same.

[0068] As Figure 5 shown, in the hybrid π - type structure with capacitive loading of the present invention, the first tapered U - shaped transmission line 15 ( Figure 5 TL1 therein) and the second tapered U - shaped transmission line 16 ( Figure 5 TL2 therein) are used to replace Figure 3Two traditional quarter - wavelength transmission lines TL0 therein, the calculation formulas for the electrical length θ1 of the first tapered U - shaped transmission line 15 and the second tapered U - shaped transmission line 16 are as follows:

[0069] θ1 = arccos(C L1 ω0Z0) (1)

[0070]

[0071] Wherein, C L1 is the total equivalent capacitance of the first - stage limiting circuit 11, C D1 is the equivalent capacitance of the PIN diode in the first series PIN diode pair 112, C' D1 is the equivalent capacitance of the PIN diode in the parallel PIN diode pair 111, Z0 is the characteristic impedance of the input - end main transmission line 14, and ω0 is the operating angular frequency.

[0072] It can be seen from formula (1) that the electrical lengths of the first tapered U - shaped transmission line 15 and the second tapered U - shaped transmission line 16 are less than 90°, and bending treatment is performed, so circuit miniaturization can be achieved.

[0073] From the principle that the traditional quarter - wavelength transmission line shown in Figure 4 (a) and Figure 4 (b) is equivalent to a π - type structure model, it is necessary for the present invention to ensure that the parallel - grounded capacitance values at both ends of the first tapered U - shaped transmission line 15 are equal and are C L1 , and at the same time ensure that the parallel - grounded capacitance values at both ends of the second tapered U - shaped transmission line 16 are equal and are C L1 ;

[0074] As shown in Figure 5 , the specific method is as follows:

[0075] The first capacitive stub 17 ( Figure 5 TL3 therein) is used to adjust the total equivalent capacitance C L2 of the second - stage limiting circuit 12, so that the sum of the equivalent capacitance of the first capacitive stub 17 and the total equivalent capacitance C L2 of the second - stage limiting circuit 12 is equal to 2C L1 , and the second capacitive stub 18 ( Figure 5 TL4 therein) is used to adjust the total equivalent capacitance C L3 of the third - stage limiting circuit 13, so that the sum of the equivalent capacitance of the second capacitive stub 18 and the total equivalent capacitance C L3 of the third - stage limiting circuit 13 is equal to C L1, thus the total turn-off capacitance of each stage of the limiting circuit is absorbed into the hybrid-π structure, making the limiter equivalent to a quasi-50-ohm transmission line model at small signals, thereby eliminating the influence of the capacitive reactance of the turn-off capacitance loaded on the transmission channel on impedance matching and expanding the operating bandwidth of the limiter.

[0076] To simplify impedance matching, the characteristic impedances of the first capacitive stub 17 and the second capacitive stub 18 are equal to the characteristic impedances of the first tapered U-shaped transmission line 15 and the second tapered U-shaped transmission line 16 in the hybrid-π structure and are Z1. Therefore, the calculation formulas for the electrical lengths θ2 and θ3 of the first capacitive stub 17 and the second capacitive stub 18 are as follows:

[0077]

[0078] θ2 = arctan[ω0Z1(2C L1 -C L2 )] (4)

[0079] θ3 = arctan[ω0Z1(C L1 -C L3 )] (5)

[0080] Where C L2 is the total equivalent capacitance of the second-stage limiting circuit 12, and C L3 is the total equivalent capacitance of the third-stage limiting circuit 13.

[0081] 3. Performance analysis of the broadband low-loss limiter chip based on the hybrid-π topology of the present invention

[0082] 3.1. Reduced insertion loss of the limiting circuit

[0083] As Figure 6 shown, it is the small-signal equivalent circuit diagram of the broadband low-loss limiter based on the hybrid-π topology of the present invention. Since the PIN diode is equivalent to its turn-off capacitance at small signals.

[0084] The first series PIN diode pair 112 in the first-stage limiting circuit 11 is equivalent to two series capacitors C D1 , and the shunt PIN diode pair 111 is equivalent to two shunt capacitors C' D1 . Therefore, the first-stage limiting circuit 11 is equivalent to two shunt capacitors C' D1 in series with four capacitors C D1 , and then in series with two shunt capacitors C' D1 ;

[0085] The second series PIN diode pair 121 in the second-stage limiting circuit 12 is equivalent to two series capacitors C D2, therefore, the second - stage limiting circuit 12 is equivalent to four capacitors C D2 connected in series;

[0086] The PIN diode single tube 131 in the third - stage limiting circuit 13 is equivalent to a capacitor C D3 , therefore, the third - stage limiting circuit 13 is equivalent to two capacitors C D3 connected in series;

[0087] Since the calculation formula for the insertion loss of the limiting circuit is as follows:

[0088] IL=4.343Z0(2πfC off ) 2 R s (6)

[0089] where, Z0 is the characteristic impedance of the main transmission line, f is the operating frequency of the limiting circuit, C off is the total equivalent capacitance of the limiting circuit, R s is the parasitic resistance of the limiting circuit;

[0090] According to the principle of capacitor series connection, the capacitance is reduced in series connection of capacitors. Therefore, the total equivalent capacitance C of the limiting circuit is reduced by using the way of capacitor series connection off , thus reducing the insertion loss of the limiting circuit.

[0091] 3.2. The steady - state power capacity of the limiting circuit is improved

[0092] The calculation formula for the steady - state power capacity of the limiting circuit is as follows:

[0093]

[0094] where, N S is the series order of PIN diodes in the limiting circuit, V BR is the breakdown voltage of the PIN diode;

[0095] When the PIN diode in the limiting circuit is in the steady state, it will bear the corresponding reverse bias voltage. Since the multi - stage PIN diodes in the limiting circuit are all in series connection, the total breakdown voltage can be increased, thus improving the steady - state power capacity of the limiting circuit.

[0096] 3.3. The transient power capacity of the limiting circuit is improved

[0097] The calculation formula for the transient power capacity of the limiting circuit is as follows:

[0098]

[0099] where, P DM$P_{max}$ is the maximum allowable dissipation power of the PIN diode, and $R_{on}$ is the total on-resistance of the PIN diodes in the limiting circuit. $R_{on}$ is much smaller than $Z_0$.

[0100] According to the principle of parallel resistors, parallel resistors can reduce the resistance value. In the first-stage limiting circuit 11, a parallel PIN diode pair 111 and two sets of series-parallel limiting units are reversely connected in parallel to the main transmission line 14 at the input end. The total on-resistance of the first-stage limiting circuit 11 is reduced by the parallel resistor method, thereby improving the transient power capacity of the limiting circuit.

[0101] 3.4. Reduced the output power of the limiting circuit

[0102] The calculation formula for the output power of the limiting circuit is as follows:

[0103]

[0104] Among them, $P_{in}$ is the incident power of the limiting circuit. Since the series connection of multiple-stage PIN diodes in the first-stage limiting circuit 11 increases the breakdown voltage while also increasing the total on-resistance, resulting in an increase in the output power. In addition, the threshold level for limiting also increases accordingly. The second-stage limiting circuit 12 of the present invention uses 2 PIN diodes in series and the third-stage limiting circuit 13 uses a single PIN diode, reducing the total on-resistance of the limiting circuit, thereby reducing the output power of the limiting circuit.

[0105] 4. Comparative analysis and demonstration

[0106] As Figure 7 and Figure 8 shown, a comparison chart of the insertion loss and power capacity of the first-stage limiting circuit with different structures of a broadband low-loss limiter based on a hybrid π-type topology is provided, showing that the proposed series-parallel limiting circuit can further reduce the insertion loss while maintaining sufficient power capacity compared to traditional series or parallel limiting circuits, solving the trade-off problem between the insertion loss and power capacity of the limiter;

[0107] As Figure 9 and 10 shown, a comparison chart of the insertion loss and output power of the limiting circuit with different stages of a broadband low-loss limiter based on a hybrid π-type topology is provided, showing that using a three-stage limiting circuit topology can effectively reduce the output power without significantly increasing the insertion loss.

[0108] As Figure 11 shown, a comparison chart of the insertion loss of a structure that replaces the traditional quarter-wavelength transmission line of a broadband low-loss limiter based on a hybrid π-type topology is provided, showing that the proposed π-type structure can further reduce the insertion loss while reducing the circuit area.

[0109] As Figure 12 shown, on the basis of the π-type structure, a hybrid π-type structure with capacitive loading is improved. The total turn-off capacitance of the PIN diodes in each stage of the limiting circuit is absorbed into the hybrid π-type structure, making the limiter equivalent to a quasi-50-ohm transmission line model at small signals, thereby eliminating the influence of the turn-off capacitance reactance loaded on the main transmission path on impedance matching, expanding the working bandwidth of the limiter. In the frequency band of DC-18 GHz, the voltage standing wave ratio drops from a maximum of 1.9 to 1.3, solving the ultra-wideband matching problem of the limiter circuit.

[0110] In summary, for the broadband low insertion loss limiter chip based on the hybrid π-type topology of the present invention, the first-stage limiting circuit 11, the second-stage limiting circuit 12, and the third-stage limiting circuit 13 are used to reflect high-power input signals and reduce the limiting output level. The hybrid π-type structure with capacitive loading is used to reduce the circuit size and improve impedance matching to increase the working bandwidth; the three-order PIN diode series structure in the first-stage limiting circuit 11 reduces the total cut-off capacitance of the first-stage limiting circuit 11, reduces the small-signal insertion loss of the limiting circuit, and the series structure increases the total breakdown voltage of the first-stage limiting circuit 11, improving the steady-state power capacity of the limiting circuit; the parallel structure in the parallel PIN diode pair 111 reduces the total on-resistance of the first-stage limiting circuit 11, reduces the power dissipated by the PIN diode itself, and increases the power reflected due to impedance mismatch of the limiting circuit, thereby improving the transient power capacity of the limiting circuit; compared with the traditional series and parallel topologies, the series-parallel limiting circuit can further reduce the small-signal insertion loss on the premise of maintaining sufficient power capacity; the hybrid π-type structure with capacitive loading is used to replace the traditional quarter-wavelength transmission line between adjacent limiting circuits, and the electrical lengths of the first tapered U-shaped transmission line 15 and the second tapered U-shaped transmission line 16 included in the two hybrid π-type structures are much less than 90° and are bent, thereby reducing the area of the limiter chip. The hybrid π-type structure with capacitive loading absorbs the PIN diode turn-off capacitance affecting impedance matching in each stage of the limiting circuit into the parallel grounded capacitance of the π-type structure, making the overall circuit equivalent to a quasi-50-ohm transmission line model at small signals, thereby expanding the working frequency band of the limiter; compared with the traditional quarter-wavelength transmission line, the hybrid π-type structure with capacitive loading can reduce the circuit size and increase the working bandwidth of the limiter, improve the versatility, and conform to the current trend of miniaturization and high integration of the radio frequency front-end system. The limiter has the advantages of low small-signal insertion loss, wide working bandwidth, and small circuit size.

[0111] The above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A broadband low-loss limiter chip based on a hybrid π-type topology, characterized in that, Comprising: A first-stage limiting circuit (11), a second-stage limiting circuit (12), and a third-stage limiting circuit (13) attached to a microwave dielectric substrate (10), an input main transmission line (14), a first tapered U-shaped transmission line (15), a second tapered U-shaped transmission line (16), a first capacitive stub (17), a second capacitive stub (18), and an output transmission line (19) etched on the microwave dielectric substrate (10); The input main transmission line (14), the first tapered U-shaped transmission line (15), the second tapered U-shaped transmission line (16), and the output transmission line (19) are connected end to end in sequence to form a transmission channel for radio frequency signals; the first-stage limiting circuit (11), the second-stage limiting circuit (12), the third-stage limiting circuit (13), the first capacitive stub (17), and the second capacitive stub (18) are all loaded on the transmission channel; The first-stage limiting circuit (11), the first tapered U-shaped transmission line (15), the second-stage limiting circuit (12), and the first capacitive stub (17) form a first π-type structure, and the second-stage limiting circuit (12), the first capacitive stub (17), the second tapered U-shaped transmission line (16), the second capacitive stub (18), and the third-stage limiting circuit (13) form a second π-type structure. The first π-type structure and the second π-type structure share the second-stage limiting circuit (12) and the first capacitive stub (17) to form a hybrid π-type structure; The first capacitive stub (17) is used to adjust the total equivalent capacitance C of the second-stage limiting circuit (12). L2 such that the equivalent capacitance of the first capacitive stub (17) and the total equivalent capacitance C of the second-stage limiting circuit (12). L2 sum up to 2C L1 The second capacitive stub (18) is used to adjust the total equivalent capacitance C of the third-stage limiting circuit (13). L3 such that the equivalent capacitance of the second capacitive stub (18) and the total equivalent capacitance C of the third-stage limiting circuit (13). L3 sum up to C L1 .

2. The broadband low insertion loss limiter chip based on the hybrid π-type topology according to claim 1, wherein The input port and output port of the chip both adopt the GSG form and use the wafer-level GaAs PIN AB process. The material of the microwave dielectric substrate (10) is GaAs, with a dielectric constant of 12.9, a loss tangent of 0.001, and a thickness of 0.1 mm.

3. The broadband low insertion loss limiter chip based on the hybrid π-type topology according to claim 1, characterized in that, The first-stage limiting circuit (11) includes two sets of series-parallel limiting units. The two sets of series-parallel limiting units are symmetrically loaded on the input main transmission line (14) in a reverse parallel form; each set of series-parallel limiting units includes a parallel PIN diode pair (111) and a first series PIN diode pair (112); the anodes of the two PIN diodes in the parallel PIN diode pair (111) in the first set of series-parallel limiting units are respectively grounded. The cathode of the parallel PIN diode pair (111) in the first set of series-parallel limiting units is connected to the anode of the first series PIN diode pair (112) in the first set of series-parallel limiting units through a microstrip line. The cathodes of the first series PIN diode pair (112) in the first set of series-parallel limiting units and the anode of the first series PIN diode pair (112) in the second set of series-parallel limiting units are both connected to the input main transmission line (14) through microstrip lines; the cathode of the first series PIN diode pair (112) in the second set of series-parallel limiting units is connected to the anodes of the two PIN diodes in the parallel PIN diode pair (111) in the second set of series-parallel limiting units through a microstrip line, and the cathodes of the two PIN diodes in the parallel PIN diode pair (111) in the second set of series-parallel limiting units are respectively grounded.

4. The broadband low insertion loss limiter chip based on the hybrid π-type topology according to claim 3, characterized in that, The described second-stage limiting circuit (12) includes two groups of series limiting units, and the two groups of series limiting units are loaded at the output end of the first tapered U-shaped transmission line (15) in a reverse parallel form; each group of series limiting units includes a second series PIN diode pair (121); the anode of the second series PIN diode pair (121) in the first group of series limiting units is grounded, and the cathode of the second series PIN diode pair (121) in the first group of series limiting units and the anode of the second series PIN diode pair (121) in the second group of series limiting units are both connected to the output end of the first tapered U-shaped transmission line (15) through a microstrip line, and the cathode of the second series PIN diode pair (121) in the second group of series limiting units is grounded.

5. The broadband low insertion loss limiter chip based on the hybrid π-type topology according to claim 4, characterized in that, The described third-stage limiting circuit (13) includes two groups of single-tube limiting units, and the two groups of single-tube limiting units are loaded at the output end of the second tapered U-shaped transmission line (16) in a reverse parallel form; each group of single-tube limiting units includes a PIN diode single tube (131), the anode of the first PIN diode single tube (131) is grounded, and the cathode of the first PIN diode single tube (131) and the anode of the second PIN diode single tube (131) are both connected to the output end of the second tapered U-shaped transmission line (16) through a microstrip line, and the cathode of the second PIN diode single tube (131) is grounded.

6. The broadband low insertion loss limiter chip based on the hybrid π-type topology according to claim 5, wherein The described input main transmission line (14) is a rectangular microstrip line, one end of the input main transmission line (14) is loaded with a radio frequency incident signal, and the other end of the input main transmission line (14) is connected to the connection common point of the two groups of first series PIN diode pairs (112) of the first-stage limiting circuit (11); the described output transmission line (19) is a tapered microstrip line, one end of the output transmission line (19) is connected to the connection common point of the two PIN diode single tubes (131) of the third-stage limiting circuit (13), and the other end of the output transmission line (19) is used as the emission end of the radio frequency signal.

7. The broadband low insertion loss limiter chip based on the hybrid π-type topology according to claim 5, characterized in that, Both the input end and the output end of the described first tapered U-shaped transmission line (15) are a section of tapered microstrip line, and the middle section is a microstrip line bent into a U shape; the input end of the first tapered U-shaped transmission line (15) is connected to the connection common point of the two groups of first series PIN diode pairs (112) of the first-stage limiting circuit (11), and the output end of the first tapered U-shaped transmission line (15) is connected to the connection common point of the two groups of second series PIN diode pairs (121) of the second-stage limiting circuit (12); both the input end and the output end of the described second tapered U-shaped transmission line (16) are a section of tapered microstrip line, and the middle section is a microstrip line bent into a U shape; the input end of the second tapered U-shaped transmission line (16) is connected to the connection common point of the two groups of second series PIN diode pairs (121) of the second-stage limiting circuit (12), and the output end of the second tapered U-shaped transmission line (16) is connected to the connection common point of the two PIN diode single tubes (131) of the third-stage limiting circuit (13).

8. The broadband low insertion loss limiter chip based on the hybrid π-type topology according to claim 7, wherein The calculation formula for the electrical length θ1 of the first tapered U-shaped transmission line (15) and the second tapered U-shaped transmission line (16) is as follows: θ1 = arccos(C L1 ω0Z0) (1) Among them, C L1 is the total equivalent capacitance of the first-stage limiting circuit (11), C D1 is the equivalent capacitance of the PIN diode in the first series PIN diode pair (112), C' D1 is the equivalent capacitance of the PIN diode in the parallel PIN diode pair (111), Z0 is the characteristic impedance of the input main transmission line (14), and ω0 is the operating angular frequency.

9. The broadband low-loss limiter chip based on the hybrid π-type topology according to claim 5, wherein The first capacitive stub (17) is an open-circuit microstrip line. One end of the first capacitive stub (17) is connected to the input end of the second tapered U-shaped transmission line (16), and the other end of the first capacitive stub (17) is open-circuited. A parallel-plate capacitor is formed between the first capacitive stub (17) and the ground plane on the back of the microwave dielectric substrate (10); the second capacitive stub (18) is an open-circuit microstrip line. One end of the second capacitive stub (18) is connected to the output end of the second tapered U-shaped transmission line (16), and the other end of the second capacitive stub (18) is open-circuited. A parallel-plate capacitor is formed between the second capacitive stub (18) and the ground plane on the back of the microwave dielectric substrate (10).

10. The broadband low insertion loss limiter chip based on the hybrid π-type topology according to claim 9, characterized in that, The calculation formulas for the electrical lengths θ2 and θ3 of the first capacitive stub (17) and the second capacitive stub (18) are as follows: θ2 = arctan[ω0Z1(2C L1 -C L2 )] (4) θ3=arctan[ω0Z1(C L1 -C L3 )] (5) Among them, Z0 is the characteristic impedance of the main transmission line (14) at the input end, θ1 is the electrical length of the first tapered U-shaped transmission line (15) and the second tapered U-shaped transmission line (16), ω0 is the operating angular frequency, C L2 is the total equivalent capacitance of the second-stage limiting circuit (12), C L3 is the total equivalent capacitance of the third-stage limiting circuit (13).

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