Calibration system for a successive approximation analog-to-digital converter

Abstract

The embodiment of the application discloses a calibration system of a successive approximation analog-to-digital converter, and relates to the field of signal calibration. The SARADC performs a process of once sampling and twice conversion on an input analog signal: in the first conversion, a disturbance signal is not added, and the process is the same as normal analog-to-digital conversion; in the second conversion, the input analog signal is not sampled, and the analog signal sampled in the first conversion is not released, but a disturbance signal is injected in the capacitor DAC through a disturbance capacitor array, without the need of injecting a disturbance signal in the input analog signal, and without the need of inputting the input analog signal with the same phase and amplitude through twice sampling.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of signal calibration, and in particular to a calibration system of a successive approximation register analog-to-digital converter. BACKGROUND

[0002] In the process of integrated circuit manufacturing, there is an error in the capacitance value in a SARADC (successive approximation register analog-to-digital converter), whether the capacitance value is made very small for the purpose of realizing a high-precision SARADC or for the purpose of realizing a high-speed SARADC. The most advanced integrated circuit manufacturing technology cannot guarantee such a high-precision capacitance, so in order to guarantee the effective precision of the SARADC, a calibration technology must be used.

[0003] There are many existing technologies for discussing the digital calibration algorithm of the SARADC. The calibration methods can be divided into analog calibration and digital calibration. The analog calibration method is limited by the precision of the device, and its calibration precision is limited, and generally increases the complexity of the analog circuit and increases the power consumption. With the continuous progress of the process, the development of the digital calibration technology, from the area, power consumption, circuit complexity, the advantage of the digital calibration technology is outstanding, and the mainstream digital calibration method now includes: the SARADC samples the input signal twice during calibration, the first sampling adds a positive offset voltage in the sampling signal, the second sampling adds a negative offset voltage in the sampling signal, and then the weight of the capacitance array is calculated. This requires that both samplings require sampling at the same phase in the period of the input signal, to ensure that the two samplings are consistent. SUMMARY

[0004] Embodiments of the present application provide a calibration system of a successive approximation register analog-to-digital converter, which can solve the problem of high calibration difficulty caused by the need for twice collecting input signals of the same phase and period in the related art. The technical solution is as follows:

[0005] In a first aspect, embodiments of the present application provide a calibration system of a successive approximation register analog-to-digital converter, comprising:

[0006] a signal source, a SARADC, an LMS calibration unit, and a data processing unit;

[0007] The SARADC includes a first capacitance array and a second capacitance array; the output end of the signal source is connected to the input end of the SARADC, the output end of the SARADC is connected to the LMS calibration unit and the data processing unit, and the LMS calibration unit and the data processing unit are connected;

[0008] The SARADC is configured to perform first analog-digital conversion on the analog signal from the signal source to obtain a first digital signal, wherein the second capacitor array is in a non-disturbance state.

[0009] The SARADC is further configured to perform second analog-digital conversion on the disturbance signal generated by the capacitor array to obtain a second digital signal, wherein the second capacitor array is in a disturbance state.

[0010] The LMS calibration unit is configured to perform calibration according to the first digital signal and the second digital signal to obtain a weight vector.

[0011] The data processing unit is configured to perform calibration on an input calibration signal by using the weight vector.

[0012] The technical scheme provided by some embodiments of the present application has at least the following beneficial effects:

[0013] The SARADC performs a sampling and conversion process twice on the input analog signal: the first conversion is the same as normal analog-digital conversion without adding a disturbance signal; the second conversion does not sample the input analog signal nor release the analog signal sampled in the first conversion, but injects a disturbance signal in the comparator through the disturbance capacitor array, without injecting a disturbance signal in the input analog signal nor sampling the input analog signal twice at the same phase and amplitude, so that the calibration by injecting a disturbance signal in the capacitor array can reduce the sampling accuracy requirement and the calibration complexity. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0015] Figure 1 is a structure diagram of a calibration system of a successive approximation analog-digital converter provided by an embodiment of the present application;

[0016] Figure 2 is a principle diagram of calculating a weight vector provided by an embodiment of the present application;

[0017] Figure 3 is a timing diagram of a calibration process provided by an embodiment of the present application;

[0018] Figure 4 is a structure diagram of a capacitor array provided by an embodiment of the present application;

[0019] Figure 5 is another structural schematic diagram of a capacitive array provided by an embodiment of the present application;

[0020] Figure 6 is another timing diagram of a calibration process provided by an embodiment of the present application.

[0021] Figure 7 is another structural schematic diagram of a capacitive array provided by an embodiment of the present application. DETAILED DESCRIPTION

[0022] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0023] Referring to Figure 1 The present application provides a structural schematic diagram of a calibration system of a successive approximation analog-to-digital converter, which comprises a signal source, a SARADC, an LMS calibration unit and a data processing unit.

[0024] The output end of the signal source is connected with the input end of the SARADC, the output end of the SAR is connected with the LMS calibration unit and the data processing unit, and the LMS calibration unit and the data processing unit are connected. The SARDAC comprises a first capacitive array and a second data conversion circuit.

[0025] The working process of the calibration system of the present embodiment comprises the following steps. First, the signal source generates an analog signal Vin, the SARADC is in an open state through the built-in first capacitive array, the second capacitive array is in a non-perturbation state, and the SARADC converts the input analog signal into a digital signal D1. Then, the SARADC does not sample the analog signal at the input end, at this time, the first capacitive array built in the SARADC still retains the analog signal obtained by the first sampling, the second capacitive array is in a perturbation state, the second capacitive array injects a perturbation signal Δa2 into the capacitive DAC, and then the SARADC converts into a digital signal D2. The LMS calibration unit calibrates the digital signal D1 and the digital signal D2 to obtain a weight vector W. Then, the data processing unit calculates the weight vector W obtained and the input analog signal D to be calibrated to perform bit-by-bit multiplication and summation to obtain a final output signal.

[0026] The LMS calibration unit can be a kind of adaptive filter, and the weight vector W can be calculated by using LMS (Least Mean Square) algorithm.

[0027] It should be noted that the calibration system of the present application can be foreground calibration or background calibration. In foreground calibration, the signal source inputs the calibration signal, which is an analog signal of a specific model, and after the LMS calibration unit calculates the weight vector W based on the calibration signal, the signal source inputs the working signal, and then the data processing unit calibrates the working signal using the calculated weight vector. In background calibration, the weight vector obtained by foreground calibration is the initial vector, the signal source inputs the working signal, and the LMS calibration unit calculates the weight vector W based on the current working signal D n The weight vector W is calculated n Then the data processing unit calibrates the next working signal D n using the weight vector W n+1 .

[0028] In the calibration process of the present application, the SARADC performs a sampling and conversion process twice on the input analog signal: the first conversion, without adding a disturbance signal, is the same as normal analog-to-digital conversion; the second conversion does not sample the input analog signal or release the analog signal sampled by the first conversion, but injects a disturbance signal in the capacitor DAC through the disturbance capacitor array, without the need to inject a disturbance signal in the input analog signal or through the input analog signal of the same phase and amplitude in the two sampling processes. Therefore, the present application can reduce the sampling accuracy requirement and the complexity of calibration by injecting a disturbance signal internally through the capacitor array.

[0029] Further, in the present application, the following uses LMS algorithm to calculate the weight vector according to the digital signal D1 and the digital signal D2. The process is described as follows.

[0030] In an ideal case, i.e., the capacitor array built-in in the SARADC is not mismatched:

[0031]

[0032]

[0033] d os is the digital domain conversion value corresponding to the offset of the comparator, D1 is the digital signal output by the SARADC when no disturbance signal is input in an ideal case, and D2 is the digital signal output by the SARADC when a disturbance signal is injected in an ideal case. The bit width of D1 and D2 is n, b 1,i represents the i-th bit value in the digital signal D1, and wi is the weight of the i-th bit value. 2,i represents the i-th bit value in the digital signal D2.

[0034]

[0035] d os Since the contributions of the two conversions are consistent, D1-D2 cancel each other out, so this method cannot calibrate the offset of the comparator.

[0036] △ d The ideal value of the disturbance signal is known, which is artificially added, and the corresponding digital domain conversion value of the disturbance signal is Ccal in the following scrambling circuit. Generally, Ccal is composed of K minimum unit capacitors, so |△ d | = K;△ d The sign is determined by the direction of scrambling. When the effect of injecting the disturbance signal on the input analog signal is equivalent to VI+△a,△ d is positive; when the effect of injecting the disturbance signal on the input analog signal is equivalent to VI-△a,△ d is negative, where△a is a positive voltage.

[0037] When there is a mismatch in the capacitor array.

[0038]

[0039] Define y = error mis -error ideal = error mis +△ d , the mathematical expectation d of which is 0, Data 1,mis is the digital signal output by the SARADC when no disturbance signal is input, Data 2,mis is the digital signal output by the SARADC when the disturbance signal is injected, b represents the bit value, and w represents the weight value. The bit width of the digital signal Data 1,mis and the digital signal Data 2,mis is n, and i represents the serial number of the bit value in the digital signal, i = 1, 2, …, n.

[0040] y = error mis +△ d .

[0041] Define the ADC quantization bit number as n, including redundant bits. m is the number of calibration periods, i.e., m times of calibration are performed. X m,n+1 is an m-row, n+1-column matrix.

[0042] X(:,1:n) = b1(:,LSB,MSB)-b2(:,LSB,MSB); X(1:m,n+1) = 1.

[0043]

[0044] The weight matrix of m calibration cycles is defined, w1 is the weight of LSB in quantized data D, w2 is the weight of the next LSB in quantized data D, and so on, w n is the weight of the MSB of quantized data D, dw is the weight of the disturbance signal. Here, the weight of the disturbance signal is also put into the weight matrix W m,n+1 of the ADC to be solved together.

[0045]

[0046] Therefore, m calibration cycles can obtain m y values: e m = d m -y m .

[0047] dm is a 0 matrix of 1 row and M columns. That is: e m = -y m .

[0048] Referring to the algorithm flowchart shown in Figure 2 , the LMS adaptive filtering algorithm is: y = X * W T ,

[0049] e(m) = d(m) - y(m), w(m+1, :) = w(m, :) + 2 * u * e(m) * x(m, :).

[0050] That is: w(m+1, :) = w(m, :) - 2 * u * y(m) * x(m, :).

[0051] u is the step factor, which affects the convergence speed, 0 < u < 1.

[0052] The initial value of the weight w is w(1, :) which is the ideal weight of each bit of quantized data D and the ideal weight of the quantized disturbance signal △ d .

[0053] In this way, the LMS calibration unit obtains a set of data (D1 and D2) each time, and continuously calculates the new weight w(m+1, :) through the adaptive algorithm, that is, the weight value of the last row in the weight matrix W m,n+1 is solved. The calibration cycle m is determined by the step factor. The smaller u is, the more calibration cycles are needed to calibrate the mismatch; when the capacitance array mismatch is dominant, the smaller u is, the higher the calibration accuracy is.

[0054] The data processing unit is responsible for converting the digital signal D into the final output digital signal of the SAR ADC. D is an n-bit binary data, and the digital signal D is generated by analog-to-digital conversion of the analog signal to be calibrated. The data processing unit multiplies the digital signal D by the weight vector generated by the LMS calibration unit bit by bit and sums to obtain the final output signal. Further, in order to prevent overflow, the obtained sum is normalized.

[0055] Referring to Figure 3 Fig. 4 shows a timing diagram of the SAR ADC according to the application.

[0056] wherein CLKS is a sampling clock signal, when CLKS is high, the SAR ADC samples the input differential signal Vip and Vim; when CLKS is low, the SAR ADC performs analog-to-digital conversion. PH1 is the first phase signal of the calibration process, which contains a complete CLKS period and is effective in high level. PH2 is the second phase signal of the calibration process, which contains a complete CLKS period and is effective in high level. PH2 immediately follows PH1. PH1 and PH2 constitute a complete calibration cycle. In the Sample phase of PH1, the ADC samples the input analog signal, and in the Convert phase of PH1, the sampled differential signal is subjected to analog-to-digital conversion to obtain binary data D1. In the entire PH2, the charge sampled from the input analog signal in the PH1 phase is maintained. In the sample phase of PH2, the disturbance signal is injected and superimposed with the sampled signal, and in the convert phase of PH2, the input signal and the disturbance signal are subjected to analog-to-digital conversion to obtain binary data D2, realizing one sampling and two conversions.

[0057] Example 1: a sub-DAC (CDAC) with a monotonic switch structure is used to form a fully differential structure SAR ADC

[0058] Figure 4 Fig. 5 shows a structure diagram of the capacitor array according to the application, which adopts a monotonic switch structure to realize a fully differential structure. The capacitor array includes a first capacitor array and a second capacitor array. The first capacitor array includes a positive DAC and a negative DAC. The positive DAC is composed of capacitors Cpn-1, Cpn-1, …, Cpl, Cp0, switches Spn-1, Spn-1, …, Spl, Sp0, Spd, a sampling switch Sps. The negative DAC is composed of capacitors Cmn-1, Cmn-1, …, Cml, Cm0, switches Smn-1, Smn-1, …, Sm1, Sm0, Smd, a sampling switch Sms. The second capacitor array includes a positive DAC and a negative DAC. The positive DAC includes a switch Spd and a capacitor Cpd. The negative DAC includes a switch Smd and a capacitor Cmd.

[0059] VRP is a positive reference voltage, and VRN is a negative reference voltage. The second capacitor array is used to inject a disturbance signal to the positive input of the comparator Comp.

[0060] The working process of the capacitor array includes: in the normal conversion mode, the ADC sampling phase, the switches Sps and Sms are turned on; in the positive phase DAC, the switches Spn-1, Spn-2, …, Sp, Sp0, and Spd are turned on to VRP; in the negative phase DAC, the switches Smn-1, Smn-2, …, Sm1, Sm0, and Smd are turned on to VRP, the upper plate samples the input analog signal, and the lower plate simultaneously performs pre-charging; at the end of sampling, the switches Sps and Sims are disconnected from the input analog signal Vip and Vim. Subsequently, the conversion phase is entered, and first, the MSB comparison is performed; at this time, the switches Spn-1, Spn-2, …, Sp1, Sp0, and Spd remain turned on to VRP, and the switches Smn-1, Smn-2, …, Sm1, Sm0, and Smd remain turned on to VRP; at this time, VP = Vip, and VM = Vim, the comparator Comp compares VP and VM; if VP > VM, the switch Spn-1 is selected to VRN, and the selection characteristics of the other switches remain unchanged; if VP < VM, the switch Smn-1 is selected to VRN, and the selection characteristics of the other switches remain unchanged. After waiting for the capacitor array to be established, the next highest bit comparison is performed. In this way, the LSB comparison is performed until completion.

[0061] The SAR ADC is in the calibration process as follows:

[0062] The conversion process of the working mode of the SAR ADC under PH1 is consistent with the normal mode, which is not repeated here. Under PH2, when the CLKS is high, the ADC is in the sampling phase, at this time the SAR ADC does not sample the input VIPVIM, but injects a disturbance signal into the sampled input analog signal through the end capacitors Cpd and Cmd, and the disturbance signal can be (VRP-VRN) or (VRN-VRP). The specific operation is as follows: the ADC sampling phase, Sps and Sms are disconnected. The switches Spn-1, Spn-2, …, Sp1, Sp0 in the positive phase DAC are turned on to VRP; the switches Smn-1, Smn-2, …, Sm1, Sm0 in the negative phase DAC are turned on to VRP; Spd is turned on to VRN, and Smd is turned on to VRP, at this time, it is equivalent to adding Cd / Ctot*(VRP-VRN) disturbance in VIP-VIM; another option: Spd is turned on to VRP, and Smd is turned on to VRN, at this time, it is equivalent to adding -Cd / Ctot*(VRP-VRN) disturbance in VIP-VIM. When the sampling is finished, Sps, Sms are disconnected with the input analog signal Vip, Vim. Then enter the conversion phase, first perform MSB comparison, at this time Spn-1, Spn-2, …, Sp1, Sp0 remain turned on to VRP, Smn-1, Smn-2, …, Sm1, Sm0 remain turned on to VRP, Spd, Smd remain the original gating characteristics, at this time VP=Vip-Cd / Ctot*(VH-VL), VM=Vim, for the second option VP=Vip, VM=Vim-Cd / Ctot*(VH-VL), the comparator Comp compares VPVM, if VP>VM, the switch Spn-1 is turned on to VRN, and the other switches remain unchanged; if VP<VM, the switch Smn-1 is turned on to VRN, and the other switches remain unchanged. Wait for the capacitor array to be established, then perform the next highest bit comparison. In this way, the LSB comparison is completed.

[0063] Referring to Figure 5 Fig. 2 shows another structure of the capacitor array provided by the embodiment of the application, the first capacitor array includes switches Sn-1-S0, Sd, capacitors Cn-1-C0, Cd, and the second capacitor array includes switch Scal and capacitor Ccal. The second capacitor array injects a disturbance signal at the second phase signal PH2.

[0064] Wherein, VI is an input analog voltage signal, VRP is a positive reference voltage signal, VRN is a negative reference voltage signal, and the moving terminals of each switch from left to right are the first moving terminal, the second moving terminal and the third moving terminal.

[0065] In normal conversion mode, the ADC sampling phase, switch Ss is on, VP = VCM; switch Sn-1, Sn-2, …, S1, S0, Sd are selected to the input voltage VI, and Scal is selected to VRN; at the end of sampling, switch Ss is first disconnected, and then enters the conversion phase, and then MSB comparison is performed, at this time switch Sn-1 is selected to VRP; switches Sn-1 ~ S0, Sd, Scal are selected to VRN.

[0066] VP = Cdac / Ctot*(Cn-1 / Cdac(VRP-VRN)+VRN-Vi)+Vcm, VM = Vcm, wherein Ctot = Cdac+Ccal, The comparator Comp compares VP and VM, if VP > VM, switch Sn-1 is selected to VRN, switch Sn-2 is selected to VRP, and the selection characteristics of other switches remain unchanged; if VP < VM, switch Sn-2 is selected to VRP, and the selection characteristics of other switches remain unchanged. After the DAC capacitor array is established, the next high bit comparison is performed. In this way, the LSB comparison is completed.

[0067] Wherein, referring to Figure 6 The timing diagram of the SARDAC calibration process is shown in the figure:

[0068] The working mode of the SAR ADC under PH1 is consistent with the conversion process of the normal mode, which will not be repeated here;

[0069] In PH2 phase, the sampling phase can be omitted, so that the working frequency of the ADC can be improved when it is calibrated as a background.

[0070] Under PH2 phase, the disturbance signal is injected into the sampled input analog signal by selecting Vcal through the calibration capacitor Ccal all the time, and the disturbance amplitude is: -(Vcal-VRN)*Ccal / Ctot. This disturbance is superimposed on Vi, which is equivalent to input Vi-(Vcal-VRN)*Ccal / Ctot. First, MSB comparison is performed, at this time switch Ss is disconnected, and switch Scal is selected to Vcal. Switch Sn-1 is selected to VRP, and switches Sn-2 to S0, Sd are selected to VRN. The comparator Comp compares VP and VM, if VP > VM, switch Sn-1 is selected to VRN, switch Sn-2 is selected to VRP, and the selection characteristics of other switches remain unchanged; if VP < VM, switch Sn-2 is selected to VRP, and the selection characteristics of other switches remain unchanged. After the DAC is established, the next high bit comparison is performed. In this way, the LSB comparison is completed.

[0071] Referring to Figure 7 Another structural schematic diagram of the capacitor array is shown in the figure.

[0072] In Figure 7In the middle, the first capacitor array includes capacitors Cpn-1~Cp0, Cpd, switches Spn-1~switch Sp, switch Spd, capacitors Cmn-1~Cm0, Cmcal. The second capacitor array includes capacitor Cpcal and switch Spcal, capacitor Cmcal and switch Smcal. The second capacitor array is used to introduce the disturbance signal, the connection relationship between the components can be seen from Figure 7 As shown, no longer described here.

[0073] Among them, Figure 7 In the middle, VIM is the negative phase analog input voltage signal, VIP is the positive phase analog input voltage signal, VRP is the positive reference voltage signal, VRN is the negative reference voltage signal, VIM is the common mode voltage signal, Vcalp is the positive excitation voltage signal, Vcaln is the negative excitation voltage signal.

[0074] Among them, in the normal conversion mode, the ADC sampling phase, first judge the size relationship of VIP and VIM, and the result is the highest bit. Positive DAC, Sps is turned on, VP=VCM; Spn-1, Spn-2, ……Sp1, Sp0, Spd are selected to the input voltage VIP, and Spcal is selected to VCM; Negative DAC, Sms is turned on, VM=VCM; Smn-1, Smn-2, ……Sm1, Sm0, Smd are selected to the input voltage VIM, and Smcal is selected to VCM; Sps and Sms are first disconnected at the end of sampling, and then enter the conversion phase, first MSB comparison, at this time Spn-1 is selected to VCM, Spn-2, ……Sp1, Sp0, Spd, Spcal are selected to VCM; Smn-1 is selected to VCM, Smn-2, ……Sm1, Sm0, Smd, are selected to VCM, and Smcal is selected to VCM.

[0075] VP=Vcm-VIP+Vcm.

[0076] VP=Vcm-VIN+Vcm.

[0077] The comparator Comp compares the size of VP and VM, if VP>VM, VIP

[0078] Then from the second highest bit to continue comparison. When VIP>VIM, the switch Spn-2 in the positive DAC is selected to VRP, and the other switch selection characteristics remain unchanged. The switch Smn-2 in the negative DAC is selected to VRN, and the other switch selection characteristics remain unchanged. After waiting for the DAC to be established, the second highest bit comparison is performed. When VP>VM, the switch Spn-2 in the positive DAC is selected to VCM, the switch Spn-2 is selected to VRP, and the other switch selection characteristics remain unchanged. The switch Smn-2 in the negative DAC is selected to VCM, the switch Smn-3 is selected to VRN, and the other switch selection characteristics remain unchanged. When VP<VM, the switch Spn-2 in the positive DAC is selected to VRP, the switch Spn-2 is selected to VRP, and the other switch selection characteristics remain unchanged. The switch Smn-2 in the negative DAC is selected to VRN, the switch Smn-3 is selected to VRN, and the other switch selection characteristics remain unchanged. And so on, until the LSB comparison is completed.

[0079] When VIP<VIM, the switch Spn-2 in the positive DAC is selected to VRN, and the other switch selection characteristics remain unchanged. The switch Smn-2 in the negative DAC is selected to VRP, and the other switch selection characteristics remain unchanged. After waiting for the DAC to be established, the second highest bit comparison is performed. When VP>VM, the switch Spn-2 in the positive DAC is selected to VCM, the switch Spn-2 is selected to VRN, and the other switch selection characteristics remain unchanged. The switch Smn-2 in the negative DAC is selected to VCM, the switch Smn-3 is selected to VRP, and the other switch selection characteristics remain unchanged. When VP<VM, the switch Spn-2 in the positive DAC is selected to VRN, the switch Spn-3 is selected to VRN, and the other switch selection characteristics remain unchanged. The switch Smn-2 in the negative DAC is selected to VRP, the switch Smn-3 is selected to VRP, and the other switch selection characteristics remain unchanged. And so on, until the LSB comparison is completed.

[0080] The SARADC in the calibration process works as follows:

[0081] The working mode of the SARADC under PH1 is consistent with the conversion process of the normal mode, which is not repeated here.

[0082] In PH2, the sampling phase can be omitted, so that the working frequency of the SARADC can be improved when working as a background calibration.

[0083] In the PH2 phase, the sampled input analog signal is disturbed by the calibration capacitor Cpcal always selected Vpcal, the calibration capacitor Cmcal always selected Vmcal, the disturbance signal is injected into the positive phase DAC, the disturbance amplitude is -(Vpcal-VCM)*Cpcal / Cptot, the disturbance signal is injected into the negative phase DAC, the disturbance amplitude is -(Vmcal-VCM)*Cmcal / Cmtot, the disturbance is superimposed on VIP and VIM respectively, the input is equivalent to VIP-(Vpcal-VCM)*Cpcal / Cptot and VIM-(Vmcal-VCM)*Cmcal / Cmtot. The analog-digital conversion process is the same as the normal conversion mode, which is not repeated here.

[0084] The above-described embodiments do not constitute a limitation on the protection scope of the technical solutions. Any modifications, equivalent replacements, improvements, and the like made within the spirit and principles of the above-described embodiments shall be included in the protection scope of the technical solutions.

Claims

1. A calibration system for a successive approximation analog-to-digital converter, comprising: Signal source, SARADC, LMS calibration unit, and data processing unit; The SARADC includes a first capacitor array and a second capacitor array; the output terminal of the signal source is connected to the input terminal of the SARADC, the output terminal of the SARADC is connected to the LMS calibration unit and the data processing unit, and the LMS calibration unit and the data processing unit are connected. The SARADC is used to perform a single sampling of the analog signal from the signal source and perform a first analog-to-digital conversion based on the single sampling to obtain a first digital signal; wherein, during the first analog-to-digital conversion, the second capacitor array is in an unscrambled state; The SARADC is further configured to, based on the first sampling, inject a perturbation signal through the second capacitor array without resampling the analog signal, and perform a second analog-to-digital conversion to obtain a second digital signal; wherein, during the second analog-to-digital conversion, the second capacitor array is in a scrambling state; The LMS calibration unit is used to calibrate and obtain a weight vector based on the first digital signal and the second digital signal. The data processing unit is used to calibrate the input signal to be calibrated using the weight vector.

2. The system according to claim 1, characterized in that, The first capacitor array includes: switches Spn-1 to Sp0, capacitors Cpn-1 to Cp0, capacitors Cmn-1 to Cm0, and switches Smn-1 to Sm0; n is an integer greater than 1. The second capacitor array includes a switch Spd, a capacitor Cpd, a capacitor Cmd, and a switch Smd; Each switch includes a first moving terminal, a second moving terminal, and a fixed terminal. The first moving terminal is used to input a positive reference voltage signal VRP, and the second moving terminal is used to input a negative reference voltage VRN. The fixed terminals of each switch in switches Spn-1 to Sp0 and Spd are connected to the positive input terminal of the comparator through corresponding capacitors; The fixed terminals of each switch from Smn-1 to Sm0 and Smd are connected to the negative input terminal of the comparator through corresponding capacitors.

3. The system according to claim 1, characterized in that, The first capacitor array includes switches Sn-1 to S0, switch Sd, and capacitors Cn-1 to C0; The second capacitor array includes a switch Scal and a capacitor Ccal; Each switch includes a first moving terminal, a second moving terminal, a third moving terminal, and a fixed terminal. The first moving terminal is used to input an analog voltage signal, the second moving terminal is used to input a positive reference voltage signal, the third moving terminal is used to input a negative reference voltage signal, and the fixed terminal is connected to the positive input terminal of the comparator through a corresponding capacitor.

4. The system according to claim 1, characterized in that, The first capacitor array includes: switches Spn-1 to Sp0, switch Spd, capacitors Cpn-1 to Cp0, capacitor Cpd, capacitors Cmn-1 to Cm0, capacitor Cmd, and switches Smn-1 to Sm0 and Smd. The second capacitor array includes a switch Spcal, a capacitor Cpcal, a capacitor Cmcal, and a switch Smcal. Each of the switches Spn-1 to Sp0 is provided with a first moving terminal, a second moving terminal, a third moving terminal, a fourth moving terminal, and a fixed terminal. The first moving terminal is used to input a positive input voltage signal, the second moving terminal is used to input a positive reference voltage signal, the third moving terminal is used to input a negative reference voltage signal, and the fourth moving terminal is used to input a common-mode voltage signal. The fixed terminal is connected to the positive input terminal of the comparator through a corresponding capacitor. Each switch in switches Smn-1 to Sm0 is provided with a first moving terminal, a second moving terminal, a third moving terminal, a fourth moving terminal, and a fixed terminal. The first moving terminal is used to input the reverse input voltage signal, the second moving terminal is used to input the positive reference voltage signal, the third moving terminal is used to input the negative reference voltage signal, and the fourth moving terminal is used to input the common-mode voltage signal. The fixed terminal is connected to the negative input terminal of the comparator through the corresponding capacitor. The switch Spd has a first moving terminal, a second moving terminal, and a fixed terminal. The first moving terminal is used to input a positive reference voltage signal, the second moving terminal is used to input a negative reference voltage signal, and the fixed terminal is connected to the positive input terminal of the comparator through a capacitor Cpd. The switch Spcal has a first moving terminal, a second moving terminal, and a fixed terminal. The first moving terminal is used to input the common-mode voltage signal, the second moving terminal is used to input the positive excitation voltage signal, and the fixed terminal is connected to the positive input terminal of the comparator through the capacitor Cpcal. The switch Cmd has a first moving terminal, a second moving terminal, and a fixed terminal. The first moving terminal is used to input a negative analog voltage signal, the second moving terminal is used to input a negative reference voltage signal, and the fixed terminal is connected to the negative input terminal of the comparator through the capacitor Cmd. The switch Smcal has a first moving terminal, a second moving terminal, and a fixed terminal. The first moving terminal is used to input the common-mode voltage signal, the second moving terminal is used to input the negative excitation voltage signal, and the fixed terminal is connected to the negative input terminal of the comparator through the capacitor Cpcal.

5. The system according to claim 2, 3, or 4, characterized in that, In background calibration mode, the data processing unit calibrates the current input signal to be calibrated based on the weight vector obtained from the previous calculation.

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