Analog-to-digital converter and control method

Abstract

The present application relates to the field of analog-digital conversion, and discloses a method and a converter for converting an analog input signal into a digital output signal, the method comprising adding a digitally controlled offset voltage into a comparison stage of a successive approximation analog-digital converter circuit, wherein the digitally controlled offset voltage is periodically repeated, each period comprising at least two voltage steps, and each voltage step having a value equal to a product of an integer multiple of an analog voltage (ALSB) corresponding to a least significant bit (LSB) of an N-bit digital signal and 2 (K+1) , operating the successive approximation analog-digital converter circuit to successively generate at least two N-bit digital signals in accordance with the at least two stepped digitally controlled offset voltages, adding the at least two N-bit digital signals to obtain a sum result, and dividing the sum result by a divider module to obtain an (N+K)-bit digital signal. (‑K) (K+1) (K+1) (K+1) ​​​​

Description

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 143,537, entitled “ADC Apparatus and Control Method,” filed January 29, 2021, and the benefit of U.S. Formal Application No. 17 / 644,589, filed December 16, 2021, which is incorporated herein by reference. Technical Field

[0002] The present invention relates to analog-to-digital converters (ADCs), and in a particular embodiment, to successive approximation ADCs. Background Technology

[0003] ADCs are commonly used in electronic systems to convert analog signals into digital signals. These digital signals can then be further processed by various digital processors, such as digital audio / video processors and wireless communication processors. In some applications, an ADC can be implemented as a standalone semiconductor device. Alternatively, an ADC can be integrated with other circuitry onto a single integrated circuit. Among the various types of ADCs, successive approximation ADCs are widely used in applications requiring high resolution and accuracy.

[0004] A successive approximation ADC converts an analog signal to a digital signal by comparing various output values ​​of a digital-to-analog converter (DAC) with the input analog signal over multiple clock cycles. For example, in the first conversion cycle, the most significant bit (MSB) of the digital signal is determined by comparing the input analog signal with the DAC's mid-range output (i.e., the analog output corresponding to 100...00, where the DAC's MSB is set to logic 1). If the value of the input analog signal is greater than the DAC's mid-range output, the MSB of the digital signal is set to logic 1. Conversely, if the value of the input analog signal is less than the DAC's mid-range output, the MSB of the digital signal is set to logic zero. In the second conversion cycle, based on the result of the first conversion cycle, the input analog signal is compared with the DAC's 1 / 4-range or 3 / 4-range output. The second most significant bit is determined in the second conversion cycle. This comparison method continues until the least significant bit (LSB) of the digital signal is determined. Once the LSB is determined, the analog-to-digital conversion is complete, and the digital signal is stored in the successive approximation ADC's register.

[0005] A general-purpose successive approximation ADC (e.g., 10-bit resolution) is sufficient for most applications. However, some applications may require a higher resolution successive approximation ADC (e.g., 11-bit or 12-bit resolution). A simple and reliable method is desired to improve the resolution of a general-purpose successive approximation ADC to meet diverse application needs. Summary of the Invention

[0006] Preferred embodiments of this disclosure address or circumvent these and other problems by providing a higher resolution successive approximation ADC through the addition of a numerically controlled offset voltage to the successive approximation comparator stage.

[0007] According to one embodiment, a method for converting an analog input signal into a digital output signal includes adding a numerically controlled offset voltage to the comparator stage of a successive approximation analog-to-digital converter circuit, wherein the numerically controlled offset voltage repeats periodically, each cycle including at least 2 (K+1) There are several voltage steps, and the value of each voltage step is equal to an integer multiple of the analog voltage (ALSB) corresponding to the least significant bit (LSB) of the N-bit digital signal multiplied by 2. (-K) According to at least 2 (K+1) Step-by-step controlled offset voltage, operating the successive approximation analog-to-digital converter circuit sequentially to generate at least 2 (K+1) N-bit digital signals will have at least 2 (K+1) The sum of N-bit digital signals is obtained by adding the sum, and the sum is divided by the division module to obtain a digital signal with (N+K) bits.

[0008] According to another embodiment, the converter includes a comparator stage configured to receive the output signal of a sample-and-hold module and the output of a digital-to-analog converter, an offset voltage generator configured to generate a numerically controlled offset voltage added to one input of the comparator stage, and wherein the numerically controlled offset voltage repeats periodically, and each cycle includes at least 2 (K+1) Each voltage step, successive approximation logic module is configured to receive the output signal of the comparator stage, and based on at least 2 (K +1) The numerically controlled offset voltage of the step generates at least 2 (K+1) The summing module is configured to receive the output signal of the successive approximation logic module, and the divider module is configured to receive the summation result generated by the summing module, wherein the converter is configured to be based on at least 2 (K+1) The numerically controlled offset voltage of the step generates a digital signal with (N+K) bits.

[0009] According to another embodiment, a method includes adding a numerically controlled offset voltage to the comparator stage of a successive approximation analog-to-digital converter circuit, wherein the numerically controlled offset voltage is periodically repeated, and each cycle includes at least 2 (K+1) -1 voltage step, the value of each voltage step being an integer multiple of the analog voltage (ALSB) corresponding to the least significant bit (LSB) of the N-bit digital signal and 2. (-K) The product of, where the numerically controlled offset voltage is in the ALSB (2 (-K) -1) times to ALSB (1-2) (-K)Between ) times, the operation of the successive approximation analog-to-digital converter circuit is based on at least 2 (K+1) -1 step of numerically controlled offset voltage, sequentially generating at least 2 (K+1) Given an N-bit digital signal, calculate 2. (K+1) The summation is obtained by weighting 1 N-bit digital signals, where the N-bit digital signal corresponding to the output signal of the successive approximation analog-to-digital converter under zero voltage offset is added twice to the summation result, and the summation result is divided by the divider module to obtain (N+K)-bit digital signals.

[0010] The features and technical advantages of this disclosure have been outlined rather broadly above to facilitate a better understanding of the detailed description that follows. Additional features and advantages of this disclosure will be described below, forming the subject matter of the claims. Those skilled in the art will understand that the disclosed concepts and specific embodiments can be readily used as the basis for modifying or designing other structures or processes to achieve the same purpose as those disclosed. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure as set forth in the appended claims. Attached Figure Description

[0011] To gain a more complete understanding of this disclosure and its advantages, reference is now made to the following description in conjunction with the accompanying drawings, wherein:

[0012] Figure 1 The illustration shows block diagrams of various embodiments of an ADC according to the present disclosure;

[0013] Figure 2 The illustration shows a block diagram of a successive approximation ADC including a numerically controlled offset voltage added to the input voltage path, according to various embodiments of the present disclosure.

[0014] Figure 3 The illustration shows a block diagram of a successive approximation ADC including a numerically controlled offset voltage added to the ADC reference voltage path, according to various embodiments of the present disclosure.

[0015] Figure 4 The illustration shows a block diagram of a successive approximation ADC including a numerically controlled offset voltage added to the input voltage path via an input voltage buffer, according to various embodiments of the present disclosure.

[0016] Figure 5 Various embodiments according to this disclosure are shown. Figure 4 The diagram shown illustrates the successive approximation of the ADC.

[0017] Figure 6 Various embodiments according to this disclosure are shown. Figure 2 The timing diagram of the successive approximation ADC is shown below;

[0018] Figure 7 Flowcharts of methods for implementing higher resolution ADCs according to various embodiments of the present disclosure are shown;

[0019] Figure 8 Various embodiments according to this disclosure are shown. Figure 2 Another timing diagram of the successive approximation ADC shown; and

[0020] Figure 9 A flowchart is shown of another method for implementing a higher resolution ADC according to various embodiments of the present disclosure.

[0021] Unless otherwise stated, the numbers and symbols corresponding to different figures generally refer to the corresponding parts. The figures are drawn to clearly illustrate relevant aspects of the various embodiments and are not necessarily drawn to scale. Detailed Implementation

[0022] The following discusses in detail the making and use of the presently preferred embodiments. However, it should be understood that this disclosure provides many applicable inventive concepts that can be embodied in a variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways of making and using this disclosure and do not limit the scope of this disclosure.

[0023] This disclosure is described with respect to a preferred embodiment in a specific context, namely a higher resolution successive approximation ADC. However, this disclosure can also be applied to various systems and applications that convert analog signals into digital signals. Various embodiments will be explained in detail below with reference to the accompanying drawings.

[0024] Figure 1 The illustration shows block diagrams of successive approximation ADCs according to various embodiments of the present disclosure. The successive approximation ADC 100 includes a sample-and-hold module 112, a comparator stage 114, a successive approximation logic module 116, a digital-to-analog converter (DAC) 118, a summing module 120, and a divider module 122. The successive approximation ADC 100 also includes a digitally controlled offset voltage (not shown, but...). Figure 2-5 (As shown in the diagram). Depending on different design requirements, a numerically controlled offset voltage can be added to the input voltage path (e.g., Figure 2 The successive approximation ADC 200 shown is an example. Alternatively, a numerically controlled offset voltage can be added to the ADC reference voltage path (e.g., Figure 3 The successive approximation ADC 300 shown is also possible. Furthermore, a voltage buffer (e.g., Figure 4 The successive approximation ADC 400 shown adds a numerically controlled offset voltage to the input voltage path.

[0025] In some embodiments, the successive approximation ADC 100 can be implemented as a 10-bit ADC. By employing digitally controlled offset voltages, the successive approximation ADC 100 can be extended to a higher resolution ADC (e.g., an 11-bit or 12-bit ADC).

[0026] like Figure 1 As shown, the sample-and-hold module 112 is configured to receive the input signal VIN. VIN is an analog signal. The sample-and-hold module 112 can be configured to operate during a sampling phase or a conversion phase. During the sampling phase, an internal switch is turned on. The input signal VIN can be sampled and stored in a holding circuit. In some embodiments, the sampled voltage can be stored on a capacitor, capacitor network, etc. During the conversion phase, the internal switch may be turned off to hold the sampled voltage on the capacitor. This sampled voltage can then be provided to the comparator stage 114. Through a successive comparison process, the ADC 100 generates a digital output corresponding to the input signal VIN.

[0027] like Figure 1 As shown, the output of the sample-and-hold module 112 is fed to the first input of the comparator stage 114. The second input of the comparator stage 114 is configured to receive the output signal generated by the DAC 118. The DAC 118 is used to convert the digital output signal generated by the successive approximation logic module 116 into a corresponding analog signal. This analog signal is compared with the output signal of the sample-and-hold module 112 at the comparator stage 114. The comparison result generated by the comparator stage 114 is fed into the successive approximation logic module 116. Based on the comparison result, the successive approximation logic module 116 generates a digital output signal corresponding to the input signal VIN.

[0028] In operation, the successive approximation ADC 100 determines the value of each bit of the digital output signal sequentially based on the output of the comparator stage 114. The successive approximation ADC 100 begins the conversion phase by temporarily setting the most significant bit (MSB) of the digital signal to 1 and all other bits to 0. This digital signal is then applied to the DAC 118. In the DAC 118, an analog signal is generated based on this digital signal.

[0029] The analog signal generated by DAC 118 is compared with the input signal VIN. If the input signal VIN is greater than the analog signal generated by DAC 118, the successive approximation logic module 116 sets the MSB of the digital signal to 1. On the other hand, if the input signal VIN is less than the analog signal generated by DAC 118, the successive approximation logic module 116 sets the MSB of the digital signal to 0. After this comparison, the value of the MSB of the digital signal has been determined.

[0030] The approximation process continues. In the next cycle, the second bit is temporarily set to 1, and the remaining undetermined bits are set to 0. The output of the DAC 118 is compared with the input signal VIN again. If the input signal VIN is greater than the analog signal generated by the DAC 118, the second bit is set to 1; otherwise, it is set to 0. After this comparison, the value of the second bit is determined. The approximation process continues until the least significant bit (LSB) of the digital signal is determined. After the LSB of the digital signal is determined, one analog-to-digital conversion cycle is completed. The content of the digital signal after the LSB is determined represents a successive approximation of the digital output of the ADC 100.

[0031] In some embodiments, the successive approximation ADC 100 is configured to generate an N-bit digital signal. This is achieved by employing a 2... (K +1) The numerically controlled offset voltage of the successive approximation ADC 100 can generate an N+K bit digital signal to improve the resolution of the successive approximation ADC 100.

[0032] In operation, a numerically controlled offset voltage is added to the comparator stage of the successive approximation ADC 100. In some embodiments, the numerically controlled offset voltage repeats periodically. In each cycle, the numerically controlled offset voltage has 2... (K+1) Each voltage step is equal to an integer multiple of the analog voltage (ALSB) corresponding to the LSB of the N-bit digital signal multiplied by 2. (-K) Throughout this description, the analog voltage corresponding to the LSB of the N-bit digital signal is alternatively referred to as the ALSB. In each cycle, the numerically controlled offset voltage is at (2) times the value of the ALSB. (-K) -1) times to ALSB (1-2) (-K) Within a range of ) times. Each voltage step occurs at least once in each cycle, and the sum of the voltage steps in a cycle is zero.

[0033] The successive approximation analog-to-digital converter circuit (e.g., successive approximation logic module 116) is configured to be based on 2 (K+1) Two numerically controlled offset voltages are generated sequentially. (K+1) N-bit digital signals. In the summation module 120, 2 (K+1) N-bit digital signals are added together and fed into divider module 122. In divider module 122, the summation result generated by summation module 120 is divided by 2 to obtain a (N+K)-bit digital signal. The following describes the process in conjunction with... Figure 2-9 Explain the detailed structure and working principle of the numerical control offset voltage.

[0034] Figure 2The illustration shows a block diagram of a successive approximation ADC according to various embodiments of the present disclosure, including the addition of a numerically controlled offset voltage to the input voltage path. A numerically controlled offset voltage 202 is added to the input voltage path of the successive approximation ADC 200. (As shown...) Figure 2 As shown, the numerically controlled offset voltage 202 is placed between the output of the sample-and-hold module 112 and the first input of the comparator stage 114. The output voltage of the sample-and-hold module 112 and the numerically controlled offset voltage 202 are added together. The sum of the output voltage of the sample-and-hold module 112 and the numerically controlled offset voltage 202 is fed to the first input of the comparator stage 114.

[0035] In some embodiments, the numerically controlled offset voltage 202 has 2 (K+1) One voltage step. 2 (K+1) The value of each step in the voltage step is equal to an integer multiple of the N-bit digital signal's ALSB multiplied by 2. (-K) 2 (K+1) Steps are added sequentially to the input voltage path. The successive approximation analog-to-digital converter circuit is configured based on the numerically controlled offset voltage 202. (K+1) Step sequence generates 2 (K+1) An N-bit digital signal. 2 (K+1) N-bit digital signals are fed into summing module 120. In summing module 120, 2 (K+1) N-bit digital signals are summed together. This sum is fed into divider module 122. In divider module 122, the sum is divided by 2 to obtain a digital signal with (N+K) bits. This analog-to-digital conversion process is repeated by a successive approximation analog-to-digital converter circuit. (See below for reference.) Figure 6 Discuss the detailed process.

[0036] When K equals 1, the numerical control offset voltage 202 has 4 voltage steps per cycle. The offset range of the numerical control offset voltage 202 is -ALSB / 2 to ALSB / 2. The offset of the first step is 0. The offset of the second step is ALSB / 2. The offset of the third step is 0. The offset of the fourth step is -ALSB / 2. When K equals 2, the numerical control offset voltage 202 has 8 voltage steps per cycle. The offset range of the numerical control offset voltage 202 is -ALSB×3 / 4 to ALSB×3 / 4. The offset of the first step is 0. The offset of the second step is ALSB / 4. The offset of the third step is ALSB×2 / 4. The offset of the fourth step is ALSB×3 / 4. The offset of the fifth step is 0. The offset of the sixth step is -ALSB / 4. The offset of the seventh step is -ALSB×2 / 4. The offset of the eighth step is -ALSB×3 / 4. It should be noted that in the two examples above, the order of each voltage step of the offset voltage is arbitrary. The order of the offset voltage steps can vary, as long as each step occurs at least once in each cycle and the sum of all offset voltages in a cycle is equal to 0.

[0037] The following example will further illustrate this. Figure 2 The diagram illustrates the operating principle of the successive approximation ADC 200. In some embodiments, K = 1, N = 4. The numerically controlled offset voltage 202 has 4 voltage steps per cycle. The successive approximation ADC 200 without the numerically controlled offset voltage 202 can generate a 4-bit digital signal. By adding the numerically controlled offset voltage 202, the successive approximation ADC 200 can generate a 5-bit digital signal.

[0038] The successive approximation ADC 200 has a full range of 1.6V. The ALSB value is 0.1V. The numerically controlled offset voltage 202 has four voltage steps, each equal to an integer multiple of half of ALSB (half of 0.1V). In the first step, the product of zero and ALSB is added to the input voltage path. In other words, the offset voltage is 0V. In the second step, the product of 0.5 and ALSB is added to the input voltage path. In other words, the offset voltage is 0.05V. In the third step, the product of zero and ALSB is added to the input voltage path. In other words, the offset voltage is 0V. In the fourth step, the product of -0.5 and ALSB is added to the input voltage path. In other words, the offset voltage is -0.05V.

[0039] In some embodiments, the input voltage is equal to 0.87V. The binary representation of the ADC reference voltage is 1000. The corresponding analog voltage is 0.8V. When the ADC process begins, the successive approximation analog-to-digital converter circuit generates four 4-bit binary numbers based on four different voltage steps. In the first step, 0V is added to the input voltage. The successive approximation ADC circuit generates 1000 (binary form). The corresponding decimal value is 8. In the second step, 0.05V is added to the input voltage. The total voltage of 0.92V is fed into the comparator stage. The successive approximation ADC circuit generates 1001 (binary form). The corresponding decimal value is 9. In the third step, 0V is added to the input voltage. The successive approximation ADC circuit generates 1000 (binary form). The corresponding decimal value is 8. In the fourth step, -0.05V is added to the input voltage. The total voltage of 0.82V is fed into the comparator stage. The successive approximation ADC circuit generates 1000 (binary form). The corresponding decimal value is 8.

[0040] Adding the digital signal results from these four steps and then dividing by 2, the final decimal value is 17. This decimal value corresponds to a 5-bit binary number. In this example, N equals 4 and K equals 1. K is used to set the step size of the numerically controlled offset voltage 202. N is the existing resolution of the successive approximation ADC. By adding the numerically controlled offset voltage to the input voltage path and applying the above summation and division algorithm, the resolution of the successive approximation ADC 200 is increased by K bits.

[0041] Figure 3 The diagram illustrates a block diagram of a numerically controlled offset voltage added to the ADC reference voltage path in various embodiments of the present disclosure to approximate the ADC. Figure 3 The successive approximation ADC300 shown is similar to Figure 2 The successive approximation ADC200 shown differs in that the digitally controlled offset voltage 202 is added to the ADC reference voltage path. The working principle of the successive approximation ADC 300 is similar to that described above. Figure 2 The similarities discussed will not be repeated here.

[0042] Figure 4 The diagram illustrates a block diagram of a numerically controlled offset voltage being added to the input voltage path of a successive approximation ADC via an input buffer in various embodiments of the present disclosure. Figure 3 The successive approximation ADC 400 shown is similar to Figure 2 The successive approximation ADC 200 shown differs in that the numerically controlled offset voltage 202 is passed through an input voltage buffer (such as...). Figure 5 (As shown) is added to the input voltage path. The working principle of the successive approximation ADC 400 is similar to that described above. Figure 2 The similarities discussed will not be repeated here.

[0043] Figure 5 Various embodiments according to this disclosure are illustrated. Figure 4 The diagram shows a successive approximation ADC. Comparator stage 114 can be implemented as follows: Figure 5 The comparator 124 shown. The input voltage buffer can be implemented as follows: Figure 5 The voltage follower shown is used throughout the description. The input voltage buffer may alternatively be referred to as a voltage follower.

[0044] Voltage follower 502 is coupled to sample-and-hold module 112. For example... Figure 5 As shown, the sample-and-hold module 112 includes a switch S1 and a capacitor C1. Sample-and-hold circuits in successive approximation ADCs are well-known in the art and will not be discussed in detail to avoid repetition.

[0045] Voltage follower 502 has a first input terminal configured to receive an input voltage VIN and a second input terminal connected to the output of voltage follower 502 via numerically controlled offset voltage 202. The output voltage of voltage follower 502 is equal to the sum of the input voltage VIN and the numerically controlled offset voltage.

[0046] Figure 6 Various embodiments according to this disclosure are illustrated. Figure 2 The timing diagram shown is for the successive approximation ADC. Figure 6 The horizontal axis represents the time interval. There are five vertical axes. The first vertical axis, Y1, represents the starting signal of the successive approximation ADC. The second vertical axis, Y2, represents the digitally controlled offset voltage (d_vos). <k:0>) of 2 (K+1) Step. The third vertical axis Y3 represents the sampling clock. The fourth vertical axis Y4 represents the N-bit digital output signal (data) of the successive approximation ADC. <n-1:0>The fifth vertical axis Y5 represents the (N+K) bit digital output signal (adc_data<(N+K-1):0>) that successively approximates the ADC.

[0047] The numerical control offset voltage repeats periodically. In each cycle, the numerical control offset voltage has 2... (K+1) Each voltage step. For example... Figure 6 As shown, the first period is from the first time t1 to the fourth time t4. Figure 6 As shown, the first cycle includes 2 (K+1) One voltage step (from step 0 to step 2) (K+1) -1). The second period is from time t4 (fourth time) to time t8 (eighth time). The second period includes 2... (K +1) One voltage step (from step 0 to step 2) (K+1) -1), such as Figure 6 As shown.

[0048] At time t0, in response to the rising edge of the start signal, analog-to-digital conversion begins. The first step of the numerically controlled offset voltage is added to the comparator stage of the successive approximation ADC (e.g., the first voltage step has been applied and stabilized, and is ready to be added to the upcoming sampled analog voltage). After an appropriate delay, at the first time t1, the sample-and-hold circuit obtains a sampled analog voltage from the input analog signal and adds the first step of the numerically controlled offset voltage to the sampled signal. In response to this modified input voltage (the sum of the input voltage and the first voltage step of the numerically controlled offset voltage), at the second time t2, the successive approximation ADC generates the first N-bit digital signal C0. Similarly, in the next analog-to-digital conversion cycle, the second voltage step of the numerically controlled offset voltage is added to the comparator stage of the successive approximation ADC (e.g., the second voltage step is added to the sampled analog voltage). In response to this modified input voltage (the sum of the input voltage and the second voltage step of the numerically controlled offset voltage), at the third time t3, the successive approximation ADC generates the second N-bit digital signal C1. The successive approximation ADC repeats analog-to-digital conversion by sequentially adding different voltage steps of numerically controlled offset voltage until, at the fourth time t4, the successive approximation ADC generates the final N-bit digital signal C(2). (K+1) -1).

[0049] In generating an N-bit digital signal C(2) (K+1) -1) After that, the summation module that successively approximates the ADC will 2 (K+1) N-bit digital signals (C0, C1, ..., C2) (K+1) -1)) added together. The divider module that successively approximates the ADC will combine 2 (K+1) The sum of the N-bit digital signals is divided by 2 to generate the first (N+K)-bit digital signal D0, such as... Figure 6 As shown.

[0050] In subsequent analog-to-digital conversion cycles, the successive approximation ADC repeats the same analog-to-digital conversion process. Specifically, from time t4 to time t8, the second cycle of the numerically controlled offset voltage is added sequentially to the comparator stage of the successive approximation ADC. (K+1) One voltage step. The ADC generates two voltage steps sequentially, approximating each other. (K+1) N-bit digital signals (C(2) (K+1) ),C(2 (K+1) +1),...,C(2 (K+2) -2) and C(2) (K+2) -1)) As Figure 6 As shown.

[0051] like Figure 6 As shown, in generating an N-bit digital signal C(2 (K+1) After that, the summation module that successively approximates the ADC calculates 2... (K+1) Summing N-bit digital signals (C1,...,C2) (K+1) (Added together). The divider module that successively approximates the ADC will combine 2 (K+1) The sum of the N-bit digital signals is divided by 2 to generate the second (N+K)-bit digital signal D1 at the fifth time t5, such as... Figure 6 As shown.

[0052] Similarly, in generating an N-bit digital signal C(2 (K+1) After +1), the summation module that successively approximates the ADC will 2 (K+1) N-bit digital signals (C2,...,C2) (K+1) Summing +1), the divider module, which successively approximates the ADC, will... (K+1) The sum of the N-bit digital signals divided by 2 generates the third (N+K)-bit digital signal D2 at time t6, as follows: Figure 6 As shown.

[0053] Furthermore, in generating an N-bit digital signal C(2 (K+1) After +2), the summation module that successively approximates the ADC will... (K+1) Summing N-bit digital signals (C3,...,C(2(K+1)+2)) and successively approximating the divider module of the ADC will result in 2 (K+1) The sum of the N-bit digital signals divided by 2 generates the fourth (N+K)-bit digital signal D3 at the sixth time t7, as follows: Figure 6 As shown.

[0054] The successive approximation ADC repeats this analog-to-digital conversion process. At the eighth time t8, the summing module of the successive approximation ADC will... (K+1) N-bit digital signals (C(2) (K+1) ),...,C(2 (K+2) -1)) added together. The divider module that successively approximates the ADC will combine 2 (K +1) The sum of N-bit digital signals is divided by 2 to generate an (N+K)-bit digital signal D(2). (K+1) ).

[0055] It should be noted that Figure 6 The signals marked with X shown are unknown signals. Unknown signals should be ignored during analog-to-digital conversion. Figure 6 As shown, without a numerically controlled offset voltage and the associated higher-resolution ADC, C0 is the first digital output signal of the successive approximation ADC. With a numerically controlled offset voltage and the associated higher-resolution ADC, D0 is the first digital output signal of the successive approximation ADC. From t2 to t4, we have (2... (K+1) -1) analog-to-digital conversion cycles. In other words, a higher resolution ADC will only result in (2) analog-to-digital conversion cycles. (K+1) -1) delay of analog-to-digital conversion cycles.

[0056] Figure 7 The illustration shows flowcharts of methods for implementing higher resolution ADCs according to various embodiments of the present disclosure. Figure 7 The flowchart shown is merely an example and should not be used to unduly limit the scope of the claims. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, additions, removals, substitutions, rearrangements, and repetitions may be made. Figure 7 The steps shown are as follows.

[0057] In step 702, a numerically controlled offset voltage is added to the comparator stage of the successive approximation analog-to-digital converter circuit. The numerically controlled offset voltage repeats periodically, with at least 2 [units] in each cycle. (K+1) Each voltage step is equal to an integer multiple of the least significant bit (LSB) of the N-bit digital signal and the corresponding analog signal (ALSB), plus 2. (-K) The product of.

[0058] In step 704, the successive approximation analog-to-digital converter circuit is configured based on at least 2 of the above. (K+1) Step-by-step control offset voltage sequential generation 2 (K+1) An N-bit digital signal.

[0059] In step 706, 2 (K+1) The summation module adds up the N-bit digital signals to obtain the summation result.

[0060] In step 708, the summation result generated by the summation module is divided by the divider module to obtain a digital signal with (N+K) bits.

[0061] In the divider module, the summation result is divided by 2 to obtain a digital signal with (N+K) bits.

[0062] The method further includes placing a numerically controlled offset voltage between the output of the sample-and-hold module and the first input of the comparator stage, wherein the output voltage of the sample-and-hold module and the numerically controlled offset voltage are added together, and the sum of the output voltage of the sample-and-hold module and the numerically controlled offset voltage is fed to the first input of the comparator stage.

[0063] The method further includes placing a digitally controlled offset voltage between the output of the digital-to-analog converter circuit and the second input of the comparator stage, wherein the output voltage of the digital-to-analog converter circuit and the digitally controlled offset voltage are added together, and the sum of the output voltage of the digital-to-analog converter circuit and the digitally controlled offset voltage is fed into the second input of the comparator stage.

[0064] The method further includes placing a numerically controlled offset voltage at the input of the sample-and-hold module, wherein the numerically controlled offset voltage and the input voltage of the sample-and-hold module are added together, and the sum of the input voltage and the numerically controlled offset voltage is fed into the sample-and-hold module.

[0065] The numerically controlled offset voltage is coupled to the sample-and-hold module via an input voltage buffer. The input voltage buffer is a voltage follower. The voltage follower has a first input configured to receive an analog input signal, and a second input connected to the output of the voltage follower via the numerically controlled offset voltage, wherein the output voltage of the voltage follower is equal to the sum of the analog input signal and the numerically controlled offset voltage.

[0066] A digital signal with (N+K) bits is equal to (2 (K+1) It is generated after a delay of -1) analog-to-digital conversion cycles.

[0067] In some embodiments, the voltage stepping within each cycle of the numerically controlled offset voltage can be further simplified, so that it has only 2 steps. (K+1) -1 step. 2 (K+1) -1 voltage step enables the successive approximation ADC 100 to generate (N+K) bit digital signals, thereby improving the resolution of the successive approximation ADC 100.

[0068] Similarly, in operation, a numerically controlled offset voltage is added to the comparator stage of the successive approximation ADC 100. In some embodiments, the numerically controlled offset voltage repeats periodically. In each cycle, the numerically controlled offset voltage has (2 (K+1) -1) voltage steps. The value of each voltage step is equal to an integer multiple of ALSB and 2. (-K) The product of . The voltage step value is from ALSB (2 (-K) -1) times to ALSB (1-2) (-K) Within a range of ) times. Each voltage step value occurs at least once in each cycle, and the sum of the voltage step values ​​for one cycle is zero. More specifically, the numerically controlled offset voltage step includes the following 2 (K+1) -1 value: {(2 (-K) -1), (2·2) (-K) -1), (3·2) (-K) -1),...,((2 (K) -1)·2 (-K) -1),0,(1-(2 (K) -1)·2 (-K) ),...,(1-3·2 (-K) ),(1-2·2 (-K) ),(1-2 (-K) )}X ALSB and can have any order.

[0069] The successive approximation analog-to-digital converter circuit is configured to be based on (2 (K+1) -1) numerically controlled offset voltage steps, sequentially generating 2 (K+1) -1 N-bit digital signal. (2) (K+1) -1) N-bit digital signals are fed into the summing module 120. In the summing module 120, (2 (K+1) -1) N-bit digital signals are added together. The N-bit digital signal corresponding to the 0 voltage offset is added twice to the sum. This sum is then fed into divider module 122. In divider module 122, the sum is divided by 2 to obtain a digital signal with (N+K) bits. The successive approximation analog-to-digital converter circuit repeats this analog-to-digital conversion process. (See below for reference.) Figure 8 Discuss the detailed process.

[0070] In some embodiments, when K equals 1, the numerical control offset voltage 202 has 3 voltage steps. The offset voltage values ​​of the numerical control offset voltage 202 are -ALSB / 2, 0, and ALSB / 2. The offset of the first step can be set to 0. The offset of the second step can be set to ALSB / 2. The offset of the third step can be set to -ALSB / 2. When K equals 2, the numerical control offset voltage 202 has 7 voltage steps. The offset voltage values ​​of the numerical control offset voltage 202 are -ALSB×3 / 4, -ALSB / 2, -ALSB / 4, 0, ALSB / 4, ALSB / 2, and ALSB×3 / 4. The offset of the first step can be set to 0. The offset of the second step can be set to ALSB / 4. The offset of the third step can be set to ALSB / 2. The offset of the fourth step can be set to ALSB×3 / 4. The offset of the fifth step can be set to -ALSB / 4. The offset of the sixth step can be set to -ALSB / 2. The offset of the seventh step can be set to -ALSB×3 / 4. It is important to note that in the two examples above, the order of the offset voltage steps is arbitrary, as long as ALSB and each integer are multiplied by 2 in each cycle. (-K) The product occurs once, and the sum of all offset voltages in one cycle is zero. It should also be noted that integer multiples of ALSB multiplied by 2... (-K) The value range is within the range of ALSB (2). (-K) -1) times to (1-2) times (-K) Between 1.5 and 1.5 times.

[0071] The following example will further illustrate this. Figure 2 The diagram illustrates the operating principle of the successive approximation ADC 200. In some embodiments, K = 1, N = 4. The numerically controlled offset voltage 202 has 3 levels. Without the numerically controlled offset voltage 202, the successive approximation ADC 200 can generate a 4-bit digital signal. By adding the numerically controlled offset voltage 202, the successive approximation ADC 200 can generate a 5-bit digital signal.

[0072] The successive approximation ADC 200 has a full range of 1.6V. The ALSB value is 0.1V. The numerically controlled offset voltage 202 has three voltage steps. Each step is an integer multiple of half of ALSB (half of 0.1V), for a total of three voltage steps. In the first step, the product of zero and ALSB is added to the input voltage path. In other words, the offset voltage is 0V. In the second step, the product of 0.5 and ALSB is added to the input voltage path. In other words, the offset voltage is 0.05V. In the third step, the product of -0.5 and ALSB is added to the input voltage path. In other words, the offset voltage is -0.05V.

[0073] In some embodiments, the input voltage is equal to 0.87V. The binary representation of the ADC reference voltage is 1000. The corresponding analog voltage is 0.8V. When the ADC process begins, the successive approximation analog-to-digital converter circuit generates four 4-bit binary numbers based on three distinct steps. In the first step, 0V is added to the input voltage. The successive approximation ADC circuit generates 1000 (binary form). The corresponding decimal value is 8. In the second step, 0.05V is added to the input voltage. The total voltage of 0.92V is fed into the comparator stage. The successive approximation ADC circuit produces 1001 (binary form). The corresponding decimal value is 9. In the third step, -0.05V is added to the input voltage. The total voltage of 0.82V is fed into the comparator stage. The successive approximation ADC circuit generates 1000 (binary form). The corresponding decimal value is 8.

[0074] The digital signal results from these three steps are added together, with the digital signal result corresponding to the 0V voltage offset (the first step in this example) added twice to form a weighted sum, which is then divided by 2. The decimal value of the final result is rounded up to the nearest integer. In the current example, the final result is 17, corresponding to an analog voltage of 8.5V. The decimal value corresponds to a 5-bit binary number 10001. In this example, N equals 4, and K equals 1. K is used to set the step size of the numerically controlled offset voltage 202. N defines the resolution of the existing successive approximation ADC. By adding the numerically controlled offset voltage to the input voltage path and applying the above summation and division algorithm, the resolution of the successive approximation ADC 200 is increased by K bits.

[0075] Figure 8 Various embodiments according to this disclosure are illustrated. Figure 2 Another timing diagram of the successive approximation ADC is shown. Figure 8 The horizontal axis represents the time interval. There are five vertical axes. The first vertical axis, Y1, represents the starting signal of the successive approximation ADC. The second vertical axis, Y2, represents 2... (K+1) -1 step of digitally controlled offset voltage (d_vos) <k:0>The third vertical axis, Y3, represents the sampling clock. The fourth vertical axis, Y4, represents the N-bit digital output signal (data) of the successive approximation ADC. <n-1:0>The fifth vertical axis Y5 represents the (N+K) bit digital output signal (adc_data<(N+K-1):0>) that successively approximates the ADC.

[0076] The numerical control offset voltage exhibits periodic repetition. Within each cycle, the numerical control offset voltage has 2... (K+1) -1 step. For example... Figure 8 As shown, the first period is from the first time t1 to the fourth time t4. The first period includes (2 (K+1) -1) voltage steps (from voltage step 0 to voltage step (2) (K+1) -2)), such as Figure 8 As shown. The second period is from the fourth time t4 to the eighth time t8. The second period includes (2 (K+1) -1) voltage steps (from voltage step 0 to voltage step (2) (K+1) -2)), such as Figure 8 As shown.

[0077] At time t0, in response to the rising edge of the start signal, analog-to-digital conversion begins. The first step of the numerically controlled offset voltage is added to the comparator stage of the successive approximation ADC (e.g., applying the first voltage step and stabilizing it, preparing it for addition to the upcoming sampled analog voltage). After an appropriate delay, at the first time t1, the sample-and-hold circuit obtains a sampled analog voltage from the input analog signal and then applies the first numerically controlled offset voltage to the sampled signal. In response to this modified input voltage (the sum of the input voltage and the first voltage step of the numerically controlled offset voltage), at the second time t2, the successive approximation ADC generates the first N-bit digital signal C0. Similarly, in the next analog-to-digital conversion cycle, the second voltage step of the numerically controlled offset voltage is added to the comparator stage of the successive approximation ADC (e.g., adding the second voltage step to the sampled analog voltage). In response to this modified input voltage (the sum of the input voltage and the second voltage step of the numerically controlled offset voltage), at the third time t3, the successive approximation ADC generates the second N-bit digital signal C1. The successive approximation ADC repeats analog-to-digital conversion by sequentially adding different voltage steps of numerically controlled offset voltage until, at the fourth time t4, the successive approximation ADC generates the final N-bit digital signal C(2). (K+1) -2).

[0078] In generating an N-bit digital signal C(2) (K+1) -2) after that, the (2) (K+1) -1) N-bit digital signals (C0, C1, ..., C2) (K+1) -2)) is processed in the summation module that successively approximates the ADC, where 2 (K+1) Add the numbers together. 2 (K+1) The numbers include C0, C1, ..., C(2). (K+1) -2) and an N-bit digital signal corresponding to the output of the successive approximation ADC when the numerical control offset voltage is 0. This N-bit digital signal can be C0 to C(2) (K+1) -2) any one, depending on the actual sequence of the offset voltage steps. The divider module of the successive approximation ADC will 2 (K+1) The sum of the N-bit digital signals is divided by 2 to generate the first (N+K)-bit digital signal D0, such as... Figure 8 As shown.

[0079] In subsequent analog-to-digital conversion cycles, the successive approximation ADC repeats the same analog-to-digital conversion process. Specifically, from time t4 to time t8, a digitally controlled offset voltage of the second cycle (2π / 3) is added to the comparator stage of the successive approximation ADC. (K +1) -1) voltage steps. The successive approximation ADC generates (2) voltage steps sequentially. (K+1) -1) N-bit digital signals (C(2) (K+1) -1),C(2 (K+1) ),C(2 (K+1) +1),..., and C(2) (K+2) -3)) As Figure 8 As shown.

[0080] like Figure 8 As shown, in generating an N-bit digital signal C(2 (K+1) -1) After that, the summation module that successively approximates the ADC is applied to 2 (K+1) Summing N-bit digital signals, where the digital signals include C1, ..., C2. (K+1) -1) and an N-bit digital signal corresponding to the successive approximation ADC output when the numerical control offset voltage is 0. This N-bit digital signal can be C1 to C(2) (K+1) -1) any one of them, depending on the actual sequence of the voltage offset steps. The sum is then fed into the divider module that successively approximates the ADC, where 2 (K+1) The sum of the N-bit digital signals is divided by 2 to generate the second (N+K)-bit digital signal D1 at the fifth time t5, such as... Figure 8 As shown.

[0081] Similarly, in generating an N-bit digital signal C(2 (K+1) After that, the summation module that successively approximates the ADC calculates 2... (K+1) Summing N-bit digital signals, including C2, ..., C(2). (K+1) This includes an N-bit digital signal that corresponds to the output of the successive approximation ADC when the numerical control offset voltage is 0. This N-bit digital signal can be C2 to C(2). (K+1) The order of the offset steps depends on the actual sequence of the offset steps. The sum is then fed into the divider module that successively approximates the ADC, where 2 (K+1) The sum of the N-bit digital signals is divided by 2 to generate the third (N+K)-bit digital signal D2 at time t6. Figure 8 As shown.

[0082] Furthermore, in generating an N-bit digital signal C(2 (K+1) +1) After that, the summation module that successively approximates the ADC is applied to 2 (K+1) Summing N-bit digital signals, including C3, ..., C2. (K+1) +1) and an N-bit digital signal corresponding to the successive approximation ADC output when the numerical control offset voltage is 0. This N-bit digital signal can be C3 to C(2) (K+1) Any of +1), depending on the actual sequence of voltage offset steps. The sum is then fed into the divider module that successively approximates the ADC, where 2 (K+1) The sum of the N-bit digital signals divided by 2 generates the fourth (N+K)-bit digital signal D3 at the sixth time t7, as follows: Figure 8 As shown.

[0083] The successive approximation ADC repeats this analog-to-digital conversion process. At the eighth time t8, the summation module of the successive approximation ADC performs a summation on 2... (K +1) Summing N-bit digital signals, including (C(2 (K+1) -1),...,C(2 (K+2) -3)) and an N-bit digital signal corresponding to the successive approximation ADC output when the numerically controlled offset voltage is 0. This N-bit digital signal can be C(2 (K+1) -1)~C(2 (K+2) -3) any one of them, depending on the actual sequence of the voltage offset steps. Then the sum is fed into the divider module of the successive approximation ADC, where 2 (K+1) The sum of N-bit digital signals divided by 2 generates an (N+K)-bit digital signal D(2). (K+1) -1) such as Figure 8 As shown.

[0084] It should be noted that, Figure 8 Signals marked with an X are unknown signals. Unknown signals should be ignored during analog-to-digital conversion. For example... Figure 8 As shown, without a numerically controlled offset voltage and the associated higher-resolution ADC, C0 is the first digital output signal of the successive approximation ADC. With a numerically controlled offset voltage and the associated higher-resolution ADC, D0 is the first digital output signal of the successive approximation ADC. From t2 to t4, we have (2... (K+1) -2) analog-to-digital conversion cycles. In other words, a higher resolution ADC only brings (2) (K+1) -2) delay of analog-to-digital conversion cycles.

[0085] It should also be noted that, although Figure 8 Based on Figure 2 The illustrated embodiment describes the working principle of a successive approximation ADC, but... Figure 3-5 The illustrated embodiments are applicable to the above-mentioned... Figure 8 The description is a successive approximation of the ADC.

[0086] Figure 9 The illustration shows flowcharts of methods for implementing higher resolution ADCs according to various embodiments of the present disclosure. Figure 9 The flowchart shown is merely an example and should not be used to unduly limit the scope of the claims. Those skilled in the art will recognize many variations, substitutions, and modifications. For example, additions, removals, substitutions, rearrangements, and repetitions may be made. Figure 9 The steps shown are as follows.

[0087] In step 902, a numerically controlled offset voltage is added to the comparator stage of the successive approximation analog-to-digital converter circuit. The numerically controlled offset voltage repeats periodically, having at least 2 [units] in each cycle. (K+1) -1 voltage step, and the value of each voltage step is equal to an integer multiple of the analog voltage (ALSB) corresponding to the least significant bit (LSB) of the N-bit digital signal and 2. (-K) The product of , which ranges from ALSB (2 (-K) -1) times to (1-2) times (-K) ) times.

[0088] In step 904, the successive approximation analog-to-digital converter circuit is configured based on at least 2 (K+1) -1 numerical control offset voltage, sequentially generating 2 (K+1) -1 N-bit digital signal.

[0089] In step 906, calculate 2 (K+1) The weighted summation of -1 N-bit digital signals yields the summation result. This includes adding the N-bit digital signals corresponding to the successive approximation of the ADC output when the numerical control offset voltage is 0 twice in a summation module to obtain the weighted summation result.

[0090] In step 908, the summation result generated by the summation module is divided by the division module to obtain a digital signal with (N+K) bits.

[0091] In the divider module, the summation result is divided by 2 to obtain a digital signal with (N+K) bits.

[0092] In equal to (2) (K+1) A digital signal with (N+K) bits is generated after a delay of -2) analog-to-digital conversion cycles.

[0093] While embodiments of the present disclosure and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations may be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims.

[0094] Furthermore, the scope of this application is not intended to be limited to specific embodiments of the processes, machines, manufactures, compositions of matter, means, methods, and steps described in the specification. Those skilled in the art will readily understand from the disclosure of this disclosure processes, machines, manufactures, compositions of matter, means, methods, or steps that perform substantially the same function or achieve substantially the same results as the corresponding embodiments described herein that can be utilized according to this disclosure. Therefore, the appended claims are intended to include such processes, machines, manufactures, compositions of matter, means, methods, or steps within their scope.

Claims

1. A method of converting an analog input signal to a digital output signal, characterized by, The method includes: A numerically controlled offset voltage is added to the comparator stage of the successive approximation analog-to-digital converter circuit, wherein the numerically controlled offset voltage repeats periodically, and each cycle includes at least 2 (K+1) Each voltage step is equal to an integer multiple of the analog voltage (ALSB) corresponding to the least significant bit (LSB) of the N-bit digital signal multiplied by 2. (-K) The value; Operate the successive approximation analog-to-digital converter circuit to be based on at least 2 (K+1) The numerically controlled offset voltage of the step is generated sequentially by at least 2 (K+1) An N-bit digital signal; At least 2 (K+1) The summation result is obtained by adding N-bit digital signals; and The summation result is divided by the divider module to obtain an (N+K) bit digital signal.

2. The method as described in claim 1, characterized in that, In each cycle of the numerically controlled offset voltage, each voltage step occurs at least once and the sum of all the numerically controlled offset voltages in a cycle is equal to 0.

3. The method as described in claim 1, characterized in that, In the divider module, the summation result is divided by 2 to obtain an (N+K) bit digital signal.

4. The method as described in claim 1, characterized in that, Also includes: The numerically controlled offset voltage is placed between the output terminal of the sample-and-hold module and the first input terminal of the comparator stage, wherein the output voltage of the sample-and-hold module and the numerically controlled offset voltage are added together, and the sum of the output voltage of the sample-and-hold module and the numerically controlled offset voltage is fed to the first input terminal of the comparator stage.

5. The method of claim 1, wherein, Also includes: The numerically controlled offset voltage is placed between the output terminal of the digital-to-analog converter circuit and the second input terminal of the comparator stage, wherein the output voltage of the digital-to-analog converter circuit is added to the numerically controlled offset voltage, and the sum of the output voltage of the digital-to-analog converter circuit and the numerically controlled offset voltage is fed to the second input terminal of the comparator stage.

6. The method of claim 1, wherein, Also includes: The numerically controlled offset voltage is placed at the input terminal of the sample-and-hold module, wherein the numerically controlled offset voltage and the input voltage of the sample-and-hold module are added together, and the sum of the analog input signal and the numerically controlled offset voltage is fed to the input terminal of the sample-and-hold module.

7. The method as described in claim 6, characterized in that, The numerically controlled offset voltage is coupled to the sample-and-hold module through an input voltage buffer.

8. The method as described in claim 7, characterized in that, The input voltage buffer is a voltage follower, and wherein: The voltage follower has a first input terminal configured to receive an analog input signal, and a second input terminal connected to the output of the voltage follower via the numerically controlled offset voltage, wherein the output voltage of the voltage follower is equal to the sum of the analog input signal and the numerically controlled offset voltage.

9. The method as described in claim 1, characterized in that, A digital signal with (N+K) bits undergoes (2 (K+1) It is generated after a delay of -1) analog-to-digital conversion cycles.

10. A converter characterized by include: The comparator stage is configured to receive the output signal from the sample-and-hold module and the output of the digital-to-analog converter. An offset voltage generator is configured to generate a numerically controlled offset voltage added to one input of the comparator stage, wherein the numerically controlled offset voltage repeats periodically, and each cycle includes at least 2 (K+1) One voltage step; a successive approximation logic module configured to receive an output signal of the comparison stage and to generate at least 2 (K+1) N-bit digital signals based on the number-controlled offset voltage of the step (K+1) ; The summation module is configured to receive the output signal of the successive approximation logic module; as well as, A divider module is configured to receive a summation result generated by the summation module, wherein the converter is configured to be based on at least 2 (K+1) The numerically controlled offset voltage of the step generates a digital signal with (N+K) bits.

11. The converter as claimed in claim 10, characterized in that, In each cycle of the numerically controlled offset voltage, each voltage step occurs at least once and the sum of all the numerically controlled offset voltages in a cycle is equal to 0.

12. The converter as claimed in claim 10, characterized in that, At least 2 (K+1) Each voltage value in each voltage step is equal to an integer multiple of the analog voltage (ALSB) corresponding to the least significant bit (LSB) of the N-bit digital signal multiplied by 2. (-K) The value of .

13. The converter as claimed in claim 10, characterized in that, The successive approximation logic module is configured to generate a 2 (K+1) N-bit digital signal based on the digitally controlled offset voltage of at least 2 (K+1) voltage steps.

14. The converter as claimed in claim 13, characterized in that, The summation module is used to calculate 2 (K+1) Summing N-bit digital signals yields the summation result; as well as The summation result generated by the summation module is divided by 2 to obtain an (N+K) bit digital signal.

15. The converter as claimed in claim 10, characterized in that, The numerically controlled offset voltage is placed between the output terminal of the sample-and-hold module and the first input terminal of the comparator stage, wherein the output voltage of the sample-and-hold module and the numerically controlled offset voltage are added together, and the sum of the output voltage of the sample-and-hold module and the numerically controlled offset voltage is fed to the first input terminal of the comparator stage.

16. The converter as claimed in claim 10, characterized in that, The numerically controlled offset voltage is applied between the output of the digital-to-analog converter and the second input of the comparator stage.

17. The converter as claimed in claim 10, characterized in that, The numerically controlled offset voltage is added to the input of the sample-and-hold module via a voltage follower.

18. The converter as claimed in claim 17, characterized in that, The voltage follower has a first input terminal configured to receive an analog input signal, and a second input terminal connected to the output of the voltage follower via the numerically controlled offset voltage, wherein the output voltage of the voltage follower is equal to the sum of the numerically controlled offset voltage and the analog input signal.

19. A method for converting an analog input signal into a digital output signal, characterized in that, include: A numerically controlled offset voltage is added to the comparator stage of a successive approximation analog-to-digital converter circuit, wherein the numerically controlled offset voltage repeats periodically, and each cycle includes at least 2 (K+1) -1 voltage step, and the value of each voltage step is equal to an integer multiple of the analog voltage (ALSB) corresponding to the least significant bit (LSB) of the N-bit digital signal and 2. (-K) The product of, wherein the value of the numerically controlled offset voltage is within the range of the analog voltage (ALSB) corresponding to the least significant bit (LSB) of the N-bit digital signal (2). (-K) -1) times the analog voltage (ALSB) corresponding to the least significant bit (LSB) of an N-bit digital signal (1-2). (-K) Between ) times; Operate the successive approximation analog-to-digital converter circuit to be based on at least 2 (K+1) The numerically controlled offset voltage, in -1 voltage step increments, sequentially generates at least 2 (K+1) -1 N-bit digital signal; Calculate 2 (K+1) The summation result is obtained by weighting 1 N-bit digital signals, wherein the N-bit digital signal corresponding to the output of the successive approximation analog-to-digital converter circuit at zero voltage offset is added twice to the summation result; as well as, The summation result is divided by the division module to obtain a digital signal with (N+K) bits.

20. The method as described in claim 19, characterized in that, In each cycle of the numerically controlled offset voltage, each voltage step occurs at least once and the sum of all the numerically controlled offset voltages in one cycle is equal to 0; as well as, A digital signal with (N+K) bits in (2 (K+1) It is generated after a delay of -2) analog-to-digital conversion cycles.

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