An LDPC decoding method and related devices

Abstract

The present application discloses an LDPC decoding method and related devices, which relate to the technical field of data processing, can improve the error correction ability of LDPC decoding of an electrical solid-state device for data processing, and can be used for data processing of a solid-state drive main controller. The LDPC decoding method includes: determining the numerical space range to which each check node information in a parity check matrix belongs, where the parity check matrix is used to represent a low-density parity check code LDPC of a solid-state drive controller; performing a compression operation on the check node information according to the numerical space range to which the check node information belongs to obtain compressed information, where different numerical space ranges correspond to different compression operations; and sending the compressed information to a decision module.

Description

Technical Field

[0001] This application relates to the technical field of data processing, and in particular, to an LDPC decoding method and related devices. Background Art

[0002] LDPC (Low-Density Parity-Check Codes) has good comprehensive performance in key indicators such as error correction ability, decoding throughput rate, and algorithm complexity. It is widely used in mobile or fixed network standards and is also the mainstream error correction code for current solid-state storage controllers.

[0003] Currently, most LDPC decoding uses algorithms derived from min-sum. However, the existing min-sum algorithms or the derived algorithms have poor error correction ability. Summary of the Invention

[0004] Embodiments of this application provide an LDPC decoding method and related devices, which can improve the error correction ability of LDPC decoding of a solid-state drive controller.

[0005] In a first aspect of the embodiments of this application, an LDPC decoding method is provided, including:

[0006] Determine the numerical space range to which each check node information in the parity check matrix belongs, where the parity check matrix is used to represent the Low-Density Parity-Check (LDPC) code of a solid-state drive controller;

[0007] Perform a compression operation on the check node information according to the numerical space range to which the check node information belongs to obtain compressed information, where different numerical space ranges correspond to different compression operations;

[0008] Send the compressed information to a decision module.

[0009] In some embodiments, the performing a compression operation on the check node information according to the numerical space range to which the check node information belongs to obtain compressed information includes:

[0010] Perform a compression operation on the numerical space of the check node information according to the numerical space range to which the check node information belongs to obtain compressed information.

[0011] In some embodiments, before determining the numerical space range to which each check node information in the parity check matrix belongs, it further includes:

[0012] Determine the target bit width of data compression;

[0013] Determine the numerical space range according to the target bit width.

[0014] In some embodiments, performing a compression operation on the check node information according to the numerical space range to which the check node information belongs to obtain compressed information includes:

[0015] When the check node information belongs to a first numerical range, performing an integer-taking operation on the check node information to perform a compression operation on the check node information to obtain the compressed information, where the first numerical range is greater than or equal to a first node value and less than or equal to a second node value, and both the first node value and the second node value are determined according to the target bit width;

[0016] When the check node information does not belong to the first numerical range, performing a compression operation with a non-fixed ratio on the check node information to obtain the compressed information.

[0017] In some embodiments, the first node value is -kN + 1, and the second node value is kN - 1, where N = 2 q-1 -1, q is the target bit width minus 1, k is an integer, 2 ≤ k ≤ dv - 1, and dv is the average column weight of the parity check matrix corresponding to the check node information.

[0018] In some embodiments, performing a compression operation on the check node information according to the numerical space range to which the check node information belongs to obtain compressed information includes:

[0019] Performing a compression operation on the check node information according to the numerical space range to which the check node information belongs according to the following formula to obtain compressed information:

[0020]

[0021] where L is the value of the check node information, Q(L) is the compressed numerical space range corresponding to the compressed information, b is an integer, -kN + 1 ≤ b ≤ kN - 1, k is an integer, 2 ≤ k ≤ dv - 1, dv is the average column weight of the check matrix corresponding to the check node information, Δ is a positive integer, N = 2 q-1 -1, q is the target bit width minus 1, r is a positive integer, and 1 ≤ r ≤ N - 1.

[0022] In some embodiments, before determining the numerical space range to which each check node information in the parity check matrix belongs, it further includes:

[0023] Obtaining the log-likelihood ratio of the data stored in the solid-state drive;

[0024] Replace the check node information with the log-likelihood ratio to obtain replaced check node information;

[0025] Calculate the minimum value of all rows in the parity check matrix to obtain updated variable node information;

[0026] Calculate the decision value according to the replaced check node information and the updated variable node information;

[0027] Update the check node information with the decision value to obtain updated check node information;

[0028] The judging the numerical space range to which each check node information in the parity check matrix belongs includes:

[0029] Judge the numerical space range to which each of the updated check node information in the parity check matrix belongs.

[0030] In some embodiments, after sending the compressed information to the decision module, it includes:

[0031] Perform decompression processing on the compressed information to obtain decompressed check node information;

[0032] Make a decision on the decompressed check node information.

[0033] In a second aspect of the embodiments of the present application, there is provided an LDPC decoding device, including:

[0034] A judgment module, configured to judge the numerical space range to which each check node information in the parity check matrix belongs, where the parity check matrix is used to represent the low-density parity-check code LDPC of the solid-state drive controller;

[0035] A compression module, configured to perform compression operations on the check node information according to the numerical space range to which the check node information belongs, to obtain compressed information, and different numerical space ranges correspond to different compression operations;

[0036] A transmission module, configured to send the compressed information to the decision module.

[0037] In a third aspect of the embodiments of the present application, there is provided an electronic device, including:

[0038] A memory, in which a computer program is stored;

[0039] A processor, configured to implement the LDPC decoding method as described in the first aspect when executing the computer program.

[0040] In a fourth aspect of the embodiments of the present application, a computer-readable storage medium is provided. A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the LDPC decoding method described in the first aspect is implemented.

[0041] The LDPC decoding method and related devices provided in the embodiments of the present application determine the numerical space range to which each check node information in the parity check matrix belongs, and perform a compression operation on the check node information according to the numerical space range to which the check node information belongs to obtain compressed information. Different numerical space ranges correspond to different compression operations. The compression operation can perform compression operations for different numerical space ranges. This differential compression according to different numerical space sizes, rather than fixed-ratio compression, can compress the check node information in a larger numerical space to a greater extent, compress the check node information in a smaller numerical space to a smaller extent, or not compress the check information in some smaller numerical spaces, which can ensure that the numerical space or bit width of the check node information in the smaller numerical space will not be too low, thereby ensuring the error correction performance and preventing the decline of the error correction ability due to fixed-ratio compression of all check node information. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 is a schematic flowchart of an LDPC decoding method provided in an embodiment of the present application;

[0043] Figure 2 is a schematic block diagram of an LDPC decoding device provided in an embodiment of the present application;

[0044] Figure 3 is a schematic block diagram of an electronic device provided in an embodiment of the present application;

[0045] Figure 4 is a schematic block diagram of a computer-readable storage medium provided in an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0046] In order to better understand the technical solutions provided in the embodiments of this specification, the technical solutions in the embodiments of this specification will be described in detail below with reference to the drawings and specific embodiments. It should be understood that the specific features in the embodiments of this specification and the embodiments are detailed descriptions of the technical solutions in the embodiments of this specification, rather than limitations on the technical solutions of this specification. Without conflict, the technical features in the embodiments of this specification and the embodiments can be combined with each other.

[0047] In this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element. The term "more than two" includes two or more than two cases.

[0048] LDPC has good comprehensive performance in key indicators such as error correction ability, decoding throughput rate and algorithm complexity. It is widely used in mobile or fixed network standards and is also the mainstream error correction code for current solid-state storage controllers. Currently, most LDPC decoders use algorithms derived from min-sum. However, the existing min-sum algorithms or the derived algorithms have poor error correction ability.

[0049] In view of this, the embodiments of the present application provide an LDPC decoding method and related devices, which can improve the error correction ability of LDPC decoding of the main controller chip of a solid-state drive.

[0050] In the first aspect of the embodiments of the present application, an LDPC decoding method is provided. Figure 1 It is a schematic flowchart of an LDPC decoding method provided by the embodiments of the present application. As Figure 1 shown, the LDPC decoding method provided by the embodiments of the present application includes:

[0051] S100: Determine the numerical space range to which each check node information in the parity check matrix belongs, where the parity check matrix is used to represent the low-density parity-check code LDPC of the solid-state drive controller. LDPC can be defined by a parity check matrix, and there is a corresponding Tanner bipartite graph for each parity check matrix. The Tanner bipartite graph includes variable nodes and check nodes. Each variable node can represent a column in the parity check matrix, and each check node can represent a row in the parity check matrix.

[0052] S200: Compress the check node information according to the numerical space range to which the check node information belongs to obtain compressed information, where different numerical space ranges correspond to different compression operations. Compression operations can be performed for different numerical space ranges, and this is differential compression according to different numerical space sizes. Compression with a non-fixed compression ratio can compress the check node information in a larger numerical space to a greater extent, compress the check node information in a smaller numerical space to a smaller extent, or not compress the check information in some smaller numerical spaces, which can ensure the accuracy of the check node information in the smaller numerical space, and thus further ensure the error correction performance. It will not cause a decline in the error correction ability due to fixed-ratio compression of all check node information.

[0053] S300: Send the compressed information to the decision module. Send the compressed information after compression to the decision module for decision-making, and the decision result can reflect the error correction result. The decision-making process can be to compare the check node information with the stored information. When a difference is found, it can be regarded as an error occurring, and then the error correction process is completed.

[0054] It should be noted that generally, the bit width of the input data and the bit width of the internal operation are two factors that the decoder needs to focus on regarding the error correction ability. If the internal bit width of the LDPC decoder is large, it will increase the area of the chip where the decoder is located and the wiring difficulty. The current general method is to reduce the bit width by using bit width compression. However, the existing min-sum algorithm or the derived algorithms perform the same ratio of compression on the input data, that is, uniform compression. For example, all data are compressed by the same multiple without distinction. Although the smaller the bit width, the better the performance of the decoder in terms of complexity, power, and throughput, such compression will cause a decline in the error correction ability. Especially when the bit width is reduced to a certain value, the error correction ability will deteriorate severely. It should be noted that the numerical space can obtain the bit width parameter.

[0055] In view of the above problems, the LDPC decoding method provided by the embodiments of the present application determines the numerical space range to which each check node information in the parity check matrix belongs, and performs a compression operation on the check node information according to the numerical space range to which the check node information belongs, so as to obtain compressed information. Different numerical space ranges correspond to different compression operations. The compression operation can perform compression operations for different numerical space ranges. This differential compression according to different numerical space sizes, rather than fixed-ratio compression, can compress the check node information in a larger numerical space to a greater extent, compress the check node information in a smaller numerical space to a smaller extent, or not compress the check information in some smaller numerical spaces, which can ensure that the numerical space or bit width of the check node information in the smaller numerical space will not be too low, thereby ensuring the error correction performance and preventing the decline of the error correction ability caused by fixed-ratio compression of all check node information.

[0056] In some embodiments, step S200 may include:

[0057] Perform a compression operation on the numerical space of the check node information according to the numerical space range to which the check node information belongs, so as to obtain compressed information. The compression of the numerical space can be reflected as the compression of the bit width, and the numerical space can reflect the bit width parameter. It should be understood that the numerical space is the distribution range of the values of the check node information. In the case where the data is too scattered, the compression algorithm can also be a logarithmic compression algorithm, which is not specifically limited in the embodiments of the present application.

[0058] The LDPC decoding method provided by the embodiments of the present application determines the numerical space range to which each check node information in the parity check matrix belongs, and performs a numerical space compression operation on the check node information according to the numerical space range to which the check node information belongs, so as to obtain compressed information. Bit width compression can be achieved. Different numerical space ranges correspond to different compression operations. The compression operation can perform compression operations for different numerical space ranges. This differential compression according to different numerical space sizes, rather than fixed-ratio compression, can compress the check node information in a larger numerical space to a greater extent, compress the check node information in a smaller numerical space to a smaller extent, or not compress the check information in some smaller numerical spaces, which can ensure that the numerical space or bit width of the check node information in the smaller numerical space will not be too low, thereby ensuring the error correction performance and preventing the decline of the error correction ability caused by fixed-ratio compression of all check node information.

[0059] In some embodiments, before step S100, it further includes:

[0060] Determine the target bit width for data compression. Exemplarily, the target bit width can be 4 bits (bits) or 5 bits, which is not specifically limited in the embodiments of the present application. The bit width size to be compressed can be preset in advance as the target bit width.

[0061] Determine the numerical space range according to the target bit width. The size of the target bit width can affect the formulation of the numerical space range.

[0062] Exemplarily, step S200 may include:

[0063] When the check node information belongs to the first numerical range, perform an integer operation on the check node information to perform a compression operation on the check node information to obtain compressed information, where the first numerical range is greater than or equal to the first node value and less than or equal to the second node value, and both the first node value and the second node value are determined according to the target bit width. Exemplarily, if the check node information is represented in binary, the rounding operation can be to assign a value of 0 to the highest bit of the check node information to achieve the rounding operation, and the rounding operation is also a way of compression.

[0064] When the check node information does not belong to the first numerical range, perform a non-fixed ratio compression operation on the check node information to obtain compressed information. The highest bit of the binary check node information can be assigned a value of 1.

[0065] Exemplarily, the first node value is -kN + 1, and the second node value is kN - 1, where N = 2 q-1 -1, the output interval is kN or a multiple thereof, and the maximum output modulus value is k N N or a multiple thereof. q is the target bit width minus 1, k is an integer, 2 ≤ k ≤ dv - 1, and dv is the average column weight of the parity check matrix corresponding to the parity check node information. It can be considered that the numerical space range between the first node value and the second node value is a smaller bit width range, and a smaller degree of compression can be performed, for example, by the rounding operation method, to ensure that the bit width of the check nodes in the smaller numerical space will not be too low to avoid a decrease in the error correction performance due to too low a bit width.

[0066] In some embodiments, step S200 may include:

[0067] According to the numerical space range to which the check node information belongs, perform a compression operation on the check node information according to the following formula to obtain compressed information:

[0068]

[0069] Among them, L is the value of the check node information, Q(L) is the compressed value space range corresponding to the compressed information, b is an integer, -kN + 1 ≤ b ≤ kN - 1, k is an integer, 2 ≤ k ≤ dv - 1, dv is the average column weight of the check matrix corresponding to the check node information, Δ is a positive integer, N = 2 q-1 -1, q is the target bit width minus 1, r is a positive integer, 1 ≤ r ≤ N - 1. Among them, (0, b), (0, N), (0, -N), (1, r), (1, -r), (1, N), and (1, -N) represent the value space range. It can be seen from the above formula that when the value L of the check node information is between -kNΔ and -kNΔ, the compressed value space range is (-N, N). Beyond the range of [-kNΔ, -kNΔ], the compressed value space range is (-N, 1) or (1, N). It can be seen that the larger the value of the input check node information, the greater the degree of compression, and the smaller the value of the input check node information, the smaller the degree of compression. If the input value L is an integer, the compression operation can also be implemented by looking up a table. For k N NΔ ≤ L ≤ -k N The look-up table address for the case of NΔ can be L + k N NΔ, and the content stored at this address is its corresponding Q(L) value. Therefore, the size of the table is 2k N NΔ + 1. When the absolute value of L is not greater than N, the corresponding Q(L) value can be obtained by looking up the table, otherwise (1, ±N) is output.

[0070] Exemplarily, if the target bit width is 4bit and Δ = 1, then q = 3, k = 2, N = 3, and the output Q(L) is {(0, 0), (0, ±1), (0, ±2), (0, ±3), (1, ±1), (1, ±2), (1, ±3)}, -5 ≤ b ≤ 5, r = 1 or r = 2, and the integer values of the nodes in the corresponding value space ranges are 0, ±1, ±2, ±3, ±kN, ±k 2 N, ±k 3 N, that is, 0, ±1, ±2, ±3, ±6, ±12, ±24.

[0071] Exemplarily, the target bit width is 5 bits, Δ = 1, then q = 4, k = 2, N = 7, and the compressed Q(L) is {(0,0), (0,±1), (0,±2), (0,±3), (0,±4), (0,±5), (0,±6), (0,±7), (1,±1), (1,±2), (1,±3), (1,±4), (1,±5), (1,±6), (1,±7)}. The integer values of the nodes in the corresponding numerical space ranges are 0, ±1, ±2, ±3, ±4, ±5, ±6, ±7, ±14, ±28, ±56, ±112, ±224, ±448, ±896 respectively, and the intervals of both linear and non-linear values can be increased.

[0072] The LDPC decoding method provided by the embodiments of the present application can reduce the internal bit width to about 50% of the original by performing non-linear mapping on the intermediate operation results of the decoder, reducing the chip area, power consumption, and wiring difficulty. An appropriate compression algorithm can be selected according to the data characteristics to ensure the compression effect while maintaining the error correction ability.

[0073] In some embodiments, before step S100, it further includes:

[0074] Obtain the log-likelihood ratio of the data stored in the solid-state drive. The log-likelihood ratio LLR information can be represented by L_c n Indicate.

[0075] Replace the check node information with the log-likelihood ratio to obtain the replaced check node information. Replace the check node information Lq m,n with L_c n Replace it. Wherein, m and n can represent the check nodes in the parity check matrix H, n can represent the variable nodes in the parity check matrix H, and both m and n are natural numbers greater than 0. That is, the variable nodes n form the columns of the parity check matrix H, and the check nodes m form the rows of the parity check matrix H.

[0076] Calculate the minimum value of all rows in the parity check matrix to obtain the updated variable node information.

[0077] Exemplarily, calculate the updated variable node information L_r m,n According to the following formula:

[0078] L_r m,n =

[0079] (∏ n′∈H(m),n′≠n sgn(Lq m,n′ ) × min n′∈H(m),n′≠n (|Lq m,n′ |) × α), Formula (1)

[0080] Wherein, L_r m,nTo update the variable node information, Lq m,n′ To replace the parity check node information, i.e., Lq m,n′ = L_c n , where α is a correction coefficient, H(m) is the variable node adjacent to the parity check node m, n′ is the other variable nodes outside n, that is, the value ranges of n′ and n are the same, but n′≠n, and n′ and n cannot take the same value at the same time.

[0081] Calculate the decision value according to the replaced parity check node information and the updated variable node information.

[0082] Exemplarily, calculate the decision value according to the following formula:

[0083] sum_lr n = L_c n +∑ m∈H(n) L_r m,n , formula (2)

[0084] where sum_lr n is the decision value, and H(n) is the parity check node adjacent to the variable node n.

[0085] Update the parity check node information using the decision value to obtain the updated parity check node information.

[0086] Calculate the updated parity check node information according to the following formula:

[0087] L = sum_lr n - L_r m,n , substituting formula (1) and formula (2) into it, the updated parity check information L can be obtained.

[0088] Step S100 may include:

[0089] Determine the numerical space range to which each updated parity check node information in the parity check matrix belongs. That is, the parity check node information in step S100 is the updated parity check node information.

[0090] In some embodiments, after step S300, it may include:

[0091] Perform decompression processing on the compressed information to obtain decompressed parity check node information.

[0092] Judge the decompression verification node information. That is, the decompression verification node information can be compared with the data stored in the solid-state drive to determine whether they are the same. If they are the same, no error has occurred; if they are different, an error has occurred. Here, the same and different can be exactly the same or the same within the error range. The embodiments of the present application do not make specific limitations. Then, the process of decoding and error correction can be completed. The decompression error process can be completed by referring to a table, and the table for lookup is the comparison table in the compression process. For example, when the compressed value is subjected to rounding operation, its corresponding integer can be restored by referring to the table during the decompression process.

[0093] In the second aspect of the embodiments of the present application, an LDPC decoding device is provided. Figure 2 It is a schematic block diagram of an LDPC decoding device provided by the embodiments of the present application. As Figure 2 shown, an LDPC decoding device provided by the embodiments of the present application includes:

[0094] A judgment module 400, configured to judge the numerical space range to which each check node information in the parity check matrix belongs, where the parity check matrix is used to represent the low-density parity check code LDPC of the solid-state drive controller;

[0095] A compression module 500, configured to perform a compression operation on the check node information according to the numerical space range to which the check node information belongs, to obtain compressed information;

[0096] A transmission module 600, configured to send the compressed information to the judgment module.

[0097] The LDPC decoding device provided by the embodiments of the present application judges the numerical space range to which each check node information in the parity check matrix belongs, and performs a compression operation on the check node information according to the numerical space range to which the check node information belongs, to obtain compressed information. Different numerical space ranges correspond to different compression operations. The compression operation can perform compression operations for different numerical space ranges. This differential compression according to different numerical space sizes, rather than fixed-ratio compression, can compress the check node information in a larger numerical space to a greater extent, compress the check node information in a smaller numerical space to a smaller extent, or not compress the check information in some smaller numerical spaces, which can ensure that the numerical space or bit width of the check node information in the smaller numerical space will not be too low, thereby ensuring the error correction performance and preventing the decline of the error correction ability due to fixed-ratio compression of all check node information.

[0098] In the third aspect of the embodiments of the present application, an electronic device is provided. Figure 3 It is a schematic block diagram of an electronic device provided by the embodiments of the present application. As Figure 3As shown, the electronic device includes: a memory 700 in which a computer program is stored; and a processor 800 that implements the LDPC decoding method as described in the first aspect when executing the computer program.

[0099] The LDPC decoding method includes the following steps:

[0100] Determine the numerical space range to which each check node information in the parity check matrix belongs, where the parity check matrix is used to represent the low-density parity-check code LDPC of the solid-state drive controller.

[0101] Perform a compression operation on the check node information according to the numerical space range to which the check node information belongs to obtain compressed information, where different numerical space ranges correspond to different compression operations.

[0102] Send the compressed information to the decision module.

[0103] In the fourth aspect of the embodiments of the present application, a computer-readable storage medium is provided. Figure 4 It is a schematic block diagram of a computer-readable storage medium provided by the embodiments of the present application. As Figure 4 shown, a computer program 900 is stored on the computer-readable storage medium, and when the computer program 900 is executed by a processor, the LDPC decoding method as described in the first aspect is implemented.

[0104] The LDPC decoding method includes the following steps:

[0105] Determine the numerical space range to which each check node information in the parity check matrix belongs, where the parity check matrix is used to represent the low-density parity-check code LDPC of the solid-state drive controller.

[0106] Perform a compression operation on the check node information according to the numerical space range to which the check node information belongs to obtain compressed information, where different numerical space ranges correspond to different compression operations.

[0107] Send the compressed information to the decision module.

[0108] It should be noted that in the above embodiments, the descriptions of the various embodiments have their own emphases. For parts not described in detail in a certain embodiment, reference may be made to the relevant descriptions of other embodiments.

[0109] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-readable program code.

[0110] The present application is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to the embodiments of the present application. It should be understood that each flow and / or block in the flowchart and / or block diagram, as well as the combination of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate a means for implementing the functions specified in Figure 1 one or more of the flows Figure 1 or blocks or the combination of blocks.

[0111] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufactured article including an instruction means that implements the functions specified in Figure 1 one or more of the flows Figure 1 or blocks or the combination of blocks.

[0112] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are performed on the computer or other programmable device to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in Figure 1 one or more of the flows Figure 1 or blocks or the combination of blocks.

[0113] The embodiments of the present application also provide a computer program product, which includes computer software instructions. When the computer software instructions run on a processing device, the processing device is caused to execute the process of the LDPC decoding method.

[0114] A computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, the processes or functions according to the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center in a wired manner (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or a wireless manner (such as infrared, wireless, microwave, etc.). The computer-readable storage medium may be any available medium that can be stored by a computer or a data storage device such as a server or a data center that includes one or more available media integrated. The available medium may be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (SSD)), etc.

[0115] Those skilled in the art can clearly understand that for the convenience and conciseness of description, the specific working processes of the above-described systems, devices, and units can refer to the corresponding processes in the foregoing method embodiments and will not be elaborated herein.

[0116] In several embodiments provided in the present application, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the displayed or discussed couplings or direct couplings or communication connections to each other may be indirect couplings or communication connections through some interfaces, devices, or units, and may be in electrical, mechanical, or other forms.

[0117] The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0118] In addition, in each embodiment of the present application, each functional unit may be integrated into one processing unit, may exist separately physically for each unit, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of a software functional unit.

[0119] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it may be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, may be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods in the various embodiments of the present application. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical discs that can store program codes.

[0120] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present application.

[0121] Although the preferred embodiments of this specification have been described, those skilled in the art can make additional changes and modifications once they know the basic creative concept. Therefore, the appended claims are intended to be construed to include the preferred embodiments and all changes and modifications that fall within the scope of this specification.

[0122] Obviously, those skilled in the art can make various changes and modifications to this specification without departing from the spirit and scope of this specification. Thus, if these modifications and variations of this specification fall within the scope of the claims of this specification and their equivalent technologies, this specification is also intended to include these modifications and variations.

Claims

1. An LDPC decoding method, characterized in that, including: Determine the target bit width of data compression; Determine the numerical space range according to the target bit width; Judge the numerical space range to which each check node information in the parity check matrix belongs, where the parity check matrix is used to represent the low-density parity check code LDPC of the solid-state drive controller; Perform a compression operation on the check node information according to the numerical space range to which the check node information belongs, to obtain compressed information, where different numerical space ranges correspond to different compression operations; Send the compressed information to the decision module; The performing a compression operation on the check node information according to the numerical space range to which the check node information belongs to obtain compressed information includes: When the check node information belongs to the first numerical range, perform an integer-taking operation on the check node information to perform a compression operation on the check node information to obtain the compressed information, where the first numerical range is greater than or equal to the first node value and less than or equal to the second node value, and both the first node value and the second node value are determined according to the target bit width; When the check node information does not belong to the first numerical range, perform a non-fixed ratio compression operation on the check node information to obtain the compressed information; The value of the first node is -kN + 1, and the value of the second node is kN - 1, where N = 2 q-1 -1, q is the target bit width minus 1, k is an integer, 2 ≤ k ≤ dv - 1, and dv is the average column weight of the parity check matrix corresponding to the check node information; The performing a compression operation on the check node information according to the numerical space range to which the check node information belongs to obtain compressed information includes: Perform a compression operation on the check node information according to the numerical space range to which the check node information belongs according to the following formula to obtain compressed information: Wherein, L is the value of the check node information, Q(L) is the compression value space range corresponding to the compression information, b is an integer, -kN + 1 ≤ b ≤ kN - 1, k is an integer, 2 ≤ k ≤ dv - 1, dv is the average column weight of the check matrix corresponding to the check node information, Δ is a positive integer, N = 2 q-1 -1, q is the target bit width minus 1, r is a positive integer, 1 ≤ r ≤ N - 1.

2. The LDPC decoding method according to claim 1, wherein The performing a compression operation on the check node information according to the numerical space range to which the check node information belongs to obtain compressed information includes: Perform a compression operation on the numerical space of the check node information according to the numerical space range to which the check node information belongs to obtain compressed information.

3. The LDPC decoding method according to claim 1, wherein Before judging the numerical space range to which each check node information in the parity check matrix belongs, it further includes: Obtain the log-likelihood ratio of the data stored in the solid-state drive; Replace the check node information with the log-likelihood ratio to obtain the replaced check node information; Calculate the minimum value of all rows in the parity check matrix to obtain the updated variable node information; Calculate the decision value according to the replaced check node information and the updated variable node information; Update the check node information with the decision value to obtain the updated check node information; The judging the numerical space range to which each check node information in the parity check matrix belongs includes: Judge the numerical space range to which each of the updated check node information in the parity check matrix belongs.

4. The LDPC decoding method according to claim 1, wherein After sending the compressed information to the decision module, it includes: Perform decompression processing on the compressed information to obtain decompressed check node information; Make a decision on the decompressed check node information.

5. An LDPC decoding device, characterized in that, including: A judgment module, configured to judge the numerical space range to which each check node information in the parity check matrix belongs, where the parity check matrix is used to represent the low-density parity check code LDPC of the solid-state drive controller; Before determining the numerical space range to which each check node information in the parity check matrix belongs, it further includes: Determine the target bit width of data compression; Determine the numerical space range according to the target bit width; A compression module for performing a compression operation on the check node information according to the numerical space range to which the check node information belongs to obtain compressed information, and different numerical space ranges correspond to different compression operations; A transmission module for sending the compressed information to the decision module; The performing a compression operation on the check node information according to the numerical space range to which the check node information belongs to obtain compressed information includes: When the check node information belongs to the first numerical range, perform an integer-taking operation on the check node information to perform a compression operation on the check node information to obtain the compressed information, where the first numerical range is greater than or equal to the first node value and less than or equal to the second node value, and both the first node value and the second node value are determined according to the target bit width; When the check node information does not belong to the first numerical range, perform a compression operation with a non-fixed ratio on the check node information to obtain the compressed information; The value of the first node is -kN + 1, and the value of the second node is kN - 1, where N = 2 q-1 -1, q is the target bit width minus 1, k is an integer, 2 ≤ k ≤ dv - 1, and dv is the average column weight of the parity check matrix corresponding to the check node information; The performing a compression operation on the check node information according to the numerical space range to which the check node information belongs to obtain compressed information includes: Perform a compression operation on the check node information according to the numerical space range to which the check node information belongs according to the following formula to obtain compressed information: Wherein, L is the value of the check node information, Q(L) is the compression value space range corresponding to the compression information, b is an integer, -kN + 1 ≤ b ≤ kN - 1, k is an integer, 2 ≤ k ≤ dv - 1, dv is the average column weight of the check matrix corresponding to the check node information, Δ is a positive integer, N = 2 q-1 -1, q is the target bit width minus 1, r is a positive integer, 1 ≤ r ≤ N - 1.

6. An electronic device, characterized in that, Includes: A memory in which a computer program is stored; A processor that, when executing the computer program, implements the LDPC decoding method according to any one of claims 1-4.

7. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the LDPC decoding method according to any one of claims 1-4 is implemented.

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