Apparatus for Controlling a NAND Flash Memory Device and Method of Controlling the Same

Abstract

A control device for a NAND flash memory device according to an embodiment includes: a NAND flash memory; a controller configured to generate command signals to program, read, and erase data in the NAND flash memory; and an auxiliary power circuit configured to maintain power for operating the memory and the controller during a first time period starting from a first time point at which a voltage from a power supply is less than a preset voltage, wherein the controller is configured to block the command signals during the first time period, and wherein power supplied to the memory is blocked for at least a second time period starting from a second time point after the first time.

Description

Technical Field

[0001] The embodiment relates to an apparatus for controlling a NAND flash memory device, and more particularly, to an apparatus for controlling a NAND flash memory device capable of preventing data corruption that may occur in an unstable power environment such as a sudden power failure, and a control method thereof. Background Art

[0002] Recently, there has been an increasing demand for non-volatile memory devices that can be electrically programmed and erased and do not require a refresh function for periodically rewriting data. In addition, in order to develop large-capacity memory devices capable of storing a large amount of data, research on high-integration technologies for memory devices is actively underway. Here, 'programming' refers to an operation of writing data into a memory cell, and 'erasing' refers to an operation of removing the data written in the memory cell.

[0003] Therefore, a NAND flash memory device has been proposed for the high integration of non-volatile memory devices. In the NAND flash memory device, a plurality of memory cells are connected in series (i.e., a structure in which adjacent cells share a drain or a source with each other) to form a string. Different from a NOR-type flash memory device, a NAND flash memory device is a memory device that reads information sequentially, and the programming operation and the erasing operation of the NAND flash memory device are performed by injecting or emitting electrons into the floating gate by controlling the threshold voltage of the memory cell using the Fowler-Nordheim (FN) tunneling method.

[0004] Therefore, an erased cell has a negative threshold voltage due to the emission of electrons from the floating gate, and the state of the erased cell is referred to as an on-cell. And a programmed cell has a positive threshold voltage by injecting electrons into the floating gate, and the state of the programmed cell is referred to as an off-cell.

[0005] Meanwhile, recently, wireless communication and global positioning system (GPS) technologies have been combined, and telematics for providing various mobile communication services (e.g., location information, safe driving, entertainment, financial services, reservation, and product purchase) is being applied in vehicles. In addition, a NAND flash memory device as described above is provided in the telematics, and thus, data generated during driving is programmed in real time.

[0006] In addition, in the event of a serious accident, the safety-related eCall function in telematics automatically attempts to connect the call to the single emergency number 112 in Europe. At this time, if the driver loses consciousness or is unable to make a call directly, the eCall function automatically provides the vehicle's location, type, color, and the number of occupants to the emergency service center. Most countries are building an emergency service system that operates similarly to eCall in the event of a vehicle accident, and since this function is related to human life, high reliability is required.

[0007] However, the NAND flash memory device applied to telematics as described above has a problem of data corruption such as charge gain in an unstable power state. In other words, the NAND flash memory device applied to telematics products has a fundamental weakness in terms of reliability. For example, there are intermittent failures of data corruption during power interruption due to charge gain, which is a structural weakness, so there is a problem that the eCall function cannot be executed normally. Summary of the Invention

[0008]

Technical Problem

[0009] Embodiments provide an apparatus and a control method for controlling a NAND flash memory device, which can fundamentally solve data corruption caused by charge gain occurring during power interruption.

[0010] In addition, embodiments provide an apparatus and a control method for controlling a NAND flash memory device, which can solve problems that may occur during the operation of the memory during power interruption by preventing access to the memory when a power interruption is detected.

[0011] Furthermore, embodiments provide an apparatus and a control method for controlling a NAND flash memory device, which can solve data corruption caused by charge gain when power is blocked during a programming operation or an erase operation of a NAND flash by supplying auxiliary power until the ongoing operation is completed when a power interruption is detected while a NAND flash operation is in progress.

[0012] In addition, embodiments provide a control apparatus and a control method for a NAND flash memory device, which allow the flash memory to operate normally when power is restored by performing a power-off timing of the flash memory when a power interruption is detected and performing a power-on timing when normal power is detected.

[0013] The technical problems to be solved in the embodiments are not limited to the above technical problems, and other technical problems not mentioned will be clearly understood by those of ordinary skill in the art to which the present invention pertains from the following description.

[0014]

Technical Solution

[0015] A control device for a NAND flash memory device according to an embodiment includes: a NAND flash memory; a controller configured to generate command signals to program, read, and erase data in the NAND flash memory; and an auxiliary power circuit configured to maintain power for operating the memory and the controller during a first time period starting from a first time point when a voltage from a power supply is less than a preset voltage, wherein the controller is configured to block the command signals during the first time period, and wherein, starting from a second time point after the first time, power supplied to the memory is blocked for at least a second time.

[0016] In addition, when the first time point is a programming operation time (tPROG) or an erase operation time (tBERS) of the memory, the auxiliary power circuit supplies auxiliary power to complete the programming operation or the erase operation of the memory.

[0017] In addition, the first time is a time until a programming operation or an erase operation executed in the memory before the first time point is completed.

[0018] In addition, the control device further includes a power management IC (PMIC) that is connected to the power supply and supplies power to the memory and the controller.

[0019] In addition, the auxiliary power circuit is disposed between the PMIC and the memory.

[0020] In addition, the controller is configured to control the PMIC such that power is supplied to the memory after the power supply is blocked for at least the second time.

[0021] In addition, the control device further includes an input voltage detector configured to detect a voltage level of the power supply, and the auxiliary power circuit is connected to a power input terminal of the PMIC.

[0022] In addition, the input voltage detector is configured to detect a voltage level of an input terminal of the auxiliary power circuit.

[0023]

Beneficial Effects

[0024] The embodiment detects an unstable state of the input power and controls the operation of the NAND flash memory device based on this, so that defects such as data corruption that may occur when the NAND flash memory device operates in an unstable state of the input power can be prevented. Specifically, according to the embodiment, when the input power is unstable, flash access is blocked, so that failures of the NAND flash memory device in an unstable environment of the input power can be prevented.

[0025] In addition, in an embodiment, when an operation of a NAND flash memory device is in progress when a power interruption is detected, auxiliary power is supplied until the ongoing operation is completed. Accordingly, data corruption caused by charge gain that occurs when power is blocked during a programming operation or an erase operation of the NAND flash memory device can be solved. Accordingly, the operation reliability of the NAND flash memory device can be improved.

[0026] In addition, in an embodiment, when a power interruption is detected, a power-off timing sequence of the NAND flash memory device is executed, and when normal power is detected, a power-on timing sequence is executed. Accordingly, operation reliability and user satisfaction can be improved because the flash memory operates normally when the input power is restored. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a view for explaining the structure of a memory cell of a NAND flash memory device.

[0028] Figure 2 is a view showing Figure 1 an equivalent circuit diagram of a memory cell array of

[0029] Figure 3 is a view schematically showing a programming operation and an erase operation of a NAND flash memory device.

[0030] Figure 4 is a view showing an erase operation of a NAND flash memory device.

[0031] Figure 5 is a view showing charge gain in a NAND flash memory device.

[0032] Figure 6 is a block diagram showing components of a NAND flash memory system according to a first embodiment.

[0033] Figure 7 and Figure 8 is for explaining Figure 6 a modified example of the NAND flash memory system shown in

[0034] Figure 9 is a view for stepwise explaining a method of operating a NAND flash memory system according to an exemplary embodiment.

[0035] Figure 10 and Figure 11 is a view showing a power timing according to a change in an input voltage.

[0036] Figure 12 and 13It is a flowchart for gradually explaining a method of controlling a NAND flash memory system according to an embodiment.

[0037] Figure 14 It is a view showing the change in input voltage when the vehicle starts.

[0038] Figure 15 It is a flowchart for gradually explaining a method of activating a memory protection function according to an embodiment. Detailed Description of the Invention

[0039] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0040] However, the spirit and scope of the present invention are not limited to the parts of the described embodiments, but can be implemented in various other forms, and within the spirit and scope of the present invention, one or more elements of the embodiments can be selectively combined and replaced.

[0041] In addition, unless otherwise clearly defined and described, the terms (including technical terms and scientific terms) used in the embodiments of the present invention can be interpreted as having the same meaning as commonly understood by those of ordinary skill in the art to which the present invention pertains, and terms such as those defined in a common dictionary can be interpreted as having a meaning consistent with their meaning in the relevant technical background. In addition, the terms used in the embodiments of the present invention are used to describe the embodiments and are not intended to limit the present invention.

[0042] In this specification, unless otherwise specifically stated in a phrase, the singular form may also include the plural form, and when described as "at least one (or more) of A (and), B, and C", it may include at least one of all combinations that can be combined among A, B, and C. In addition, when describing the elements of the embodiments of the present invention, terms such as first, second, A, B, (a), and (b) may be used.

[0043] These terms are only used to distinguish an element from other elements, and these terms are not limited to the nature, order, or sequence of the elements. In addition, when an element is described as "connected", "coupled", or "joined" to another element, it not only includes that the element is directly "connected", "coupled", or "joined" to the other element, but also includes that the element is "connected", "coupled", or "joined" by another element between the element and the other element.

[0044] In addition, when described as being formed or disposed "on (above)" or "under (below)" each element, "on (above)" or "under (below)" may include not only two elements being directly connected to each other, but also one or more other elements being formed or disposed between the two elements. Further, when expressed as "on (above)" or "under (below)", it may include not only the upward direction based on one element, but also the downward direction.

[0045] Figure 1 is a view for explaining the structure of a memory cell of a NAND flash memory device.

[0046] Referring to Figure 1 , the operation of a NAND flash memory device consists of three operations, which include erase, program, and read.

[0047] The program operation of a NAND flash memory device is performed in units of pages.

[0048] In the program operation, by applying a constant voltage (e.g., 19V) to the control gate (CG) of the memory cell, electrons move in the direction of the floating gate (FG) 10. At this time, the state of the memory cell becomes OFF TR or the OFF cell state, and becomes a positive (+) threshold voltage Vt. In this case, the program operation of the flash memory device may not be completed in one step, but can be performed in multiple steps, and the desired data can be programmed by increasing the voltage applied to the control gate.

[0049] In addition, the erase operation of a NAND flash memory device is performed in units of blocks, and may mean changing the cell from 0 to 1.

[0050] At this time, when applying a specific voltage (e.g., 20V) from the P substrate to perform the erase operation of the NAND flash memory device, electrons in the floating gate 10 of the memory cell move downward through the F-N tunneling effect. Further, due to the emission of electrons from the floating gate 10, the erased memory cell may have a negative (-) threshold voltage Vt. In this case, the state of the erased memory cell may be referred to as ON TR or the ON cell state.

[0051] In addition, the read operation of a NAND flash memory device refers to an operation of outputting data as 1 or 0 by checking whether the state of the memory cell is ON TR or OFF TR.

[0052] Figure 2 is a diagram showing Figure 1 the equivalent circuit diagram of the memory cell array of

[0053] Referring to Figure 2, the memory cell array of the NAND flash memory device includes a plurality of blocks. In addition, in each of the plurality of blocks, a plurality of bit lines BL0 to BLn are arranged in parallel.

[0054] In addition, a plurality of strings corresponding to each of the plurality of bit lines BL0 to BLn are provided in each of the plurality of blocks. Each of the plurality of strings may include a drain select transistor (DST) and a source select transistor (SST) for selecting the corresponding string. Additionally, a plurality of memory cells MC0 to MCn (where n may be 15, 31, or 63) are connected in series between the drain select transistor DST and the source select transistor SST. Further, the sources of the source select transistors SST of each of the plurality of strings are commonly connected to a common source line (CSL).

[0055] In addition, the gates of the drain select transistors DST configured in the plurality of strings are connected to a drain select line (DSL), and the gates of the source select transistors SST are connected to a source select line (SSL). Further, the control gates (CG) of each of the memory cells MC0 to MCn are connected to word lines WL0 to WLn.

[0056] The NAND flash memory device having the memory cell array configured as described above performs read and program operations in units of pages and performs an erase operation in units of blocks. Here, the page unit includes all the memory cells whose control gates are commonly connected to one word line.

[0057] Figure 3 is a view schematically showing the program operation and the erase operation of the NAND flash memory device.

[0058] Referring to Figure 3 , the program operation and the erase operation of the NAND flash memory device mean changing the state of the memory cell from '0' to '1' or from '1' to '0'.

[0059] As Figure 2 shown, a floating gate FG is located between the control gate CG and the P substrate. Here, the floating gate FG is insulated from the control gate CG or the P substrate by an oxide layer, whereby electrons therein are trapped. In this case, when electrons are in the floating gate FG, the threshold voltage Vt of the memory cell can be changed by affecting the electric field emitted from the control gate CG. That is, the threshold voltage Vt of the memory cell can be changed to a positive (+) value (+Vt) or a negative value (-Vt) based on 0V according to the number of electrons present in the floating gate FG.

[0060] When reading the information of a memory cell by applying a specific voltage to the control gate CG as described above, the threshold voltage Vt varies according to the number of electrons in the floating gate FG, whereby current flows or does not flow. Whether the read current flows or not can be interpreted as data '1' and '0'. In addition, a multi-level cell (MLC) device that stores one or more bits of information in a single memory cell reads the amount rather than simply determining the flow of current in order to measure the number of electrons stored in the floating FG.

[0061] Referring to Figure 3 (a) thereof, in the programming operation of a NAND flash memory device, a predetermined voltage (e.g., 19V) is applied to the control gate of the memory cell, such that electrons move in the direction of the floating gate 10. At this time, the state of the memory cell changes to the OFF TR state to have a positive (+) threshold voltage Vt.

[0062] That is, as shown in Figure 3 (a) thereof, when a predetermined voltage is applied to the control gate CG, electrons move to the floating gate 10, and the threshold voltage Vt of the corresponding memory cell can be increased to be greater than or equal to the reference threshold voltage RV by increasing the number of moving electrons. In addition, when the threshold voltage Vt of the memory cell increases to be greater than or equal to the reference threshold voltage RV, the state of the memory cell can change from '1' to '0'. Here, the reference threshold voltage RV can be set to various values according to the memory specifications, for example, it can be set to a specific value greater than 0V.

[0063] In addition, referring to Figure 3 (b) thereof, when a constant voltage (e.g., 20V) is applied from the P substrate during the erase operation of the NAND flash memory device, electrons in the floating gate 10 of the memory cell move downward through the F-N tunneling effect.

[0064] That is, as shown in Figure 3 (b) thereof, during the erase operation, the number of electrons in the floating gate decreases, and thus, the threshold voltage (Vt) of the corresponding memory cell may decrease. In addition, when the threshold voltage Vt of the memory cell decreases to be less than the reference threshold voltage RV, the state of the corresponding memory cell can change from '0' to '1'.

[0065] As described above, the programming operation and the erase operation of the NAND flash memory device can be divided based on the reference threshold voltage RV of the memory cell, which changes according to the amount of charge present in the floating gate 10, as shown in Figure 3As shown in (a) and (b) thereof. That is, when the threshold voltage Vt of the memory cell is equal to or greater than the reference threshold voltage RV, the NAND flash memory device recognizes it as '0' and performs a programming operation. In addition, when the threshold voltage Vt of the memory cell is less than the reference threshold voltage RV, the NAND flash memory device recognizes it as '1' and performs an erase operation.

[0066] However, when a power instability condition (e.g., momentary power interruption) occurs during the process of moving electrons according to the programming operation or erase operation as described above. That is, while the threshold voltage (Vt) of the memory cell increases from a negative (-) value to a positive (+) value according to the movement of electrons or as Figure 3 shown in (a) thereof, when the power is temporarily interrupted while the threshold voltage (Vt) of the memory cell decreases from a positive (+) value to a negative (-) value, the NAND flash memory device may not be able to accurately recognize whether a programming operation or an erase operation was being performed before the power was interrupted.

[0067] Figure 4 An embodiment is shown in which the erase operation of the NAND flash memory device is shown in the order of the time flow.

[0068] Referring to Figure 4 , the NAND flash memory device can perform an erase operation according to a control signal input from a controller (to be described later). The control signal can include a command signal and an address signal. Additionally, Figure 4 VCC in [[ ]] can refer to the power supply voltage, and VSS can refer to the ground voltage.

[0069] Therefore, Figure 4 The cycle type of [[ ]] indicates whether the data input in each cycle is a command or an address. For example, when the cycle type is a command, the data currently input through the data bus represents a command, and when the cycle type is an address, the data currently input through the data bus represents an address. Additionally, I / O[7:0] represents the data bus, and the ready (RDY) signal is a signal that notifies the controller whether the NAND flash memory device is ready or in use (e.g., an erase operation is in progress). At the first time when this signal reaches a low level, the NAND flash memory device notifies the controller that the erase operation is currently in progress, which is to notify the controller that the erase operation of the NAND flash memory device is currently in progress at tBERS when this signal becomes low. That is, the NAND flash memory device maintains the high state of the pin that sends the ready (RDY) signal among the multiple pins connected to the controller until it becomes a busy state for performing a specific operation, and can change to a low state at the time point when it reaches the busy state.

[0070] In this case, the erase operation of the NAND flash memory device as described above can be mainly divided into three sections. The first section is the time for transmitting commands and addresses to the NAND flash memory device, the second section is the time (tWB) required until the NAND flash memory device enters the busy state for performing a specific operation, and the third section is the time (tBERS) for erasing memory cells in units of blocks.

[0071] In addition, the NAND flash memory device as described above operates based on a power supply voltage (e.g., VCC). However, when the power supply voltage decreases to a level at which the NAND flash memory device cannot operate properly, intermittent data corruption occurs.

[0072] That is, when the input voltage decreases below a certain level while the NAND flash memory device is performing a programming operation or an erase operation, the NAND flash memory device stops operating and then resumes the programming operation or the erase operation when the normal voltage is input.

[0073] In this case, when a power reset (or power interruption) is performed during a programming operation or an erase operation as described above, different from volatile memories, non-volatile memories such as NAND flash memory devices generate charge gain. Here, charge gain refers to a state in which the threshold voltage Vt of a cell is in an edge region where '0' and '1' cannot be distinguished. Here, the edge region refers to a region where the threshold voltage Vt of a cell is between 0V and a reference threshold voltage RV. In this case, since the memory may perform incorrect operations, the reliability of the product is greatly reduced.

[0074] Figure 5 is a view showing charge gain in a NAND flash memory device. Referring to Figure 5 , the NAND flash memory device includes charge gain generated during a programming operation and charge gain generated during an erase operation.

[0075] As Figure 5 shown in (a) of, the NAND flash memory device can perform a programming operation according to a command from a controller. And, when power is cut off while electrons are moving due to a programming operation, the movement of electrons stops when the power is cut off. Here, the threshold voltage Vt of the memory cell may be in an edge region where '0' and '1' cannot be distinguished when the programming operation stops. And, when the threshold voltage Vt of the memory cell is in the edge region as described above, the controller (to be described later) cannot clearly determine whether the threshold voltage Vt of the memory cell is '0' or '1'. This may lead to system failures.

[0076] As Figure 5As shown in (b), the NAND flash memory device can perform an erase operation according to a command from the controller. Also, when power is cut off while electrons are moving due to the erase operation, the movement of the electrons stops when the power is cut off. Here, at the time point when the erase operation stops, the threshold voltage Vt of the memory cell may be in the marginal region where '0' and '1' cannot be distinguished. And when the threshold voltage Vt of the memory cell is in the marginal region as described above, the controller (to be described later) cannot clearly determine whether the threshold voltage Vt of the memory cell is '0' or '1'. This may cause a system failure.

[0077] Hereinafter, a NAND flash memory system according to an embodiment will be described.

[0078] Figure 6 is a block diagram showing elements of a NAND flash memory system according to a first embodiment.

[0079] Referring to Figure 6 , the system 100 includes a power supply device and a control device 200. The power supply device may include a converter 110, an input voltage detector 120, and a detection signal transmitter 130.

[0080] The converter 110 of the power supply device may receive an input voltage corresponding to the main power, convert the input voltage into a voltage required for each element of the control device 200, and output the converted voltage.

[0081] In addition, the input voltage detector 120 of the power supply may detect the voltage of the main power and output the detected signal.

[0082] In addition, the detection signal transmitter 130 of the power supply device may send the output signal of the input voltage detector 120 to the control device 200.

[0083] The control device 200 may include a storage device. The control device 200 may operate by using the voltage input from the power supply device as a driving voltage. The control device 200 may communicate with the vehicle controller 300 and store data sent from the vehicle controller 300. For example, the control device 200 may be provided in a vehicle to support the eCall function of the vehicle. That is, the control device 200 may communicate with the vehicle controller 300 to store information for reporting and requesting rescue in an emergency. For example, the information may include accident location information, vehicle type information, driving direction information, the number of seat belts used at the time of the accident, etc.

[0084] The control device 200 may include a memory 210, a power supply unit 220, an auxiliary power unit 230, and a controller 240. Additionally, the controller 240 of the control device 200 may control the memory 210. Preferably, the controller 240 may receive operation signals (e.g., ready output signal and busy output signal) from the memory 210 and access the memory 210 based on the received operation signals. The operation signals may correspond to the timing of the NAND flash memory devices constituting the memory 210. Here, the timing may be converted into different time periods according to the operation type of the device. For example, the different time periods for each operation type include a time tR (read operation) for loading data from a memory cell (not shown) into a page register (not shown), a time tPROG (programming operation) for loading data from the page register into the memory cell, a time tBERS (erase operation) for erasing the memory cells in units of blocks, etc.

[0085] Furthermore, the controller 240 of the control device 200 may control the access to the memory 210 based on an output signal that operates according to the input voltages sent from the power supply devices 110, 120, and 130.

[0086] Specifically, the controller 240 of the control device 200 may stop the operation of the memory based on the output signal of the input voltage detector 120 of the power supply devices sent from the power supply devices 110, 120, 130 in the case of an unstable condition of the input voltage of the memory 210 or a data protection condition. Here, stopping the operation of the memory 210 may mean stopping the access to the memory 210. In addition, it may mean preventing the output of commands for controlling the operation of the memory 210. That is, the controller 240 of the control device 200 detects an unstable condition of the input voltage or a data protection condition while the protection function of the memory 210 is turned on, and based on this, may stop the operation of the memory 210.

[0087] Hereinafter, the control device 200 and the power supply devices 110, 120, and 130 will be described in detail.

[0088] The power supply device may include a converter 110, an input voltage detector 120, and a detection signal transmitter 130. At this time, although each component of the power supply devices 110, 120, and 130 is shown in the figure as being separately configured from the control device 200, the embodiments are not limited thereto. That is, some elements constituting the power supply devices 110, 120, and 130 may be included in the control device 200.

[0089] The converter 110 may receive an input voltage and convert the input voltage to generate an output voltage.

[0090] The converter 110 may be implemented as a regulator. That is, the regulator may receive an input voltage through an input terminal and output an output voltage obtained by converting the input voltage through an output terminal. The voltage supplied to the control device 200 by the regulator may be a driving voltage for each element constituting the control device 200. For example, the voltage supplied to the control device 200 by the regulator may be the driving voltage of the memory 210. The regulator supplies a stable driving voltage to the control device 200 by stabilizing and outputting the input voltage, so that the memory 210 constituting the control device 200 operates stably.

[0091] Meanwhile, the input voltage input to the converter 110 may be supplied from a power supply unit (not shown). For example, the power supply unit may be a battery of a vehicle equipped with a NAND flash memory system.

[0092] The input voltage detector 120 may detect the level of the input voltage input through the power supply unit and output a voltage detection signal according to the detected level.

[0093] In this case, the input voltage may have a first level V1 under normal conditions.

[0094] In addition, when the input voltage has a level within a range between the first level V1 and a second level V2 less than the first level V1, the input voltage detector 120 may output a first voltage detection signal. In addition, when the level of the input voltage is less than the second level V2, the input voltage detector 120 may output a second voltage detection signal, and the second level V2 is less than the first level V1. Here, the first voltage detection signal may be a low-level detection signal, and the second voltage detection signal may be a high-level detection signal, but it is not limited thereto.

[0095] To this end, the input voltage detector 120 may include a comparator (not shown). The comparator may receive a reference signal corresponding to the second level V2 through a positive terminal, receive the input voltage through a negative terminal, and output a high-level voltage detection signal or a low-level voltage detection signal according to the comparison result between the input voltage and the reference signal.

[0096] Meanwhile, the input voltage detector 120 may adjust the detection voltage through a voltage dividing resistor or the like. The voltage dividing resistor divides the input voltage according to a predetermined voltage division ratio and sends it to the comparator.

[0097] The detection signal transmitter 130 may be connected to the control device 200, so that the voltage detection signal detected by the input voltage detector 120 may be sent to the control device 200. Specifically, the detection signal transmitter 130 may be connected to the controller 240 of the control device 200, and may send a high signal or a low signal to the controller 240 based on the voltage detection signal.

[0098] To this end, the detection signal transmitter 130 may include a first resistor to a third resistor R1, R2, and R3, and a transistor S1. The first resistor to the third resistor R1, R2, R3, and the transistor S1 may be a logic circuit that converts the high voltage of the voltage detection signal into a low voltage that can be received by the controller 240 of the control device 200 and outputs it. The detailed connection structure and its operation will be described below.

[0099] The first resistor R1 may have one end connected to the output terminal of the input voltage detector 120, and the other end connected to one end of the third resistor R3 and the base of the transistor S1.

[0100] The second resistor R2 may have one end connected to the power terminal of the power supply unit 220 of the control device 200, and the other end connected to the collector of the transistor S1 and the signal input terminal GPIO of the controller 240.

[0101] The third resistor R3 may have one end connected to the other end of the first resistor R1 and the base of the transistor S1, and the other end connected to the emitter of the transistor S1 and the ground terminal.

[0102] The transistor S1 may have a base connected to the output terminal of the input voltage detector 120 through the first resistor R1, a collector connected to the signal input terminal GPIO of the controller 240, and an emitter connected to the ground terminal.

[0103] The transistor S1 may receive the voltage detection signal of the input voltage detector 120 through the base.

[0104] Specifically, the transistor S1 may be turned on or off by the voltage detection signal of the input voltage detector 120 input to the base. For example, the voltage detection signal may be a high signal or a low signal as described above. In addition, when a high signal is applied to the base, the transistor S1 may be switched to the on state, so that a second detection signal indicating a voltage abnormality may be output to the collector. In addition, when a low signal is applied to the base, the transistor S1 may be switched to the off state, so that a first detection signal indicating a normal voltage, which is a high signal, may be output to the collector terminal. At the same time, in the embodiment, the transistor S1 is turned on by a high signal and turned off by a low signal, but the embodiment is not limited thereto, and its operation may be interchanged.

[0105] The memory 210 can be a non-volatile memory in which data can be programmed, erased, and read. For example, the memory 210 can be a non-volatile memory device that can be electrically programmed and erased and does not require a refresh function to rewrite data at a predetermined period. Specifically, the memory 210 can be a NAND-type flash memory device.

[0106] Since the memory 210 has been described in detail with reference to Figures 1 to 5 it, a detailed description thereof will be omitted here.

[0107] The power supply unit 220 is connected to the output terminal (out) of the converter 110 to receive the output voltage of the converter 110 and stabilize the received output voltage to apply a driving voltage to the memory 210. That is, the power supply unit 220 can be a power management IC (PMIC) that supplies a driving voltage to the memory 210. The PMIC constituting the power supply unit 220 can be a power control module, which is composed of a discrete power device module for power output, a high-voltage power circuit, a low-voltage digital circuit, and a high-low voltage analog circuit. Accordingly, the power control module can be used to convert, distribute, charge, and control the input voltage input to the control device 200 according to the memory 210.

[0108] The auxiliary power supply 230 can be provided between the power supply unit 220 and the memory 210. The auxiliary power unit 230 can be a capacitor that performs a charging operation in a first condition and a discharging operation in a second condition. Here, the first condition can be a condition in which a normal-range input voltage is input to the input terminal of the present system, and the second condition can be a condition in which a low voltage outside the normal range is input to the input terminal.

[0109] In a situation where the system is powered on, when the output voltage of the power supply unit 220 is lower than a preset second level V2, the auxiliary power unit 230 can supply a driving voltage to the memory 210 by discharging. At this time, the discharging time of the auxiliary power unit 230 is determined in proportion to the capacitance of the capacitor constituting the auxiliary power unit 230. Therefore, in an embodiment, the capacitance of the capacitor constituting the auxiliary power supply unit 230 can be determined in consideration of the time for loading data from the memory cells of the memory 210 to the page register, the time for loading data from the page register to the memory cells, and the time for erasing the memory cells in units of blocks.

[0110] The controller 240 can control the operation of the memory 210.

[0111] Specifically, the controller 240 can access the memory 210 to control the programming operation, erasing operation, and reading operation of the memory 210.

[0112] To this end, the controller 240 can be connected to the memory 210 via a bus. In addition, the controller 240 can send commands and addresses to the memory 210 via the bus, and can send and receive data.

[0113] Meanwhile, the controller 240 can monitor the output signal of the detection signal transmitter 130. That is, the controller 240 can monitor the change in the input voltage input to the system.

[0114] In addition, when a first detection signal notifying that the input voltage is normal is input via the detection signal transmitter 130, the controller 240 accesses the memory 210 to perform a programming operation or an erase operation.

[0115] At this time, when a second detection signal notifying an abnormality of the input voltage is input via the detection signal transmitter 130, the controller 240 blocks the output of commands to the memory 210 from the time point when the second detection signal is input.

[0116] In other words, when the second detection signal is input via the detection signal transmitter 130, the controller 240 blocks the output of commands to stop accessing the memory 210.

[0117] Then, the controller 240 ignores all commands related to the operation of the memory 210 from the time when the second detection signal is input, and blocks the output of commands to the memory 210 from the time point when the second detection signal is input.

[0118] In addition, the controller 240 and the memory 210 can be powered off after a predetermined time from the time point when the second detection signal is input. Here, the predetermined time can refer to the time until the operation (programming operation or erase operation) previously performed by the memory 210 is normally completed by the auxiliary power supplied by the auxiliary power supply unit 230.

[0119] When the input voltage of the main power of the system drops to a third level V3 corresponding to the power-off voltage of the memory 210, the power-off of the memory 210 can be performed. That is, when the input voltage of the main power drops to the third level V3, the memory 210 may be powered off naturally due to insufficient power.

[0120] In addition, even if the input voltage of the main power returns to the first level V1 without dropping to the third level V3, the memory 210 can be powered off. To this end, the vehicle controller 300 can turn off the power supply unit 220 of the control device 200 to turn off the control device 200. Thereafter, the vehicle controller 300 can turn on the power supply unit 220 again to power on the control device 200.

[0121] However, the memory 210 in the embodiment may be a NAND flash memory device corresponding to a non-volatile memory. In this case, different from the RAM which is a volatile memory, the data stored in the NAND flash memory device is not erased even when the input power is cut off. Therefore, the NAND flash memory device does not have to worry about internal data loss even when the input power is cut off, and thus does not require auxiliary power supply even when the power is suddenly cut off. However, different from the RAM, the NAND flash memory device distinguishes '0' and '1' by comparing the threshold voltage Vt of the memory cell with the edge region set based on the reference threshold voltage RV, as Figures 1 to 5 described in

[0122] Therefore, if the memory 210 is in the programming operation or the erasing operation when the second detection signal is input, and the power-off timing continues without completing the programming operation or the erasing operation, the programming operation or the erasing operation continues at a later power recovery time.

[0123] However, as described above, when the threshold voltage Vt of the memory cell has a value in the edge region (0V to the reference threshold voltage RV) at the time of power recovery, it is impossible to determine whether the value of the memory 210 is '0' or '1', so the controller 240 may malfunction. Therefore, when the time point of inputting the second detection signal is the programming operation time (tPROG) or the erasing operation time (tBERS) of the memory 210, the controller 240 can delay the power-off timing until the programming operation or the erasing operation is completed. In other words, the controller 240 can supply auxiliary power to prevent the memory 210 from being powered off until the programming operation or the erasing operation currently being executed by the memory 210 is completed.

[0124] In addition, the memory 210 can be driven by the discharge voltage of the auxiliary power supply 230 under the data protection condition of the memory 210 as described above to complete the programming operation or the erasing operation. In addition, when the programming operation or the erasing operation is completed, the memory 210 can send its completion signal to the controller 240.

[0125] The controller 240 can recognize that the operation of the memory 210 has been completed, and can continue the power-off timing of the memory 210.

[0126] The embodiment detects the unstable state of the input power and controls the operation of the NAND flash memory device based on this, so that defects such as data corruption that may occur when the NAND flash memory device operates in an unstable state of the input power can be prevented. Specifically, according to the embodiment, when the input power is unstable, the flash access is blocked, so that the NAND flash memory device can be prevented from malfunctioning in an environment with unstable input power.

[0127] In addition, in an embodiment, when an operation of a NAND flash memory device is in progress during power interruption detection, auxiliary power is supplied until the ongoing operation is completed. Accordingly, data corruption due to charge gain, which occurs when power is blocked during a programming operation or an erase operation of the NAND flash memory device, can be resolved. Accordingly, the operational reliability of the NAND flash memory device can be improved.

[0128] In addition, in an embodiment, when power interruption is detected, a power-off timing of the NAND flash memory device is executed, and when normal power is detected, a power-on timing is executed. Accordingly, since the flash memory operates normally when the input power is restored, operational reliability and user satisfaction can be improved.

[0129] Meanwhile, the Figure 6 auxiliary power unit 230 in has been described as being provided in the control device 200, but the auxiliary power unit 230 may be provided at a position other than between the power supply unit 220 and the memory 210 in the control device 200.

[0130] Figure 7 and Figure 8 are views for explaining Figure 6 a modified example of the NAND flash memory system shown in.

[0131] Meanwhile, only Figure 7 and Figure 8 differ in the arrangement position of the auxiliary power unit for supplying auxiliary power to the memory 210 when an abnormal input voltage occurs, and other features may be the same as those in Figure 6 . Accordingly, only the auxiliary power supply unit will be described below.

[0132] Referring to Figure 7 , the NAND flash memory system may include a converter 110, an input voltage detector 120, a detection signal transmitter 130, a memory 210, a power supply unit 220, and a controller 240. In addition, an auxiliary power unit 140 is provided between the output terminal of the converter 110 and the input terminal of the power supply unit 220. In addition, the auxiliary power unit 140 provides a discharge voltage to the power supply unit 220 when an abnormal input voltage occurs in the system, such that a driving voltage through the discharge voltage is transmitted to the memory 210.

[0133] In addition, referring to Figure 8, the NAND flash memory system may include a converter 110, an input voltage detector 120, a detection signal transmitter 130, a memory 210, a power supply unit 220, and a controller 240. In addition, an auxiliary power unit 150 is provided at an input terminal of the converter 110. Further, the auxiliary power unit 150 provides a discharge voltage to the converter 110 when an abnormal condition occurs in the input voltage of the system, so that a driving voltage can be transmitted to the memory 210 through the discharge voltage.

[0134] Figure 9 is a view for step - by - step explaining a method of operating a NAND flash memory system according to an exemplary embodiment.

[0135] Referring to Figure 9 , the controller 240 may access the memory 210 and send commands and addresses to the memory 210 in a situation where the input voltage is within a normal range. That is, the controller 240 sends commands to the memory 210 under normal conditions, so that at least one of a programming operation, an erase operation (or delete operation), and a read operation of the memory 210 can be performed (S100).

[0136] Thereafter, the controller 240 may check a voltage detection signal input through a signal input terminal GPIO in a polling or interrupt method. In addition, the controller 240 may determine whether a second detection signal is received, where the second detection signal indicates that an input voltage lower than a second level V2 is detected through the signal input terminal GPIO (S110).

[0137] In addition, when the second detection signal indicating that an input voltage lower than the second level V2 is detected is received, the controller 240 stops accessing the memory 210 and blocks the output of commands provided to the memory 210 (S120).

[0138] Figure 10 and Figure 11 is a view showing a power timing according to a change in the input voltage.

[0139] Referring to Figure 10 , the input voltage may have a first level V1 under normal conditions. In addition, when the input voltage drops to a second level V2, the input voltage detector 120 and the detection signal transmitter 130 may output a voltage abnormality detection signal.

[0140] Therefore, the controller 240 may stop accessing the memory 210 (ACCESS STOP) at a first time point T1 when the voltage abnormality detection signal is received.

[0141] Thereafter, the level of the input voltage may continue to decrease to a third level V3. In addition, when the input voltage decreases to the third level V3, the memory 210 may be powered off due to insufficient power.

[0142] Meanwhile, as Figure 10 shown, the power input to the system may be temporarily cut off, and the level of the input voltage may decrease to 0V.

[0143] However, in contrast, the power input to the system can be restored to the normal voltage level after being temporarily cut off.

[0144] That is, referring to Figure 11 , the input voltage can have a first level V1 under normal conditions. In addition, when the input voltage decreases to a second level V2, the input voltage detector 120 and the detection signal transmitter 130 can output a voltage abnormality detection signal.

[0145] Therefore, the controller 240 can stop accessing the memory 210 (ACCESS STOP) at the first time point T1 when receiving the voltage abnormality detection signal.

[0146] Thereafter, the input voltage can rise back to its normal level at a second time point T2.

[0147] At this time, even when the input voltage returns to the first level V1, the controller 240 cannot normally control the memory 210 because the access stop operation has been executed as described above. Therefore, the vehicle controller 300 turns off the power supply unit 220 to power off the control device 200. To this end, the vehicle controller 300 can include an input voltage detector for detecting the input voltage of the main power (see Figure 6 ). Alternatively, the vehicle controller 300 can be connected to the input voltage detector 120 to monitor the input state of the main power. In addition, the vehicle controller 300 can turn off the power supply unit 220 based on the input state of the main power.

[0148] And, when the input voltage maintains the first level V1 from a third time point T3 to a fourth time point T4 after a predetermined time, the vehicle controller 300 controls the power supply unit 220 to energize the power supply unit 220 so as to energize the control device 200.

[0149] Figure 12 and Figure 13 are flowcharts for step - by - step illustrating the method of controlling a NAND flash memory system according to an embodiment.

[0150] Referring to Figure 12, according to an embodiment, in a situation where the input voltage is within the normal range in the power supply timing of the NAND flash memory system, the controller 240 accesses the memory 210 and provides commands and addresses to the memory 210. That is, the controller 240 sends commands to the memory 210 under normal conditions, enabling at least one of the programming operation, erasure operation (or deletion operation), and read operation of the memory 210 to be performed (S200).

[0151] Thereafter, the controller 240 determines whether the input voltage is less than the second level (V2) based on the voltage detection signal (S210).

[0152] Then, when the input voltage drops below the second level V2, the controller 240 stops accessing the memory 210 (S220).

[0153] Thereafter, the input voltage can drop below the third level V3, which is less than the second level V2, or the input voltage can recover from the second level V2 to the first level V1 (S230, S250).

[0154] In addition, when the input voltage drops to the third level V3, the memory 210 may be powered off due to insufficient power.

[0155] In addition, when the input voltage recovers from the second level V2 to the first level V1, the control device 200 can perform a reset operation (S260 and S270). Specifically, the vehicle controller 300 can power off the control device 200 by turning off the power supply 220 of the control device 200 to perform a reset operation on the control device 200 (S260). Thereafter, the vehicle controller 300 can turn on the power supply unit 220 again to power on the control device 200 (S270).

[0156] Meanwhile, referring to Figure 13 , according to an embodiment, in a situation where the input voltage is within the normal range in the power supply timing of the NAND flash memory system, the controller 240 accesses the memory 210 and provides commands and addresses to the memory 210. That is, the controller 240 sends commands to the memory 210 under normal conditions, enabling at least one of the programming operation, erasure operation (or deletion operation), and read operation of the memory 210 to be performed (S200).

[0157] Thereafter, the controller 240 determines whether the data protection status of the memory 210 is detected (S310). That is, the controller 240 can determine whether the input voltage has dropped below the second level V2, which is lower than the first level V1.

[0158] Further, when the input voltage drops below a second level (V2), which is lower than the first level V1, the controller 240 ignores the input command and prevents the command from being sent to the memory 210 (S320).

[0159] In addition, the auxiliary power supply unit 230 supplies auxiliary power to the memory 210 so that operations (programming operations or erasing operations) performed in the memory 210 before the detection of the protection condition can be completed normally (S330).

[0160] Thereafter, the control device 200 can be powered off (S340). That is, when the input voltage continues to drop to a third level V3, the control device 200 can be powered off naturally due to insufficient power. On the other hand, when the input voltage returns to the first level V1 again, the vehicle controller 300 can reset the control device 200 by turning off the power supply unit 220 of the control device 200 and then turning on the power supply unit 220 again.

[0161] As described above, in the embodiment, when a power interruption is detected, the controller 240 executes a memory protection function. Here, the power interruption may occur due to the disconnection of the battery. And when the input voltage changes due to the separation of the battery as described above, the embodiment can execute the memory protection function as described above. However, even when the vehicle is started, an instantaneous change in the input voltage may occur. And in the embodiment, when the memory protection function is executed by recognizing the vehicle start-up condition as an unstable condition of the input voltage of the memory 210 or a data protection condition, the life of the memory 210 may be reduced.

[0162] That is, the life of the memory 210 may be reduced in proportion to the number of programming operations and read operations. For example, the performance of the memory 210 may deteriorate in proportion to the number of programming operations and read operations. And generally, when the memory is turned on or off, the programming operations or read operations are performed the most. In this case, when the memory protection function as described above is run when the vehicle is started, the frequency of turning on or off the memory increases, so there is a problem of deterioration of the performance of the memory.

[0163] Therefore, in the embodiment, the memory protection function as described above is not run when the vehicle is started. In other words, the unstable condition of the input voltage of the memory or the data protection condition does not include the input change condition that occurs when the vehicle is started. In the embodiment, the memory protection function as described above is not executed when the vehicle is started, so as to minimize the risk of memory deterioration.

[0164] Generally, the battery is not removed or replaced while the ACC is on. Additionally, in an embodiment, when the battery is removed or replaced, an unstable input voltage condition or a data protection condition of the memory may be detected. In such a case, vehicle startup is typically performed while the ACC is on. Thus, in an embodiment, the battery protection function is turned off while the ACC is on.

[0165] Figure 14 is a view showing the change in the input voltage when the vehicle starts.

[0166] Referring to Figure 14 , when the vehicle starts, ACC turn - on is performed at the first time point T1. In this case, the input voltage can be the above - mentioned first level V1. Additionally, the startup operation can be performed at the second time point T2 while the ACC is on. In this case, the input voltage can decrease based on the second time point T2 and can decrease to a second level V2 that is less than the first level V1 at the third time point T3. In this case, in an embodiment, when the input voltage decreases to the second level V2, the memory protection function operates. However, as described above, the change in the input voltage when the ACC is on is for starting the engine. Thus, in an embodiment, the change in the input voltage in the ACC - on state is ignored. For example, in an embodiment, the memory protection function can operate while the ACC is off.

[0167] Figure 15 is a flowchart for step - by - step explaining a method of activating the memory protection function according to an embodiment. Referring to Figure 15 , according to an embodiment, the controller 240 can detect the power state of the vehicle. That is, the controller 240 can detect whether the power state of the vehicle is the ACC - on state or the ACC - off state. Then, when the power state of the vehicle is the ACC - on state (S410), the controller 240 turns off the memory protection function (S420). In other words, in an embodiment, when the power state of the vehicle is the ACC - on state (or the ignition - on state), the controller 240 turns off the memory protection function. Thus, the controller 240 ignores the change in the input voltage that occurs when the startup operation is performed in the ACC - on state.

[0168] Subsequently, the controller 240 can determine whether the power state of the vehicle has changed to the ACC - off state (S430). That is, the controller 240 can determine whether the ignition device of the vehicle is turned off.

[0169] In addition, when the power state of the vehicle changes to the ACC off state, the controller 240 determines whether a predetermined time has elapsed since the change from ACC to the ACC off state (S440). For example, the controller 240 may determine whether one second has elapsed since the power state of the vehicle changed to ACC off.

[0170] And, if the predetermined time has not elapsed, the controller 240 may wait for the predetermined time (S450).

[0171] Furthermore, if the predetermined time has passed, the controller 240 turns on the memory protection function to operate the memory protection function according to the change in the input voltage (S460).

[0172] In other words, in the embodiment, referring to Figure 9 、 Figure 12 and Figure 13 the memory protection function described can be selectively operated only when the power state of the vehicle is the ACC off state.

[0173] Therefore, even when the input voltage changes when the vehicle is started, the embodiment can prevent the memory from being turned on or off, thereby increasing the lifespan of the memory.

[0174] On the other hand, in the present embodiment, for whether data corruption occurs before applying the function of the present embodiment to the NAND flash memory device of the same product and whether a failure occurs after applying the function of the present embodiment, a reliability test of the function is performed by selecting samples.

[0175] This is for (1) testing whether a failure occurs by turning off the main power during the programming operation or erase operation of the product before applying the function of the present embodiment, and (2) after applying the function of the present embodiment to the same product, performing the same test to verify the effectiveness of the function of the present embodiment.

[0176] Therefore, in the case of Sample 1, it was confirmed that two failures occurred when 1500 power-on / power-off operations were performed and when 2900 power-on / power-off operations were performed before applying the function of the present embodiment. However, it was confirmed that after applying the function of the present embodiment to Sample 1, no failure occurred even when the power-on / power-off operation was repeated 60,000 times or more.

[0177] In addition, in the case of Sample 2, three failures occurred at the time point of approximately 90 power-on / power-off operations, at the time point of approximately 250 operations, and at the time point of approximately 1110 power-on / power-off operations before the function of this embodiment was applied. However, it was confirmed that no failure occurred even when the power-on / power-off operation was repeated 60,000 times or more after the function of this embodiment was applied to Sample 2.

[0178] In addition, in the case of Sample 3, one failure occurred when approximately 370 power-on / power-off operations were performed before the function of this embodiment was applied. However, it was confirmed that no failure occurred even when the power-on / power-off operation was repeated 60,000 times or more after the function of this embodiment was applied to Sample 3.

[0179] The embodiment detects an unstable state of the input power and controls the operation of the NAND flash memory device based on this. Therefore, defects such as data corruption that may occur when the NAND flash memory device operates in an unstable state of the input power can be prevented. Specifically, according to the embodiment, when the input power is unstable, flash access is blocked. Therefore, the NAND flash memory device can be prevented from failing in an environment where the input power is unstable.

[0180] In addition, in the embodiment, when the operation of the NAND flash memory device is in progress when a power interruption is detected, auxiliary power is supplied until the ongoing operation is completed. Therefore, data corruption caused by charge gain that occurs when the power is interrupted during the programming operation or erasing operation of the NAND flash memory device can be solved. Therefore, the operation reliability of the NAND flash memory device can be improved.

[0181] In addition, in the embodiment, when a power interruption is detected, the power-off timing of the NAND flash memory device is executed, and when normal power is detected, the power-on timing is executed. Accordingly, since the flash memory operates normally when the input power is restored, the operation reliability and user satisfaction can be improved.

Claims

1. A control device for a NAND flash memory device, comprising: a NAND flash memory; a controller configured to generate command signals to program, read, and erase data in the NAND flash memory when the voltage level of a power supply is a first level; and an auxiliary power circuit configured to maintain power for operating the memory and the controller during a first time period starting from a first time point when the voltage level of the power supply changes to be less than or equal to a second level, wherein the second level is less than the first level, wherein the controller is configured to block the command signals during the first time period, wherein starting from a second time point after the first time period has elapsed, regardless of the voltage level of the power supply, power supplied to the memory is blocked for at least a second time period, and wherein before the second time period has elapsed since the second time point, when the voltage level of the power supply maintains the first level, the controller blocks power supply to the NAND flash memory.

2. The control device according to claim 1, wherein when the first time point is the programming operation time (tPROG) or the erase operation time (tBERS) of the memory, the auxiliary power circuit supplies auxiliary power to complete the programming operation or the erase operation of the memory.

3. The control device according to claim 2, wherein when the first time point is in an electrical migration based on the programming operation time (tPROG) or the erase operation time (tBERS) of the memory, the auxiliary power circuit is configured to supply auxiliary power for completing the programming operation or the erase operation of the memory.

4. The control device according to claim 1, wherein the first time period is the time until completion of the programming operation or the erase operation performed in the memory before the first time point.

5. The control device according to claim 1, further comprising: a power management IC PMIC connected to the power supply and supplying power to the memory and the controller.

6. The control device according to claim 5, wherein the auxiliary power circuit is provided between the PMIC and the memory.

7. The control device according to claim 5, wherein the controller is configured to control the PMIC such that after the power supply is blocked for at least the second time period, power is supplied to the memory.

8. The control device according to claim 5, further comprising: an input voltage detector configured to detect the voltage level of the power supply, and wherein the auxiliary power circuit is connected to the power input terminal of the PMIC.

9. The control device according to claim 8, wherein the input voltage detector is configured to detect the voltage level at the input terminal of the auxiliary power circuit.

10. The control device according to claim 8, further comprising: a detection signal transmitter configured to transmit the voltage level detected by the input voltage detector to the controller.

11. The control device according to claim 10, wherein The detection signal transmitter includes a first resistor, a second resistor, a third resistor, and a transistor.

12. The control device according to claim 11, wherein, one end of the first resistor is connected to the output terminal of the input voltage detector, wherein, the other end of the first resistor is connected to one end of the third resistor and the base of the transistor, wherein, one end of the second resistor is connected to the power terminal of the power supply, wherein, the other end of the second resistor is connected to the collector of the transistor and the signal input terminal of the controller, wherein, one end of the third resistor is connected to the one end of the first resistor and the base of the transistor; and wherein, the other end of the third resistor is connected to the emitter of the transistor and the ground terminal.

13. The control device according to claim 5, further comprising: a regulator disposed between the power supply and the PMIC; wherein, the auxiliary power circuit is disposed between the regulator and the PMIC.

14. The control device according to claim 1, wherein, the controller is configured to ignore the voltage change of the power supply in the ACC on state.

15. The control device according to claim 1, wherein, when starting from a third time point after the second time period, the voltage level of the power supply is greater than or equal to the first level for a third time period, the controller is configured to supply power to the memory.

16. The control device according to claim 1, wherein, when the voltage of the power supply is restored to the first level while the power is held, the controller is configured to reset the memory.

17. The control device according to claim 1, wherein, when a predetermined time has elapsed since the time point when ACC off is detected, the controller is configured to run a memory protection function based on the voltage change of the power supply.

18. A method for controlling a NAND flash memory device, comprising: detecting the voltage level of a power supply; generating a command signal to program, read, and erase data in the NAND flash memory when the voltage level of the power supply is at a first level; stopping access to the memory when the detected voltage level is less than or equal to a second level, wherein the second level is less than the first level; supplying auxiliary power to the memory and the controller for a first time period starting from a first time point when the detected voltage level becomes less than or equal to the second level; and starting from a second time point after the first time period has elapsed, blocking the power supplied to the memory for at least a second time period regardless of the voltage level of the power supply, wherein, stopping access includes: blocking the command signal for controlling the memory, and wherein, before the second time period has elapsed since the second time point, when the voltage level of the power supply remains at the first level, blocking the power supply to the NAND flash memory.

19. The method according to claim 18, wherein, the supplying of the auxiliary power includes: When the first time point is the programming operation time (tPROG) or the erasing operation time (tBERS) of the memory, auxiliary power is supplied to complete the programming operation or the erasing operation of the memory.

20. The method according to claim 19, wherein, the first time period is the time until the programming operation or the erasing operation performed in the memory before the first time point is completed.

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