Envelope tracking system with fast transition time for radio frequency (RF) amplifiers

Abstract

An envelope tracking system includes an envelope signal generator; a power modulator coupled to the envelope signal generator, the power modulator including a switching regulator path configured to provide an output voltage at an output node to a power amplifier when in an average power tracking (APT) mode, the switching regulator path configured to operate with a linear path to provide the output voltage at the output node to the power amplifier when in an envelope tracking (ET) mode; a capacitor having a first terminal and a second terminal, the first terminal coupled to ground; a switch coupled between the output node and the second terminal of the capacitor, the switch configured to selectively disconnect the capacitor from the output node; and a circuit coupled between the output node and the second terminal of the capacitor, the circuit including a bidirectional current limiting switch, the circuit configured to charge or discharge the capacitor such that a voltage across the capacitor changes from a first voltage to a second voltage.

Description

[0001] Related applications

[0002] This application claims priority and benefit to U.S. Provisional Patent Application No. 62 / 950,662, filed December 19, 2019, entitled “ENVELOPE TRACKING SYSTEMHAVING FAST TRANSITION TIME FOR A RADIO FREQUENCY (RF) AMPLIFIER Transformation,” the contents of which are incorporated herein by reference in their entirety, as fully set forth below and used for all applicable purposes. Technical Field

[0003] This disclosure generally relates to electronic devices, and more specifically to control circuitry for power amplifiers. Background Technology

[0004] In radio frequency (RF) transceivers, communication signals are typically amplified and transmitted by a transmission segment. The transmission segment may include one or more circuits that amplify and transmit the communication signals. One or more amplifier circuits may include one or more amplifier paths with one or more stages, which may include one or more driver stages, one or more power amplifier stages, and one or more impedance matching circuits. Typically, one or more amplifier circuits may be required to provide different levels of power amplification over a wide bandwidth, while attempting to provide efficiency and linearity for a variety of different transmitted signals.

[0005] Power amplifier (PA) output is typically controlled based on several different factors, and in some cases, by a tracking power supply that supplies the power amplifier with a voltage dependent on the PA output power. The tracking power supply can be implemented as an APT (Average Power Tracking) power modulator only, where the power amplifier is supplied with a fixed voltage related to the average power amplifier output power, or as an ET (Envelope Tracking) power modulator, which adds the ability to supply the power amplifier with a voltage related to the instantaneous power amplifier output power. Many ET power modulators operate at high power amplifier output power in either ET or APT mode and at low power amplifier output power in APT mode. In some instances, the time allowed to transition from one APT power level to another may be very short, approximately one (1) microsecond (μs) or less. When power transition times are required to be close to one (1) μs, conventional APT and ET power modulators may struggle to achieve the desired output voltage within the allowed time. Summary of the Invention

[0006] Various embodiments of the systems, methods, and apparatuses within the scope of the appended claims have multiple aspects, none of which individually governs the desired properties described herein. Without limiting the scope of the appended claims, some notable features are described herein.

[0007] Details of one or more embodiments of the subject matter described in this specification are set forth in the following drawings and description. Other features, aspects, and advantages will become apparent from the description, drawings, and claims. Note that the relative dimensions in the following drawings may not be drawn to scale.

[0008] One aspect of this disclosure provides an envelope tracking system, comprising: an envelope signal generator; a power modulator coupled to the envelope signal generator, the power modulator including a switching regulator path configured to provide an output voltage at an output node to a power amplifier in average power point tracking (APT) mode, the switching regulator path being configured to operate in conjunction with a linear path in envelope tracking (ET) mode to provide an output voltage at an output node to the power amplifier; a capacitor having a first terminal and a second terminal, the first terminal being coupled to ground; a switch coupled between the output node and the second terminal of the capacitor, the switch being configured to selectively disconnect the capacitor from the output node; and a circuit coupled between the output node and the second terminal of the capacitor, the circuit including a bidirectional current-limiting switch configured to charge or discharge the capacitor such that the voltage on the capacitor changes from a first voltage to a second voltage.

[0009] Another aspect of this disclosure provides a method for communication, comprising: supplying a first voltage to a power amplifier using a switching regulator path, and supplying the first voltage to the power amplifier using a linear path when switching from the first voltage to a second voltage in a first mode, or when switching from the first mode to the second mode, while the switching regulator path is decoupled from an output capacitor.

[0010] Another aspect of this disclosure provides an envelope tracking system, comprising: an envelope signal generator; a power modulator coupled to the envelope signal generator, the power modulator including a switching regulator path configured to provide an output voltage to a power amplifier in average power tracking (APT) mode, the switching regulator path being configured to operate together with a linear path to provide an output voltage to the power amplifier in envelope tracking (ET) mode; a circuit system configured to activate elements associated with the ET mode at least in part based on MIPI triggers before symbol boundaries; and a switch configured to disconnect an output capacitor to be charged to a first output voltage (APT) from the power modulator while providing the output voltage to the power amplifier in ET mode.

[0011] Another aspect of this disclosure provides a method for communication, comprising: providing a first voltage in a first mode to a power amplifier using a linear path; providing a second voltage to the power amplifier using the linear path when switching from the first voltage to a second voltage in a second mode, while a switching regulator path is decoupled from an output capacitor and the switching regulator path charges the output capacitor to the second voltage; and when the output capacitor is charged to the second voltage, deactivating the linear path and coupling the switching regulator path to the output capacitor such that the switching regulator path provides the second voltage in the second mode. Attached Figure Description

[0012] In the accompanying drawings, unless otherwise indicated, the same reference numerals refer to the same parts in various views. For reference numerals designated with letter characters such as "102a" or "102b", the letter character designation distinguishes two identical parts or elements present in the same drawing. When the reference numerals are intended to cover all parts with the same reference numeral in all drawings, the letter character designation of the reference numerals may be omitted.

[0013] Figure 1 This is a diagram showing a wireless device communicating with a wireless communication system.

[0014] Figure 2 This is a block diagram illustrating a wireless device in which exemplary technologies of the present disclosure may be implemented.

[0015] Figure 3 It's a diagram. Figure 2 A schematic diagram of an exemplary embodiment of the power modulator.

[0016] Figure 4 It's illustrated in more detail. Figure 3 A schematic diagram of an exemplary embodiment of the power modulator.

[0017] Figure 5 It shows the description Figure 2 A timeline diagram of an exemplary embodiment of the operation of the envelope tracking system.

[0018] Figure 6 It shows the description Figure 2 A timeline diagram of an exemplary embodiment of the operation of the envelope tracking system.

[0019] Figure 7 It shows Figure 3 and Figure 4 A schematic diagram of an exemplary embodiment of the charging circuit.

[0020] Figure 8 It shows Figure 7 A schematic diagram of an exemplary embodiment of the charging circuit.

[0021] Figure 9 This is a flowchart describing the operation of an exemplary embodiment of an envelope tracking system according to an exemplary embodiment of the present disclosure.

[0022] Figure 10 This is a flowchart describing the operation of an exemplary embodiment of an envelope tracking system according to an exemplary embodiment of the present disclosure.

[0023] Figure 11 This is a functional block diagram of an apparatus for an envelope tracking system according to exemplary embodiments of the present disclosure.

[0024] Figure 12 This is a functional block diagram of an apparatus for an envelope tracking system according to exemplary embodiments of the present disclosure. Detailed Implementation

[0025] The word “exemplary” is used in this document to mean “serving as an example, instance, or illustration.” Any aspect described herein as “exemplary” should not be construed as preferred or advantageous over other aspects.

[0026] Exemplary embodiments of this disclosure relate to an envelope tracking system with a fast transition time of a radio frequency (RF) power amplifier. In an exemplary embodiment, the envelope tracking system can be configured to allow a power transition time of approximately one (1) μs, which may include power transition times less than one (1) μs or greater than one μs. For example, power transition times from less than one (1) μs to 1.5 μs, 2 μs, or between one (1) μs and ten (10) μs can be considered. In an exemplary embodiment, the envelope tracking system described herein can be implemented in new radio (NR) or 5G communication systems.

[0027] With the development of portable communication systems, the market continues to demand higher output power from amplifiers, particularly power amplifiers, and faster transition times from one power level to another. For example, in 5G communication systems, power transitions may occur symbol by symbol, thus requiring power level transitions to be completed in less than one (1) μs in some cases. Conventional envelope tracking systems typically employ a switching regulator path and a linear path. In APT operating mode, the switching regulator path is configured to provide the power amplifier with an average power tracking (APT) output voltage. Due to the time required for the switching regulator to charge / discharge the large-value output capacitor to the desired voltage, the switching regulator path in such conventional systems typically requires approximately 10 μs to transition between the voltages required for different PA output powers. The switching regulator path operates efficiently but may have low bandwidth and / or slow settling times.

[0028] In envelope tracking (ET) operating mode, a linear path is used in conjunction with a switching regulator path to provide the power amplifier with a supply voltage that has a higher bandwidth and a faster settling time than the switching regulator path. In ET operating mode, most of the output power (at DC and low frequencies) is typically provided by the efficient switching regulator path, while high-frequency energy is typically provided by the less efficient linear path. The power conversion efficiency of the power modulator may be higher in APT mode than in ET mode, but the output voltage settling time may be lower in ET mode than in APT mode. However, in ET mode, the PA is generally more efficient at high output power than in APT mode; therefore, by using ET mode at high PA output power and APT mode at low PA output power, the overall battery current can generally be reduced.

[0029] Due to the output capacitor charging time limitation, conventional APT power modulators or ET power modulators operating in APT mode may only achieve an APT-to-APT mode output voltage transition settling time of approximately 10 μs. In the embodiments described herein, this limitation can be mitigated by switching the power modulator from APT mode to ET mode during the output capacitor charging / discharging period, and then switching back to APT mode after the output capacitor has stabilized at the desired voltage. The power modulator output voltage can then stabilize to the desired voltage much faster, for example, within one (1) μs. The impact on power modulator efficiency can only be reduced by switching to ET mode during the output capacitor charging / discharging period (which may be approximately, for example, <10 μs).

[0030] Figure 1 This diagram illustrates communication between wireless device 110 and wireless communication system 120. Wireless communication system 120 can be a Long Term Evolution (LTE) system, a Code Division Multiple Access (CDMA) system, a Global System for Mobile Communications (GSM) system, a Wireless Local Area Network (WLAN) system, a 5G system, or some other wireless system. The CDMA system can implement Wideband CDMA (WCDMA), CDMA 1X, Evolved Data Optimized (EVDO), Time Division Synchronous CDMA (TD-SCDMA), or some other version of CDMA. For simplicity, Figure 1 A wireless communication system 120 is shown, comprising two base stations 130 and 132 and a system controller 140. Typically, a wireless communication system may include any number of base stations and any collection of network entities.

[0031] Wireless device 110 may also be referred to as user equipment (UE), mobile station, terminal, access terminal, subscriber unit, station, etc. Wireless device 110 may be a cellular phone, smartphone, tablet computer, wireless modem, personal digital assistant (PDA), handheld device, laptop computer, smartbook, netbook, tablet computer, cordless phone, medical device, drone, vehicle, wearable device, device configured to connect to one or more other devices (e.g., via the Internet of Things), wireless local loop (WLL) station, Bluetooth device, etc. Wireless device 110 can communicate with wireless communication system 120. Wireless device 110 can also receive signals from broadcast stations (e.g., broadcast station 134), signals from one or more satellites in a Global Navigation Satellite System (GNSS) (e.g., satellite 150), etc. Wireless device 110 may support one or more radio technologies for wireless communication, such as LTE, WCDMA, CDMA 1X, EVDO, TD-SCDMA, GSM, 802.11, 5G, etc.

[0032] Wireless device 110 may support carrier aggregation, such as that described in one or more LTE or 5G standards. In some embodiments, a single data stream is transmitted on multiple carriers using carrier aggregation, as opposed to separate carriers used for the respective data stream. Wireless device 110 may be able to operate in a wide range of communication bands over a broad frequency range, including those used by, for example, LTE, WiFi, 5G, or other communication bands.

[0033] Carrier aggregation (CA) can generally be classified into two types: intra-band CA and inter-band CA. Intra-band CA refers to operation on multiple carriers within the same frequency band. Inter-band CA refers to operation on multiple carriers in different frequency bands.

[0034] Figure 2 This is a block diagram illustrating a wireless device 200 in which exemplary technologies of this disclosure may be implemented. For example, the wireless device 200 may be... Figure 1 The illustrated embodiment of wireless device 110. In some embodiments, wireless device 200 may be an embodiment of base station 130 or 132, or the transmission portion of wireless device 200 may be implemented in broadcast station 134.

[0035] Figure 2 An example of a transceiver 220 with a transmitter 230 and a receiver 250 is shown. Typically, signal conditioning in the transmitter 230 and receiver 250 can be performed by one or more stages of amplifiers, filters, up-converters, down-converters, etc. These circuit blocks can be used with... Figure 2 The configurations shown are arranged differently. Furthermore, Figure 2Other circuit blocks, not shown, can also be used to regulate the signals in transmitter 230 and receiver 250. Unless otherwise stated, Figure 2 Any signal in any of the other figures in the accompanying drawings may be single-ended or differential. Figure 2 Some circuit blocks can also be omitted.

[0036] exist Figure 2 In the example shown, wireless device 200 typically includes a transceiver 220 and a data processor 210. Data processor 210 may include memory (not shown) for storing data and program code, and typically includes analog and / or digital processing elements. Transceiver 220 includes a transmitter 230 and a receiver 250 supporting bidirectional communication. Typically, wireless device 200 may include any number of transmitters and / or receivers for any number of communication systems and frequency bands. All or part of transceiver 220 may be implemented on one or more analog integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc.

[0037] Transmitters or receivers can be implemented using either superheterodyne or direct conversion architectures. In a superheterodyne architecture, the signal undergoes frequency conversion in multiple stages between radio frequency (RF) and baseband, for example, from RF to intermediate frequency (IF) in one stage, and then from IF to baseband in another stage at the receiver. In a direct conversion architecture, the signal undergoes frequency conversion between RF and baseband in a single stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. Figure 2 In the example shown, transmitter 230 and receiver 250 are implemented using a direct conversion architecture.

[0038] In the transmission path, data processor 210 processes the data to be transmitted and provides in-phase (I) and quadrature (Q) analog output signals to transmitter 230. In an exemplary embodiment, data processor 210 includes digital-to-analog converters (DACs) 214a and 214b for converting digital signals generated by data processor 210 into I and Q analog output signals, such as I and Q output currents, for further processing. In other embodiments, DACs 214a and 214b are included in transceiver 220, and data processor 210 provides data (e.g., for I and Q) digitally to transceiver 220.

[0039] Within transmitter 230, low-pass filters 232a and 232b filter the I and Q analog output signals, respectively, to remove unwanted images caused by the previous digital-to-analog conversion. Amplifiers (Amps) 234a and 234b amplify the signals from low-pass filters 232a and 232b, respectively, and provide I and Q baseband signals. Up-converter 240 up-converts the I and Q baseband signals using the I and Q transmission (TX) local oscillator (LO) signals from TX LO signal generator 290, and provides up-converted signals. Filter 242 filters the up-converted signal to remove unwanted images caused by frequency up-conversion and to receive noise in the frequency band. Power amplifier (PA) 244 amplifies the signal from filter 242 to obtain the desired output power level and provides the transmitted RF signal. The transmitted RF signal is routed via duplexer or switch 256 and transmitted via antenna 257. Although the examples discussed herein use I and Q signals, those skilled in the art will understand that the transceiver components can be configured to use polarization modulation.

[0040] In an exemplary embodiment, the wireless device 200 may include an envelope tracking system 243. The envelope tracking system 243 is illustratively shown as having components, elements, circuitry, and other functionalities that may be located in the data processor 210 and the transmitter 230. In an exemplary embodiment, the envelope tracking system 243 may include an envelope signal generator 245 (shown in the data processor 210 for illustrative purposes) and a power modulator 246 (shown in the transmitter 230 for illustrative purposes). In an exemplary embodiment, as... Figure 2 As shown, the envelope tracking system 243 may include some or all of the components in the transmitter 230.

[0041] In an exemplary embodiment, envelope signal generator 245 may include elements that can be configured to generate a signal on connection 253 representing a power level to be supplied to power amplifier 244. The signal generated by envelope signal generator 245 may be a voltage signal or a current signal, depending on the implementation. In an exemplary embodiment, envelope signal generator 245 may include a delay / alignment function 247, envelope shaping element 248, envelope detection element 249, and envelope tracking (ET) DAC 251. Envelope detection element 249 determines the amplitude of the RF signal from the I and Q signals. Envelope shaping element 248 applies a nonlinear function to the raw output of envelope detection element 249 to prevent the processed envelope signal on connection 253 from falling below a specified minimum voltage (typically on the order of 1V) or a specified minimum current. In some exemplary embodiments, ET DAC 251 provides an analog representation as a signal on connection 253 (e.g., as a differential voltage) of the digital envelope voltage generated by envelope detection element 249 and envelope shaping element 248. The delay / alignment element 247 adjusts the relative delay between the RF path signal and the envelope path signal to ensure that the RF signal at PA 244 and the voltage output at connection 255 of the power modulator 246 are precisely aligned in time.

[0042] In an exemplary embodiment, and as will be described below, the power modulator 246 may include a switching regulator path, a linear path, and associated circuitry configured to receive signals on connection 253 and provide a power supply voltage corresponding to a target output power to PA 244 via connection 255.

[0043] In some embodiments, the power modulator 246 may be implemented in a chip including a microcontroller; the chip may be mounted on a PCB, on which other transmitter 230 components or RF front-end components (e.g., duplexers or switches 256, filters 242 or 254 or other components not shown) may be mounted, and the microcontroller may be used to modulate PA 244 and one or more other front-end components.

[0044] In the receiving path, antenna 257 receives the communication signal and provides the received RF signal, which is routed through duplexer or switch 256 and provided to low-noise amplifier (LNA) 252. Duplexer or switch 256 is designed to operate at a specific RX-TX duplexer frequency interval, such that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 252 and filtered by filter 254 to obtain the desired RF input signal. Down-conversion mixers 261a and 261b mix the output of filter 254 with the I and Q received (RX)LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 280 to generate I and Q baseband signals. The I and Q baseband signals are amplified by amplifiers 262a and 262b and further filtered by low-pass filters 264a and 264b to obtain the I and Q analog input signals provided to data processor 210. In the illustrated exemplary embodiment, the data processor 210 includes analog-to-digital converters (ADCs) 216a and 216b for converting analog input signals into digital signals for further processing by the data processor 210. In some embodiments, ADCs 216a and 216b are included in transceiver 220 and provide data digitally to the data processor 210. Similarly, an ET DAC 251 may be implemented in transceiver 220 and may be configured to digitally receive information from the data processor 210 and provide analog signals to the power modulator 246 via connection 253.

[0045] exist Figure 2 In this configuration, TX LO signal generator 290 generates I and QTX LO signals for frequency up-conversion, while RX LO signal generator 280 generates I and QRX LO signals for frequency down-conversion. Each LO signal is a periodic signal with a specific fundamental frequency. Phase-locked loop (PLL) 292 receives timing information from data processor 210 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from LO signal generator 290. Similarly, PLL 282 receives timing information from data processor 210 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from LO signal generator 280.

[0046] Wireless device 200 may support carrier aggregation (CA) and may (i) receive multiple downlink signals transmitted by one or more cells on multiple downlink carriers at different frequencies and / or (ii) transmit multiple uplink signals to one or more cells on multiple uplink carriers. However, those skilled in the art will understand that the aspects described herein can be implemented in systems, devices, and / or architectures that do not support carrier aggregation.

[0047] Some components of transceiver 220 Figure 2The transceiver 220 is illustrated functionally, and in some embodiments, the illustrated configuration may or may not represent a physical device configuration. For example, as described above, the transceiver 220 may be implemented in various integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc. In some embodiments, the transceiver 220 is implemented on a substrate or board, such as a printed circuit board (PCB) having various modules. For example, the power amplifier 244, filter 242, power modulator 246, and duplexer or switch 256 may be implemented in separate modules or as discrete components, while the remaining elements illustrated in the transceiver 220 may be implemented in a single transceiver chip.

[0048] Power amplifier 244 may include one or more stages, such as driver stages, power amplifier stages, or other components, which may be configured to amplify communication signals of one or more frequencies at one or more power levels in one or more frequency bands. Depending on various factors, power amplifier 244 may be configured to operate using one or more driver stages, one or more power amplifier stages, one or more impedance matching networks, and may be configured to provide linearity, efficiency, or a combination of linearity and efficiency.

[0049] Typically, power amplifier circuits are expected to provide linear power amplification over a desired bandwidth, which can be wide, support high data rate transmission, provide high efficiency over the desired power output range and bandwidth, and support multiple power modes.

[0050] Figure 3 It's a diagram. Figure 2 A schematic diagram 300 illustrates an exemplary embodiment of the power modulator 246. In the exemplary embodiment, the power modulator 246 includes an ET receiver 370, a switching regulator path 310, and a linear path 320. The power modulator 246 also includes an inductor 312, a switch 314, a capacitor 316, and a charging circuit 350. In the exemplary embodiment, as will be further described below, the charging circuit 350 may be implemented as a bidirectional current-limiting switch, which may be configured to charge or discharge the capacitor 316 based on maximum and minimum currents. The switch 314 may be supplied by a data processor 210 (… Figure 2 The signal can be controlled by either the ET receiver 370, the switching regulator path 310, the linear path 320, the charging circuit 350, or the switch 314. In an exemplary embodiment, the ET receiver 370, the switching regulator path 310, the linear path 320, the charging circuit 350, and the switch 314 can be fabricated as an on-die circuit system, while the inductor 312 and the capacitor 316 can be discrete components located on a printed circuit board (PCB). The capacitor 316 can be referred to as an "APT capacitor" (C APTThis can be either an APT capacitor or an APT capacitor, as it filters the voltage supplied by the switching regulator path 310. Capacitor 316 may have a first terminal that can be coupled to system ground, and a second terminal that can be coupled to switch 314 and charging circuit 350. Capacitor 316 may also be selectively coupled to node 315 via switch 314. Switch 314 may be referred to as an "APT switch" (S...). APT (or APT switch)

[0051] In an exemplary embodiment, the ET receiver 370 in the power modulator 246 is connected to the envelope signal generator 245 via connection 253. Figure 2 The ET receiver 370 provides a signal to the linear path 320 via connection 371. The power modulator 246 provides a signal to the power amplifier (such as...) via connection 255. Figure 2 PA 244 provides the voltage output. The voltage at node 315 can be precisely regulated by power modulator 246 and can be directly fed by PA power supply connected to connection 255.

[0052] In an exemplary embodiment, the output of the ET receiver 370 on connection 371 may be a current provided to the linear path 320 to control the voltage at node 315.

[0053] When operating in Average Power Point Tracking (APT) mode, switch 314 is closed, and the square wave output of the switching regulator path 310 is fed by inductor 312 and APT capacitor (C). APT The filter 316 provides a regulated DC voltage at node 315 (VPA). The voltage VPA (Power Amplifier Supply Voltage) refers to the signal supplied to the power amplifier 244. In APT mode, the linear path 320 is disconnected and remains at high impedance, therefore it does not affect the voltage at node 315.

[0054] When the power modulator 246 operates in envelope tracking (ET) mode, switch 314 is open, and both linear path 320 and switching regulator path 310 are active. Linear path 320 amplifies the envelope signal from the envelope signal generator (245) on connection 253. Figure 2The voltage of the switching regulator path 310 is used to provide a regulated output voltage (VPA) at node 315. The switching regulator path 310 can be controlled by the linear path 320 via connection 323 and can be configured to provide most of the output power (DC and low-frequency power), for example, with high efficiency. In an exemplary embodiment, the switching regulator path 310 includes a controller 311 and a power stage 313, wherein the controller 311 provides a "duty cycle" input to the power stage 313 in the form of one or more (e.g., digital) signals having a controlled duty cycle that depends on whether the power stage 313 has two or more switching levels. When the linear path 320 controls the switching regulator path 310, the duty cycle control of the power stage 313 of the switching regulator path 310 can be controlled by the controller 321 in the linear path 320, rather than the controller 311 in the switching regulator path 310, via connection 323, as illustrated by the dashed connection from connection 323 to the power stage 313. In some embodiments, the output of linear path 320 or a lead otherwise coupled to node 315 may be coupled to controller 311 to enable the regulator to control switching regulator path 310 based on signals on the output or lead. Linear path 320 may be configured to provide high-frequency AC power, but in some embodiments may have lower efficiency than switching regulator path 310.

[0055] In a conventional power modulator, when it is necessary to change the APT mode output voltage, there is no charging circuit 350, and the APT capacitor 316 is directly charged / discharged by the switching regulator path 310 (via switch 314).

[0056] According to an exemplary embodiment, when utilizing Figure 3 The exemplary embodiment shown performs the process from the initial or first voltage V APT 1. Transition to the final or second voltage V APT When the APT voltage is 2, the APT capacitor 316 is disconnected from the output of the power modulator 246 via the APT switch 314, and the power modulator 246 is temporarily switched to ET operation mode, where the linear path 320 provides the initial APT voltage (V). APT 1). Due to the very fast settling time of ET mode, the output voltage (VPA) at node 315 will gradually decrease until the final APT voltage (V... APT 2) Rapid transition is possible. When linear path 320 supplies voltage to node 315, APT capacitor 316 is charged / discharged by charging circuit 350 to the second or final voltage V. APT 2. Simultaneously, the output of the power modulator 246 is disconnected at node 315 by opening APT switch 314. Once the voltage across APT capacitor 316 equals V... APT2. The APT capacitor 316 is reconnected to the output of the power modulator 246 via the closed APT switch 314, and the operating mode of the power modulator 246 changes from ET mode back to APT mode, while the switching regulator path 310 now provides the final voltage V at node 315. APT 2. In this way, the voltage from the first voltage V is achieved. APT Rapid voltage changes or transitions from voltage 1 to the second voltage VAPT2. When the power supply modulator 246 is temporarily in ET mode (also known as ET transient mode), its efficiency may be lower, but this may not have a significant impact on the overall APT efficiency because the percentage of time spent in transient ET mode is smaller than that in APT mode.

[0057] A similar process can be implemented to achieve a fast ET-APT voltage transition. In this case, the output voltage transitions from the envelope modulation voltage during ET mode to the voltage V in APT mode. APT However, it can be called V. APT _initial(V APT 1) The initial voltage across the APT capacitor 316 may differ from the desired voltage V. APT _final(V APT 2) They are very different. From V APT 1 to V APT The voltage transition across the APT capacitor 316 presents the same challenges as the APT-APT voltage transition, and the solution is similar. During the ET-APT mode transition, the power modulator 246 remains in ET mode while simultaneously switching V... APT Voltage V APT 2 is provided to node 315. During this time, charging circuit 350 draws APT capacitor 316 from V... APT 1. Charge or discharge to V APT 2. When the APT capacitor 316 reaches voltage V APT After step 2, the power modulator 246 switches to APT mode, where the switching regulator path 310 outputs V. APT 2 is provided to node 315.

[0058] Figure 4 It's illustrated in more detail. Figure 3 A schematic diagram 400 illustrates an exemplary embodiment of the power modulator 246. In the exemplary embodiment, the switching regulator path 410 is... Figure 3An exemplary embodiment of the switching regulator path 310. In an exemplary embodiment, the switching regulator path 410 includes a first DC-to-DC converter 417 coupled to a system or battery voltage VBAT. The first DC-to-DC converter 417 provides a voltage output to an inductor 412 coupled to node 415. In an exemplary embodiment, the first DC-to-DC converter 417 may be a multi-stage buck converter configured to be powered from voltage VBAT or selectively powered by VBAT and a boost voltage that may be higher than VBAT. In an exemplary embodiment, voltage VPA may be higher than voltage VBAT, such that the first DC-to-DC converter 417 may be configured to provide a voltage higher than VBAT.

[0059] In an exemplary embodiment, the power modulator 246 includes a signal generator 245 configured to receive a signal from the envelope signal generator via connection 253. Figure 2 An ET receiver 470 receives signals. The ET receiver 470 provides signals to the linear path 420 via connection 471. In an exemplary embodiment, the signal on connection 471 may be the current flowing through resistor 460, thereby aiding in the control of the voltage (VPA) at node 415.

[0060] In an exemplary embodiment, linear path 420 is Figure 3 An exemplary embodiment of linear path 320. In an exemplary embodiment, linear path 420 includes a second DC-to-DC converter 425 coupled to the system or battery voltage VBAT, an amplifier 427, and a capacitor 431. In an alternative exemplary embodiment, capacitor 431 may be optional, or DC-to-DC converter 425 may also be powered (selectively or continuously) by a boost voltage, which may be a voltage higher than VBAT. A reference voltage is provided to the non-inverting input of amplifier 427 via connection 428. Node 415 is coupled to the inverting input of amplifier 427 via connection 429. The high-frequency AC power provided by amplifier 427 can be combined with the DC / low-frequency power provided by switching regulator path 410 at node 415. The output (VPA) at node 415 can be tightly controlled to provide a supply voltage to PA 244 via connection 255. The efficiency of linear path 420 can be improved by maintaining the DC voltage on capacitor 431, thereby allowing amplifier 427 to operate from a lower supply voltage than is possible using a DC combiner. The DC voltage on capacitor 431 can be controlled by a controller in linear path 420, which provides "duty cycle" control to switching regulator path 410 via connection 423 (similar to...). Figure 3 The controller 321 (and / or the data processor 210 or another controller) regulates, for example, to ensure that the average current supplied through the inductor 412 is equal to the average load current drawn by the PA 244, similar to Figure 3Connection 323 is described in the diagram. In this embodiment, zero average current can flow through capacitor 431, so the voltage across capacitor 431 remains a constant, controlled voltage. In some embodiments, connection 423 is coupled to a node between amplifier 427 and capacitor 431, and to a first DC-to-DC converter 417 or an element such as a driver, which may be internal to or provide "duty cycle" control to the first DC-to-DC converter 417.

[0061] An exemplary embodiment of the power modulator 246 includes a charging circuit 450, a switch 414, and a capacitor 416. The capacitor 416 may be referred to as an "APT capacitor" (C...). APT This can be either an APT capacitor or an APT capacitor, as it filters the voltage provided by the switching regulator path 410. Capacitor 416 may have a first terminal that can be coupled to system ground, and a second terminal that can be coupled to switch 414 and charging circuit 450. Capacitor 416 can also be selectively coupled to node 415 via switch 414. Switch 414 may be referred to as an "APT switch" (S...). APT (or APT switch)

[0062] Figure 5 It shows the description Figure 2 Figure 500 shows a timeline of an exemplary embodiment of the operation of the envelope tracking system. In some 5G operating modes, it may be desirable to provide a rapid transition from one APT voltage to another. For example, it may be desirable to... Figure 3 Node 315 or Figure 4 The voltage at node 415 changes from one fixed APT voltage to another in less than 1 μs. In this operational example, the voltage regulator path is switched ( Figure 4 310, Figure 4 It is difficult to charge capacitor 316 (or 416) to a second voltage different from the first voltage in such a short time because the current required to achieve this voltage transition is impractical.

[0063] In an exemplary embodiment, timeline 500 shows a horizontal axis 502, which shows time increasing to the right. The APT mode is shown during time 516, the transient ET mode during time 517, and the APT mode during time 518. Power modulator 246 ( Figure 2 , 3 The voltage output VPA of (and 4) is shown via trace 504.

[0064] Figure 500 also shows a system timeline 508 including one or more Mobile Industrial Processor Interface (MIPI) triggered messages or events, with an exemplary one shown using reference numeral 510. Figure 500 also shows trace 506 representing the output of a Differential Envelope Tracking (ET) DAC, such as... Figure 2 The ET DAC 251. As will be described below, the trace 506 showing the output of the ET DAC is indicated by dashed lines because it is the data processor 210 ( Figure 2 How can the power modulator 246 be supplied with power? Figure 4 Examples of providing voltage signals. In an exemplary embodiment, data processor 210 may use a MIPI trigger (such as MIPI trigger 510) to pass voltage information to power modulator 246 via a MIPI interface, in which case the ET_DAC voltage will not be used in APT modes 516 and 518 or transient ET mode 517. For example, the voltage reference of linear path 420 used during transient ET mode 517 ( Figure 4 The voltage information sent via the MIPI interface using the MIPI trigger 510 can be used to build the power modulator 246. Figure 4 This internal linear path reference will replace the ET_DAC voltage in APT mode and ET transient mode, as shown by trace 506. A similar method of replacing ET_DAC during APT mode and ET transient mode can be used during ET-APT or APT-ET transitions.

[0065] The communication symbol boundary 520, which also represents the RF signal symbol boundary, is shown as an example of a point where the voltage supplied to the power amplifier 244 by the power modulator 246 can transition from one voltage level to another. This transition point can be precisely aligned in time with the RF signal symbol boundary.

[0066] In an exemplary embodiment, during APT mode 516, the voltage regulator (410, Figure 4 The VPA voltage can be provided, as shown by trace 504, up to the communication symbol boundary 520. In an exemplary embodiment, when it is desired to change the voltage output provided by the switching regulator path 410 during a voltage transition (APT>APT transition) or a transition from ET mode to APT mode (ET>APT), the APT capacitor ( Figure 3 316 Figure 4 416) By disconnecting the APT switch ( Figure 3 314, Figure 4 (414) can be at time 513 with the output of power modulator 246 shown as point 515 ( Figure 3 315 Figure 4(415) Disconnect. After a short period of time 524 allowing the linear path to "warm up," enable the linear path at time 514. Figure 3 320 Figure 4 (420), the power modulator 246 can be switched to ET mode. Events at times 514 and 513 can occur in or out of the indicated order, or simultaneously. The timing of the MIPI trigger 510 can be adjusted to allow for a linear path ( Figure 3 320 Figure 4 (420) has sufficient preheating time. Figure 5 In the example shown, MIPI trigger 510 occurs at time 512, which in this example begins the warm-up period 524, during which the linear path ( Figure 3 320 Figure 4 The power modulator 246 is preheated (420). Since the power modulator 246 is in ET mode, the power modulator output (trace 504) is able to support a rapid voltage transition at the communication symbol boundary 520. The power modulator 246 can provide an adjustable timing delay of X μs (522) to ensure that the power modulator output voltage transition occurs simultaneously with the RF symbol boundary, which in this exemplary embodiment is the communication symbol boundary 520. The power modulator 246 remains in ET mode, and the linear path 320 or 420 provides the final APT voltage, while the APT capacitor ( Figure 3 316 Figure 4 416) is connected to the charging circuit via the switching regulator path 310 or 410. Figure 3 350 Figure 4The APT capacitor 316 (416) is charged to the final APT voltage at time 528 (see trace 532). Once the APT capacitor 316 (416) is charged to the final APT voltage at time 528 (see trace 532), the APT switch 314 (414) is turned on again, and the power modulator 246 is then returned to the APT operating mode, with the switching regulator path 310 or 410 providing the voltage VPA at node 315 or 415. In this way, the entire APT-APT voltage transition described includes a short period of time 517, during which the power modulator 246 is in transient ET mode, the linear path 320 or 420 provides the voltage VPA, and the switching regulator path 310 or 410 charges the APT capacitor 316 or 416 to the final APT voltage. In an exemplary embodiment, the typical duration of the transient ET mode 517 can be on the order of 10 μs to 20 μs, with most of this period used for charging and discharging the APT capacitor 316 or 416. The state of charge of capacitor 316 (416) can be determined solely by, for example, an analog comparator and associated circuitry (not shown) that measures the voltage (VPA) at node 719 (or 819) and the voltage (VCAP) at node 729 (or 829), as follows: Figure 7 and Figure 8 As shown in the diagram. When the absolute value of the voltage difference between nodes 719 (819) and 729 (829) becomes less than the threshold voltage, capacitor 316 (416) is considered to be charged. Such analog comparators and related circuitry are known to those skilled in the art.

[0067] In an exemplary embodiment, the transient ET mode 517 includes the time period between time 526 and time 515 when capacitor 316 (416) is coupled to node 315 (415), the time period between time 515 and time 528 when capacitor 316 (416) is decoupled from node 315 (415), and the time period after time 528 until the start of APT mode 518 when capacitor 316 (416) is recoupled to node 315 (415). The time period during which capacitor 316 (416) is decoupled from node 315 (415) (i.e., between time 515 and time 528) can be considered as normal ET mode operation. In this way, the transition from ET mode to APT mode is illustrated as occurring between time 515 and time 528 when capacitor 316 (416) is decoupled from node 315 (415) and when capacitor 316 (416) is recoupled to node 315 (415) and until time 528 when APT mode 518 (capacitor 316 (416) is coupled to node 315 (415) and switching regulator path 310 (410) provides APT voltage) begins.

[0068] Figure 6 This illustrates the description of the APT to ET transition process. Figure 2 Figure 600 shows a timeline of an exemplary embodiment of the operation of the envelope tracking system. In the exemplary embodiment, timeline 600 shows a horizontal axis 602, which shows time increasing to the right. The APT mode is shown during time 616, the transient ET mode with a fixed APT voltage provided by linear path 320 or 420 is shown during time 617, and the ongoing ET mode with (e.g., rapidly) changing ET voltage provided by linear path 320 or 420 is shown during time 619. Power modulator 246 ( Figure 2 , 3 The voltage output VPA of 4) is shown by trace 604.

[0069] Figure 600 also shows a system timeline 608, which includes one or more MIPI trigger messages, one of which is shown using reference numeral 610. Figure 600 also shows a trace 606 representing the output of an envelope tracking (ET) DAC, such as Figure 2 The ET DAC 251. As mentioned below, the trace 606 of the ET DAC output is shown as a dashed line up to the communication symbol boundary 620, as it is the data processor 210 ( Figure 2 How can the power modulator 246 be supplied with power? Figure 4 This is one example of providing a voltage signal. In another exemplary embodiment, the data processor 210 may use a signal embedded in a MIPI trigger such as MIPI trigger 610 to pass voltage information to the power modulator 246, in which case trace 606 will be omitted during APT mode 616 and ET mode 617.

[0070] The communication symbol boundary 620 is shown as an example of a point where the symbol power level changes. It can be observed that the output voltage of the power modulator 246 has little or no discontinuity at the communication symbol boundary 620, thus minimizing the risk of RF signal damage.

[0071] In an exemplary embodiment, during APT mode 616, the switch regulator path (310, Figure 3 Or 410, Figure 4 The power supply modulator 246 can provide the voltage shown by trace 604. In an exemplary embodiment, when it is desired to change the voltage provided by the switching regulator path 410 to the voltage provided by the linear path 420, for example when transitioning from APT mode to ET mode (APT>ET), the power supply modulator 246 ( Figure 3 and Figure 4The APT switch 414 can be configured to enable linear path 320 (420) before communication symbol boundary 620 to help provide voltage VPA to node 315 (415) at point 650. As mentioned above, linear path 320 (420) can be activated by MIPI trigger 610 occurring at time 614, allowing linear path 320 (420) sufficient time to warm up (shown at time 624), so that linear path 320 (420) is fully on at time 626 and may be able to provide voltage VPA during ET transition time 617, resulting in uninterrupted output voltage VPA at node 315 (415) starting at time 650. Figure 4 ) or 314 Figure 3 Disconnect at point 615 at time 613, and disconnect APT capacitor 416 ( Figure 4 ) or 316 ( Figure 3 The linear path 320 or 420 is disconnected from the output node 315 (415) so that, starting at time 613 and before the communication symbol boundary 620, the linear path 320 or 420 provides voltage VPA to node 315 (415). In this exemplary embodiment, after the communication symbol boundary 620, the linear path 320 or 420 continues to provide voltage VPA in ET mode during time 619.

[0072] Figure 7 It shows Figure 3 The charging circuit 350 and Figure 4 A schematic diagram 700 of an exemplary embodiment of 450 is shown. In the exemplary embodiment, the charging circuit 700 includes an N-type circuit system 710 and a P-type circuit system 720.

[0073] In an exemplary embodiment, the N-type circuit system 710 includes NMOS transistors 712, 714, and 716. Diode 715 represents the body diode of transistor 714, and diode 717 represents the body diode of transistor 716. The gates of transistors 712, 714, and 716 are coupled to node 718.

[0074] In an exemplary embodiment, the P-type circuit system 720 includes PMOS transistors 722, 724, and 726. Diode 725 represents the body diode of transistor 724, and diode 727 represents the body diode of transistor 726. The gates of transistors 722, 724, and 726 are coupled to node 728.

[0075] The drains of transistors 714 and 724 are coupled to node 719, which may include power amplifier 244. Figure 2 The voltage output VPA of )

[0076] The drains of transistors 716 and 726 are coupled to node 729, which may include a capacitor 416 (C) APT The voltage output VCPA.

[0077] If the voltage at node 719 is higher than the voltage at node 729, current will flow toward node 729 through two paths. In this example, current will flow through a first path including transistor 714 and diode 717, and current will flow through a second path including diode 725 and transistor 726. When the voltage VGN at connection 718 is sufficiently high relative to the voltage VCAP at node 729, transistor 716 will conduct and will carry some or all of the current from diode 717. A similar situation will occur for transistor 724 and diode 725. When the voltage VGP at connection 728 is sufficiently low relative to the voltage VPA at node 719, transistor 724 will conduct and will carry some or all of the current from diode 725. If the voltage at node 729 is higher than the voltage at node 719, current will also flow through two paths. In this example, current will flow toward node 719 through a first path including transistor 716 and diode 715, and current will flow through a second path including diode 727 and transistor 724. Similar to the above, transistors 714 and 726 can be turned on and can conduct some or all of the current from diodes 715 and 727, respectively. Given the symmetry between diodes 715 and 717 and between diodes 725 and 727, the N-type circuit system 710 and the P-type circuit system 720 form a bidirectional switch. The conduction ratio between the N-type circuit system 710 and the P-type circuit system 720 will depend on the voltage ranges of VCAP and VPA. The N-type circuit system 710 will conduct more for the lower voltage range, where the P-type circuit system may deplete the voltage margin of VGP at connection 728, and the P-type circuit system 720 will conduct more for the higher voltage range, where the N-type circuit system may deplete the voltage margin of VGN at connection 718.

[0078] The current flowing through the N-type circuit system 710, which includes transistors 716, 714, 717, and 715, will be mirrored through transistor 712, and the replicated current will flow through connection 766. Similarly, the current flowing through the P-type circuit system 720, which includes transistors 726, 724, 727, and 725, will be mirrored through transistor 722, and the replicated current will flow through connection 768.

[0079] The output of P_mirror controller 730 can be provided to summing node 742 via connection 762, and the output of N_mirror controller 750 can be provided to summing node 742 via connection 764. P_mirror controller 730 and N_mirror controller 750 provide signals that can be used to maintain bidirectional current limiting functionality in N-type circuit system 710 and P-type circuit system 720. In an exemplary embodiment, P_mirror controller 730 and N_mirror controller 750 can control the current flowing to APT capacitor 316 (416) while it is charged / discharged to a final APT voltage (e.g., ...). Figure 5 (trace 532). P_mirror controller 730 and N_mirror controller 750 do not need to be implemented together with the circuitry used to implement N-type circuitry system 710 and P-type circuitry system 720; one or both of P_mirror controller 730 and N_mirror controller 750 may be implemented in the same IC or close to N-type circuitry system 710 and P-type circuitry system 720, or one or both of P_mirror controller 730 and N_mirror controller 750 may be implemented in one or more controllers (e.g., in data processor 210) away from N-type circuitry system 710 and / or P-type circuitry system 720. Summation node 742 sums the currents on connections 762 and 764 and provides input to bias function (H(S)) 740.

[0080] The bias function H(S)740 provides a gate voltage (VGN) to node 718 and a gate voltage (VGP) to node 728. The bias function H(S)740 controls VGN on connection 718 and VGP on connection 728 to limit the total current flowing through the P-type circuit system 710 and N-type circuit system 720 between nodes 719 (VPA) and 729 (VCAP), ensuring that the total current flowing between nodes 719 and 729 is constant.

[0081] Figure 8 It shows Figure 7 A schematic diagram 800 of an exemplary embodiment of the charging circuit 700, together with the switch regulator path 410 ( Figure 4 ), linear path 420 ( Figure 4 ), inductor 412 and power amplifier 244 ( Figure 4 ).Apart from Figure 7 An embodiment of the charging circuit 700 Figure 8 In addition to the components shown, the switch regulator path 410 is also illustrated. Figure 4 ), linear path 420 ( Figure 4 ), inductor 412 and power amplifier 244 ( Figure 4 (For reference only.)

[0082] and Figure 7 The corresponding components are similar Figure 8 The components in the code will be labeled using the 8XX naming convention, where Figure 8 Components marked 8XX are similar to Figure 7 Components marked with 7XX. For example, Figure 7 The N-type circuit system 710 in the middle is similar to Figure 8 The N-type circuit system 810 is described above, and is an exemplary embodiment thereof. Further, Figure 8 In and Figure 7 Some reference numerals for elements similar to those in the figures are omitted for clarity. For example, Figure 8 The reference numerals for at least some transistors and diodes in the N-type circuit system 810 and P-type circuit system 820 may be omitted for clarity of the figures. Figure 8 It is usually shown in more detail Figure 7 Examples of P_mirror controller 730 and N_mirror controller 750.

[0083] In an exemplary embodiment, circuit 800 includes a current mirror 870 that mirrors the current through connection 864 to current I2 on connection 875. In an exemplary embodiment, current mirror 870 includes transistors 872 and 874, the sources of which are coupled to a secondary voltage VDDAUX. The drain of transistor 872 is coupled to connection 875, and current I2 flows to node 885. The drain of transistor 874 is coupled through connection 864 to the drain of transistor 856 in N_mirror controller 850.

[0084] The N_mirror controller 850 includes transistors 852, 854, 856, and 858, an amplifier (GM stage) 855, and a capacitor 857. The drain of transistor 852 is coupled to the drain of transistor 822 in the P-type circuit system 820 via connection 868. Current IMp1 flows to transistor 852 in connection 868. The gates of transistors 852 and 856 receive the bias signal VN_n. The gates of transistors 854 and 858 are coupled to the output of amplifier 855. A minimum and maximum voltage selector 890 between nodes 829 (VCAP) and 819 (VPA) provides a voltage MIN(VCAP,VPA) to the inverting input of amplifier 855. The voltage selector function can have voltages VPA and VCAP as inputs and voltages MIN(VCAP,VPA) and MAX(VCAP,VPA) as outputs. Voltage MIN(VCAP,VPA) is the minimum voltage between VCAP and VPA, and voltage MAX(VCAP,VPA) is the maximum voltage between VCAP and VPA.

[0085] Circuit 800 also includes a P_Mirror controller 830 having transistors 832, 834, 836, and 838, an amplifier (GM stage) 835, and a capacitor 837. The drain of transistor 838 is coupled to the drain of transistor 812 in the N-type circuit system 810 via connection 866. Current IMn1 flows to transistor 812 in connection 866. The gates of transistors 834 and 838 receive a bias signal VN_p. The gates of transistors 832 and 836 are coupled to the output of amplifier 835. A minimum and maximum voltage selector 890 provides a voltage MAX(VCAP, VPA) to the inverting input of amplifier 835.

[0086] Current I1 flows from the drain of transistor 834 to node 842 in connection 862. Node 842 adds currents I1 and I2 and provides the added current to the inverting input of amplifier 844 and the non-inverting input of amplifier 846.

[0087] In an exemplary embodiment, the non-inverting input of amplifier 844 is coupled to the inverting input of amplifier 846. Amplifier 844 provides a bias signal VGN to node 818, and amplifier 846 provides a bias signal VGP to node 828. Amplifiers 844 and 846 regulate the sum of currents I1 and I2 by maintaining a constant voltage at connection 842. Current I1 is a copy of the current flowing through N-type circuit system 810, and current I2 is a copy of the current flowing through P-type circuit system 820. By maintaining the sum of currents (I1+I2) constant, the entire loop maintains a constant total current between node 819 (VPA) and node 829 (VCAP), thereby achieving bidirectional current limiting.

[0088] Figure 9 This is a flowchart 900 describing the operation of an exemplary embodiment of an envelope tracking system according to exemplary embodiments of the present disclosure. The blocks in method 900 may be executed in or out of the order shown, and in some embodiments, they may be executed at least partially in parallel. In an exemplary embodiment, method 900 will refer to... Figure 2 Envelope tracking system 243 and power modulator 246, Figure 4 Some or all of the components in the power modulator 246 and Figure 5 Timeline 500. However, method 900 applies to all exemplary embodiments of the envelope tracking system, envelope signal generator, and power modulator described herein.

[0089] In block 902, and optionally in parallel with the operation of block 904, linear path 420 is activated and configured to direct power amplifier 244 ( Figure 4 This provides a voltage output VPA_FB. This corresponds to... Figure 5 The time 514 in the example. In an exemplary embodiment, the linear path 420 may receive, for example, data from the MIPI trigger 510 ( Figure 5 The signal is used to begin preheating before the linear path 420 is turned on and activated in box 902.

[0090] In box 904, switch 414 (S) APT , Figure 4 ) can be disconnected. Disconnecting switch 414 causes the switch regulator path 410 to be connected to capacitor 416 (C). APT , Figure 4 Decoupling. This can correspond to Figure 5 The time in the middle is 513.

[0091] In box 906, when linear path 420 is power amplifier 244 ( Figure 5 When the VPA trace 504 (part 525) provides the voltage signal VPA_FB, the switching regulator path 410 provides voltage to the charging circuit 450 ( Figure 5 The portion 532 of VPA trace 504 in the figure corresponds to capacitor 416 (C). APT Charging. For example, linear path 420 and switching regulator path 410 cooperate to provide a voltage signal VPA to power amplifier 244, while also charging capacitor 416 (C) via charging circuit 450. APT )Charge.

[0092] In box 908, capacitor 416 (C) is defined. APT Whether it is charged to the desired voltage. If the capacitor 416 (C) is determined in box 908. APTIf the capacitor 416 is not charged to the desired voltage, the process returns to block 906, and the switching regulator path 410 continues to charge the capacitor 416 (C) via the charging circuit 450. APT ) charging. If capacitor 416 (C) is determined in box 908 APT Once the voltage is charged to the desired level, the process proceeds to step 912.

[0093] In box 912, switch 414 (S) APT The ) is closed. This corresponds to Figure 5 At time point 528, closing switch 414 couples switch regulator path 410 to capacitor 416 (C). APT , Figure 4 ).

[0094] In box 914, linear path 420 is closed. This can correspond to Figure 5 The time point between time point 528 in the middle and the start of APT mode 518.

[0095] In block 916, the switching regulator path 410 provides voltage VPA. This corresponds to Figure 5 APT mode 518 in the middle.

[0096] Figure 10 This is a flowchart 1000 describing the operation of an exemplary embodiment of an envelope tracking system according to exemplary embodiments of the present disclosure. The blocks in method 1000 may be executed in or out of the order shown, and in some embodiments, they may be executed at least partially in parallel. In exemplary embodiments, method 1000 will refer to... Figure 2 Envelope tracking system 243 and power modulator 246, Figure 4 Some or all of the components in the power modulator 246 and Figure 6 Timeline 600. However, method 1000 applies to all exemplary embodiments of the envelope tracking system, envelope signal generator, and power modulator described herein.

[0097] In block 1002, and optionally in parallel with the operation of block 1004, linear path 420 is activated and configured to direct power amplifier 244 ( Figure 4 The system provides a voltage output VPA. In this exemplary embodiment, the ET_DAC, shown by trace 606, references the output voltage VPA when the system is in APT mode. The enabled linear path corresponds to... Figure 6 The time 614 in the example. In an exemplary embodiment, the linear path 420 may receive, for example, data from the MIPI trigger 610 ( Figure 6 The signal is used to start preheating before the linear path 420 is turned on in box 1002.

[0098] In box 1004, linear path 420 is driven by capacitor 416 (C APT , Figure 4 The capacitor load is represented by (), and the output VPA is provided. This can correspond to Figure 6 The time in the middle is 614.

[0099] In box 1006, switch 414 (S) APT , Figure 4 ) can be disconnected. Disconnecting switch 414 causes the switch regulator path 410 to be connected to capacitor 416 (C). APT , Figure 4 Decoupling. This can correspond to Figure 6 The time in the middle is 613.

[0100] In box 1008, linear path 420 provides voltage VPA. This corresponds to Figure 6 EET mode 619 in the middle.

[0101] Figure 11 This is a functional block diagram of an apparatus 1100 for an envelope tracking system according to exemplary embodiments of the present disclosure. The apparatus 1100 includes a component 1102 for activating a linear path in the envelope tracking system. In some embodiments, the component 1102 for activating the linear path in the envelope tracking system may be configured to perform in method 900 (…). Figure 9 One or more of the functions described in operation block 902. In an exemplary embodiment, component 1102 for activating the linear path of the envelope tracking system may include an envelope signal generator 245, for example configured to turn on linear path 420 (or any alternative embodiment of linear path 420) to provide an output (VPA) to power amplifier 244.

[0102] The apparatus 1100 also includes a component 1104 for decoupling the switching regulator path 410 from the capacitor 416. In some embodiments, the component 1104 for decoupling the switching regulator path 410 from the capacitor 416 may be configured to perform method 900. Figure 9 One or more functions are described in operation block 904. In an exemplary embodiment, component 1104 for decoupling the switch regulator path 410 from capacitor 416 may include envelope signal generator 245, for example configured to cause switch 414 (S APT (or any alternative embodiment of switch 414) disconnect.

[0103] The device 1100 also includes a function for C APT The charging component 1106 simultaneously provides a voltage output via a linear path. In some embodiments, it is used for charging C. APTThe component 1106, which provides voltage output via a linear path while charging, can be configured to perform in method 906. Figure 9 One or more of the functions described in operation block 906. In an exemplary embodiment, this is used to provide voltage output to C while simultaneously providing voltage output on the linear path. APT The charging component 1106 may include a switching regulator path 410, for example configured to charge capacitor 416 (C) via charging circuit 450. APT The linear path diagram 42 provides a voltage signal VPA to the power amplifier 244.

[0104] The device 1100 also includes a method for determining C APT Component 1108 indicating whether it is being charged. In some embodiments, it is used to determine C. APT Whether the component 1108 is charged or not can be configured to perform in method 908 ( Figure 9 One or more of the functions described in operation block 908. In an exemplary embodiment, for determining C APT The component 1108 that determines whether a device is being charged may include a comparator and associated circuitry (not shown), for example, configured to measure node 719. Figure 7 (or 819,) Figure 8 The voltage (VPA) at point 729 and node 729 Figure 7 (or 829,) Figure 8 The voltage VCAP at point 719(819) is used to determine whether the absolute value of the voltage difference between nodes 719(819) and 729(829) becomes less than the threshold voltage, thereby determining whether capacitor 416 is charged to the desired voltage.

[0105] Device 1100 also includes a means for coupling the switching regulator path 410 to capacitor 416 (C APT , Figure 4 Component 1112. In some embodiments, it is used to couple the switching regulator path 410 to the capacitor 416 (C). APT , Figure 4 Component 1112 can be configured to execute in method 900. Figure 9 One or more of the functions described in operation block 912. In an exemplary embodiment, this is used to couple the switching regulator path 410 to capacitor 416 (C). APT , Figure 4 Component 1112 may include envelope signal generator 245, for example configured to cause switch 414 (S APT (or any alternative embodiment of switch 414) Close.

[0106] The apparatus 1100 also includes a component 1114 for stopping the linear path providing the output VPA. In some embodiments, the component 1114 for stopping the linear path providing the output VPA can be configured to perform in method 900 ( Figure 9 One or more of the functions described in operation block 914. In an exemplary embodiment, component 1114 for stopping the linear path providing the output VPA may include envelope signal generator 245, for example configured to disconnect linear path 420.

[0107] The apparatus 1100 also includes a component 1116 for switching the regulator path to provide a voltage output VPA. In some embodiments, the component 1116 for switching the regulator path to provide a voltage output VPA can be configured to perform in method 900 ( Figure 9 One or more of the functions described in operation block 916. In an exemplary embodiment, component 1116 for the switching regulator path to provide voltage output VPA may include envelope signal generator 245, for example configured to turn on switching regulator path 410 such that switching regulator path 410 provides voltage output VPA.

[0108] Figure 12 This is a functional block diagram of an apparatus 1200 for an envelope tracking system according to exemplary embodiments of the present disclosure. The apparatus 1200 includes a component 1202 for activating a linear path in the envelope tracking system. In some embodiments, the component 1202 for activating the linear path in the envelope tracking system may be configured to perform in method 1000 (… Figure 10 One or more of the functions described in operation block 1002. In an exemplary embodiment, component 1202 for activating the linear path of the envelope tracking system may include an envelope signal generator 245, for example configured to conduct linear path 420 (or any alternative embodiment of linear path 420) to provide an output (VPA) to power amplifier 244.

[0109] Device 1200 also includes a means for driving capacitor 416 (C APT , Figure 4 The component 1204 represents the capacitive load and provides the output VPA. In some embodiments, it is used to drive the capacitor 416 (C) APT , Figure 4 The component 1204, which represents the capacitive load and provides the output VPA, can be configured to perform in method 1000. Figure 10 One or more of the functions described in operation block 1004. In an exemplary embodiment, for driving the capacitor 416 (C APT , Figure 4The component 1204, which represents a capacitive load and provides an output VPA, may include a linear path 420, for example configured to drive a capacitor 416 (C) APT , Figure 4 ) represents the capacitive load and provides the output VPA.

[0110] Device 1200 also includes a means for connecting the switching regulator path 410 to capacitor 416 (C APT , Figure 4 The decoupling component 1206. In some embodiments, it is used to decouple the switching regulator path 410 from the capacitor 416 (C). APT , Figure 4 The decoupled component 1206 can be configured to execute in method 1000. Figure 10 One or more of the functions described in operation block 1006. In an exemplary embodiment, this is used to connect the switch regulator path 410 to capacitor 416 (C). APT , Figure 4 The decoupling component 1206 may include an envelope signal generator 245, for example configured to cause switch 414 (S) to... APT (or any alternative embodiment of switch 414) disconnect.

[0111] The apparatus 1200 also includes a component 1208 for providing an output VPA. In some embodiments, the component 1208 for providing the output VPA may be configured to perform in method 1000 ( Figure 10 One or more of the functions described in operation block 1008. In an exemplary embodiment, component 1208 for providing an output VPA may include linear path 420, for example, configured to provide an output VPA.

[0112] The envelope tracking system described in this paper can be implemented on one or more ICs, analog ICs, RFICs, mixed-signal ICs, ASICs, printed circuit boards (PCBs), electronic devices, etc. The envelope tracking system described in this paper can also be manufactured using various IC process technologies, such as complementary metal-oxide-semiconductor (CMOS), N-channel MOS (NMOS), P-channel MOS (PMOS), bipolar junction transistors (BJTs), bipolar CMOS (BiCMOS), silicon-germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), silicon-on-insulator (SOI), etc.

[0113] The apparatus for implementing the envelope tracking system described herein may be a standalone device or part of a larger device. The device may be (i) a standalone IC, (ii) a collection of one or more ICs, which may include a memory IC for storing data and / or instructions, (iii) an RF IC, such as an RF receiver (RFR) or an RF transmitter / receiver (RTR), (iv) an ASIC, (v) a module that may be embedded in other devices, (vi) a receiver, a cellular phone, a wireless device, a mobile phone or mobile unit, (vii) etc.

[0114] In one or more exemplary designs, the described functionality can be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functionality can be stored as one or more instructions or code on or transmitted through a computer-readable medium. Computer-readable media include computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one place to another. Storage media can be any available medium accessible to a computer. By way of example, but not limited to, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and is accessible to a computer. Other such non-transient computer-readable media may also be implemented. Further, any connection is appropriately referred to as a computer-readable medium. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, optical fiber, twisted pair, digital subscriber line (DSL), or wireless technologies (such as infrared, radio, and microwave), then coaxial cable, optical fiber, twisted pair, DSL, or wireless technologies (such as infrared, radio, and microwave) are included in the definition of media. The disks and optical discs used herein include: optical discs (CDs), laser discs, optical discs, digital universal discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these should also be included within the scope of computer-readable media.

[0115] Although the selected aspects have been illustrated and described in detail, it should be understood that various substitutions and modifications may be made herein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. An envelope tracking system, comprising: an envelope signal generator; a power modulator coupled to the envelope signal generator, the power modulator including a switching regulator path configured to provide an output voltage at an output node to a power amplifier when in an average power tracking (APT) mode, the switching regulator path configured to operate with a linear path to provide the output voltage at the output node to the power amplifier when in an envelope tracking (ET) transient mode; a capacitor having a first terminal and a second terminal, the first terminal coupled to ground; a switch coupled between the output node and the second terminal of the capacitor, the switch configured to selectively disconnect the capacitor from the output node; and circuitry coupled between the output node and the second terminal of the capacitor, the circuitry including a bidirectional current limiting switch, the circuitry configured to charge or discharge the capacitor based on a maximum current and a minimum current while the capacitor is disconnected from the output node during the ET transient mode, such that a voltage across the capacitor changes from a first voltage to a second voltage.

2. The envelope tracking system of claim 1, wherein the circuitry further includes an N-type transistor and a P-type transistor configured to allow bidirectional current flow.

3. The envelope tracking system of claim 1, wherein the linear path is configured to be activated by a mobile industry processor interface (MIPI) trigger prior to a time at which the linear path provides the output voltage to the power amplifier.

4. The envelope tracking system of claim 1, wherein the bidirectional current limiting switch is configured to charge or discharge the capacitor based on a maximum current and a minimum current.

5. The envelope tracking system of claim 4, wherein the bidirectional current limiting switch is configured to charge or discharge the capacitor based on an N-type transistor and a P-type transistor in respective N-type control circuitry and P-type control circuitry.

6. The envelope tracking system of claim 5, wherein the N-type control circuitry and P-type control circuitry further include an amplification stage.

7. The envelope tracking system of claim 5, wherein an output of the N-type control circuitry and an output of the P-type control circuitry are combined and provided to a bias function configured to provide a current limiting function to the bidirectional current limiting switch.

8. A method for communication, comprising: providing a first voltage to a power amplifier using a switching regulator path; and when switching from a first mode to a second mode, providing the first voltage to the power amplifier using a linear path and simultaneously decoupling the switching regulator path from an output capacitor, charging the output capacitor to a second voltage using a charging circuit, wherein the charging circuit includes a bidirectional current limiting switch configured to charge or discharge the output capacitor based on a maximum current and a minimum current; and ​ wherein the first mode comprises an average power tracking (APT) mode and the second mode comprises an envelope tracking (ET) mode.

9. The method of claim 8, further comprising: activating the linear path using a mobile industry processor interface (MIPI) trigger before a time at which the linear path is to provide the first voltage.

10. The method of claim 8, further comprising: providing a seamless transition when switching from the first mode to the second mode.

11. The method of claim 8, further comprising: determining the maximum and minimum currents using N-type and P-type transistors in respective N-type and P-type control circuitry.

12. The method of claim 11, wherein the N-type and P-type control circuitry further comprises an amplification stage.

13. The method of claim 11, further comprising: combining an output of the N-type control circuitry with an output of the P-type control circuitry to produce a bias signal configured to provide a current limiting function to the bidirectional current limiting switch.

14. An envelope tracking system, comprising: an envelope signal generator; a power modulator coupled to the envelope signal generator, the power modulator comprising a switching regulator path configured to provide an output voltage to a power amplifier when in an average power tracking (APT) mode, the switching regulator path configured to operate with a linear path to provide the output voltage to the power amplifier when in an envelope tracking (ET) mode; circuitry configured to activate the linear path associated with the ET mode during an ET transient mode based at least in part on a MIPI trigger before a symbol boundary, wherein the linear path continues to provide the output voltage in the ET mode after the symbol boundary; and a switch configured to disconnect an output capacitor charged to a first output voltage (APT) from the power modulator while the output voltage is provided to the power amplifier in the ET transient mode, wherein a charging circuit comprises a bidirectional current limiting switch configured to charge or discharge the output capacitor based on a maximum and minimum current.

15. The envelope tracking system of claim 14, wherein the power modulator provides a seamless voltage output transition from an APT mode to an ET mode.

16. A method for communication, comprising: providing a first voltage to a power amplifier in a first mode using a switching regulator path; when switching from the first voltage to a second voltage in a second mode, providing the second voltage to the power amplifier using a linear path while the switching regulator path is decoupled from an output capacitor and a charging circuit charges the output capacitor to the second voltage; and when the output capacitor is charged to the second voltage, deactivating the linear path and coupling the switching regulator path to the output capacitor such that the switching regulator path provides the second voltage in the first mode; wherein the first mode comprises an average power tracking (APT) mode and the second mode comprises an envelope tracking (ET) transient mode; and wherein the charging circuit includes a bidirectional current limiting switch configured to charge or discharge the output capacitor based on a maximum current and a minimum current.

17. The method of claim 16, further comprising: activating the linear path using a mobile industry processor interface (MIPI) trigger before the time at which the linear path is to provide the first voltage.

18. The method of claim 16, further comprising: determining the maximum current and the minimum current using N-type transistors and P-type transistors in respective N-type control circuitry and P-type control circuitry.

19. The method of claim 18, wherein the N-type control circuitry and P-type control circuitry further comprise an amplification stage.

20. The method of claim 18, further comprising: combining an output of the N-type control circuitry with an output of the P-type control circuitry to produce a bias signal configured to provide a current limiting function to the bidirectional current limiting switch.

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