Method for adjusting the system clock frequency of a hearing system, hearing device and hearing system

Abstract

The present invention relates to a method, a hearing device, and a hearing system for adjusting the system clock frequency of a hearing system, and in one aspect, to a method for adjusting a second system clock frequency of a slave device or a second device to a first system clock frequency of a first device connected thereto via a unidirectional or bidirectional wireless data communication link, in order to reduce the clock offset between the first system clock frequency and the second system clock frequency.

Description

Technical Field

[0001] In one aspect, the present invention relates to a method of adjusting a second system clock frequency of a second head-mounted hearing device or a second system of a head-mounted hearing device to a first system clock frequency of a first head-mounted hearing device connectable thereto via a unidirectional or bidirectional wireless data communication link in order to reduce a clock offset or mismatch between the first system clock frequency and the second system clock frequency. Background Art

[0002] Hearing systems are known in the art that include a pair of wirelessly connected independent devices, such as a first head-mounted hearing device and a second head-mounted hearing device, instrument or hearing aid, which exchange digital audio signals via a unidirectional or bidirectional wireless data communication link. The digital audio signals may include corresponding digital microphone signal streams or other types of digital audio streams generated by the microphone means of the first device and the microphone means of the second hearing device in response to incoming sounds. One or both of the first head-mounted hearing device and the second head-mounted hearing device may utilize a pair of ipsilateral and contralateral microphone signals to perform various complex binaural beamforming algorithms on the corresponding digital microphone signal streams to spatially filter the incoming sounds in each hearing aid, thereby providing corresponding binaural beamformed microphone signals to the user's left and right ears. These binaural beamformed microphone signals may exhibit an improved signal-to-noise ratio relative to the monaural microphone signals transmitted by each microphone means or other types of signal enhancement utilizing binaural signal processing algorithms and mechanisms.

[0003] However, the perceived quality of such binaural processed microphone signals or other types of digital audio signals depends on an accurate match or alignment between the respective system clock frequencies of the first head-mounted hearing device and the second head-mounted hearing device, because for example the binaural beamforming algorithm heavily relies on an accurate timing relationship between the ipsilateral and contralateral digital microphone signals. Such an accurate match of the respective system clock frequencies represents a technical challenge because the first device and the second device typically include independent clock generator circuits that, like all other actual electronic circuits and components, have limited precision and accuracy. This means that there will inevitably be a certain deviation or mismatch between the system clock frequency of the first device and the system clock frequency of the second device. The lack of precision of the system clock generator may be caused by many factors, such as manufacturing tolerances of the actual clock frequency, temperature drift, aging effects, etc. Another practical limitation of the precision of the system clock generator is the limitation of the size, cost and power consumption of the miniature housing of small head-mounted communication devices (such as hearing aids and instruments, etc.), which is particularly evident for devices such as head-mounted hearing devices.

[0004] The accuracy of a typical commercially available crystal-based clock generator can be approximately + / -20 ppm to 30 ppm, which means that the worst-case difference between the clock frequencies of the first and second hearing devices can be approximately 60 ppm (parts per million). For an audio sampling frequency of approximately 20 kHz, this clock frequency difference or mismatch results in an inaccurate timing relationship between the ipsilateral and contralateral digital microphone signals and also results in at least one sample overflow event or underflow event per second in the hearing device acting as the slave of the master hearing device. Although these sample overflow events and underflow events can be hidden or masked by various types of so-called sample realignment processes or algorithms, these alignment algorithms further increase the undesirable latency of the digital audio signal and are computationally demanding without completely eliminating the perceived quality degradation of the processed digital audio signal.

[0005] Accordingly, there is a need in the art to provide a more accurate alignment of the system clock frequencies of a pair of wirelessly connected and data communicating independent devices. Preferably, compact, inexpensive, and low-power circuits and components are used.

[0006] US2017 / 0064651 A1 discloses a hearing system that includes a master or source hearing aid device connected to a slave or terminal hearing aid device via a wireless communication link. The hearing system provides a timestamp-based controller for synchronizing the terminal or source sampling rate with an external packet rate. The hearing system utilizes arrival and departure timestamps to obtain sampling rate synchronization between the master / source hearing device and the slave / terminal hearing device. At the terminal hearing aid device, a feedback loop controller uses the difference between the arrival and departure timestamps of a particular received data packet to adjust the sampling rate actuator of the slave hearing device using a fractional delay technique.

[0007] US10,117,203 B2 discloses a hearing aid system that includes a master device and a slave device. The master device is communicatively coupled to the slave device via a wireless link. The master device has a master clock and generates a master timestamp for a specified event timed by the master clock. The master timestamp is transmitted to the slave device via the wireless link. The slave device has a slave clock and generates a slave timestamp for a specified event timed by the slave clock. The slave clock is adjusted to synchronize with the master clock using the master timestamp and the slave timestamp. SUMMARY OF THE INVENTION

[0008] A first aspect of the present invention relates to a method of adjusting a system clock frequency of a hearing system including a first device and a second device, the method comprising the steps of:

[0009] a) establishing a wireless data communication link between the first device and the second device via respective data communication interfaces,

[0010] b) Control a data transmission clock via a wireless data communication link according to a first system clock frequency of a first device.

[0011] c) Transmit data from the first device to the second device via the wireless data communication link.

[0012] d) Receive and decode input data via a data communication interface of the second device to extract a first digital audio stream.

[0013] e) Write consecutive digital audio samples of the first digital audio stream into a receive buffer of the second device according to the data transmission clock.

[0014] f) Read consecutive digital audio samples of the first digital audio stream from the receive buffer according to a second system clock frequency of the second device.

[0015] g) Increase or decrease the second system clock frequency to match the first system clock frequency based on a detected overflow event in or of the receive buffer and a detected underflow event.

[0016] The first device of this hearing system may include an audio - supported portable device or terminal such as a smartphone, a portable computer, a laptop, a tablet, etc., while the second device may include a head - mounted hearing device, such as headphones, an active hearing protection device, or a traditional hearing aid. The audio - supported portable device or terminal may be battery - powered using a rechargeable battery device or unit.

[0017] According to other embodiments of this hearing system, each of the first device and the second device includes a head - mounted hearing device, such as headphones, an active hearing protection device, or a traditional hearing aid, e.g., a hearing aid or instrument of the so - called BTE, ITE, ITC, CIC, or RIC type. Some embodiments of the head - mounted hearing device may include at least one housing part shaped and sized to be placed at or in the user's left or right ear, or at least one housing part shaped and sized to be placed at or behind the user's left or right ear auricle.

[0018] According to one embodiment of this hearing system, the second head - mounted hearing device includes an implant component or device configured to be placed in the user's skull and configured to provide an audio stimulation signal to the user's hearing nerve via an implanted electrode array, the audio stimulation signal being derived from a first digital audio stream provided by a first hearing device (e.g., a hearing aid).

[0019] Data transmitted over a wireless data communication link may comprise or be arranged as data packets according to a proprietary or standardized communication protocol, as discussed in more detail below with reference to the accompanying drawings. Some embodiments of the method are based on a two-way wireless data communication link, while other embodiments are based on a one-way wireless data communication link, where data is only transmitted from a first device to a second device.

[0020] Those skilled in the art will understand that any frequency difference or deviation between the data transmission clock set by the first system clock frequency of the first device and the second system clock frequency of the second device or slave device will ultimately result in an underflow or overflow in the receive buffer, since consecutive digital audio samples are written into the receive buffer at a higher frequency than they are read out again, and vice versa, as discussed in more detail below with reference to the accompanying drawings. If the second device includes such a transmit buffer, the corresponding underflow / overflow mechanism naturally applies to the transmit buffer described below. An increase or decrease in the second system clock frequency over time can be regarded as an adaptive adjustment of the latter frequency, which is configured to minimize the frequency difference or deviation between the second system clock frequency and the first system clock frequency.

[0021] The second device may include a transmit buffer, the hearing system may include a two-way wireless data communication link, and the method may include the following steps:

[0022] h) Writing digital audio samples of a second digital audio stream generated by the second device into a transmit buffer of the second device for temporary storage according to a second system clock signal of the second device (preferably a head-mounted hearing device);

[0023] i) Reading out consecutive digital audio samples of the second digital audio stream from the transmit buffer according to a first system clock signal of the first device;

[0024] j) Increasing or decreasing the second system clock frequency to match the first system clock frequency based on a detected overflow event and underflow event of the transmit buffer or a detected overflow event and underflow event of the receive buffer.

[0025] The one-way or two-way wireless data communication link may be based on near-field magnetic coupling using respective magnetic coil antennas of a first hearing device and a second hearing device, such as NFMI. The one-way or two-way wireless data communication link may use, for example, a carrier frequency between 5 and 50 MHz, as discussed in more detail below with reference to the accompanying drawings.

[0026] According to one embodiment of the method of adjusting the system clock frequency of a hearing system, step g) includes the following steps:

[0027] - In response to an overflow event in the receive buffer or optionally in response to an underflow event in the transmit buffer (if the latter exists in the second hearing device), increase the second system clock frequency of the second device; and / or

[0028] - In response to an underflow event in the receive buffer or an overflow event in the transmit buffer (if the latter exists in the second hearing device), decrease the second system clock frequency.

[0029] The frequency of the second system clock can be adjusted, for example, in frequency steps of a predetermined size and decreased in frequency steps of a predetermined size. In response to each overflow event in the receive buffer and / or each underflow event in the transmit buffer, the increase in the second system clock frequency can be performed in a single frequency step, for example, by a second digital processor of the second headset hearing device; and in response to each underflow event in the receive buffer and / or each overflow event in the transmit buffer, the decrease in the second system clock frequency can likewise be performed in a single frequency step, for example, by the second digital processor. The predetermined size of the frequency step can correspond, for example, between 0.5 ppm and 5 ppm of the nominal system clock frequency of the second device. The nominal value of the second system clock frequency of the second headset hearing device can be between, for example, 2 MHz and 64 MHz, depending on the battery resources and computational requirements of the particular type of headset hearing device. The nominal value of the first system clock frequency of the first headset hearing device can be in the same range.

[0030] The processor of the second headset hearing device (such as a digital processor like a software-programmable CPU or a software-programmable or hard-wired DSP) can adjust the second system clock frequency by repeatedly writing the clock frequency setting to a digital control or configuration register of a system clock generator configured to generate the second system clock signal, as discussed in more detail below with reference to the accompanying drawings.

[0031] One embodiment of the method of adjusting the system clock frequency of the second headset hearing device includes, for example, repeatedly writing the current clock frequency setting to a non-volatile memory address or location of the second headset hearing device by a digital processor (such as the CPU or DSP of the second headset hearing device). The digital processor can be configured to repeatedly write the current clock frequency setting not only to a digital configuration register but also to a non-volatile memory address or location of a non-volatile memory (such as flash memory or EEPROM) of the second headset hearing device. The digital processor can read the stored clock frequency setting from the non-volatile memory location at startup or boot-up, for example, caused by the power-on of the second headset hearing device, and use the restored clock frequency setting as a good starting point for the desired or target clock frequency of the master clock signal used in the opposing or first headset hearing device.

[0032] According to another embodiment of the present method, there is a delay or pause of at least 100 ms (e.g., more than 500 ms) after each increase or decrease in the second system clock frequency, without any frequency adjustment occurring independently of any underflow and overflow events. The pause is beneficial because it limits the speed at which the carrier frequency of a wireless data communication link can change or move, as discussed in more detail below with reference to the accompanying drawings.

[0033] Those skilled in the art will understand that the detection of overflow and underflow events in the receive buffer and / or transmit buffer can be performed by the second digital processor in a variety of ways. According to one embodiment, an overflow event is detected in response to the receive buffer and / or transmit buffer being full in terms of physical memory location or address, and an underflow event is similarly detected in response to the physical memory location or address of the receive buffer and / or transmit buffer being empty. According to an alternative embodiment, an overflow event is detected in response to exceeding a certain maximum memory threshold or upper limit associated with the receive buffer and / or associated with the transmit buffer, even if the buffer in question is not completely full in terms of physical storage location or address. Similarly, an underflow event can be detected in response to crossing or exceeding a certain minimum or lower memory threshold or limit associated with the receive buffer and / or associated with the transmit buffer, even if the buffer in question is not completely empty in terms of physical storage location or address. This detection of overflow and underflow events by using maximum or minimum memory thresholds respectively can be regarded as the detection of early warnings of impending overflow or underflow events and allows the digital processor to take appropriate corrective measures.

[0034] One embodiment of the present method relies on detecting overflow and underflow events by using maximum or minimum memory thresholds respectively, and includes the following steps:

[0035] - Mark an overflow event in the receive buffer in response to consecutive digital audio samples of the first digital audio stream exceeding a predetermined maximum address or threshold of the receive buffer,

[0036] - Mark an underflow event in the receive buffer in response to consecutive digital audio samples of the first digital audio stream being below a predetermined minimum address or threshold of the receive buffer; and / or

[0037] - Mark an overflow event in the transmit buffer in response to digital audio samples of the second digital audio stream exceeding a predetermined maximum address or threshold of the transmit buffer,

[0038] - Mark an underflow event in the transmit buffer in response to digital audio samples of the second digital audio stream being below a predetermined minimum address or threshold of the transmit buffer.

[0039] Each of the receive buffer and the transmit buffer may have a relatively small size, for example, having a storage capacity between 4 and 20 digital audio samples.

[0040] One embodiment of the method uses so-called sample realignment to perceptually hide or mask the audible effects of overflow events and / or underflow events in the receive buffer and / or the transmit buffer, as discussed in more detail below with reference to the accompanying drawings. Such sample realignment may include:

[0041] - Responsive to an underflow event or an overflow event in the transmit buffer, performing sample realignment on the digital audio samples stored in the transmit buffer by, for example, a second digital processor; and / or

[0042] - Responsive to an underflow event or an overflow event in the receive buffer, performing sample realignment on the consecutive digital audio samples stored in the receive buffer by, for example, a second digital processor.

[0043] One embodiment of the method includes the following steps:

[0044] - Generating a first digital audio sample stream by a processor of the second head-mounted hearing device by repeatedly reading the digital audio samples temporarily stored in the receive buffer, and optionally,

[0045] - Generating a second digital audio sample stream by a digital processor of the second head-mounted hearing device by reading the digital audio samples generated by a microphone device of the second head-mounted hearing device in response to incoming sound. The second processor of the second head-mounted hearing device may be configured to generate various types of bilateral signals based on the first digital audio sample stream and the second digital audio sample stream, such as a bilaterally beamformed microphone signal, which may exhibit high directivity to effectively suppress ambient noise in the sound environment of the hearing aid user, thereby improving speech intelligibility and user comfort.

[0046] A second aspect of the invention relates to a hearing system, comprising:

[0047] A first device, which includes a first microphone device, a first digital processor, a first system clock generator configured to provide a master clock signal at a master clock frequency, and a first data communication interface configured to transmit and receive data via a wireless data communication link;

[0048] Wherein the data transmission clock of the wireless data communication link is set by the master clock frequency; and

[0049] A second hearing device, which includes a second digital processor, a second system clock generator configured to provide a slave clock signal with an adjustable clock frequency, and a second data communication interface configured to receive data via the wireless data communication link;

[0050] The second data communication interface and / or the second digital processor are configured to:

[0051] - Receive and decode input data to generate a first digital audio stream,

[0052] - Write consecutive audio samples of the first digital audio stream to a receive buffer of the second data communication interface for temporary storage according to a data transfer clock,

[0053] - Read consecutive digital audio samples of the first digital audio stream from the receive buffer according to a slave clock signal,

[0054] - Based on detected overflow and underflow events of the receive buffer, increase or decrease the frequency of the slave clock signal to match the master clock frequency.

[0055] Those skilled in the art will understand that the second data communication interface and the second digital processor may actually be fully or at least partially integrated on a common semiconductor circuit, such that the functions of the second data communication interface can be implemented by a combination of analog and digital hardware and executable program instructions executed by the second digital processor.

[0056] Those skilled in the art will understand that certain embodiments of the second hearing device may include a hearing aid and additionally include a microphone device for receiving incoming sound. Alternative embodiments of the second hearing device such as a cochlear implant may not have its own microphone device and receive a digital audio stream derived from the microphone signal of the first head-mounted hearing device via the one-way or two-way wireless data communication link discussed previously.

[0057] The second digital processor of the second device may be configured to increase or decrease the slave clock frequency in a step of a predetermined size according to the above method. The first digital processor of the first device of the hearing system may also be configured to perform hearing loss compensation on the digital audio stream derived from the microphone signal provided by the first microphone device in response to incoming sound.

[0058] A third aspect of the present invention relates to a hearing device, such as the second head-mounted hearing device described above, such as a hearing aid of the BTE, ITE, ITC, CIC or RIC type or the cochlear implant described above. The hearing device may include:

[0059] - An adjustable system clock generator configured to provide an adjustable system clock frequency,

[0060] - A digital processor that operates according to the adjustable system clock frequency,

[0061] - A data communication interface at least configured to receive data via a wireless data communication link; the data communication interface and / or the digital processor are configured to:

[0062] - Receive and decode input data from a wireless data communication link to provide a first digital audio stream,

[0063] - Write consecutive digital audio samples of the first digital audio stream into a receive buffer for temporary storage according to the data transmission clock of the wireless data communication link,

[0064] - Read consecutive digital audio samples of the first digital audio stream from the receive buffer according to an adjustable system clock frequency,

[0065] - Increase or decrease the adjustable system clock frequency based on overflow events and underflow events detected in the receive buffer to match the frequency of the data transmission clock. BRIEF DESCRIPTION OF THE DRAWINGS

[0066] In the following, exemplary embodiments of the present invention will be described in more detail with reference to the accompanying drawings, in which:

[0067] Figure 1 Schematically shows a binaural or bilateral hearing aid system according to an exemplary embodiment of the present invention, which includes a left ear hearing aid and a right ear hearing aid connected by a bidirectional wireless data communication channel;

[0068] Figure 2 Shows a block diagram of the right ear hearing aid of a binaural or bilateral hearing aid system operating as a slave device according to a first embodiment of the present invention;

[0069] Figure 3 Schematically shows the operation and data content of the receive buffer and the transmit buffer of an exemplary wireless communication interface of the right ear hearing aid; and

[0070] Figure 4 Is a flowchart of system clock frequency adjustment executed by a digital processor of the right ear hearing aid according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0071] Various exemplary embodiments of this hearing system will be described below with reference to the accompanying drawings. Those skilled in the art will understand that the drawings are schematic and simplified for clarity, and thus only show the details essential for understanding the present invention, while omitting other details. The same reference numerals always refer to the same elements. Therefore, the same elements do not need to be described in detail for each drawing.

[0072] Figure 1A binaural or bilateral hearing system 12 is schematically shown, which includes a left ear wearable hearing device or hearing aid 10L and a right ear wearable hearing device or hearing aid 10R, each of which includes at least one wireless communication interface 34L, 34R for connecting to the other hearing device. In this embodiment, the left and right ear hearing aids 10L, 10R are interconnected by a unidirectional or bidirectional wireless data communication connection or link 5, which supports real-time streaming of digital or digitized audio signals (such as digital microphone signals) at least from the left ear hearing aid 10L to the right ear hearing aid 10R, but preferably in both directions. Each of the left ear wearable hearing device 10L and the right ear wearable hearing device 10R may include a conventional hearing aid, such as a so-called BTE, ITE, ITC, CIC or RIC type hearing aid, wherein the shape and size of at least one housing portion are adapted to be placed at or in the user's left or right ear. A unique ID code or number may be associated with each of the left ear hearing device 10L and the right ear hearing device 10R to verify identity before initializing any data exchange. Each of the wireless communication interfaces 34L, 34R may include a magnetic coil antenna 15L, 15R and be based on near-field magnetic coupling, such as NFMI operating at a carrier frequency between 5 and 50 MHz (such as between 5 - 15 MHz, for example 10.66 MHz). The protocol that controls the sending and receiving of data, such as data organized or structured as individual data packets, through the bidirectional wireless data communication connection or link 5 may be a proprietary protocol that is robust to EMI interference and results in low power consumption. The data exchanged between the hearing devices 10L, 10R through the bidirectional wireless data communication connection or link 5 may include real-time digital audio signals, particularly various types of digital microphone signals. Each of the data packets may, for example, include a header portion that holds various types of protocol-related parameters and control information and a payload portion that includes a plurality of digital audio signal samples, such as digital microphone signal samples between 2 and 512 digital audio signal samples.

[0073] One of the left ear hearing device 10L and the right ear hearing device 10R of the binaural hearing system 50 is preferably designated as the main hearing device, and the opposite one is designated as the slave hearing device, for example, during the fitting or adaptation of the hearing system for the user. Those skilled in the art will understand that the system clock signal of the main hearing device can control the data transmission clock or frequency on the bi-directional wireless data communication link 5 or through the bi-directional wireless data communication link 5 via the transport layer of the protocol, as discussed in more detail below. In certain embodiments of the present hearing system, the left ear hearing device 10L and the right ear hearing device 10R may be substantially the same in terms of hardware components and circuits. The unique identification of each of the left ear hearing device 10L and the right ear hearing device 10R may be provided by certain parameters, identifiers (such as the aforementioned unique ID), and possibly software routines. Therefore, the following description of the features, components, and signal processing functions of the left ear hearing device 10L may also be applied to the right ear hearing aid 10R in a corresponding manner, and vice versa. The left ear hearing aid 10L may include a ZnO2 battery (not shown) or a rechargeable battery connected to supply power to the hearing aid circuit 13L. The left ear hearing device 10L includes a microphone device 16L, which preferably includes at least a first omnidirectional microphone and a second omnidirectional microphone, as discussed in more detail below.

[0074] Another embodiment of the present hearing system 50 includes a head-mounted hearing device 10L, which may include a BTE housing portion, while the second hearing device 10R is or at least includes an implant component or device located in the user's skull and configured to provide an audio stimulation signal to the user's auditory nerve through an implanted electrode array. The left ear hearing device 10L includes an optional second wireless communication interface 42L and an RF antenna 44L, which are configured to communicate via a second wireless communication link 50. The second wireless communication link 50 and the interface may be configured to operate in the 2.4 GHz Industrial, Scientific, and Medical (ISM) frequency band and may comply with the Bluetooth LE standard. Due to the industry standard compatible characteristics of the second wireless communication link 50 and the interface 42L, the second wireless communication link 50 may provide a convenient data connection to various types of portable communication devices (such as smartphones, mobile phones, tablets, and personal computers, etc.). The right ear hearing device 10R may include a similar optional second wireless communication interface 42R and an RF antenna 44R, as shown for the same purpose.

[0075] The right ear hearing device 10R further includes a digital processor 24R, which may include a hearing loss processor or algorithm and other types of microphone signal processing functions and algorithms. Those skilled in the art will understand that each of the digital processors 24L, 24R may include a software programmable microprocessor, such as a programmable digital signal processor (DSP). The operation of each of the left ear hearing device 10L and the right ear hearing device 10R may be controlled by a suitable operating system executed on the software programmable microprocessor. The operating system may be configured to manage hearing aid hardware and software resources, such as including communication protocol processing, calculation of single-ear or bilateral beamformed microphone signals, hearing loss compensation processing of (one or more) microphone signals, the first wireless data communication interface 34L and the second wireless data communication interface 42L, certain memory resources, etc. The operating system may schedule tasks to efficiently use the hearing device resources, and may further include accounting software for cost allocation, including power consumption, processor time, memory location, wireless transmission, and other resources. The digital processor 24R may be configured, for example, to perform single-ear beamforming on the digital microphone signals provided by the microphone device 16R of the right ear hearing device 10R. The digital processor 24R may additionally or alternatively be configured to perform bilateral beamforming based on a combination of ipsilateral microphone signals (i.e., the digital microphone signals provided by the microphone device 16R) and one or more contralateral digital microphone signals, as discussed in more detail below. The hearing loss processor is preferably configured to compensate for the hearing loss of the user or patient of the right ear hearing device 10R. To this end, the hearing loss processor may include, for example, a known dynamic range compressor circuit or digital signal processing algorithm for compensating for the frequency-dependent loss of the user's dynamic range - which is commonly designated as recruitment in the art. Thus, the digital processor 24R generates and outputs a bilateral or single-ear beamformed microphone signal with additional hearing loss compensation to the speaker or receiver 32R. The speaker or receiver 32R converts the beamformed and compensated microphone signal into a corresponding acoustic signal for transmission into the user's right ear canal.

[0076] The right ear hearing device 10R further includes a system clock generator or system clock circuit 37R, which is configured to provide corresponding clock signals to one or more digital logic circuits and components of the hearing aid circuit 13L, specifically including the schematically shown digital processor 24R. As shown, the RF wireless communication interface 42R is preferably timed by the slave clock signal, where the RF wireless communication interface 42R may include a clock multiplier circuit to increase the frequency of the slave clock signal multiple times to provide the carrier frequency of the RF wireless communication interface 42R, such as 2.4 GHz. The left ear hearing device 10L includes a similar system clock generator 37L, which is configured to provide a master clock signal (not shown) to various similar digital logic circuits and components of the hearing device 10L.

[0077] Each of the system clock generators 37L, 37R preferably includes a crystal oscillator so that the master clock signal and the slave clock signal have good accuracy and stability. Each of the system clock generators 37L, 37R can be configured to provide or generate a nominal frequency of the master clock signal and the slave clock signal between 10 MHz and 64 MHz (e.g., approximately 32 MHz). The system clock generator 37L of the left ear hearing device 10L can be configured to provide a substantially fixed master clock frequency or a programmable clock frequency. Those skilled in the art will understand that if the relevant hardware components and circuits of the right ear hearing device 10R and the left ear hearing device 10L are the same, the functions of the system clock generators 37L, 37R as the master clock generator and the slave clock generator, respectively, can be interchanged as needed. The operations as the master hearing device and the slave hearing device can be defined or programmed, for example, during the fitting of the hearing aid system by appropriately setting various programming parameters in a non-volatile memory area or address (not shown) of each of the right ear hearing device 10R and the left ear hearing device 10L.

[0078] As described above, the accuracy of commercially available crystal-based clock generators is limited and may have a tolerance of approximately + / -30 ppm relative to the nominal clock frequency, which results in the differences, misalignments, or offsets between the frequencies of the master clock signal and the slave clock signal of the left ear hearing device 10L and the right ear hearing device 10R discussed previously. At least the system clock generator 37R of the right ear hearing device 10R can be adjustable or programmable to allow the slave clock signal (not shown) to be increased or decreased in a well-defined manner, e.g., continuously or by frequency steps relative to the nominal or current frequency of the slave clock signal. This adaptive clock frequency adjustment is preferably performed so as to match or align the frequency of the slave clock signal with the frequency of the master clock signal. Those skilled in the art will understand that the sampling frequency of the digital audio samples processed by the digital processor 24L of the left ear hearing device 10L can be proportional to or locked to the frequency of the slave clock signal provided by the system clock generator 37R, while the sampling frequency of the digital audio samples processed by the digital processor 24R of the right ear hearing device 10R and provided through the wireless communication interface 34R can be proportional to the frequency of the master clock signal provided by the system clock generator 37L.

[0079] Figure 2 is a schematic block diagram of an exemplary embodiment of a right ear head-mounted hearing device or hearing aid 10R of the above-described binaural or bilateral hearing system 50. The wireless communication interface 34R is configured to receive and decode input data packets from the magnetic coil antenna 15R to provide a first digital audio stream. Successive digital audio samples of the first digital audio stream are written into the receive buffer Rx for temporary storage and are subsequently processed by the digital processor 24R through a proprietary or standardized bi-directional data interface 17R (e.g., l2 C-compatible interface or l 2 read out, etc. The consecutive digital audio samples of the first digital audio stream are written into the receive buffer Rx synchronously with the data transmission clock on the wireless channel 5, i.e., synchronously with the master clock signal retrieved by the wireless communication interface 34R. This process is performed by Figure 3 schematically shown, where the most recent digital audio sample CF1A is written to the lowest address of the receive buffer Rx, for example, using a suitably configured digital state machine or controller (not shown) of the wireless communication interface 34R, which is timed or operates in synchronization with the retrieved master clock signal CLK_M. The actual receive buffer Rx may have a physical size that stores 4 to 40 digital audio samples (e.g., approximately 5 audio samples). Each digital audio sample may include 12 to 20 bits. The actual transmit buffer Tx may have the same storage capacity and other attributes.

[0080] On the other hand, the oldest, i.e., the earlier received digital audio sample XXXX is read from the highest memory address or cell of the receive buffer Rx synchronously with the slave clock signal CLK_S, since both the digital processor 24R and the bidirectional data interface 17R are timed or clocked by the latter clock signal and thus operate in synchronization with the slave clock signal CLK_S. Therefore, the reading or writing of digital audio samples into the receive buffer Rx is controlled by the master clock signal CLK_M, while the reading out of digital audio samples is controlled by the slave clock signal CLK_S. Since the system clock generators 37L and 37R are physically separate and independently operating components, an inevitable deviation or mismatch between the frequencies of the master clock signal CLK_M and the slave clock signal CLK_S will, over time, due to the finite length / size of the buffer, result in an overflow event or an underflow event in the receive buffer Rx. If the frequency of the master clock signal is higher than the frequency of the slave clock signal, after a time interval set by the frequency deviation and the size of the buffer, the Rx buffer will overflow, i.e., run out of unused or empty memory cells or addresses, because digital audio samples are written into the buffer at a higher frequency than they are read out again.

[0081] If the frequency of the master clock signal is lower than the frequency of the slave clock signal, after a time interval set by the frequency deviation between the master clock signal and the slave clock signal and the size of the buffer, the receive buffer Rx will underflow as a response, i.e., the digital audio samples will become empty. This occurs because the digital audio samples are written to the buffer at a lower frequency than they are read out again. Similarly, if the frequency of the master clock signal is higher than the frequency of the slave clock signal, the receive buffer Rx will overflow as a response because the digital audio samples are written to the buffer more frequently, i.e., at a higher rate, than they are read out again. The underflow and / or overflow events that occur periodically in the Rx buffer can be hidden by the digital state machine or controller of the wireless communication interface 34R using the sample realignment algorithm mentioned above. The digital state machine can be configured, for example, to monitor the storage utilization of the Rx buffer, and if the latter is emptied beyond a certain or predetermined minimum address or threshold (shown as Rx_th-low in Figure 3 ), the digital state machine can be configured to flag or indicate the underflow event of the receive buffer Rx to the digital processor 24R. The digital state machine can also continue to repeat or copy the remaining digital audio samples CF1A to adjacent addresses of the Rx buffer to prevent the Rx buffer from being empty and thus underflowing.

[0082] In the opposite case where the memory cells of the Rx buffer are full or occupied beyond a predetermined maximum address or threshold of the Rx buffer (not shown), the digital state machine can be configured, for example, to flag or indicate the overflow event of the receive buffer Rx to the digital processor 24R and continue to further remove or delete the digital audio samples to prevent the Rx buffer from exhausting the physical memory and overflowing due to the latter reason. Those skilled in the art will understand that the memory cells of each of the receive buffer Rx and the transmit buffer Tx can include volatile memory, such as RAM or register file, etc. The volatile memory can be formed integrally with the digital processor 24R on a common semiconductor substrate, or the volatile memory can be arranged on a separate memory device.

[0083] Figure 3Also schematically shown is the corresponding operation of the transmit buffer Tx, where successive digital audio samples of the second digital audio stream generated by the right ear head-mounted hearing device 10R are written into the Tx buffer by the digital state machine of the wireless communication interface 34R to be temporarily stored synchronously with the clock signal CLK_S and thus be subject to the timing control of the latter. The second digital audio stream (where the digital audio samples or signals may represent digital microphone signals obtained from the microphone device 16R) may be sent by the digital processor 24R to the digital state machine of the wireless communication interface 34R via the bidirectional data interface 17R. The digital state machine repeatedly writes the received digital audio samples to the appropriate address or location in the transmit buffer Tx. At the same time, the earlier stored digital audio samples are read out from the highest memory address or cell in the transmit buffer Tx synchronously with the retrieved master clock signal CLK_M, since the timing and clock frequency on the wireless communication interface 5 as described above are controlled by the latter. Thus, in a manner corresponding to the receive buffer Rx, the transmit buffer Tx will periodically suffer from overflow events and / or underflow events over time due to clock frequency mismatch or offset and the limited length of the Tx buffer, unless preventive measures as described below are taken. These overflow events and underflow events in the transmit buffer Tx are preferably handled in a manner corresponding to those in the receive buffer Rx by using sample realignment when needed.

[0084] Sample realignment can be triggered by the data content (stored digital audio samples) in the Tx buffer being below the previously discussed minimum address or threshold or location (such as Figure 3 Tx_th-low as shown) or exceeding the previously discussed predetermined maximum address or threshold (such as Figure 3 Tx_th-up as shown). Thus, the digital state machine or controller of the wireless communication interface 34R is preferably configured to mark or indicate the above-mentioned overflow and underflow events in at least one of the transmit buffer Tx and the receive buffer Rx. Those skilled in the art will understand that strictly speaking, since the transmit buffer Tx and the receive buffer Rx operate in opposite manners to each other, it is only necessary to monitor the overflow and underflow events of one of the transmit buffer Tx and the receive buffer Rx. In some embodiments of the present invention, the digital state machine of the wireless communication interface 34R may be configured to indirectly indicate the above-mentioned overflow and underflow events by marking the corresponding sample realignment operations / events in the transmit buffer Tx and / or the receive buffer Rx. Thus, the digital state machine may be configured to mark or indicate such sample realignment events to the digital processor 24R by specifically indicating in which of the Rx buffer and the Tx buffer the sample realignment occurs and whether the sample realignment is caused by an overflow or underflow of the buffer under discussion.

[0085] The digital processor 24R is configured to perform an adaptive adjustment of the frequency of the slave clock signal generated by the system clock generator 37R based on the overflow and underflow events in the transmit buffer Tx discussed above, as discussed in the flowchart of Figure 2 and Figure 4 discussed. As Figure 2 schematically shown, the system clock generator 37R may include a digital control or configuration register 35R, which may be accessed and written by the digital processor 24R or possibly by another processor of the device circuitry 13R. The digital processor 24R may include, for example, a digital output port P_1 connected to the digital control or configuration register 35R for writing a clock frequency setting to the digital control or configuration register 35R, for example, according to an absolute frequency setting or as a frequency change value, such as increasing the current clock frequency by one frequency step or decreasing the current clock frequency by one frequency step. Alternatively, the wireless communication interface 34R may include a separate digital processor (e.g., a suitably configured digital state machine) that directly writes the clock frequency setting to the digital control or configuration register 35R. In both cases, each frequency step of the clock configuration register may result in a specific relative clock frequency adjustment, for example, between 0.5 ppm and 5 ppm of the nominal system clock frequency. Thus, if the nominal system clock frequency is 32 MHz, the minimum frequency step may correspond to an absolute clock frequency adjustment between 16 Hz and 160 Hz.

[0086] According to an embodiment of the present invention, the digital processor 24R is configured to repeatedly write the current clock frequency setting to a non-volatile memory address or location of the non-volatile memory of the second headset hearing device 10R in addition to writing it to the digital control or configuration register 35R of the system clock generator 37R. At startup or power-on of the digital processor 24R, the latter may read the stored clock frequency setting from the non-volatile memory address or location and use it as a good starting point, i.e., relatively close to the true clock frequency of the master clock signal in the relative hearing device 10L, to further adjust the slave clock frequency. Thus, a small clock offset between the master clock signal and the slave clock signal is ensured immediately after startup or power-on of the current hearing device system rather than waiting for the adaptive adjustment of the slave clock frequency to eventually minimize the clock offset during operation of the hearing system after each system startup.

[0087] In Figure 4In step 401, during monitoring of activities on the wireless communication interface 34R, an adjustment of the clock frequency of the system clock generator 37R is triggered by the digital processor 24R, where the digital processor 24R receives an underflow event or an overflow event marked by the digital state machine of the wireless communication interface 34R. The digital processor 24R proceeds to step 403 in response to the detected event and checks whether the event is a sample realignment event performed by repeating or duplicating digital audio samples stored in the transmit buffer Tx. If this is the case (Y), the digital processor 24R proceeds to step 405 and increases the clock frequency of the clock signal CLK_S by a single frequency step as described above. The increase in the clock frequency of the clock signal CLK_S is performed because the repetition of digital audio samples in the transmit buffer Tx indirectly indicates an upcoming underflow event in the transmit buffer Tx. This in turn means that the clock frequency of the clock signal CLK_S is lower than the clock frequency of the master clock signal CLK_M, causing the transmit buffer Tx to gradually empty, and this situation is counteracted by an increase in the frequency of the clock signal CLK_S. The digital processor 24R then proceeds to step 411, which is an optional pause of a predetermined duration, where no further adjustment of the clock frequency of the clock signal CLK_S is performed. The predetermined pause duration can be at least 100 ms, for example more than 500 ms. The pause can be beneficial because it limits the speed at which the carrier frequency of the two-way wireless data communication link 5 can be offset, assuming that the carrier frequency is derived from the system clock generator 37. A slower change in the carrier frequency of the two-way wireless data communication link 5 enhances the quality and stability of the wireless connection and suppresses audible artifacts in the wireless connection, such as audible artifacts caused by the sample realignment discussed previously.

[0088] If in step 403 the digital processor 24R determines, in response to a sample realignment event, that the event is not a duplicate of the digital audio samples stored (N) in the transmit buffer Tx, the digital processor 24R proceeds to step 407 and checks whether the event is a sample removal. If the latter condition is true (Y), the digital processor 24R proceeds to step 409 and reduces the clock frequency of the clock signal CLK_S by a single frequency step as described above. If the check in step 407 instead results in a negative answer (N), the digital processor 24R may jump back to the initial step 401 and wait for a new event. The final reduction of the clock frequency of the clock signal CLK_S is performed in step 409 because the deletion or removal of the digital audio samples in the transmit buffer Tx indirectly indicates an overflow event in the transmit buffer Tx. This in turn means that the clock frequency of the clock signal CLK_S is higher than the clock frequency of the master clock signal CLK_M, leading to a potential overflow of the transmit buffer Tx unless corrective measures are taken. This potential overflow situation is preferably counteracted by reducing the frequency of the clock signal CLK_S. After step 409, the digital processor 24R proceeds to step 411 and maintains the optional pause as described above. After the pause period has elapsed, the digital processor 24R returns to the initial step 401, where it waits for a new event.

[0089] Those skilled in the art will understand that the above-described adaptive adjustment of the clock frequency of the slave clock signal CLK_S of the system clock generator 37R performed by the digital processor 24R of the right ear hearing device 10R will tend over time to align the frequency of the slave clock signal CLK_S with the frequency of the master clock signal CLK_M. The speed of this adjustment loop depends in particular on the pause period during the adjustment process and the size of each frequency step of the slave clock signal CLK_S. The digital processor 24R uses the overflow and underflow events of the receive buffer Rx or the transmit buffer Tx to determine in which direction (i.e., up / down) the current frequency of the slave clock signal must be adjusted. This process allows the frequency of the slave clock signal CLK_S to continuously or repeatedly track the change in the clock frequency of the master clock signal over time, thereby minimizing the clock offset between the corresponding clock signals of the system clock generator 37L of the left ear hearing device 10L and the system clock generator 37R of the right ear hearing device 10R.

Claims

1. A method for adjusting the system clock frequency of a hearing system including a first device and a second device, the method comprising the following steps: a) Establishing a wireless data communication link between the first device and the second device through their respective data communication interfaces; b) Transmitting data from the first device to the second device through the wireless data communication link; c) Receiving data through the data communication interface of the second device; d) Decoding the data by the second device to extract a first digital audio stream; e) Writing consecutive digital audio samples of the first digital audio stream into the receive buffer of the second device according to a data transmission clock, wherein the data transmission clock is based on a first system clock frequency of the first device; f) Reading consecutive digital audio samples of the first digital audio stream from the receive buffer according to a second system clock frequency of the second device; g) Increasing or decreasing the second system clock frequency to match the first system clock frequency based on a detected overflow event and a detected underflow event of the receive buffer of the second device.

2. The method according to claim 1, wherein the wireless data communication link is bidirectional; The method further comprises the following steps: h) Writing digital audio samples of a second digital audio stream generated by the second device into the transmit buffer of the second device for temporary storage according to a second system clock signal of the second device; i) Reading consecutive digital audio samples of the second digital audio stream from the transmit buffer according to the first system clock frequency of the first device; j) Increasing or decreasing the second system clock frequency to match the first system clock frequency based on a detected overflow event and underflow event of the transmit buffer of the second device or a detected overflow event and underflow event of the receive buffer of the second device.

3. The method according to claim 2, wherein step g) comprises the following steps: - Increasing the second system clock frequency of the second device in response to an overflow event in the receive buffer or an underflow event in the transmit buffer; and / or - Decreasing the second system clock frequency in response to an underflow event in the receive buffer or an overflow event in the transmit buffer.

4. The method according to claim 1, wherein step g) further comprises the following steps: - Increasing the second system clock frequency in frequency steps of a predetermined size and decreasing the second system clock frequency in frequency steps of a predetermined size.

5. The method according to claim 2, further comprising the following steps: - Increasing the second system clock frequency by a single frequency step in response to each overflow event in the receive buffer and / or each underflow event in the transmit buffer; and - Decreasing the second system clock frequency by a single frequency step in response to each underflow event in the receive buffer and / or each overflow event in the transmit buffer.

6. The method according to claim 4 or 5, wherein the predetermined size of the frequency step corresponds to between 0.5 ppm and 5 ppm of the nominal system clock frequency.

7. The method according to claim 2, wherein the processor of the second device adjusts the second system clock frequency by repeatedly writing a clock frequency setting to a digital control or configuration register of a system clock generator that generates a second system clock signal.

8. The method according to claim 6, further comprising the steps of: - Repeatedly writing a current clock frequency setting to a non-volatile memory address or location of the second device by the processor.

9. The method according to claim 1, wherein there is a pause of at least 100 ms after each increase or decrease of the second system clock frequency, without any frequency adjustment occurring independently of any underflow event and overflow event.

10. The method according to claim 9, wherein there is a pause of more than 500 ms after each increase or decrease of the second system clock frequency, without any frequency adjustment occurring independently of any underflow event and overflow event.

11. The method according to claim 2, further comprising the steps of: - Marking an overflow event in the receive buffer in response to consecutive digital audio samples of a first digital audio stream exceeding a maximum address or threshold of the receive buffer, - Marking an underflow event in the receive buffer in response to consecutive digital audio samples of a first digital audio stream falling below a minimum address or threshold of the receive buffer; and / or - Marking an overflow event in the transmit buffer in response to digital audio samples of a second digital audio stream exceeding a maximum address or threshold of the transmit buffer, - Marking an underflow event in the transmit buffer in response to digital audio samples of a second digital audio stream falling below a minimum address or threshold of the transmit buffer.

12. The method according to claim 2, further comprising the steps of: - Performing sample realignment on consecutive digital audio samples stored in the receive buffer in response to an underflow event or an overflow event in the receive buffer; and / or - Performing sample realignment on digital audio samples stored in the transmit buffer in response to an underflow event or an overflow event in the transmit buffer.

13. The method according to claim 2, further comprising the steps of: - Generating a first digital audio sample stream by the processor of the second device by repeatedly reading digital audio samples temporarily stored in the receive buffer, - Generating a second digital audio sample stream by the processor of the second device by reading digital audio samples generated by a microphone device of the second device in response to incoming sound, - Generating a bilateral beamforming signal by the processor of the second device based on the first digital audio sample stream and the second digital audio sample stream.

14. A hearing system, comprising: A first device, comprising a first microphone device, a first digital processor, a first system clock generator configured to provide a main clock signal at a main clock frequency, and a first data communication interface configured to transmit and receive data via a wireless data communication link; wherein a data transmission clock of the wireless data communication link is set by the main clock frequency; and A second device, comprising a second digital processor, a second system clock generator configured to provide a slave clock signal having an adjustable clock frequency, and a second data communication interface configured to receive data via the wireless data communication link; The second data communication interface and / or the second digital processor are configured to: - Decode the data to generate a first digital audio stream, - Write consecutive audio samples of the first digital audio stream into a receive buffer of the second data communication interface for temporary storage according to the data transmission clock, - Read consecutive digital audio samples of the first digital audio stream from the receive buffer according to the slave clock signal, - Increase or decrease the frequency of the slave clock signal to match the master clock frequency based on a detected overflow event and a detected underflow event of the receive buffer.

15. The hearing system according to claim 14, wherein the first data communication interface includes a first magnetic coil antenna, and the second data communication interface includes a second magnetic coil antenna, and the first magnetic coil antenna and the second magnetic coil antenna are configured to support a bidirectional or unidirectional wireless data communication link based on near-field magnetic coupling between the first magnetic coil antenna and the second magnetic coil antenna.

16. The hearing system according to claim 14 or 15, wherein at least one of the first device and the second device includes a head-mounted hearing device.

17. The hearing system according to claim 16, wherein, The head-mounted hearing device is a hearing aid, a hearing instrument, headphones or active ear protectors.

18. A hearing device, comprising: - An adjustable system clock generator configured to provide an adjustable system clock frequency, - A digital processor operating according to the adjustable system clock frequency, - A data communication interface configured to at least receive data via a wireless data communication link; the data communication interface and / or the digital processor are configured to: - Decode the data to provide a first digital audio stream, - Write consecutive digital audio samples of the first digital audio stream into a receive buffer for temporary storage according to the data transmission clock of the wireless data communication link, - Read consecutive digital audio samples of the first digital audio stream from the receive buffer according to the adjustable system clock frequency, - Increase or decrease the adjustable system clock frequency based on an overflow event and an underflow event detected in the receive buffer to match the frequency of the data transmission clock.

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