A high-precision cascade inverter synchronous control method

Abstract

The present invention discloses a high-precision cascade inverter synchronous control method, comprising: using a main controller to periodically send fundamental wave data and control instructions to a cascade module controller; using the cascade module controller to receive the fundamental wave data and control instructions, and using a synchronization detection unit provided therein to record a serial communication signal at a sampling frequency that is a multiple of the communication baud rate, and determining a clock offset based on the time interval between two adjacent level changes in the serial communication signal; using a synchronization counting unit provided in the cascade module controller to correct a synchronization counting unit counter based on the clock offset; adjusting a carrier counting unit counter based on the corrected synchronization counting unit counter; comparing the adjusted carrier counting unit counter with the fundamental wave data to generate a switching signal for a power device, thereby achieving synchronous control of the cascade inverter. The present invention can achieve relatively high precision and stability, and the synchronization level can be selected based on cost and demand.

Description

Technical Field

[0001] The present invention relates to the technical field of inverter synchronous control, and in particular to a high-precision cascade inverter synchronous control method. Background Art

[0002] With the development of modern industry, the control performance of frequency converters needs to be optimized to adapt to more application scenarios. Among them, the control performance of cascaded modular frequency converters is yet to be challenged. Cascaded frequency converters all adopt star-type point-to-point centralized control. The synchronization between cascaded modules and the signal integrity of execution commands will limit the upper limit of the frequency converter's systematic improvement.

[0003] Conventional main controllers and cascade modules have the following control methods:

[0004] 1. Connect the main controller and cascade modules according to the number of signals, such as enable signal, left bridge arm signal, right bridge arm signal, and fault feedback signal;

[0005] Advantages: Fast signal transmission, no loss of switching signals of power devices.

[0006] Disadvantages: The number of connections increases linearly with the module data, resulting in high device implementation costs. For example, a 10-level system with 30 cascaded modules requires 120 signal lines. Poor scalability also increases the difficulty of subsequent maintenance.

[0007] 2. The main controller and cascade modules are connected via full-duplex serial communication, and the signal is transmitted through encoding and decoding

[0008] Advantages: The number of connections is greatly reduced, and there is room for increasing the transmission of other signals and data, such as bypass signals, sensor feedback signals, feedback temperature data, DC voltage data, etc.

[0009] Disadvantages: The switching signal of the power device will lose control accuracy due to the communication frame length, resulting in unpredictable output voltage and current distortion, which cannot be compensated by other means and will affect the control performance of the system.

[0010] Due to cost considerations, most cascade inverter manufacturers use custom communication protocols for data exchange between the main controller and the power modules. This offers a certain degree of flexibility, but also presents technical differences. The communication method is asynchronous, and the communication medium is plastic optical fiber. The higher the transmission bandwidth of the photoelectric conversion module, the more expensive it is. The second connection control implementation method is more common, with a control board built into the cascade module to enable serial communication with the main controller. In theory, signal loss can be reduced by increasing the communication baud rate, but in practice, the baud rate is limited by external hardware conditions.

[0011] In summary, the existing cascade inverter control method mostly chooses the serial communication connection solution, because the defects affect the expansion of application scenarios, especially in high-tech fields such as steel rolling. Summary of the Invention

[0012] In view of the above-mentioned deficiencies in the prior art, the present invention provides a high-precision cascade inverter synchronous control method.

[0013] In order to achieve the above-mentioned object of the invention, the technical solution adopted by the present invention is:

[0014] A high-precision cascade inverter synchronous control method comprises the following steps:

[0015] S1, using the main controller to periodically send fundamental wave data and control instructions to the cascade module controller through the established serial full-duplex communication link;

[0016] S2. Receive fundamental wave data and control instructions using the cascade module controller, and record the serial communication signal using a sampling frequency that is a multiple of the communication baud rate through a synchronous detection unit, and determine the clock offset based on the time interval between two adjacent level changes in the serial communication signal;

[0017] S3, using the synchronous counting unit provided in the cascade module controller to correct the synchronous counting unit counter according to the clock offset;

[0018] S4, adjusting the carrier counting unit counter to be equal according to the corrected synchronization counting unit counter;

[0019] S5. Compare the adjusted carrier counting unit counter with the fundamental wave data to generate a switching signal of the power device, thereby realizing synchronous control of the cascaded inverter.

[0020] Optionally, in step S2, the synchronization detection unit records the serial communication signal at a sampling frequency that is a multiple of the communication baud rate, and determines the clock offset according to a time interval between two adjacent level changes in the serial communication signal, specifically including:

[0021] S2-1, obtain the serial communication baud rate, and set the magnification according to the highest working clock, and determine the sampling frequency according to the serial communication baud rate and the set magnification;

[0022] S2-2, using a synchronous counting unit counter to record the count value of the level change in the serial communication signal in a cyclic counting manner;

[0023] S2-3, calculating the time interval between two adjacent level changes in the serial communication signal based on the count value of level changes in the current serial communication signal and the count value of level changes in the adjacent serial communication signal;

[0024] S2-4. Determine whether the time interval between two adjacent level changes in the serial communication signal satisfies the set multiplier of the counting cycle; if so, determine that no clock offset occurs; otherwise, determine that a clock offset occurs.

[0025] Optionally, in step S2-1, the sampling frequency is determined according to the serial communication baud rate and the set magnification as follows:

[0026] f c =N*f s

[0027] Among them, f c is the sampling frequency, N is the multiplication factor set according to the highest working clock, f s is the serial communication baud rate.

[0028] Optionally, in step S2-3, the time interval between two adjacent level changes in the serial communication signal is calculated based on the count value of level changes in the current serial communication signal and the count value of level changes in adjacent serial communication signals as follows:

[0029]

[0030] Where y is the time interval between two adjacent level changes in the serial communication signal, y1 is the count value of level changes in adjacent serial communication signals, y2 is the count value of level changes in the current serial communication signal, and m*N is the number of cyclic sampling periods.

[0031] Optionally, step S2-4 is specifically as follows:

[0032] Determine whether the time interval between two adjacent level changes in the serial communication signal meets the set multiplier of the counting cycle;

[0033] If y=x*N, it is determined that no clock offset occurs;

[0034] If y=x*N+N±n is satisfied, it is determined that a clock offset n has occurred.

[0035] Optionally, in step S3, the synchronous counting unit provided in the cascade module controller is used to correct the synchronous counting unit counter according to the clock offset:

[0036] If the time interval between two adjacent level changes in the serial communication signal satisfies y=x*N+N+n, then the count of the synchronous counting unit counter is added with the clock offset n;

[0037] If the time interval between two adjacent level changes in the serial communication signal satisfies y=x*N+Nn, the count of the synchronous counting unit counter is subtracted from the clock offset n.

[0038] Optionally, in step S4, adjusting the carrier counting unit counter according to the corrected synchronization counting unit counter is specifically as follows:

[0039] Adjust the counting period of the synchronous counting unit counter and the triangle wave period of the carrier counting unit counter to be an integral multiple, and make the peak moment or low point moment of the triangle wave of the carrier counting unit counter coincide with the jump edge of the synchronous counting unit counter.

[0040] The present invention has the following beneficial effects:

[0041] The present invention sends a serial signal through the main controller, and the synchronous detection unit at the receiving end collects the communication signal to identify the deviation between the counter of the synchronization unit and the clock of the sending end, which can achieve relatively high accuracy and stability, and the synchronization level can be selected according to cost and demand; and by sending the fundamental wave and generating the triangular carrier in the cascade module and then comparing them, compared with the asynchronous system that directly sends the switch control signal, the advantage is that the passing bandwidth is reduced, the real-time performance of the switch control signal is improved, and the distortion of the switch signal and the distortion of the output voltage are not caused, thereby improving the control accuracy of the inverter output voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 The figure is a flow chart of a high-precision cascade inverter synchronous control method according to an embodiment of the present invention.

[0043] Figure 2 The figure is a schematic diagram of the principle of a high-precision cascade inverter synchronous control method in an embodiment of the present invention. DETAILED DESCRIPTION

[0044] The specific embodiments of the present invention are described below to facilitate understanding of the present invention by those skilled in the art. However, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the appended claims, these changes are obvious, and all inventions and creations utilizing the concepts of the present invention are protected.

[0045] like Figure 1 and Figure 2 As shown, the embodiment of the present invention provides a high-precision cascade inverter synchronous control method, including the following steps S1 to S5:

[0046] S1, using the main controller to periodically send fundamental wave data and control instructions to the cascade module controller through the established serial full-duplex communication link;

[0047] In an optional embodiment of the present invention, the present invention first connects the main controller and the cascade module controllers in star point-to-point communication, and establishes a serial full-duplex communication link between the main controller and the cascade module controllers.

[0048] Then the main controller is used to periodically send fundamental wave data (modulated data) and control instructions, such as enable control signal, bypass control signal, blocking control signal, left and right bridge arm exchange signal, etc.

[0049] S2. Receive fundamental wave data and control instructions using the cascade module controller, and record the serial communication signal using a sampling frequency that is a multiple of the communication baud rate through a synchronous detection unit, and determine the clock offset based on the time interval between two adjacent level changes in the serial communication signal;

[0050] In an optional embodiment of the present invention, the present invention utilizes each cascade module controller to receive fundamental wave data and control instructions;

[0051] Then, the synchronous detection unit set up in each cascade module controller records the serial communication signal at a sampling frequency that is a multiple of the communication baud rate, samples and searches for level changes in the serial communication signal, monitors the time interval between two adjacent level changes, and determines whether clock offset occurs through calculation.

[0052] Specifically, in step S2, the synchronization detection unit records the serial communication signal at a sampling frequency that is a multiple of the communication baud rate, and determines the clock offset based on the time interval between two adjacent level changes in the serial communication signal. Specifically, the steps S2-1 to S2-4 are as follows:

[0053] S2-1, obtain the serial communication baud rate, and set the magnification according to the highest working clock, and determine the sampling frequency according to the serial communication baud rate and the set magnification;

[0054] Specifically, the present invention determines the sampling frequency according to the serial communication baud rate and the set magnification as follows:

[0055] f c =N*f s

[0056] Among them, f c is the sampling frequency, f s is the serial communication baud rate, N is the multiplication factor set according to the highest working clock. The larger the value of N, the higher the accuracy of synchronous control. The synchronization accuracy is ±0.5*T c , T c The frequency period is N times the communication baud rate, which does not increase the hardware cost and achieves high-precision synchronization effect.

[0057] S2-2, using a synchronous counting unit counter to record the count value of the level change in the serial communication signal in a cyclic counting manner;

[0058] S2-3, calculating the time interval between two adjacent level changes in the serial communication signal based on the count value of level changes in the current serial communication signal and the count value of level changes in the adjacent serial communication signal;

[0059] Specifically, the present invention uses a synchronous detection unit to record the value y1 of the counter when the level of the most recent communication signal changes, and the value y2 of the counter when the level of the communication signal changes again, thereby calculating the time interval between two adjacent level changes in the serial communication signal:

[0060]

[0061] Where y is the time interval between two adjacent level changes in the serial communication signal, and m*N is the number of sampling periods in the cycle.

[0062] S2-4. Determine whether the time interval between two adjacent level changes in the serial communication signal satisfies the set multiplier of the counting cycle; if so, determine that no clock offset occurs; otherwise, determine that a clock offset occurs.

[0063] Specifically, the present invention determines whether the time interval between two adjacent level changes in the serial communication signal meets the set multiplier of the counting period; the counting period here is the sampling frequency;

[0064] If y=x*N is satisfied, it is determined that no clock offset has occurred; where x is the multiplication factor of the set counting period;

[0065] If y=x*N+N±n is satisfied, it is determined that a clock offset n has occurred.

[0066] The present invention uses a synchronous detection unit to determine whether the time interval between two adjacent level changes meets the set multiplication rate of the counting cycle to detect the clock offset flag N±n and determine the occurrence of clock offset n, so that the counter can select an appropriate counting width to save resources.

[0067] S3, using the synchronous counting unit provided in the cascade module controller to correct the synchronous counting unit counter according to the clock offset;

[0068] In an optional embodiment of the present invention, the present invention receives the clock offset flag N±n detected by the synchronization detection unit by the synchronization counting unit respectively provided in each cascade module controller, and corrects the synchronization counting unit counter according to the clock offset flag N±n as follows:

[0069] If the time interval between two adjacent level changes in the serial communication signal satisfies y=x*N+N+n, then the count of the synchronous counting unit counter is added with the clock offset n;

[0070] If the time interval between two adjacent level changes in the serial communication signal satisfies y=x*N+Nn, the count of the synchronous counting unit counter is subtracted from the clock offset n.

[0071] Specifically, N+n represents the synchronous counting unit counter that needs to be compensated for the smaller count plus the clock offset n, and Nn represents the synchronous counting unit counter that needs to be compensated for the larger count minus the clock offset n. Ultimately, the receiving end's counting frequency is equal to the sending end's clock frequency, thereby maintaining synchronization. The synchronization accuracy is ±0.5*T c .

[0072] S4, adjusting the carrier counting unit counter to be equal according to the corrected synchronization counting unit counter;

[0073] In an optional embodiment of the present invention, the present invention implements carrier synchronization by using a carrier counting unit respectively provided in each cascade module controller according to a modified synchronization counting unit counter.

[0074] Specifically, the count in the carrier counting unit increases and decreases in the form of a triangular wave. Therefore, the present invention adjusts the counting period of the synchronous counting unit counter and the triangular wave period of the carrier counting unit counter to be an integer multiple, and makes the peak moment or low point moment of the triangular wave of the carrier counting unit counter coincide with the jump edge of the synchronous counting unit counter, thereby realizing carrier phase correction and carrier synchronization, and the synchronization accuracy is ±0.5*T c .

[0075] S5. Compare the adjusted carrier counting unit counter with the fundamental wave data to generate a switching signal of the power device, thereby realizing synchronous control of the cascaded inverter.

[0076] In an optional embodiment of the present invention, the present invention compares the fundamental wave data received by each cascade module controller with the adjusted carrier counting unit counter to generate a switching signal for the power device. The switching signal will not lose real-time performance or uncertainty caused by distortion due to serial communication, thereby realizing synchronous control of the cascaded inverter.

[0077] Specifically, the fundamental wave data value is compared with the carrier counter count value. If the fundamental wave data value is greater than the carrier counter count value, a pulse signal of 1 is output; if the fundamental wave data value is less than the carrier counter count value, a pulse signal of 0 is output. The switching signals output by all cascaded modules are synchronized with an accuracy of ±Tc, ultimately achieving synchronous control of the inverter.

[0078] In the present invention, all receiving ends of the cascade modules of the inverter main controller connected in a star shape adopt the same implementation method, thereby realizing source synchronization, and finally achieving the switching signal synchronization of all cascade modules, and realizing the synchronization performance of the inverter internal control based on the star physical structure and software module.

[0079] This invention proposes a high-precision cascade inverter synchronization control method. A main controller transmits a serial signal, and a synchronization detection unit on the receiving end collects the communication signal and identifies the deviation between the synchronization unit's counter and the transmitting end's clock. This method achieves relatively high accuracy and stability, while also enabling the synchronization level to be selected based on cost and demand. The data recovery module and data sorting are conventional in the field. The data recovery module receives and processes serial port data, while the data sorting module parses the output received data into control variables according to predefined communication rules.

[0080] The cascade inverter control implemented based on this method is achieved by sending the fundamental wave and generating a triangular carrier in the cascade module and then comparing them. Compared with the asynchronous system that directly sends the switch control signal, the advantage is that it reduces the passing bandwidth and improves the real-time performance of the switch control signal. It will not cause the distortion of the switch signal and the distortion of the output voltage, thereby improving the control accuracy of the inverter output voltage.

[0081] Using Manchester encoding to achieve clock homology control requires sacrificing 50% of the communication bandwidth; if 8b10b encoding is used, 20% of the bandwidth will be sacrificed, and the addition of a clock recovery module will also place certain requirements on chip resources.

[0082] In addition, the main controller is selected to send synchronization data regularly to synchronize the carrier counter in the cascade module to achieve synchronization, but it increases the amount of communication data and the resource usage of the main controller. The regular synchronization data has the highest transmission priority to ensure the accuracy and stability of synchronization. This method requires the coordination of system control timing and communication data in implementation to avoid intersection of synchronization data and control data.

[0083] The advantage of this method is its strong applicability, allowing high-precision synchronization performance at lower communication baud rates without sacrificing communication bandwidth, without requiring additional data to occupy the communication link, automatic synchronization at the receiving end, and fast response time, without having to consider the impact of synchronization on system timing.

[0084] This method requires no special hardware and relies solely on software modifications, making implementation costs manageable. No synchronization data is required within the communication frame; the receiving end automatically detects and synchronizes the clock, requiring only modifications to the receiving end's functional modules. This method is independent of the serial communication data content, supports live module operation without affecting synchronization, and requires no waiting time for synchronization.

[0085] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0086] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0087] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0088] Specific embodiments are used in the present invention to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core ideas. At the same time, for those skilled in the art, according to the ideas of the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the contents of this specification should not be understood as limiting the present invention.

[0089] Those skilled in the art will appreciate that the embodiments described herein are intended to help readers understand the principles of the present invention, and it should be understood that the scope of protection of the present invention is not limited to such specific descriptions and embodiments. Those skilled in the art can make various other specific variations and combinations based on the technical teachings disclosed in the present invention without departing from the essence of the present invention, and such variations and combinations are still within the scope of protection of the present invention.

Claims

1. A high-precision cascade inverter synchronous control method, characterized in that: The following steps are involved: S1, using the main controller to periodically send fundamental wave data and control instructions to the cascade module controller through the established serial full-duplex communication link; S2. Receive fundamental wave data and control instructions using a cascade module controller, record serial communication signals using a sampling frequency that is a multiple of the communication baud rate through a synchronous detection unit, and determine a clock offset based on the time interval between two adjacent level changes in the serial communication signal; specifically, including: S2-1, obtain the serial communication baud rate, and set the magnification according to the highest working clock, and determine the sampling frequency according to the serial communication baud rate and the set magnification; S2-2, using a synchronous counting unit counter to record the count value of the level change in the serial communication signal in a cyclic counting manner; S2-3, calculating the time interval between two adjacent level changes in the serial communication signal based on the count value of level changes in the current serial communication signal and the count value of level changes in the adjacent serial communication signal; S2-4, determining whether the time interval between two adjacent level changes in the serial communication signal meets the set multiplier of the counting period; if so, determining that no clock offset has occurred; otherwise, determining that a clock offset has occurred; S3, using the synchronous counting unit provided in the cascade module controller to correct the synchronous counting unit counter according to the clock offset; S4, adjusting the carrier counting unit counter to be equal according to the corrected synchronization counting unit counter; S5. Compare the adjusted carrier counting unit counter with the fundamental wave data to generate a switching signal of the power device, thereby realizing synchronous control of the cascaded inverter.

2. A high-precision cascade inverter synchronous control method according to claim 1, characterized in that: In step S2-1, the sampling frequency is determined according to the serial communication baud rate and the set magnification as follows: ， in, f c is the sampling frequency, N The magnification is set according to the maximum working clock. f s is the serial communication baud rate.

3. A high-precision cascade inverter synchronous control method according to claim 1, characterized in that: In step S2-3, the time interval between two adjacent level changes in the serial communication signal is calculated based on the count value of the level change in the current serial communication signal and the count value of the level change in the adjacent serial communication signal: ， in, y is the time interval between two adjacent level changes in the serial communication signal. y 1 is the count value of the level change in the adjacent serial communication signal, y 2 is the count value of the level change in the current serial communication signal. m * N is the number of sampling periods in the loop.

4. A high-precision cascade inverter synchronous control method according to claim 1, characterized in that: Step S2-4 is specifically as follows: Determine whether the time interval between two adjacent level changes in the serial communication signal meets the set multiplier of the counting cycle; If satisfied y = x * N , it is determined that no clock offset occurs; If satisfied y = x * N+N±n , then it is determined that clock offset occurs n .

5. The high-precision cascade inverter synchronous control method according to claim 1, characterized in that: In step S3, the synchronous counting unit provided in the cascade module controller is used to correct the synchronous counting unit counter according to the clock offset. Specifically, the following steps are performed: If the time interval between two adjacent level changes in the serial communication signal satisfies y = x * N+N+n , then add the clock offset to the count of the synchronous counting unit counter n ; If the time interval between two adjacent level changes in the serial communication signal satisfies y = x * N+Nn , then the count of the synchronous counting unit counter is subtracted from the clock offset n .

6. A high-precision cascade inverter synchronous control method according to claim 1, characterized in that: In step S4, adjusting the carrier counting unit counter according to the corrected synchronization counting unit counter is specifically as follows: Adjust the counting period of the synchronous counting unit counter and the triangle wave period of the carrier counting unit counter to be an integral multiple, and make the peak moment or low point moment of the triangle wave of the carrier counting unit counter coincide with the jump edge of the synchronous counting unit counter.

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