Low voltage drop linear voltage regulator circuit, chip and terminal equipment

Abstract

The present invention discloses a low voltage difference linear voltage regulator circuit, a chip and a terminal device, wherein the low voltage difference linear voltage regulator circuit comprises: a reference voltage generating unit, which is used to generate a reference voltage and output it to a voltage conversion unit; a voltage conversion unit, which is used to generate a regulated voltage according to the reference voltage and selectively output the regulated voltage, wherein the regulated voltage is greater than or equal to the reference voltage. The technical solution of the present invention can effectively reduce the circuit area and the power consumption of the circuit.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a low voltage difference linear voltage stabilization circuit, a chip and a terminal device. Background Art

[0002] Low Dropout Regulator (LDO) is a universal voltage regulator circuit. LDO can provide a stable output voltage within a certain input voltage variation range and load variation range. It has the characteristics of good low-voltage working characteristics and high precision.

[0003] Traditional low voltage drop linear voltage regulator circuits are usually independent circuit structures and need to work together with peripheral independent circuits to achieve target functions.

[0004] However, setting up multiple independent circuits will occupy too much area. At the same time, the increase in components will increase the power consumption of the circuit, which will increase the difficulty of circuit design. Summary of the invention

[0005] The technical problem solved by the present invention is how to design a low voltage difference linear voltage stabilization circuit structure to reduce the area occupied and power consumption of the circuit.

[0006] In order to solve the above technical problems, an embodiment of the present invention provides a low voltage difference linear voltage regulator circuit. The low voltage difference linear voltage regulator circuit includes: a reference voltage generating unit, which is used to generate a reference voltage and output it to a voltage conversion unit; a voltage conversion unit, which is used to generate a regulated voltage according to the reference voltage and selectively output the regulated voltage, wherein the regulated voltage is greater than or equal to the reference voltage.

[0007] Optionally, the voltage conversion unit includes: an impedance subunit, a first end of the impedance subunit is connected to the reference voltage; a switch subunit, a first end of the switch subunit is coupled to a second end of the impedance subunit, and the second end of the switch subunit outputs the regulated voltage.

[0008] Optionally, the impedance subunit is a variable resistor.

[0009] Optionally, the switch subunit includes a MOS tube or a single-pole single-throw switch, and a gate of the MOS tube is connected to a low power consumption mode control signal.

[0010] Optionally, under the control of a low power consumption mode control signal, the voltage conversion unit outputs the regulated voltage.

[0011] Optionally, the reference voltage is a bandgap reference voltage.

[0012] Optionally, the reference voltage generating unit includes a first transistor, a second transistor and a first resistor; the collector of the first transistor and the collector of the second transistor are grounded, the emitter of the second transistor is coupled to the first end of the first resistor, the emitter voltage of the first transistor is the same as the second end voltage of the first resistor, and the collector area of ​​the second transistor is a multiple of N of the collector area of ​​the first transistor, where N is a positive number.

[0013] Optionally, the regulated voltage calculation formula is as follows: VLDO = VBG + I R1 ×(n×R), Wherein, VLDO represents the regulated voltage, VBG represents the reference voltage, n represents the current coefficient, R represents the resistance value of the impedance subunit, I R1 represents the current value passing through the first resistor, V T represents the thermal voltage, and R1 represents the resistance value of the first resistor.

[0014] The embodiment of the present invention further discloses a chip, comprising the low voltage difference linear voltage stabilization circuit.

[0015] The embodiment of the present invention further discloses a terminal device, comprising the low voltage difference linear voltage stabilization circuit.

[0016] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0017] The present invention provides a low voltage difference linear voltage stabilization circuit, which generates a reference voltage through a reference voltage generation unit and outputs the reference voltage. The first end of the voltage conversion unit is coupled to the reference voltage, so that the voltage conversion unit can generate a regulated voltage according to the reference voltage to realize power supply to the peripheral circuit. At the same time, the reference voltage generation unit and the voltage conversion unit are integrated into one circuit, which can effectively reduce the circuit area, reduce the power consumption of the circuit, and further reduce the difficulty of circuit design.

[0018] Furthermore, by adjusting the impedance of the impedance subunit, the magnitude of the regulated voltage can be controlled to obtain a regulated voltage that meets the expected voltage value. And under the control of the low power mode control signal, the switch subunit can be selectively turned on to output the regulated voltage. When the switch subunit is not turned on, the circuit can still achieve the function of outputting the reference voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a structural schematic diagram of a low voltage difference linear voltage stabilization circuit provided by an embodiment of the present invention;

[0020] Figure 2 It is a structural schematic diagram of a specific subunit of a low voltage difference linear voltage stabilization circuit provided by an embodiment of the present invention;

[0021] Figure 3 It is a specific structural schematic diagram of a low voltage difference linear voltage stabilization circuit provided by an embodiment of the present invention;

[0022] Figure 4 is a specific structural schematic diagram of another low voltage difference linear voltage stabilizing circuit provided by an embodiment of the present invention;

[0023] Figure 5 It is a specific structural schematic diagram of another low voltage difference linear voltage stabilizing circuit provided by an embodiment of the present invention;

[0024] Figure 6 It is a specific structural schematic diagram of another low voltage difference linear voltage stabilization circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0025] As described in the background technology, the traditional low voltage difference linear voltage regulator circuit needs to work with peripheral circuits to achieve the target function, but setting up multiple circuits will cause the circuit to occupy too large an area, fail to reduce the power consumption of the circuit, and increase the difficulty of circuit design.

[0026] In the embodiment of the present invention, a reference voltage is generated by a reference voltage generating unit and the reference voltage is output. The first end of the voltage conversion unit is coupled to the reference voltage, so that the voltage conversion unit can generate a regulated voltage according to the reference voltage to realize power supply to the peripheral circuit. At the same time, the reference voltage generating unit and the voltage conversion unit are integrated into one circuit, which can effectively reduce the circuit area, reduce the power consumption of the circuit, and further reduce the difficulty of circuit design.

[0027] Furthermore, by adjusting the impedance of the impedance subunit, the magnitude of the regulated voltage can be controlled to obtain a regulated voltage that meets the expected voltage value. And under the control of the low power mode control signal, the switch subunit can be selectively turned on to output the regulated voltage. When the switch subunit is not turned on, the circuit can still achieve the function of outputting the reference voltage.

[0028] In order to make the above-mentioned purposes, features and advantages of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0029] The embodiment of the present invention provides a low voltage difference linear voltage stabilizing circuit, referring to Figure 1 , the low voltage difference linear voltage stabilizing circuit provided by the embodiment of the present invention is described below.

[0030] Figure 1The low voltage difference linear voltage regulator circuit 1 comprises: a reference voltage generating unit 11, used to generate a reference voltage and output it to a voltage conversion unit; a voltage conversion unit 12, used to generate a regulated voltage according to the reference voltage and selectively output the regulated voltage, wherein the regulated voltage is greater than or equal to the reference voltage.

[0031] Specifically, the voltage conversion unit 12 includes an impedance subunit and a switch subunit. Figure 2 The low voltage drop linear regulator circuit is explained in detail. Figure 2 It is a specific structural diagram of a low voltage difference linear voltage regulator circuit.

[0032] Figure 2 The low voltage difference linear voltage regulator circuit 2 shown includes: a reference voltage generating unit 11, which is used to generate a reference voltage and output it to a voltage conversion unit; an impedance subunit 121, the first end of which is connected to the reference voltage; a switch subunit 122, the first end of which is coupled to the second end of the impedance subunit, and the second end of which outputs a regulated voltage. Specifically, the switch subunit can be a MOS tube or a single-pole single-throw switch. When the switch subunit is a MOS tube, the gate of the MOS tube is connected to a low power mode control signal (not shown in the figure).

[0033] In a specific implementation, the reference voltage generating unit includes a first triode, a second triode and a first resistor. The collector of the first triode and the collector of the second triode are grounded, the emitter of the second triode is coupled to the first end of the first resistor, the emitter voltage of the first triode is the same as the voltage of the second end of the first resistor, and the collector area of ​​the second triode is a multiple of the collector area of ​​the first triode is N, where N is a positive number.

[0034] In a specific implementation, under the control of the low power mode control signal, the switch subunit is turned on, and the second end of the switch subunit outputs a regulated voltage. The calculation formula of the regulated voltage is: VLDO = VBG + I R1 ×(n×R), Wherein, VLDO represents the regulated voltage. VBG represents the reference voltage, and specifically, the reference voltage may be a bandgap reference voltage. n represents the current coefficient, R represents the resistance value of the impedance subunit in the voltage conversion unit, and I R1 Represents the current value passing through the first resistor, V T represents the thermal voltage, and R1 represents the resistance value of the first resistor. k is the Boltzmann constant, T is the thermodynamic temperature, and q is the charge of the electron.

[0035] In a specific implementation, in order to adjust the voltage value of the regulated voltage VLDO, the resistance value of the impedance subunit in the voltage conversion unit may be adjusted so that VLDO reaches a desired voltage value, so that the regulated voltage can be output at a fixed voltage value.

[0036] Those skilled in the art will appreciate that the impedance subunit may be any implementable component with impedance, such as a resistor, and the embodiment of the present invention does not limit this.

[0037] In the embodiment of the present invention, the reference voltage generation unit and the voltage conversion unit are integrated, and the circuit area is reduced without affecting the reference voltage output function and the regulated voltage output function, thereby improving the chip utilization rate and reducing the design difficulty of the R&D personnel. At the same time, a low power mode control signal can be received in the low power mode to control the output of the regulated voltage, and the size of the regulated voltage can be adjusted by the impedance subunit, so that the regulated voltage is controllable.

[0038] In a non-limiting embodiment, the reference voltage generating unit may be a bandgap reference circuit, and the reference voltage may be a bandgap reference voltage. By integrating the voltage conversion unit on the bandgap reference circuit to form a low voltage drop linear voltage regulator circuit, the output voltage can be unaffected by temperature and power supply voltage.

[0039] Figures 3 to 6 The specific embodiment of the low voltage difference linear voltage regulator circuit is now combined with Figures 3 to 6 The low voltage difference linear voltage regulator circuit is described. In this embodiment, the reference voltage generating unit is a bandgap reference circuit, and the bandgap reference circuit can output a bandgap reference voltage.

[0040] Figure 3 The following is a detailed description of a low voltage difference linear voltage stabilizing circuit provided by an embodiment of the present invention.

[0041] In the embodiment of the present invention, the reference voltage generating unit 11 may include a first PMOS transistor M1, an operational amplifier A1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first transistor Q1, and a second transistor Q2, wherein:

[0042] The source of the first PMOS tube M1 is coupled to the power source VCC;

[0043] The base and collector of the first transistor Q1 are grounded, and the base and collector of the second transistor Q2 are grounded;

[0044] A first end of the first resistor R1 is coupled to the emitter of the second transistor Q2, a first end of the second resistor R2 is coupled to the emitter of the first transistor Q1, a first end of the third resistor R3 is coupled to the second end of the first resistor R1, a second end of the second resistor R2 is connected in parallel with the second end of the third resistor R3 and is coupled to a first end of a fourth resistor R4, and a second end of the fourth resistor R4 outputs a bandgap reference voltage VBG;

[0045] The negative phase input terminal of the operational amplifier A1 is coupled between the first end of the second resistor R2 and the emitter of the first transistor Q1, the positive phase input terminal of the operational amplifier A1 is coupled between the first end of the third resistor R3 and the second end of the first resistor R1, and the output terminal of the operational amplifier A1 is coupled to the gate of the first PMOS transistor M1. The voltage of the node A between the negative phase input terminal of the operational amplifier A1 and the first end of the second resistor R2 is equal to the voltage of the node B between the positive phase input terminal of the operational amplifier A1 and the first end of the third resistor R3.

[0046] In a non-limiting embodiment, the operational amplifier A1 can be an operational amplifier manufactured using a CMOS (Complementary Metal Oxide Semiconductor) process, or other commonly used operational amplifier forms, which can be selected according to actual needs and will not be described in detail here.

[0047] Those skilled in the art will appreciate that the operational amplifier may be any implementable circuit, such as a clamping operational amplifier circuit, and the embodiments of the present invention do not limit this. The operational amplifiers described below may also be any implementable circuit, which will not be described in detail later.

[0048] In this embodiment, the voltage conversion unit 12 may include a fifth resistor R5 and a switch SW1, wherein:

[0049] A first end of the fifth resistor R5 is coupled to a second end of the fourth resistor R4, a second end of the fourth resistor R4 outputs a bandgap reference voltage VBG, and a second end of the fifth resistor R5 is coupled to a drain of the first PMOS tube M1;

[0050] A first terminal of the switch SW1 is coupled to the second terminal of the fifth resistor R5 , and a second terminal of the switch SW1 outputs a regulated voltage.

[0051] In a specific implementation, the resistance value of the second resistor R2 is equal to the resistance value of the third resistor R3, the fourth resistor R4 and the fifth resistor R5 are adjustable resistors, and the ratio of the collector area of ​​the first transistor Q1 to the collector area of ​​the second transistor Q2 is 1:N. Since the voltage of the positive input terminal and the negative input terminal of the operational amplifier are equal, the current value passing through the first resistor R1 is Among them, V Trepresents the thermal voltage, Where k is the Boltzmann constant, T is the thermodynamic temperature, and q is the charge of the electron.

[0052] In the embodiment of the present invention, the current coefficient represents the ratio of the current flowing through the resistor R5 to the current flowing through R1. After the current passes through the second resistor R2 and the third resistor R3 connected in parallel, it passes through the fourth resistor R4, so the current coefficient is 2.

[0053] The calculation formula of the reference voltage is: VBG = VBE1 + I R1 ×(R3+2×R4); the calculation formula of the regulated voltage is: VLDO=VBG+I R1 ×(2×R5)=VBE1+I R1 ×(R3+2×R4+2×R5), where VBE1 is the emitter voltage of the first transistor Q1, and the voltage value of VBE1 is determined by the structure of the first transistor Q1 and can be calculated in advance. The reference voltage VBG of a specific value can be obtained by adjusting the resistance value of the fourth resistor R4, and the regulated voltage VLDO of a specific value can be obtained by adjusting the resistance value of the fifth resistor R5. Under the control of the low power mode control signal, the switch SW1 is closed and the regulated voltage VLDO is output.

[0054] Figure 4 Another low voltage difference linear voltage stabilizing circuit provided by the embodiment of the present invention is described in detail below.

[0055] In the embodiment of the present invention, the reference voltage generating unit 11 may include a second PMOS transistor M2, a third PMOS transistor M3, an operational amplifier A2, a first resistor R1, a sixth resistor R6, a first transistor Q1, and a second transistor Q2, and the sixth resistor R6 is an adjustable resistor.

[0056] A source of the second PMOS tube M2 is coupled to the power source VCC, and a source of the third PMOS tube M3 is coupled to the power source VCC;

[0057] The base and collector of the first transistor Q1 are grounded, the emitter of the first transistor Q1 is coupled to the drain of the second PMOS transistor M2, and the base and collector of the second transistor Q2 are grounded;

[0058] A first end of the first resistor R1 is coupled to the emitter of the second transistor Q2, a first end of the sixth resistor R6 is coupled to the second end of the first resistor R1, and a second end of the sixth resistor R6 outputs a bandgap reference voltage VBG;

[0059] The negative phase input terminal of the operational amplifier A2 is coupled between the emitter of the first transistor Q1 and the drain of the second PMOS tube M2, the positive phase input terminal of the operational amplifier A2 is coupled between the first end of the second resistor R2 and the second end of the first resistor R1, the output terminal of the operational amplifier A2 is coupled to the gate of the second PMOS tube M2, and the output terminal of the operational amplifier A2 is coupled to the gate of the third PMOS tube M3. The voltage of the node A at the negative phase input terminal of the operational amplifier A2 is equal to the voltage of the node B at the positive phase input terminal of the operational amplifier A2 and the second end of the first resistor R1.

[0060] In this embodiment, the voltage conversion unit 12 may include a fifth resistor R5 and a switch SW1, wherein:

[0061] A first end of the fifth resistor R5 is coupled to the sixth resistor R6 and outputs the bandgap reference voltage VBG. A second end of the fifth resistor R5 is coupled to the drain of the third PMOS transistor M3.

[0062] A first terminal of the switch SW1 is coupled to the second terminal of the fifth resistor R5 , and a second terminal of the switch SW1 outputs a regulated voltage.

[0063] In a specific implementation, the ratio of the collector area of ​​the first transistor Q1 to the collector area of ​​the second transistor Q2 is 1:N. Since the voltage of the positive input terminal and the negative input terminal of the operational amplifier are equal, the current value passing through the first resistor R1 is Among them, V T represents the thermal voltage, Where k is the Boltzmann constant, T is the thermodynamic temperature, and q is the charge of the electron.

[0064] In this embodiment, the current coefficient is 1. The calculation formula of the reference voltage is: VBG = VBE1 + I R1 ×R6; the calculation formula of the regulated voltage is: VLDO=VBG+I R1 ×R5=VBE1+I R1 ×(R5+R6), where VBE1 is the emitter voltage of the first transistor Q1, and the voltage value of VBE1 is determined by the structure of the first transistor Q1 and can be calculated in advance. The reference voltage VBG of a specific value can be obtained by adjusting the resistance value of the sixth resistor R6, and the regulated voltage VLDO of a specific value can be obtained by adjusting the resistance value of the fifth resistor R5. Under the control of the low power mode control signal, the switch SW1 is closed and the regulated voltage VLDO is output.

[0065] Figure 5 Detailed structural diagram of another low voltage difference linear voltage stabilizing circuit is shown in FIG.

[0066] In the embodiment of the present invention, the reference voltage generating unit 11 may include a fourth PMOS transistor M4, a fifth PMOS transistor M5, a sixth PMOS transistor M6, an operational amplifier A3, a first resistor R1, a seventh resistor R7, a first transistor Q1, and a second transistor Q2, wherein the seventh resistor R7 is an adjustable resistor, wherein:

[0067] A source of the fourth PMOS tube M4 is coupled to the power supply VCC, a source of the fifth PMOS tube M5 is coupled to the power supply VCC, and a source of the sixth PMOS tube M6 is coupled to the power supply VCC;

[0068] The base and collector of the first transistor Q1 are grounded, the emitter of the first transistor Q1 is coupled to the drain of the fourth PMOS transistor M4, and the base and collector of the second transistor Q2 are grounded;

[0069] A first end of the first resistor R1 is coupled to the emitter of the second transistor Q2 , a second end of the first resistor R1 is coupled to the drain of the fifth PMOS transistor M5 , and a second end of the seventh resistor R7 outputs a bandgap reference voltage VBG;

[0070] The negative phase input terminal of the operational amplifier A3 is coupled between the emitter of the first transistor Q1 and the drain of the fourth PMOS tube M4, the positive phase input terminal of the operational amplifier A3 is coupled between the second end of the first resistor R1 and the drain of the fifth PMOS tube M5, the output terminal of the operational amplifier A3 is coupled to the gate of the fourth PMOS tube M4, the output terminal of the operational amplifier A3 is coupled to the gate of the fifth PMOS tube M5, the output terminal of the operational amplifier A3 is coupled to the gate of the sixth PMOS tube M6, and the negative phase input terminal A of the operational amplifier is coupled to the first end of the seventh resistor R7. The voltage of the node A between the negative phase input terminal of the operational amplifier A3 and the first end of the seventh resistor R7 is equal to the voltage of the node B between the positive phase input terminal of the operational amplifier A3 and the second end of the first resistor R1.

[0071] In this embodiment, the voltage conversion unit 12 may include a fifth resistor R5 and a switch SW1, wherein:

[0072] A first end of the fifth resistor R5 is coupled to the seventh resistor R7 and outputs the bandgap reference voltage VBG. A second end of the fifth resistor R5 is coupled to the drain of the sixth PMOS transistor M6.

[0073] A first terminal of the switch SW1 is coupled to the second terminal of the fifth resistor R5 , and a second terminal of the switch SW1 outputs a regulated voltage.

[0074] In a specific implementation, the ratio of the collector area of ​​the first transistor Q1 to the collector area of ​​the second transistor Q2 is 1:N. Since the voltage of the positive input terminal and the negative input terminal of the operational amplifier are equal, the current value passing through the first resistor R1 is Among them, VT represents the thermal voltage, Where k is the Boltzmann constant, T is the thermodynamic temperature, and q is the charge of the electron.

[0075] In this embodiment, the current coefficient is m, where m is the mirror ratio set by the mirror circuit. The current passing through the drain of the sixth PMOS tube M6 is I M6 Since the sixth PMOS tube M6 and the fifth PMOS tube M5 are mirror circuits, I M6 For I R1 The mirror current, I R1 with I M6 The ratio of the current values ​​is 1:m.

[0076] The calculation formula of the reference voltage is: VBG = VBE1 + m × I R1 ×R7; the calculation formula of the regulated voltage is: VLDO=VBG+m×I R1 ×R5=VBE1+m×I R1 ×(R5+R7), where VBE1 is the emitter voltage of the first transistor Q1, and the voltage value of VBE1 is determined by the structure of the first transistor Q1 and can be calculated in advance. The reference voltage VBG of a specific value can be obtained by adjusting the resistance value of the seventh resistor R7, and the regulated voltage VLDO of a specific value can be obtained by adjusting the resistance value of the fifth resistor R5. Under the control of the low power mode control signal, the switch SW1 is closed and the regulated voltage VLDO is output.

[0077] Figure 6 Detailed description of the structure of another low voltage difference linear voltage regulator circuit is as follows:

[0078] In the embodiment of the present invention, the reference voltage generating unit 11 may include a seventh PMOS transistor M7, an eighth PMOS transistor M8, a ninth PMOS transistor M9, an operational amplifier A4, a first resistor R1, an eighth resistor R8, a first triode Q1, a second triode Q2, and a third triode Q3, wherein the eighth resistor R8 is an adjustable resistor, wherein:

[0079] A source of the seventh PMOS tube M7 is coupled to the power supply VCC, a source of the eighth PMOS tube M8 is coupled to the power supply VCC, and a source of the ninth PMOS tube M9 is coupled to the power supply VCC;

[0080] The base and collector of the first transistor Q1 are grounded, the emitter of the first transistor Q1 is coupled to the drain of the first PMOS transistor M1, the base and collector of the second transistor Q2 are grounded, and the base and collector of the third transistor Q3 are grounded;

[0081] A first end of the first resistor R1 is coupled to the emitter of the second transistor Q2, a second end of the first resistor R1 is coupled to the drain of the eighth PMOS transistor M8, a first end of the eighth resistor R8 is coupled to the emitter of the third transistor Q3, and a second end of the eighth resistor R8 outputs a bandgap reference voltage VBG;

[0082] The negative phase input terminal of the operational amplifier A4 is coupled between the emitter of the first triode Q1 and the drain of the seventh PMOS tube M7, the positive phase input terminal of the operational amplifier A4 is coupled between the second end of the first resistor R1 and the drain of the eighth PMOS tube M8, the output terminal of the operational amplifier A4 is coupled to the gate of the seventh PMOS tube M7, the output terminal of the operational amplifier A4 is coupled to the gate of the eighth PMOS tube M8, and the output terminal of the operational amplifier A4 is coupled to the gate of the ninth PMOS tube M9. The voltage of the node A at the negative phase input terminal of the operational amplifier A4 is equal to the voltage of the node B at the positive phase input terminal of the operational amplifier A4 and the second end of the first resistor R1.

[0083] In this embodiment, the voltage conversion unit 12 may include a fifth resistor R5 and a switch SW1, wherein:

[0084] A first end of the fifth resistor R5 is coupled to the eighth resistor R8 and outputs the bandgap reference voltage VBG. A second end of the fifth resistor R5 is coupled to the drain of the third PMOS transistor M3.

[0085] A first terminal of the switch SW1 is coupled to the second terminal of the fifth resistor R5 , and a second terminal of the switch SW1 outputs a regulated voltage.

[0086] In a specific implementation, the ratio of the collector area of ​​the first transistor Q1 to the collector area of ​​the second transistor Q2 is 1:N. Since the voltage of the positive input terminal and the negative input terminal of the operational amplifier are equal, the current value passing through the first resistor R1 is Among them, V T represents the thermal voltage, Where k is the Boltzmann constant, T is the thermodynamic temperature, and q is the charge of the electron.

[0087] In this embodiment, the current coefficient is m, where m is the mirror ratio set by the mirror circuit. The current passing through the drain of the ninth PMOS tube M9 is I M9 Since the seventh PMOS tube M7 and the ninth PMOS tube M9 are mirror circuits, I M9 For I R1 The mirror current, I R1 with I M9 The ratio of the current values ​​is 1:m.

[0088] The calculation formula of the reference voltage is: VBG = VBE3 + m × I R1×R8; the calculation formula of the regulated voltage is: VLDO=VBG+m×I R1 ×R5=VBE1+m×I R1 ×(R5+R8), where VBE3 is the emitter voltage of the third transistor Q3, and the voltage value of VBE3 is determined by the structure of the third transistor Q3 and can be calculated in advance. The reference voltage VBG of a specific value can be obtained by adjusting the resistance value of the eighth resistor R8, and the regulated voltage VLDO of a specific value can be obtained by adjusting the resistance value of the fifth resistor R5. Under the control of the low power mode control signal, the switch SW1 is closed and the regulated voltage VLDO is output.

[0089] The embodiment of the present invention further discloses a chip, which includes a low voltage drop linear voltage regulator circuit. Specifically, the chip may be a micro controller unit (MCU) chip.

[0090] In a specific embodiment, in the MCU chip, the reference voltage generating unit may be a bandgap reference circuit, and the reference voltage may be a bandgap reference voltage. That is to say, the present application integrates a voltage conversion unit on the basis of the bandgap reference circuit of the MCU chip to form a low voltage difference linear voltage regulator circuit capable of outputting a regulated voltage. The low power mode control signal can control the working mode of the MCU chip. When the MCU chip enters the low power mode, the low voltage difference linear voltage regulator circuit outputs the reference voltage and the regulated voltage; when the MCU chip enters the non-low power mode, the low voltage difference linear voltage regulator circuit outputs the reference voltage.

[0091] The embodiment of the present invention further discloses a terminal device, which includes a low voltage difference linear voltage stabilization circuit. The terminal device can be a mobile phone, a computer, a tablet computer, or a household appliance, or a vehicle-mounted device.

[0092] The "plurality" appearing in the embodiments of the present application refers to two or more.

[0093] The first, second, etc. descriptions appearing in the embodiments of the present application are only used for illustration and distinction of the description objects. There is no order, nor do they indicate any special limitation on the number of devices in the embodiments of the present application, and cannot constitute any limitation on the embodiments of the present application.

[0094] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0095] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may be physically included separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0096] The above-mentioned integrated unit implemented in the form of a software functional unit can be stored in a computer-readable storage medium. The above-mentioned software functional unit is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to perform some steps of the method described in each embodiment of the present invention.

[0097] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A low voltage drop linear voltage regulator circuit, characterized in that: include: A reference voltage generating unit, used for generating a reference voltage and outputting the reference voltage to the voltage converting unit; a voltage conversion unit, configured to generate a regulated voltage according to the reference voltage and selectively output the regulated voltage, wherein the regulated voltage is greater than or equal to the reference voltage; The voltage conversion unit comprises: An impedance subunit, a first end of which is connected to the reference voltage; A switch subunit, wherein a first end of the switch subunit is coupled to a second end of the impedance subunit, and a second end of the switch subunit outputs the regulated voltage.

2. The low voltage difference linear voltage regulator circuit according to claim 1, characterized in that: The impedance subunit is a variable resistor.

3. The low voltage difference linear voltage regulator circuit according to claim 1, characterized in that: The switch subunit includes a MOS tube or a single-pole single-throw switch, and the gate of the MOS tube is connected to a low power consumption mode control signal.

4. The low voltage difference linear voltage regulator circuit according to claim 1, characterized in that: Under the control of the low power mode control signal, the voltage conversion unit outputs the regulated voltage.

5. The low voltage difference linear voltage regulator circuit according to claim 1, characterized in that: The reference voltage is a bandgap reference voltage.

6. The low voltage difference linear voltage regulator circuit according to claim 1, characterized in that: The reference voltage generating unit includes a first triode, a second triode and a first resistor; The collector of the first transistor and the collector of the second transistor are grounded, the emitter of the second transistor is coupled to the first end of the first resistor, the emitter voltage of the first transistor is the same as the second end voltage of the first resistor, and the collector area of ​​the second transistor is a multiple of the collector area of ​​the first transistor, which is N, and N is a positive number.

7. The low voltage difference linear voltage regulator circuit according to claim 6, characterized in that: The regulated voltage calculation formula is as follows: VLDO=VBG+I R1 ×(n×R), Wherein, VLDO represents the regulated voltage, VBG represents the reference voltage, n represents the current coefficient, R represents the resistance value of the impedance subunit, I R1 represents the current value passing through the first resistor, V T represents the thermal voltage, and R1 represents the resistance value of the first resistor.

8. A chip, characterized in that: A low voltage difference linear voltage regulator circuit comprising any one of claims 1 to 7.

9. A terminal device, characterized in that: A low voltage difference linear voltage regulator circuit comprising any one of claims 1 to 7.

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