Technique for performing command address interface training on dynamic random access memory

Abstract

The present invention relates to techniques for performing command address interface training on dynamic random access memory. Various embodiments include a memory device capable of performing command address interface training operations to determine that certain timing conditions are met, which has fewer I / O pins relative to existing methods. Existing methods for command address interface training involve loading data through a set of input pins, a clock signal, and a clock enable signal for identifying when the input pins are sampled. In contrast, the memory device of the present disclosure generates a data pattern within the memory device that matches a data pattern that is continuously sent to the memory device through an external memory controller. The memory device compares the generated data pattern with the received data pattern and sends the comparison result on one or more data output pins. The memory controller receives and analyzes the comparison result to determine whether the command address interface training passed or failed.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 144,971, entitled “TECHNIQUESFOR TRANSFERRING COMMANDS TO A DRAM,” filed on February 2, 2021. This application further claims priority to U.S. Provisional Patent Application No. 63 / 152,814, entitled “DATA SCRAMBLING ON A MEMORY INTERFACE,” filed on February 23, 2021. This application further claims priority to U.S. Provisional Patent Application No. 63 / 152,817, entitled “DRAM COMMAND INTERFACE TRAINING,” filed on February 23, 2021. This application further claims priority to U.S. Provisional Patent Application No. 63 / 179,954, entitled “DRAM WRITE TRAINING,” filed on April 26, 2021. The subject matter of these related applications is incorporated herein by reference. Background Art

[0003] Fields of various embodiments

[0004] Various embodiments relate generally to computer memory devices and, more particularly, to techniques for performing command address interface training on dynamic random access memories.

[0005] Description of Related Technology

[0006] Among other things, a computer system typically includes one or more processing units, such as a central processing unit (CPU) and / or a graphics processing unit (GPU), and one or more memory systems. One memory system is called system memory, which is accessible by the CPU and GPU. Another memory system is graphics memory, which is typically only accessible by the GPU. These memory systems include multiple memory devices. An example of a memory device that employs system memory and / or graphics memory is synchronous dynamic random access memory (SDRAM, or more briefly, DRAM).

[0007] Typically, high-speed DRAM memory devices use multiple interfaces. The interface includes a command address interface for transmitting commands and / or memory addresses to DRAM. Such commands include commands for initiating write operations, commands for initiating read operations, etc. The interface also includes a data interface for transmitting data to and from DRAM, such as during write operations and read operations. In order to reliably transmit commands and data to DRAM and transmit commands and data from DRAM, certain timing requirements must be met. One timing requirement is the setup time, which defines the minimum amount of time that a command or data signal must be stable before the clock edge of the command or data signal is transmitted respectively. Another timing requirement is the hold time, which defines the minimum amount of time that a command or data signal must be stable after the clock edge of the command or data signal is transmitted respectively. If the setup time requirement or the hold time requirement are not met, commands and / or data with one or more errors may be transmitted, thereby causing damaged command or data information.

[0008] As the speed of DRAM memory devices increases, the time between consecutive clock edges decreases, resulting in a shorter time period to meet the setup time and hold time requirements. Further, the timing of clock signals, command signals, and data signals is affected by local variations caused by process variations during manufacturing and changes in operating temperature, power supply voltage, interference from other signals, etc. Therefore, the setup time and hold time requirements are difficult to meet the requirements of increased DRAM device speeds. To alleviate this problem, DRAM memory devices generally have a skew circuit to change the timing of command signals and / or data signals relative to the clock signal. Periodically, a memory controller associated with the DRAM causes the DRAM to enter a training process for command write operations, data write operations, and / or data read operations. During such a training process, the memory controller changes the skew of one or more command address input pins, data input pins, and / or data output pins until the memory controller determines that the DRAM reliably performs command write operations, data write operations, and / or data read operations, respectively. The memory controller periodically repeats these training operations when operating conditions change over time, such as when operating temperature, power supply voltage, etc., change, so as to ensure reliable DRAM operation.

[0009] Specifically with respect to command address interface training, a memory controller transmits a command address interface training data pattern, or more briefly, a data pattern, to a DRAM memory device. Typically, a data pattern is a pseudo-random bit sequence suitable for detecting errors in a particular command address input of a DRAM memory device. When an untrained input called clock enable (CKE) is valid, the DRAM memory device samples the data pattern at the rising and / or falling edges of a clock signal (WCK) received by the memory device. The CKE pin is used to guide the sampling of the command address input data pattern in a non-continuous manner through the command address interface of the DRAM during command address interface training. The DRAM memory device presents the sampled data pattern on the data (DQ) output of the memory device. The memory controller then compares the data pattern transmitted by the memory controller to the DRAM memory device with the data pattern received by the memory device via the DQ output of the memory device. If the two data patterns match, the memory controller determines that the command address interface training is successful. If one or more bits of the two data patterns are different, the memory controller adjusts the relative skew between the CA input pins that exhibit one or more errors. The memory controller iteratively repeats the command address interface training operation and adjusts the skew of the command address input pins until the data patterns match. The memory controller then returns the DRAM to normal operation.

[0010] The disadvantage of this technique for DRAM command address interface training is that the technique uses a clock enable pin (CKE) input / output (I / O) pin and associated receiver circuit for each DRAM memory device. The additional I / O pin and the associated receiver circuit are usually only used during command address interface training and are not used during normal operation. It is worth noting that there are certain implementations in which a single pin is shared between power state transitions and CKE I / O pin usage. Even so, although dedicated I / O pins can be used to support certain power state transitions, there are other ways to support such power state transitions without using specific I / O pins. Therefore, if other ways are used to support power state transitions and other operations, it may be disadvantageous to use additional I / O pins on DRAM for clock enable. Additional I / O pins and associated receiver circuits increase system cost and complexity. In addition, additional receivers and I / O pins that receive clock enable signals cannot be used to accommodate other signals, such as additional command bits, data bits, or control signals. Further, some DRAM modules include multiple DRAM devices. In one example, a DRAM module with eight DRAM devices would require eight I / O pins because the clock enable signal is used during command-address interface training but is generally not used during normal operation.

[0011] Another disadvantage of this technique is that DRAM memory devices typically require a minimum duration between consecutive samples of the command address input pins because the command address input pins and data output pins have not yet been trained. The clock enable pulse is typically one clock cycle wide, and the timing between consecutive clock enable pulses is limited by this minimum duration. Successive samples of the command address input pins are thereby delayed in order to reliably perform command address interface training. Therefore, command address training is a non-continuous operation with time lapses between consecutive samples of the command address input pins. These time lapses extend the time required to complete command address interface training.

[0012] As noted above, what is needed in the art are more efficient techniques for performing signal training of memory devices. Summary of the invention

[0013] Various embodiments of the present disclosure set forth a computer-implemented method for performing a memory interface training operation on a memory device. The method includes receiving a first data pattern by a first input pin of the memory device. The method also includes initializing a first register on the memory device with a second data pattern. The method also includes generating a third data pattern based on the second data pattern in the first register. The method also includes comparing a first portion of the first data pattern with the third data pattern to generate a first result value indicating whether the memory device correctly received the first portion of the first data pattern. The method also includes transmitting the first result value to a first output of the memory device.

[0014] Other embodiments include, but are not limited to, systems that implement one or more aspects of the disclosed technology, as well as one or more computer-readable media including commands for executing one or more aspects of the disclosed technology, and methods for executing one or more aspects of the disclosed technology.

[0015] At least one technical advantage of the disclosed technology over the prior art is that, with the disclosed technology, a clock enable (CKE) pin is not required to perform command address interface training. Therefore, a receiver and an I / O pin are no longer required to receive a clock enable signal. Therefore, the complexity, surface area, and power consumption of the internal circuitry of the DRAM die can be reduced relative to methods involving clock enable pins. Further, the I / O pin previously used to receive a clock enable signal can be used for another function, such as an additional command bit, data bit, or control signal. Another advantage of the disclosed technology is that command address interface training is performed in a continuous manner without gaps between consecutive captures of the command address input pins. Therefore, command address interface training is performed in less time relative to prior methods. These advantages represent one or more technical improvements over prior art methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to understand in detail the manner in which the above features of the various embodiments are employed, a more specific description of the inventive concept briefly outlined above may be obtained with reference to the various embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the drawings only illustrate typical embodiments of the inventive concept and are therefore not to be construed as limiting the scope in any way, and there are other equally effective embodiments.

[0017] Figure 1 is a block diagram of a computer system configured to implement one or more aspects of various embodiments;

[0018] Figure 2 According to various embodiments, Figure 1 A block diagram of a training architecture for a memory device included in a system memory and / or a parallel processing memory of a computer system;

[0019] Figure 3 is a timing diagram according to various embodiments, showing the Figure 1 Initializing a memory device in a system memory and / or a parallel processing memory of a computer system to receive a command; and

[0020] Figure 4 According to various embodiments, a method for Figure 1 A flowchart of method steps for performing a write training operation in a memory device in a system memory and / or a parallel processing memory of a computer system. DETAILED DESCRIPTION

[0021] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of various embodiments. However, it will be apparent to one skilled in the art that the inventive concept may be practiced without one or more of these specific details.

[0022] System Overview

[0023] Figure 1 1 is a block diagram of a computer system 100 configured to implement one or more aspects of various embodiments. As shown, computer system 100 includes, but is not limited to, a central processing unit (CPU) 102 and a system memory 104 coupled to a parallel processing subsystem 112 via a memory bridge 105 and a communication path 113. Memory bridge 105 is coupled to system memory 104 via a system memory controller 130. Memory bridge 105 is further coupled to an I / O (input / output) bridge 107 via a communication path 106, and I / O bridge 107 is in turn coupled to a switch 116. Parallel processing subsystem 112 is coupled to a parallel processing memory 134 via a parallel processing subsystem (PPS) memory controller 132.

[0024] In operation, I / O bridge 107 is configured to receive user input information from input device 108, such as a keyboard or mouse, and forward the input information to CPU 102 for processing via communication path 106 and memory bridge 105. Switch 116 is configured to provide connections between I / O bridge 107 and other components of computer system 100, such as network adapter 118 and various add-in cards 120 and 121.

[0025] As also shown, the I / O bridge 107 is coupled to a system disk 114, which can be configured to store content and applications and data used by the CPU 102 and the parallel processing subsystem 112. In general, the system disk 114 provides non-volatile storage for applications and data, and may include a fixed or removable hard disk drive, a flash memory device, and a CD-ROM (compact disc read-only memory), DVD-ROM (digital versatile disc-ROM), Blu-ray, HD-DVD (high-definition DVD), or other magnetic, optical, or solid-state storage device. Finally, although not explicitly shown, other components, such as a universal serial bus or other port connection, a compact disc drive, a digital versatile disc drive, a film recording device, etc., may also be connected to the I / O bridge 107.

[0026] In various embodiments, memory bridge 105 may be a northbridge chip, and I / O bridge 107 may be a southbridge chip. Furthermore, communication paths 106 and 113, as well as other communication paths within computer system 100, may be implemented using any technically suitable protocol, including but not limited to AGP (Accelerated Graphics Port), HyperTransport, or any other bus or point-to-point communication protocol known in the art.

[0027] In some embodiments, the parallel processing subsystem 112 includes a graphics subsystem that delivers pixels to the display device 110, which can be any conventional cathode ray tube, liquid crystal display, light emitting diode display, etc. In such embodiments, the parallel processing subsystem 112 incorporates circuits optimized for graphics and video processing, including, for example, video output circuits. This circuitry may be included across one or more parallel processing units (PPUs) included in the parallel processing subsystem 112. In some embodiments, each PUPS includes a graphics processing unit (GPU), which may be configured to implement a graphics rendering pipeline to perform various operations related to generating pixel data based on graphics data provided by the CPU 102 and / or the system memory 104. Each PPU may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a memory device, or in any other technically feasible manner.

[0028] In some embodiments, parallel processing subsystem 112 includes circuitry optimized for general purpose and / or computational processing. Again, this circuitry may be included across one or more PPUs included within parallel processing subsystem 112, which are configured to perform such general purpose and / or computational operations. In other embodiments, one or more PPUs included within parallel processing subsystem 112 may be configured to perform graphics processing, general purpose processing, and computational processing operations. System memory 104 includes at least one device driver 103 configured to manage processing operations of one or more PPUs within parallel processing subsystem 112.

[0029] In various embodiments, the parallel processing subsystem 112 may be coupled to Figure 1 For example, parallel processing subsystem 112 may be integrated with CPU 102 and other connected circuits on a single chip to form a system on a chip (SoC).

[0030] In operation, CPU 102 is the main processor of computer system 100, controlling and coordinating the operation of other system components. In particular, CPU 102 issues commands that control the operation of the PPUs within parallel processing subsystem 112. In some embodiments, CPU 102 writes a command stream to a data structure ( Figure 1 The push buffer is a memory structure that is not explicitly shown in the figure and may be located in system memory 104, PP memory 134, or another storage location accessible to both CPU 102 and PPU. A pointer to the data structure is written to the push buffer to start processing the command stream in the data structure. The PPU reads the command stream from the push buffer and then executes the commands asynchronously with respect to the operation of CPU 102. In an embodiment where multiple push buffers are generated, the application program, through device driver 103, can specify an execution priority for each push buffer to control the scheduling of different push buffers.

[0031] Each PPU includes an I / O (input / output) unit that communicates with the rest of the computer system 100 through a communication path 113 and a memory bridge 105. The I / O unit generates packets (or other signals) for transmission on the communication path 113, and also receives all incoming packets (or other signals) from the communication path 113, thereby directing the incoming packets to the appropriate components of the PPU. The connection of the PPU to the rest of the computer system 100 can be changed. In some embodiments, the parallel processing subsystem 112 including at least one PPU is implemented as an add-in card that can be inserted into an expansion slot of the computer system 100. In other embodiments, the PPU may be integrated on a single chip with a bus bridge, such as a memory bridge 105 or an I / O bridge 107. Again, in other embodiments, some or all of the elements of the PPU may be included in a single integrated circuit or chip system (SoC) with the CPU 102.

[0032] The CPU 102 and the PPU within the parallel processing subsystem 112 access the system memory through the system memory controller 130. The system memory controller 130 transmits signals to the memory devices included in the system memory 104 to start the memory devices, transmit commands to the memory devices, write data to the memory devices, read data from the memory devices, etc. An exemplary memory device for the system memory 104 is a double data rate SDRAM (DDR SDRAM, or more briefly, DDR). DDR memory devices perform memory write and read operations at twice the data rate of previous generation single data rate (SDR) memory devices.

[0033] In addition, the PPU and / or other components within the parallel processing subsystem 112 access the PP memory 134 through a parallel processing system (PPS) memory controller 132. The PPS memory controller 132 sends signals to memory devices included in the PP memory 134 to start the memory devices, send commands to the memory devices, write data to the memory devices, read data from the memory devices, etc. An exemplary memory device for the PP memory 134 is synchronous graphics random access memory (SGRAM), which is a specialized form of SDRAM used for computer graphics applications. A special type of SGRAM is a graphics double data rate SGRAM (GDDR SDRAM, or more briefly, GDDR). Compared to DDR memory devices, GDDR memory devices are configured with a wider data bus in order to transfer more data bits with each memory write and read operation. By employing double data rate technology and a wider data bus, GDDR memory devices are generally able to achieve the high data transfer rates required by the PPU.

[0034] It will be understood that the system shown below is illustrative and is subject to variation and modification. The connection topology, including the number and arrangement of bridges, the number of CPUs 102, and the number of parallel processing subsystems 112, may be modified as desired. For example, in some embodiments, system memory 104 may be directly connected to CPU 102 rather than through memory bridge 105, and other devices will communicate with system memory 104 through memory bridge 105 and CPU 102. In other alternative topologies, parallel processing subsystem 112 may be connected to I / O bridge 107 or directly to CPU 102 rather than to memory bridge 105. In other embodiments, I / O bridge 107 and memory bridge 105 may be integrated into a single chip rather than existing as one or more discrete devices. Finally, in some embodiments, Figure 1 One or more components shown in FIG. 1 may not exist. For example, switch 116 may be eliminated, and network adapter 118 and add-in cards 120 , 121 may be directly connected to I / O bridge 107 .

[0035] It will be appreciated that the core architecture described below is illustrative and that variations and modifications are possible. Figure 1 The computer system 100 may include any number of CPUs 102, parallel processing subsystems 112, or memory systems, such as system memory 104 and parallel processing memory 134, within the scope of the disclosed embodiments. Further, as used herein, references to shared memory may include any one or more technically feasible memories, including but not limited to local memory shared by one or more PPUs within a parallel processing subsystem 112, memory shared between multiple parallel processing subsystems 112, cache memory, parallel processing memory 134 and / or system memory 104. Please also note that as used below, references to cache memory may include any one or more technically feasible memories, including but not limited to L1 cache, L1.5 cache, and L2 cache. In view of the foregoing, it will be appreciated by those of ordinary skill in the art that in Figure 1 The architecture described in this document in no way limits the scope of the various embodiments of the present disclosure.

[0036] Perform command address interface training operations on DRAM

[0037] Various embodiments are directed to techniques for efficiently performing command address interface training of DRAM memory devices. The disclosed techniques reduce DRAM pin overhead by eliminating the CKE pin and training the command address (CA) interface with a continuous PRBS (pseudo-random binary sequence) pattern instead. The memory controller sends a CA training enter command to the DRAM to ensure that the DRAM enters the CA training mode correctly. Once in the CA training mode, each CA-pin checker is used to compare the incoming CAPRBS pattern to the LFSR (Linear Feedback Shift Register) output that has been initialized with a starting value.

[0038] In some embodiments, the DRAM initializes the LFSR with a predetermined seed value. Additionally or alternatively, the DRAM initializes the LFSR with a seed value that has been sent to the DRAM by the memory controller. In these latter embodiments, the memory controller sends the seed value to the DRAM via the command address interface when the command address interface operates at a lower frequency and no interface training is required. In some embodiments, the DRAM initializes the LFSR by self-seeding. To self-seed, when the DRAM begins a training sequence, the DRAM loads the LFSR with a portion of an initial PRBS sequence received from the memory controller. Thereafter, the output of the LFSR is checked against the remaining PRBS sequence received from the memory controller.

[0039] The DRAM presents a pass / fail result by transmitting the pass / fail result of the comparison between the LFSR output and the data pattern from the memory controller on the DQ (data) pins of the DRAM. The DRAM sends the pass / fail result in an asynchronous manner, which allows the memory controller to reliably sample the result information without requiring the DQ pins to have been trained. Based on the results of the comparison, the memory controller can make adjustments on the memory controller and / or DRAM to change the sending and receiving of signals on the command address interface. Thereafter, the memory controller can periodically re-initiate CA training to ensure that the command address interface operates as expected or to make further adjustments to the command address interface.

[0040] Figure 2 For use according to various embodiments Figure 11 is a block diagram of a training architecture 200 for a memory device included in the system memory 104 and / or the parallel processing memory 134 of a computer system as shown. As further described, the training architecture 200 includes components for command address interface training, data read interface training, and data write interface training. Through these components, the training architecture 200 performs command address training operations, data read training operations, and data write training operations without storing training data in the DRAM core 226 of the memory device. When operating the memory device at a higher speed, the memory controller, such as the system memory controller 130 and / or the PPS memory controller 132, periodically performs these training operations to meet the setup time and hold time on all input pins and output pins of the memory device.

[0041] Generally speaking, the memory controller performs training operations in a specific order. First, the memory controller performs training operations on the command address interface. By first training the command address interface, the memory device is ready to receive commands and write mode registers as needed to perform data read interface training and data write interface training. Generally speaking, as long as the setup time and hold time are met on all command address (CA) input pins 206, the command address interface does not need to be trained. The memory controller causes the seed value and / or polynomial to be loaded into the command address linear feedback shift register (CA LFSR) 210. The memory controller applies the data pattern to one or more CA input pins 206. The CA input pin 206 is sent to the CA LFSR 210 and the exclusive OR (XOR) gate 212 through the receiver 208. The CA LFSR 210 replicates the same pattern as the memory controller. The XOR gate 212 compares the data pattern on the CA input pin 206 with the data of the CA LFSR 210. If the data pattern on the CA input pin 206 matches the data of the CA LFSR 210, the XOR gate 212 sends a low value. If the data pattern on the CA input pin 206 does not match the data from the CA LFSR 210, the XOR gate 212 sends a high value. The mode 204 input of the multiplexer 202 selects the bottom input to send the output of the XOR gate 212 to the transmitter 214 and then to one or more data (DQ), extended data (DQX) and / or error detection and correction (EDC) pins 216. The memory controller then reads one or more DQ, DQX and / or EDC pins 216 to determine whether the command address input training was successful. Once the command address input training is completed, the command address received from the memory controller passes through the CA input pin 206 and the receiver 208 and then to the DRAM core 226.

[0042] Second, the memory controller performs training operations on the data read interface. Generally speaking, the training operations on the data read interface are performed before the training operations on the data write interface. The order of the training operations ensures that the data read from the memory device is correct, which allows the memory controller to perform optimal write training operations. The memory controller causes the seed value and / or polynomial to be loaded into the read / write linear feedback shift register (R / W LFSR) 220. The mode 204 input of the multiplexer 202 selects the second of the top inputs to send the output of the R / W LFSR220 to the transmitter 214 and then to one or more data (DQ), extended data (DQX) and / or error detection and correction (EDC) pins 216. The memory controller then reads one or more DQ, DQX and / or EDC pins 216 to determine whether the received data is the expected pattern from the R / W LFSR220.

[0043] Third, the memory controller performs a training operation on the data write interface. The memory controller causes the seed value and / or polynomial to be loaded into the R / W LFSR 220. The memory controller applies a data pattern to one or more DQ, DQX, and / or EDC pins 216. The DQ, DQX, and / or EDC pins 216 are sent to the R / W LFSR 220 and the exclusive OR (XOR) gate 222 through the receiver 218. The R / W LFSR 220 replicates the same pattern as the memory controller. The XOR gate 222 compares the data pattern on the DQ, DQX, and / or EDC pins 216 with the data of the R / W LFSR 220. If the data pattern of the CA input pin 206 matches the data of the R / W LFSR 220, the XOR gate 222 sends a low value. If the data pattern of the DQ, DQX, and / or EDC pins 216 does not match the data of the R / W LFSR 220, the XOR gate 222 sends a high value. The output of the XOR gate 222 is sent to the write training result register 224 and is stored as a pass / fail write training status for each DQ, DQX, and / or EDC pin 216 that has been write trained. The memory controller reads the write training result register 224 to determine the result of the write training operation. When the memory controller reads the write training result register 224, the mode 204 input of the multiplexer 202 selects the second of the top inputs to send the output of the write training result register 224 through the transmitter 214 and then to one or more DQ, DQX, and / or EDC pins 216. The memory controller then reads one or more DQ, DQX, and / or EDC pins 216 to determine whether the data write training is successful. Once the data write training is completed, the write data received from the memory controller passes through the DQ, DQX, and / or EDC pins 216 and the receiver 218 and then reaches the DRAM core 226.

[0044] Once the data read training and data write training are completed, the mode 204 input of the multiplexer 202 selects the second from the bottom input to send the output of the DRAM core 226 to the transmitter 214 and then transmitted to one or more data (DQ), extended data (DQX), and / or error detection and correction (EDC) pins 216.

[0045] Returning to command address interface training, the DRAM generally does not know when command address interface training is needed. Instead, the memory controller determines whether and when to initiate command address interface training. The memory controller can cause the DRAM to enter command address interface training through a number of different techniques.

[0046] In some examples, the memory controller applies a fixed pattern to one or more CA input pins 206 when power is initially applied to the DRAM and / or when a reset is sent to the DRAM. During power-up and / or reset of the DRAM, the memory controller applies a low voltage to the reset input of the memory device to place the memory device in a reset state. Subsequently, the memory controller applies a high voltage to the reset input of the memory device in order to bring the memory device out of the reset state. Before applying the high voltage to the reset input, the memory controller may apply a fixed bit pattern to the CA input pins 206 of the DRAM. The fixed bit pattern is shown in the strip below. The memory device samples the state of the strip on the rising edge of the reset signal to determine the value of the fixed bit pattern. Based on the fixed bit pattern, the DRAM enters the command address interface training 316 operation.

[0047] In some examples, when the DRAM exits a low power state, such as an idle state or a self-refresh state, the DRAM may detect an asynchronously received self-refresh exit command and / or a power-on exit command. Since the memory controller sends the self-refresh exit command and / or the power-on exit command to the DRAM asynchronously, the DRAM is able to detect the command even in the absence of an active clock signal when the command address interface is not trained and / or when the command address interface is not currently executed synchronously with respect to the clock signal. For example, the memory controller may send a signal to the DRAM through the first CA input pin 206, which converts the signal from one state to another state (e.g., a high to low state or a low to high state) to command the DRAM to exit the low power state. During the signal conversion, the memory controller applies a high level or a low level to the second CA input pin 206 to indicate whether the DRAM enters a command address training operation. If the second CA input pin 206 is at a level when the first CA input pin 206 is converted, the DRAM enters a command address training operation. If the second CA input pin 206 is at another level when the first CA input pin 206 is converted, the DRAM does not enter a command address training operation.

[0048] In some examples, the memory controller may send a command to the DRAM to load a register with a specific value in the DRAM, such as a mode register, which includes a command to enter a command address training operation. The memory controller sends a command to the DRAM when the command address interface is trained or when the command address interface operates at a sufficiently low operating speed and does not require training. When the DRAM subsequently enters and subsequently exits a low power state, such as an idle state, a self-refresh state, etc., the DRAM reads the mode register. If the value in the mode register includes a command to enter command address interface training, the DRAM enters a command address training operation. If the value in the mode register does not include a command to enter command address interface training, the DRAM does not enter a command address training operation.

[0049] Upon entering the command address training operation, the DRAM enters the first mode (Mode 1) of command address training. In Mode 1, the memory controller and the DRAM independently test the setup time and the hold time for each command address input pin 206. The circuit for each command address input pin 206 includes a CA LFSR 210 that generates a pseudo-random bit sequence (PRBS). The circuit for each command address input pin 206 further includes a PRBS checker, such as an XOR gate 212, which compares the PRBS generated by the CA LFSR 210 with the PRBS received from the memory controller through the receiver 208.

[0050] The memory controller sends a known predetermined PRBS to one or more CA input pins 206 in training. By design, the memory controller and CA LFSR 210 generate the same PRBS. The PRBS can be in any technically feasible format, such as a 15-bit PRBS, a 7-bit PRBS, etc. Further, the PRBS can be based on any technically feasible seed value and / or polynomial. Each CA LFSR 210 corresponding to each CA input pin 206 can be loaded with the same seed value and / or polynomial. Additionally or alternatively, different CA LFSRs 210 corresponding to different CA input pins 206 can be loaded with different seed values ​​and / or polynomials. The memory controller synchronizes with the CA LFSR 210 by commanding the CA LFSR 210 to load the seed value through one of several possible techniques.

[0051] In some embodiments, the DRAM initializes the CA LFSR 210 with a predetermined seed value. Additionally or alternatively, the DRAM initializes the CA LFSR 210 with a seed value that has been sent to the DRAM by the memory controller. In these latter embodiments, when the command address interface operates at a lower frequency that does not require interface training, the memory controller transmits the seed value to the DRAM via the command address interface pin 206. Regardless of whether the DRAM initializes the CA LFSR 210 with a predetermined seed value or with a seed value received from the memory controller, once the memory controller has confirmed that the DRAM has initialized the CA LFSR 210 with the correct seed value, the memory controller transmits a PRBS based on the seed value. Thereafter, the memory controller sends the PRBS to each CA input pin 206 to be tested. The corresponding CA LFSR 210 generates a PRBS identical to the PRBS received by the memory controller.

[0052] In some embodiments, the DRAM initializes the CALFSR 210 by self-seeding. To self-seed, the memory controller begins sending PRBS to one or more CA input pins 206 at any starting point in the PRBS. The memory controller and the DRAM operate with the same polynomial, but do not need to start with the same seed value. The DRAM loads the CALFSR 210 with the initial portion of the initial PRBS sequence received from the memory controller via the corresponding CA input pin 206 to start the command address interface training sequence. The data sampled on each CA input pin 206 is stored in the corresponding CALFSR 210 for the CA input pin 206. Thereafter, the current data in the CA LFSR 210 is used to generate the next portion of the PRBS transmitted by the CA LFSR 210, according to the polynomial. Initially, during the self-seeding process, the CA LFSR 210 may store all zeros, all ones, or random values. Therefore, the PRBS from the memory controller may match or not match the PRBS from the CALFSR 210. Therefore, the XOR gate 212 may send an incorrect pass / fail status to the multiplexer 202. After some number of clock cycles, the self-seeding process of CALFSR 210 is completed.

[0053] Thereafter, the PRBS output of the CA LFSR 210 is checked for the remaining PRBS received from the memory controller. If the PRBS received from the memory controller is sampled correctly, the CA LFSR 210 generates the same required PRBS, and the XOR gate 212 sends a pass result. The DRAM asynchronously sends the pass result to the memory controller via the DQ / DQX / EDC output pin 216. Although the DRAM can send a pass result value or a fail result value to the DQ / DQX / EDC output pin 216 during self-seeding, once the self-seeding is completed, the DQ / DQX / EDC output 216 is converted to send a pass result value. The memory controller receives data asynchronously via the DQ / DQX / EDC output pin 216, and analyzes the data to determine the mode 1 command address interface training operation for generating a pass result value. If one or more of the DQ / DQX / EDC output pins 216 indicate a fail result value, the memory controller adjusts the skew between the corresponding CA input pin 206 and the clock signal until a pass result value for all CA input pins 206 is received consistently. The memory controller continues to perform Mode 1 command address interface training operations to determine the optimal point for each CA input pin 206 with respect to setup time and hold time.

[0054] In some embodiments, during the self-seeding process, when the CA LFSR 210 is not fully seeded, the DRAM can force a fault state on the output of all PRBS checkers, such as the XOR gate 212. The DRAM forces the fault state until a certain number of clock cycles have occurred and the CA LFSR 210 of all CA input pins 206 are fully primed and loaded with complete seed values. For example, for a 15-bit PRBS pattern, the DRAM forces the fault state to last for 15 clock cycles until the 15-bit CA LFSR 210 is fully loaded with its respective seed value. In this way, the DRAM does not send a false pass result to the memory controller when the CA LFSR 210 is loaded with the seed value. In this way, the memory controller no longer needs to ignore the first output of the XOR gate 212 when first entering the command address interface test of Mode 1. After the CA LFSR 210 is fully loaded with its respective seed value, the DRAM stops forcing the fault state on the output of the XOR gate 212. The DRAM transitions to the Checking state, where the state transitioned to the memory controller via the DQ, DQX, and / or EDC pins 216 reflects the output of the corresponding XOR gate 212. Thus, the DQ, DQX, and / or EDC pins 216 now indicate the correct pass / fail status of the corresponding XOR gate 212 , which now checks the output of each CA LFSR 210 with the incoming data received from the memory controller via the corresponding CA input pin 206 .

[0055] After Mode 1 is completed, each CA input pin 206 is trained individually with respect to the setup time and hold time involving the clock signal. However, the sampling points for different CA input pins 206 may occur at different edges of the clock signal. Therefore, the DRAM may sample certain CA input pins 206 on one edge of the clock signal and sample other CA input pins 206 on the previous edge of the clock signal and / or the subsequent edge of the clock signal. Therefore, when the memory controller sends a signal set to the CA input pins 206 of the DRAM, the DRAM may sample a portion of the signal on one edge of the clock signal and another portion of the signal on one or more different edges of the clock signal. This condition is called multi-cycle skew. To correct this problem, the memory controller converts the DRAM from Mode 1 of command-address interface training to a second mode (Mode 2) of command-address interface training.

[0056] The memory controller switches the DRAM from Mode 1 to Mode 2 by sending a pattern that does not occur in the PRBS to one or more CA input pins 206. In some instances, a 15-bit PRBS does not generate a series of 15 zeros in a row. Therefore, the memory controller can switch the DRAM from Mode 1 to Mode 2 by sending a pattern of 15 consecutive zero values ​​to one or more CA input pins 206. Additionally or alternatively, the memory controller can switch the DRAM from Mode 1 to Mode 2 by sending any pattern to one or more CA input pins 206 that does not occur in the PRBS. When the DRAM detects the pattern, the DRAM determines that the pattern is not part of the PRBS, but a command. In response, the DRAM switches from Mode 1 to Mode 2.

[0057] In Mode 2, the memory controller and DRAM test the multi-cycle skew between the command address input pins 206 in groups. The memory controller and DRAM test the multi-cycle skew in one of two sub-modes within Mode 2.

[0058] In the first sub-mode of Mode 2, a single CA input pin 206 is used as a reference pin for all CA input pins 206. The PRBS generated for the CA LFSR 210 for the single reference pin is used to compare the pattern received from the memory controller on all other CA input pins 206. In some embodiments, such a structure is implemented by a multiplexer. In such an embodiment, in Mode 1, the multiplexer routes the XOR gate 212 for each CA input pin 206 to the CA LFSR 210 for the CA input pin 206. In Mode 2, the multiplexer instead routes the XOR gate 212 for each CA input pin 206 to the CA LFSR 210 for the reference CA input pin 206. Thus, in Mode 2, each XOR gate 212 compares the PRBS for the corresponding CA input pin 206 to be received from the memory controller and the PRBS for the reference CA input pin 206 generated by the CA LFSR 210. The CA LFSR 210 for the reference pin is seeded by any of the techniques described herein.

[0059] Since the input pin 206 correctly samples the PRBS from the memory controller on the correct edge of the clock signal, the corresponding XOR gate 212 sends a pass result to the corresponding DQ, DQX and / or EDC pin 216. Since the CA input pin 206 incorrectly samples the PRBS from the memory controller on different edges of the clock signal, the corresponding XOR gate 212 sends a fail result to the corresponding DQ, DQX and / or EDC pin 216. A fail result occurs when the multi-cycle skew causes the PRBS received from the memory controller through the CA input pin 206 to not match the PRBS generated by the CALFSR210 at the reference point on at least some edges of the clock signal. When the memory controller detects a fault condition on one or more DQ, DQX and / or EDC pins 216, the memory controller skews the output data of the corresponding CA input pin 206 by one or more clock cycles. The memory controller repeatedly tests and skews the CA input pins 206 until each CA input pin 206 reliably captures the PRBS from the memory controller.

[0060] In a second sub-mode of Mode 2, a single CA input pin 206 receives a data pattern from a memory controller through a corresponding receiver 208. Circuitry for each CA input pin 206 captures the incoming data pattern and asynchronously sends the captured data pattern on the corresponding DQ, DQX, and / or EDC pins 216. In this sub-mode, the memory controller compares the data pattern received from the DRAM via the DQ, DQX, and / or EDC pins 216 with the data pattern sent to the DRAM via the CA input pins 206. If one or more DQ, DQX, and / or EDC pins 216 do not present the correct value, the memory controller skews the output data of the corresponding CA input pin 206 by one or more clock cycles. The memory controller repeatedly tests and skews the CA input pins 206 until each CA input pin 206 reliably captures the PRBS from the memory controller.

[0061] In the second sub-mode of Mode 2, the DRAM does not perform any data pattern checking, but instead returns the data captured through the CA input pin 206 to the DQ, DQX, and / or EDC pins 216. The memory controller performs data pattern checking in this sub-mode. Therefore, in this sub-mode, the memory controller may send any technically feasible data pattern to the CA input pin 206, including but not limited to PRBS, a predetermined non-PRBS pattern, a walking one pattern, a walking zero pattern, etc. Additionally or alternatively, the memory controller may send any data pattern to the CA input pin 206, based on any one or more predetermined, user-defined patterns, to the CA input pin 206. More generally, in this sub-mode, the memory controller may send any technically feasible data pattern to the CA input pin 20.

[0062] When the mode 2 test is completed, the memory controller switches the DRAM from the CA training mode to the normal operation mode. The memory controller switches the DRAM from mode 2 to the normal operation mode by sending a pattern that does not occur in the PRBS to one or more CA input pins 206. In some instances, a 15-bit PRBS does not generate a series of 15 zeros in a row. Therefore, the memory controller can switch the DRAM from mode 2 to the normal operation mode by sending a pattern of 15 consecutive zero values ​​to one or more CA input pins 206. In addition or alternatively, the memory controller can switch the DRAM from mode 2 to the normal operation mode by sending any pattern that does not occur in the PRBS to one or more CA input pins 206. When the DRAM detects the pattern, the DRAM determines that the pattern is not part of the PRBS, but a command. In response, the DRAM switches from mode 2 to the normal operation mode. The CA input pins are now trained, and the DRAM is now ready to receive commands from the memory controller.

[0063] It will be appreciated that the system shown below is illustrative and that variations and modifications are possible. Among other things, the training architecture 200 includes components for command address interface training, data read interface training, and data write interface training. However, the training architecture 200 may include components for training any other technically feasible input and / or output interface within the scope of the present disclosure.

[0064] Figure 3 According to various embodiments, Figure 1 A timing diagram 300 is provided for initializing a memory device included in the system memory 104 and / or the parallel processing memory 134 of a computer system of the present invention to receive a command.

[0065] The memory device uses a single clock signal scheme for capturing both commands and data. The rate of the clock signal is determined by the transfer rate of the highest speed interface of the memory device. Typically, the data interface transfers data at a higher rate than the command address interface. However, in some embodiments, the command address interface can transfer data at a higher rate than the data interface. The rate of the clock signal rate is set to the transfer rate of the highest speed interface, such as the data interface. The clock signal is used to transfer data to and from the memory device at a rate that typically transfers one data per clock cycle.

[0066] This clock signal is further used to send commands to the memory device at a lower transfer rate. More specifically, the command is transmitted to the memory device over multiple clock cycles of the high-speed clock signal, such as over four clock cycles. The high-speed clock signal is labeled WCK306 and is shown as Figure 2 The command address interface includes any number of I / O pins for transmitting commands to the memory device, including Figure 2 The CA input pin 206. In some embodiments, the command address interface includes five I / O pins, labeled CA[4:0], shown as CA[4:1] 308 and CA[0] 310 command I / O pins, respectively.

[0067] In some embodiments, each command is transmitted over four clock cycles of WCK 306. References to 0, 1, 2, and 3 represent four stages of command word 312. Over four cycles of WCK 306, a complete command word 312 is transmitted to the memory device over a continuous series of clock cycles 0, 1, 2, and 3. Thus, a complete command includes up to 4 clock cycles x 6 bits per clock cycle = 24 bits. Each complete command word 312 represents a command to be executed by the memory device, such as a write operation, a read operation, an activate operation, etc.

[0068] In order to synchronize the transmission of commands to the memory devices, a memory controller, such as the system memory controller 130 or the parallel processing subsystem (PPS) memory controller 132, sends a synchronization (sync) command 318 to the memory device before transmitting the command to the memory device. The synchronization command 318 indicates the valid command start point 314 for transmitting the command, that is, which clock edge corresponds to the first part of the multi-cycle command. At some time, the memory device loses synchronization and does not know which clock cycles are the valid command start points 314. For example, the memory device loses synchronization when it is powered on, loses synchronization when it recovers from reset, loses synchronization when it recovers from a low power state, such as an idle state or a self-refresh state, etc. In such a case, the memory controller sends a transmission synchronization command 318 to the memory device to implement the new command start point 314 and synchronize the memory device with the memory controller. Once synchronized, the memory device can begin to accept commands from the memory controller.

[0069] More specifically, when VPP, VDD, and VDDQ 302 are applied to the memory device, the memory device may be powered on, where VPP is a pump voltage, VDD is a main power supply voltage, and VDDQ is an I / O voltage. The memory controller applies a low voltage to the reset 304 input of the memory device to place the memory device in a reset state. Subsequently, the memory controller applies a high voltage to the reset 304 input of the memory device to take the memory device out of the reset state. Before applying the high voltage to the reset 304 input, the memory controller may apply a fixed bit pattern to the CA[4:1] 308 and CA[0] 310 command I / O pins of the memory device. The fixed bit pattern is referred to herein as a "band". The memory device samples the state of the band on the rising edge of reset 304 to determine the value of the fixed bit pattern. Based on the fixed bit pattern, the memory device may undergo certain startup procedures, such as a command address (CA) interface training 316 operation to command the memory device to determine the skew between the WCK 306 and the CA[4:1] 308 and CA[0] 310 command I / O pins. The memory controller completes the boot procedure, such as the CA interface training 316 operation, through an asynchronous communication sequence with the memory device. The CA interface training 316 operation determines the optimal skew of the CA[4:1] 308 and CA[0] 310 command I / O pins relative to WCK 306 to ensure that the setup time and hold time requirements for the [4:1] 308 and CA[0] 310 command I / O pins are met. The CA interface training 316 operation further detects and corrects any multi-cycle skew between any two or more command I / O pins to ensure that all command I / O pins capture the command bits for the same command word 312 at the same rising or falling edge of WCK 306.

[0070] After completing the CA interface training 316 operation, the memory device is in a state where it can receive commands synchronously with respect to the rising and / or falling edges of WCK 306. Alternatively, if the memory controller and the memory device have not performed the CA interface training 316 operation, the memory device is ready to receive commands synchronously at any time after the rising edge of reset 304. In either case, the memory controller sends a synchronization command 318 to the memory device before transmitting the command to the memory device on one of the command I / O pins, such as Figure 3 310 command I / O pins. When the memory device receives the synchronization command 318, the memory device counts the number of rising or falling edges of WCK 306 from the leading edge or trailing edge of the synchronization command 318. In some examples, the memory device counts four rising edges of WCK 306 after the trailing edge of the synchronization command 318 to determine the first command start point 314. The memory controller then applies phase 0 of the first command word 312 to the CA[4:1] 308 and CA[0] 310 command I / O pins. The memory controller applies phase 0 of the first command word 312 so as to be valid at the fourth rising edge of WCK 306 after the trailing edge of the synchronization command 318. The memory controller applies phases 1, 2, and 3 of the first command word 312 so as to be valid at consecutive rising edges of WCK 306. The memory device samples the four phases of the first command word 312 through CA[4:1] 308 and CA[0] 310 on these same four rising edges of WCK 306. The first rising edge of WCK 306 after phase 3 of the first command word 312 indicates the second command start point 314. The memory controller applies and the memory device transmits the four phases 0, 1, 2, 3 of the second command word 312 on four consecutive rising edges of WCK 306 starting with the second command start point 314. The first rising edge of WCK 306 after phase 3 of the second command word 312 indicates the third command start point 314, and so on.

[0071] In some embodiments, the memory device may be recovered from an idle state, a self-refresh state, etc. without going through a reset 304 or a full power down and power up of VPP, VDD, VDDQ 302. In such a case, the memory device may perform a CA interface training 316 operation by a mechanism other than strapping pin values. In some examples, the memory device may enter a CA interface training 316 operation by receiving an asynchronous command without asserting a reset 304 or a full power down and power up of VPP, VDD, VDDQ 302. According to the asynchronous process, the memory device may remove power from the receivers and transmitters of all I / O pins, including WCK 306, except for the receivers of one or more I / O pins of the memory device involved in the asynchronous process. When recovering from an idle state or a self-refresh state, the memory controller applies that the memory device searches for a specific value on one or more I / O pins of the memory device with an active receiver. For example, the memory device may maintain receiver activity for the CA[0] 310 command I / O pin and / or one or more receivers of the CA[4:1] 308 command pins during an idle or self-refresh state. When resuming from an idle or self-refresh state, the memory controller may apply and the memory device may detect specific values ​​on the CA[0] 310 command I / O pin and / or one or more CA[4:1] 308 command I / O pins. These values ​​on the CA[0] 310 command I / O pin and / or one or more CA[4:1] 308 command I / O pins may command the memory device to enter a CA interface training 316 operation.

[0072] In some examples, the memory controller can send commands to the memory device synchronously when the command address interface is trained or when operating at a sufficiently slow speed that no training is required. The memory controller sends the command to the memory device before causing the memory device to enter an idle state, a self-refresh state, etc. The memory device stores the command in a register of the memory device, such as a mode register. When the memory device is subsequently restored from the idle state, the self-refresh state, etc., the memory device reads the mode register to determine whether the mode register stores a command to enter the CA interface training 316 operation.

[0073] In response, to either the asynchronous command or the mode register command, the memory device begins a CA interface training 316 operation. Advantageously, the asynchronous process and the mode register process allow the memory controller to train the command address interface of the memory device without incurring the latency and penalty of performing a full power down / power up sequence. In contrast, when resuming from a low power state, such as an idle state, a self-refresh state, etc., the memory device quickly resumes operation of the memory controller.

[0074] Figure 4 According to various embodiments, Figure 1 The flowchart of the method steps for executing the command address interface training operation in the memory device of the system memory 104 and / or the parallel processing memory 134 of the computer system is shown. Figure 1-3 However, it can be understood by those skilled in the art that any system configured to perform the steps of the method, in any order, is within the scope of protection of the present disclosure.

[0075] As shown, method 400 begins with step 402, where the memory device determines that the memory device has received a command address (CA) training entry command. The memory controller can cause the DRAM to enter command address interface training through multiple different techniques. In some examples, when power is initially applied to the DRAM and / or when a reset is sent to the DRAM, the memory controller applies a fixed bit pattern to one or more CA input pins 206. The fixed bit pattern is referred to as a band below. The memory device samples the state of the band on the rising edge of the reset signal to determine the value of the fixed bit pattern. Based on the fixed bit pattern, the DRAM enters the command address interface training 316 operation. In some examples, when the DRAM exits a low power state, such as an idle state or a self-refresh state, the DRAM can detect an asynchronously received self-refresh exit command and / or a power-on exit command. In some examples, the memory controller can send a command DRAM transmission to load a register in the DRAM, such as a mode register, with a specific value including a command to enter a command address training operation. The memory controller sends a command to the DRAM when the command address interface is trained or when the command address interface operates at a sufficiently low operating speed that training is not required. When the DRAM subsequently enters and subsequently exits a low power state, such as an idle state, a self-refresh state, etc., the DRAM reads the mode register and enters a command address training operation based on the value stored in the mode register.

[0076] At step 404, the memory device enters a first training mode to test the individual CA input pins 206. Upon entering the command address training operation, the DRAM enters a first mode (Mode 1) of command address training. In Mode 1, the memory controller and the DRAM independently test the setup time and hold time for each command address input pin 206. The circuitry for each command address input pin 206 includes a CALFSR 210 that generates a pseudo-random bit sequence (PRBS). The circuitry for each command address input pin 206 further includes a PRBS checker, such as an XOR gate 212, which compares the PRBS generated by the CALFSR 210 with the PRBS received from the memory controller via the receiver 208.

[0077] At step 406, the memory device compares the data pattern received at each CA input pin 206 with the data pattern generated by each CA LFSR 210 for the corresponding CA input pin 206. At step 408, the memory device sends the comparison result for each CA input pin 206 to the corresponding data pin, such as DQ, DQX and / or EDC pin 216. When performing steps 406 and 408, the PRBS output of the CA LFSR 210 is checked against the PRBS received from the memory controller. If the PRBS received from the memory controller is correctly sampled, the CA LFSR 210 generates the same required PRBS, and the XOR gate 212 sends a pass result. The DRAM sends the pass result to the memory controller asynchronously through the DQ / DQX / EDC output pin 216. Although the DRAM can send a pass result value or a fail result value to the DQ / DQX / EDC output pin 216 during self-seeding, once self-seeding is completed, the DQ / DQX / EDC output 216 switches to sending a pass result value. The memory controller asynchronously receives data through the DQ / DQX / EDC output pins 216 and analyzes the data to determine if the Mode 1 command address interface training operation resulted in a pass result value. If one or more DQ / DQX / EDC output pins 216 indicate a fail result value, the memory controller adjusts the skew between the corresponding CA input pins 206 and the clock signal until all CA input pins 206 consistently receive a pass result value. The memory controller continues to perform the Mode 1 command address interface training operation to determine the optimal point for each CA input pin 206 with respect to the setup time and hold time.

[0078] In step 410, the memory device determines that the memory device has received a training mode switch command. After Mode 1 is completed, each CA input pin 206 is trained individually with respect to the setup time and hold time associated with the clock signal. However, the sampling points of different CA input pins 206 may appear at different edges of the clock signal. Therefore, the DRAM can sample certain CA input pins 206 on one edge of the clock signal, and other CA input pins 206 on the previous edge of the clock signal and / or the subsequent edge of the clock signal. Therefore, when the memory controller sends a signal set to the CA input pins 206 of the DRAM, the DRAM can sample a portion of the signal on one edge of the clock signal, and another portion of the signal on one or more different edges of the clock signal. This condition is called multi-cycle skew. In order to correct this problem, the memory controller converts the DRAM from Mode 1 of command address interface training to a second mode (Mode 2) of command address interface training.

[0079] The memory controller switches the DRAM from Mode 1 to Mode 2 by sending a pattern that does not occur in a PRBS to one or more CA input pins 206. In some examples, a 15-bit PRBS does not generate a series of 15 zeros in a row. Therefore, the memory controller can switch the DRAM from Mode 1 to Mode 2 by sending a pattern of 15 consecutive zero values ​​to one or more CA input pins 206. Additionally or alternatively, the memory controller can switch the DRAM from Mode 1 to Mode 2 by sending any pattern that does not occur in a PRBS to one or more CA input pins 206. When the DRAM detects the pattern, the DRAM determines that the pattern is not part of the PRBS, but a command. In response, the DRAM switches from Mode 1 to Mode 2.

[0080] At step 412, the memory device enters a second training mode (Mode 2) to test the CA input pins 206 as a group. In Mode 2, the memory controller and DRAM test multi-cycle skew between the command address input pins 206 as a group. The memory controller and DRAM test the multi-cycle skew through one of the two sub-modes within Mode 2. At step 414, the memory device compares the data pattern at each CA input pin 206 with the data pattern from the LFSR, such as the CA LFSR 210, for the specified CA input pin 206. In Mode 2, a single CA input pin 206 is used as a reference pin for all CA input pins 206. The PRBS generated by the CA LFSR 210 for the single reference pin is used to compare with the pattern received from the memory controller on all other CA input pins 206. In some embodiments, this structure is implemented by a multiplexer. In such an embodiment, in Mode 1, the multiplexer routes the XOR gate 212 for each CA input pin 206 to the CA LFSR 210 for that CA input pin 206. In Mode 2, the multiplexer instead routes an XOR gate 212 for each CA input pin 206 to the CA LFSR 210 for the reference CA input pin 206. Thus, in Mode 2, each XOR gate 212 compares the PRBS for the corresponding CA input pin 206 received from the memory controller with the PRBS for the reference CA input pin 206 generated by the CA LFSR 210. The CA LFSR 210 for the reference pin is seeded by any of the techniques described herein.

[0081] At step 416, the memory device sends the comparison result of each CA input pin 206 to the corresponding DQ, DQX and / or EDC pin 216. Since the CA input pin 206 correctly samples the PRBS from the memory controller on the correct edge of the clock signal, the corresponding XOR gate 212 sends a pass result to the corresponding DQ, DQX and / or EDC pin 216. Since the CA input pin 206 incorrectly samples the PRBS from the memory controller on a different edge of the clock signal, the corresponding XOR gate 212 sends a fail result to the corresponding DQ, DQX and / or EDC pin 216. A fail result occurs when a multi-cycle skew causes the PRBS received from the memory controller via the CA input pin 206 to not match the PRBS generated by the CA LFSR 210 at the reference point on at least some edges of the clock signal. When the memory controller detects a fault condition on one or more DQ, DQX and / or EDC pins 216, the memory controller skews the output data of the corresponding CA input pin 206 by one or more clock cycles. The memory controller repeatedly tests and skews the CA input pins 206 until each CA input pin 206 reliably captures the PRBS from the memory controller.

[0082] In step 418, the memory device determines that the memory device has received a training mode switch command. When the Mode 2 test is completed, the memory controller causes the DRAM to switch from the CA training mode to the normal operation mode. The memory controller causes the DRAM to switch from Mode 2 to the normal operation mode by sending a pattern that does not occur in the PRBS to one or more CA input pins 206. In some instances, a 15-bit PRBS does not generate a series of 15 zeros in a row. Therefore, the memory controller can cause the DRAM to transition from Mode 2 to the normal operation mode by sending a pattern of 15 consecutive zero values ​​to one or more CA input pins 206. In addition or alternatively, the memory controller can cause the DRAM to switch from Mode 2 to the normal operation mode by sending any pattern that does not occur in the PRBS to one or more CA input pins 206.

[0083] At step 420, the memory device exits command address interface training. When the DRAM detects a pattern that does not occur in the PRBS, the DRAM determines that the pattern is not part of the PRBS but is a command. In response, the DRAM switches from Mode 2 to the normal operating mode. At this time, the CA input pin is trained, and the DRAM is ready to receive commands from the memory controller.

[0084] The method 400 then terminates. Alternatively, the method 400 proceeds to step 402 to perform additional command address input training operations.

[0085] In summary, various embodiments relate to techniques for efficiently performing command address interface training of DRAM memory devices. The disclosed techniques reduce DRAM pin overhead by eliminating the CKE pin and instead training the command address (CA) interface with a continuous PRBS (pseudo-random binary sequence) pattern. The memory controller sends a CA training enter command to the DRAM to ensure that the DRAM correctly enters the CA training mode. Once in the CA training mode, a per-CA-pin checker is used to compare the incoming CAPRBS pattern with the LFSR (linear feedback shift register) output, which has been initialized according to a starting value.

[0086] In some embodiments, the DRAM initializes the LFSR according to a predetermined seed value. Additionally or alternatively, the DRAM initializes the LFSR according to a seed value that has been sent to the DRAM by the memory controller. In these latter embodiments, when the command address interface operates at a lower frequency and does not require interface training, the memory controller sends the seed value to the DRAM through the command address interface. In some embodiments, the DRAM initializes the LFSR by self-seeding. For self-seeding, when the DRAM begins a training sequence, the DRAM loads the LFSR according to a portion of an initial PRBS sequence received from the memory controller. Thereafter, the output of the LFSR is checked for the remaining PRBS sequence received from the memory controller.

[0087] The DRAM presents the pass / fail result of the comparison between the LFSR output and the data pattern from the memory controller by sending the pass / fail result on the DQ (data) pins of the DRAM. The DRAM sends the pass / fail result in an asynchronous manner, which allows the memory controller to reliably sample the result information without the DQ pins having been trained. Based on the results of the comparison, the memory controller can make adjustments on the memory controller and / or DRAM to change the conversion and reception of signals at the command address interface. Thereafter, the memory controller can periodically re-initiate CA training to ensure that the command address interface operates as expected or make further adjustments to the command address interface.

[0088] At least one technical advantage of the present disclosure relative to the prior art is that, according to the disclosed technology, a clock enable (CKE) pin is not required to perform command address interface training. Therefore, a receiver and an I / O pin are no longer required to receive the clock enable signal. Therefore, the complexity, surface area, and power consumption of the internal circuitry of the DRAM die can be reduced relative to the clock enable pin approach. Further, the I / O pin previously used to receive the clock enable signal can be used for another function, such as an additional command bit, data bit, or control signal. Another advantage of the present disclosure is that command address interface training is performed in a continuous manner, with no gaps between consecutive captures of the command address input pins. Therefore, command address interface training is performed in less time relative to previous methods. These advantages are presented as one or more technical improvements relative to prior art methods.

[0089] Any and all combinations of any claim elements recited in any claim and / or any elements described in this application are within the intended scope of the present disclosure and protection in any manner.

[0090] The description of the various embodiments has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments.

[0091] Aspects of the present embodiment may be embodied as a system, method, or computer program product. Therefore, aspects of the present disclosure may take the form of a complete hardware embodiment, a complete software embodiment (including firmware, resident software, microcode, etc.), or a combination of software and hardware embodiments, which may all be collectively referred to herein as a "module" or "system". In addition, aspects of the present disclosure may take the form of a computer program product embodied in one or more computer-readable media having a computer-readable program code embodied thereon.

[0092] Any combination of one or more computer-readable media may be utilized. A computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or apparatus, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of computer-readable storage media would include the following: an electrical connection with one or more conductors, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in conjunction with a command execution system, apparatus, or device.

[0093] Aspects of the present disclosure are described above with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each box of the flowchart and / or block diagram and the combination of the boxes in the flowchart and / or block diagram can be implemented by computer program commands. These computer program commands can be provided to a processor of a general-purpose computer, a special-purpose computer or other programmable data processing device, so as to produce a machine so that these computer program commands can implement the functions / actions specified in one or more boxes of the flowchart and / or block diagram when executed by the processor of the computer or other programmable data processing device. Such a processor can be, but is not limited to, a general-purpose processor, a special-purpose processor, a special-purpose processor or a field programmable gate array.

[0094] The flow chart and block diagram in the figure show the architecture, function and operation of the possible implementation of the system, method and computer program product according to each embodiment of the present disclosure. To this end, each square box in the flow chart or block diagram may represent a module, fragment or part of the code, which includes one or more executable commands for realizing the specified logical function. It should also be noted that in some alternative embodiments, the function indicated in the frame may not occur in the order indicated in the figure. For example, depending on the function involved, the two frames shown in succession can actually be executed substantially at the same time, or these frames can sometimes be executed in the opposite order. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer commands.

[0095] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the following claims.

Claims

1. A computer-implemented method for performing a memory interface training operation on a memory device, the method comprising: receiving a first data pattern on a first input pin of the memory device; initializing a first register on the memory device according to a second data pattern; generating, by the memory device, a third data pattern in the memory device based on the second data pattern in the first register; comparing, by the memory device, the first portion of the first data pattern and the third data pattern to generate a first result value indicating whether the memory device correctly received the first portion of the first data pattern; as well as The first result value is sent to a first output of the memory device.

2. The computer-implemented method of claim 1, wherein the second data pattern comprises a predetermined value.

3. The computer-implemented method of claim 1, wherein the second data pattern comprises a second portion of the first data pattern.

4. The computer-implemented method of claim 1 , further comprising: determining that the first portion of the first data pattern matches the third data pattern, The first result value indicates a pass result.

5. The computer-implemented method of claim 1 , further comprising: determining that the first portion of the first data pattern does not match the third data pattern, The first result value indicates a failure result.

6. The computer-implemented method of claim 1 , further comprising: receiving a fourth data pattern on the first input pin and the second input pin of the memory device; initializing the first register on the memory device according to a fifth data pattern; Based on the fifth data pattern, generating a sixth data pattern through the first register; comparing a first portion of the fourth data pattern received at the first input pin with the sixth data pattern to generate a second result value; comparing the first portion of the fourth data pattern received at the second input pin with the sixth data pattern to generate a third result value; sending the second result value to the first output of the memory device; as well as The third result value is sent to a second output of the memory device.

7. The computer-implemented method of claim 1 , wherein: Comparing the first portion of the first data pattern with the third data pattern includes performing an XOR operation on the first portion of the first data pattern and the third data pattern.

8. The computer-implemented method of claim 7, wherein the first result value is based on an output of the XOR operation.

9. The computer-implemented method of claim 1 , wherein: Initializing the first register on the memory device according to the second data pattern includes: receiving an initial value from a memory controller; and The initial value is stored in the first register.

10. The computer-implemented method of claim 1, wherein the first register comprises a linear feedback shift register.

11. The computer-implemented method of claim 1 , wherein at least one of the first data pattern or the second data pattern comprises a pseudo-random bit sequence.

12. A system for performing a memory interface training operation, comprising: Memory controller; as well as a memory device coupled to the memory controller and: receiving, by the memory controller, a first data pattern on a first input pin of the memory device; initializing a first register on the memory device according to a second data pattern; generating a third data pattern in the memory device based on the second data pattern in the first register; comparing a first portion of the first data pattern and the third data pattern to generate a first result value indicating whether the first portion of the first data pattern was correctly received by the memory device; as well as The first result value is sent to a first output of the memory device.

13. The system of claim 12, wherein the second data pattern comprises a predetermined value.

14. The system of claim 12, wherein the second data pattern comprises a second portion of the first data pattern.

15. The system of claim 12, wherein: The memory device is also used for: determining that the first portion of the first data pattern matches the third data pattern, The first result value indicates a pass result.

16. The system of claim 12, wherein: The memory device is also used for: determining that the first portion of the first data pattern does not match the third data pattern, The first result value indicates a failure result.

17. The system of claim 12, wherein: The memory device is also used for: receiving a fourth data pattern on the first input pin and the second input pin of the memory device; initializing the first register on the memory device according to a fifth data pattern; Based on the fifth data pattern, generating a sixth data pattern through the first register; comparing a first portion of the fourth data pattern received at the first input pin with the sixth data pattern to generate a second result value; comparing the first portion of the fourth data pattern received at the second input pin with the sixth data pattern to generate a third result value; sending the second result value to the first output of the memory device; as well as The third result value is sent to a second output of the memory device.

18. The system of claim 12, wherein: The memory device compares the first portion of the first data pattern with the third data pattern, including performing an exclusive-OR (XOR) operation on the first portion of the first data pattern and the third data pattern.

19. The system of claim 18, wherein the first result value is based on an output of the XOR operation.

20. The system of claim 12, wherein: The memory device initializes the first register on the memory device according to the second data mode by the following steps: receiving an initial value from the memory controller; and The initial value is stored in the first register.

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