Storage device life extension device and method suitable for civil aviation airborne equipment

Abstract

The present invention relates to a device and method for extending the life of a storage device suitable for civil aviation airborne equipment. The device comprises: an energy storage circuit for providing power to the device when an external power source is lost; a power-off monitoring alarm circuit for real-time monitoring of the device power status and issuing an interrupt alarm signal when an external power source is lost; a power-off interrupt processing module for triggering power-off storage of data; a timer interrupt processing module for triggering timed storage of data; a non-volatile memory space partitioning module for initializing, updating, and maintaining data storage addresses and their index addresses; and a memory access space validity detection module for detecting the validity of the data storage space. The present invention can effectively reduce the access rate to the memory storage space and improve the utilization rate of the storage space while ensuring data storage reliability, thereby achieving the purpose of extending the life of the memory.

Description

Technical Field

[0001] The present invention relates to a device and method for extending the life of a storage device applicable to civil aviation airborne equipment. Background Art

[0002] Civil aviation airborne equipment refers to the tracking and monitoring equipment installed on aircraft, specifically transceivers equipped with satellite short message communications and navigation and positioning capabilities. Due to the large number and complexity of equipment onboard an aircraft, the proper functioning of each device during operation is crucial to aircraft safety. The operational status of these devices can be reflected in the real-time status of key parameters. Furthermore, due to limited communication capabilities within the devices, critical parameter information that cannot be transmitted to monitoring personnel in real time can be temporarily stored in non-volatile memory, allowing for data review and analysis when the equipment returns to the ground for maintenance.

[0003] Existing methods for saving data in non-volatile memory mainly include single power-off saving and real-time saving. Single power-off saving may fail, and because it only saves data during a power outage, any failure will result in a loss of data, hindering subsequent data analysis. Real-time saving requires frequent erasing and writing of the non-volatile memory, significantly reducing its lifespan and affecting the normal use of the device. Summary of the Invention

[0004] The object of the present invention is to provide a device and method for extending the life of a storage device suitable for civil aviation airborne equipment.

[0005] To achieve the above-mentioned object, the present invention provides a device and method for extending the life of a storage device applicable to civil aviation airborne equipment, the device comprising:

[0006] Energy storage circuits, used to provide power to the device when external power is lost;

[0007] Power failure monitoring alarm circuit, used to monitor the power status of the device in real time and send out an interruption alarm signal when the external power supply is lost;

[0008] Power-off interrupt processing module, used to trigger power-off storage of data;

[0009] Timer interrupt processing module, used to trigger the timing storage of data;

[0010] A non-volatile memory space partitioning module is used to initialize and update the data storage address and its index address;

[0011] The memory access space validity detection module is used to perform validity detection on the data storage space.

[0012] According to one aspect of the present invention, the energy storage circuit includes a voltage stabilizing circuit, a DC / DC conversion module (DC to DC power conversion module), and an isolation circuit;

[0013] When the device is powered on, the external power supply signal passes through the voltage stabilization circuit to obtain a stable power signal, and then passes through the DC / DC conversion module to obtain a secondary regulated power signal. This power signal charges the components with energy storage function in the isolation circuit;

[0014] When the device loses power, the isolation circuit begins to discharge and provide power to other loads in the device.

[0015] According to one aspect of the present invention, a power failure monitoring alarm circuit includes a power acquisition circuit and a processor (CPU), and two voltage signals output by the power acquisition circuit are connected to the IO pins of the processor chip;

[0016] When the power signal is lost or drops below the threshold voltage, the output voltage of the power acquisition circuit changes from high level to low level, and triggers the processor to generate an interrupt signal;

[0017] After the processor detects the external power loss alarm signal output by the power acquisition circuit, it sets the power-off saving flag to be valid;

[0018] After the processor detects the device power-off alarm signal output by the power acquisition circuit, it does not perform any operation until the power is cut off.

[0019] According to one aspect of the present invention, the storage space of the storage device is divided into:

[0020] Index address space, used to store the address value of data storage space;

[0021] Data storage space, used to store real-time updated data;

[0022] The spare storage space is used as a new data storage space when the current data storage space fails, and updates the value in the index address space.

[0023] According to one aspect of the present invention, the update and maintenance module of the data to be saved in the SRAM is used to save the value of the parameter state during the operation of the device in real time;

[0024] The data storage module is used to start when it detects that the timing time has expired or the power-off signal is valid, extract the data stored in the SRAM and save it to the non-volatile memory, and judge the reliability of the data storage each time the data is stored.

[0025] A method for extending the life of a storage device applicable to civil aviation airborne equipment comprises the following steps:

[0026] a. When the device is powered on, the energy storage circuit stores electricity, the power failure monitoring alarm circuit monitors the power status of the device in real time, and the software timer counts the data in real time;

[0027] b. Determine whether the power-off save flag is valid. If the power-off save flag is invalid, update the storage information in SRAM (Static Random Access Memory) in real time and process other tasks;

[0028] c. Determine whether the timed save flag is valid. If the timed save flag is valid, determine whether the power-off save flag is valid. If the power-off save flag is invalid, store the data in the non-volatile memory.

[0029] According to one aspect of the present invention, after the timing data saving timing time expires, the timer interrupt processing module sets the timing saving flag to be valid;

[0030] When the power-off detection circuit detects that the device is powered off, the power-off interrupt processing module sets the power-off save flag to be valid, shielding other tasks and only performing data storage.

[0031] According to one aspect of the present invention, when the power-off saving flag is valid, it is determined whether the current power-off is a false power-off. If so, the power-off saving flag is set to invalid and other tasks are resumed;

[0032] Before storing data in the non-volatile memory, it is determined whether the current data storage space is valid. If so, the data is stored. Otherwise, a new valid data storage space is found and the new data storage address is updated to the index address space.

[0033] According to one aspect of the present invention, when determining a false power failure, a timer is started to count the power failures after a power failure signal is detected. If the device is still in a normal working state after a period of time, the power failure is determined to be a false power failure.

[0034] When judging the validity of the data storage space, first write the data into the current data storage space, then read the data to determine whether the read data is consistent with the written data. If so, the current data storage space is determined to be valid, otherwise it is determined to be invalid, and the memory is searched again for available storage space and the writing and reading of data are repeated. If the data storage space is determined to be invalid after a certain number of repetitions, the storage is abandoned and the updated data storage address is rewritten into the index address space.

[0035] According to one aspect of the present invention, in step (a), an initialization step is also included, including: storage space division and management, initialization configuration of timer parameters, and acquisition of data storage address.

[0036] According to one aspect of the present invention, the storage space is divided and managed as follows: a memory index address A and an initial data storage address B are set; when setting, a certain address space is reserved before the initial data storage address B for storing configuration parameter information; the address space after the initial data storage address B is used as a backup storage address space; when the current data storage space is invalid, the backup storage address is searched in a forward-to-backward order;

[0037] The initialization configuration of the timer parameters is to start the timer, set the IO level interrupt trigger mode, and enable all interrupts, including timer interrupts and IO interrupts;

[0038] When obtaining the data storage address, read the content of the index address space, and determine whether the data is valid based on the parameter value and check value in the read content. If so, extract the data storage address value B, otherwise initialize the index address space with the initial value of the data storage address.

[0039] According to the concept of the present invention, a life extension scheme for storage devices in civil aviation airborne equipment is proposed. This scheme can be applied to the research on the storage process of important parameter information on civil aviation airborne equipment, meeting the storage needs of important real-time parameter information for late-stage flight status analysis of civil aviation airborne equipment, and resolving the limitation on the service life of non-volatile memory on airborne equipment due to the limited number of erase and write cycles. While ensuring data storage reliability, it can effectively reduce the access rate to memory storage space and improve the utilization rate of storage space, thereby achieving the purpose of extending the service life of memory. The scheme uses a combination of software and hardware to perform wear leveling on the use of storage devices in civil aviation airborne equipment, thereby achieving the purpose of extending the service life of storage devices and thus ensuring the effectiveness of data storage. This scheme enables the effective preservation of key parameters during the effective service life of the equipment, and has great application value in the field of civil aviation electromechanical equipment.

[0040] According to one solution of the present invention, a power-loss warning system is added to the device circuitry. Only when power loss is detected does the memory device write to the stored parameters. During normal device operation, the stored parameters are updated and maintained in real time in the processor's SRAM and periodically written to the memory's designated address space, significantly reducing the frequency of memory accesses. Furthermore, dual-address balancing is employed to increase the amount of accessible memory space. This combined storage method and memory address space balancing effectively improves the lifespan of the device's memory.

[0041] According to one solution of the present invention, power-off preservation and timed preservation are combined, thereby reducing the access rate to the storage unit, thereby increasing the service life of the storage address unit, and improving the effectiveness of data preservation. Furthermore, a storage circuit and a power-off monitoring and alarm circuit are designed to improve the reliability of parameter preservation during power outages. The use of dual address spaces for balanced storage space effectively improves memory space utilization, thereby significantly extending the service life of the entire storage device.

[0042] According to one embodiment of the present invention, the device includes a circuit portion (energy storage circuit, power-off monitoring and alarm circuit) and a software processing portion (power-off interrupt processing module, timer interrupt processing module, non-volatile memory space partitioning module, memory access space validity detection module, memory space failure processing module, and data storage module). When the circuit portion is in operation, the device is first connected to an external power source, the energy storage circuit operates, and the energy storage components in the isolation circuit are charged until fully charged and maintain their energy state. When the external power source is lost, the energy storage components in the isolation circuit begin to discharge to ensure normal circuit operation. During this period, the power-off monitoring and alarm circuit continuously monitors the power status. Upon detecting a power loss, it triggers a software interrupt by controlling an IO level signal.

[0043] According to one solution of the present invention, a power-off preservation mechanism for airborne equipment parameters is designed to ensure that the latest parameter status before the equipment is powered off can be recorded, thereby providing the most complete data for subsequent equipment maintenance. Specifically, after the CPU detects a level interrupt signal, it sets a power-off flag in the interrupt, and then, after detecting the flag in the main loop, shields other functions and starts parameter saving.

[0044] According to one solution of the present invention, a storage space balanced usage mechanism is designed, that is, a balanced allocation of limited storage space is achieved through dual address spaces. The dual address spaces refer to: index address space A and real-time data storage space B. Index address space A is a fixed address space, and real-time data storage space B is a variable address space. The content of space A is the address value of space B. When space B changes, space A records the new address value of space B. The addressing range of space B can be all unused address spaces of the memory. Since non-volatile memory is mostly erased and written in units of "blocks" and "pages" (some are in units of "bytes"), when the current storage space B is operated, only the address unit where space B is located is affected. That is, if the storage space fails due to the number of erase and write times exceeding the erase and write times limited by the memory, only the address unit operated on will fail, and the use of other address units will not be affected.

[0045] According to one solution of the present invention, by adopting a method combining an index address space and a variable data storage space (ie, multiple backup storage spaces), balanced use of memory storage space can be effectively achieved, thereby increasing the service life of the memory.

[0046] According to one solution of the present invention, a validity detection mechanism for storage space is designed to ensure the validity of data storage. Specifically, a verification parameter is set in the stored parameter data packet, and the verification value is updated each time the data is updated; the address value of the data storage space B is read from the index space A, and then the parameter data packet to be saved is written into the space B. After writing, the data content is read back from the space B, and the read data is compared with the written data to see if they are consistent. If they are consistent, the storage space is considered valid, otherwise the space is considered invalid; after determining that the storage space is invalid, a storage address B' is re-searched from the unused address space of the memory to be used as a new data storage space, and the current parameter to be saved is written into B', and the value in the index space A is updated to B'.

[0047] According to one solution of the present invention, a timed saving mechanism for airborne equipment parameters is designed to prevent the situation where a single power-off saving is invalid, resulting in no valid data for subsequent equipment fault analysis. Timed saving is different from real-time data saving, and the storage frequency is lower, so the access frequency to the memory is lower, which can meet the limit on the number of memory erase and write times. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 A diagram schematically showing the configuration of a storage device life extension device applicable to civil aviation onboard equipment according to one embodiment of the present invention;

[0049] Figure 2 A schematic diagram showing a principle block diagram of an energy storage circuit according to an embodiment of the present invention;

[0050] Figure 3 Schematically shows a block diagram of a power failure monitoring alarm circuit according to an embodiment of the present invention;

[0051] Figure 4 A diagram schematically illustrating a storage space allocation diagram of a storage device according to an embodiment of the present invention;

[0052] Figure 5 A flowchart schematically illustrating a method for extending the life of a storage device applicable to civil aviation airborne equipment according to an embodiment of the present invention;

[0053] Figure 6 A software processing flow chart schematically showing an embodiment of the present invention for extending the life of a storage device applicable to civil aviation onboard equipment. DETAILED DESCRIPTION

[0054] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be derived from these drawings without inventive effort.

[0055] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments. The embodiments cannot be described one by one here, but the embodiments of the present invention are not limited to the following embodiments.

[0056] See also Figure 1 The storage device life extension device for civil aviation airborne equipment of the present invention includes two parts: circuit and software. The circuit part includes an energy storage circuit and a power-off monitoring alarm circuit. The software part includes an update and maintenance module for data to be saved in SRAM, a power-off interrupt processing module, a timer interrupt processing module, a data storage module, and a memory space maintenance (i.e., failure processing) module (i.e., a collection of a non-volatile memory space partitioning module and a memory access space validity detection module). Among them, the energy storage circuit is used to provide a short power signal to the device when the external power is lost, which can maintain the normal operation of the device and meet the relevant requirements of DO-160; the power-off monitoring alarm circuit is used to monitor the power status of the device in real time, and trigger an interrupt alarm by controlling the IO level signal when the external power is lost; the power-off interrupt processing module is used to respond to the power-off interrupt signal and execute power-off data storage; the timer interrupt processing module is used to realize the data timing storage function during the normal operation of the device; the non-volatile memory space partition module (i.e., Figure 1 The "dual address space division" and "spare space management" submodules in the "memory update maintenance module" are used to initialize and update the data storage address and the index address of the storage address; the memory access space validity detection module (i.e. Figure 1 The "Access Space Validity Detection" submodule in the "Memory Update Maintenance Module" is used to detect the validity of the data storage space to ensure the validity of data storage; the update and maintenance module for data to be saved in SRAM is used to save the value of the parameter status during the operation of the equipment in real time. Every time the value changes, it will be updated in SRAM in a timely manner. The data stored in SRAM is data that may be lost in the event of power failure; the data storage module will start when it detects that the timing time has expired or the power-off signal is valid, that is, the data stored in SRAM will be extracted and saved to the non-volatile memory. The reliability of the data storage must be judged each time the data is stored.

[0057] See also Figure 2The energy storage circuit includes a voltage stabilizing circuit, a DC / DC conversion module (or DC / DC circuit), and an isolation circuit. When the onboard device is powered on (i.e., there is an external power input), the external power signal passes through the voltage stabilizing circuit to obtain a stable power signal, and then passes through the DC / DC conversion module to obtain a secondary regulated power signal. This power signal charges the components with energy storage function in the isolation circuit. Among them, the Power_after voltage signal output by the isolation circuit is used to power other circuits of the device. That is, when the device is powered off (i.e., the external power is lost), the Power_befor voltage signal (i.e., the sampling voltage at this point) is lost. At this time, the components with energy storage function in the isolation circuit begin to discharge to provide the Power_after voltage (power) signal, thereby maintaining the normal operation of the device for a period of time and realizing data power-off storage.

[0058] See also Figure 3 The power-off monitoring alarm circuit includes a power acquisition circuit and a processor (CPU). The two voltage signals output by the power acquisition circuit are connected to the IO pins of the processor chip. When the power (voltage) signal is lost or drops below the threshold voltage, the voltage output by the power acquisition circuit changes from a high level to a low level. After this level signal is connected to the processor IO pin, it can trigger the processor to generate an interrupt signal. Specifically, when the processor detects the Power_Los t external power loss alarm signal (interrupt signal) output by the power acquisition circuit, the power-off save flag is set to valid; when the processor detects the Power_WRN device power-off alarm signal (interrupt signal) output by the power acquisition circuit, it means that the energy storage component in the isolation circuit is about to be exhausted. At this time, no operation is performed until the power is cut off.

[0059] See also Figure 4 The storage space of the storage device is divided into: index address space, which is used to store the address value of the data storage space; data storage space, which is used to store real-time updated data; spare storage space (that is, spare space of data storage space), which is used as new data storage space when the current data storage space fails (generally the spare space adjacent to the current data storage space), and updates the value in the index address space.

[0060] See also Figure 5 and Figure 6, a method for extending the life of storage devices suitable for civil aviation airborne equipment, mainly including power-off data preservation, timed data preservation and memory address space maintenance. Of course, this method performs initialization steps before the main loop, specifically including: storage space division and management, initialization configuration of timer parameters, and obtaining data storage address. The storage space division and management is to set the memory index address A and the initial data storage address B. When setting, a certain address space is reserved before the initial data storage address B to save some configuration parameter information, and the address space after the initial data storage address B is used as a backup storage address space. When the current data storage space is invalid, it is stored in the order from front to back (i.e. Figure 4 The backup storage address is searched in the order of the backup storage space B' from left to right in the index. The initialization configuration of the timer parameters is to start the timer, set the IO level interrupt trigger mode, and enable all interrupts (that is, turn on all interrupts so that the interrupts can respond normally), including timer interrupts and IO interrupts. When obtaining the data storage address, read the content of the index address space, and judge whether the data is valid based on the parameter value and check value in the read content. If it is valid, extract the data storage address value B (which has the same meaning as the above-mentioned "initial data storage address B", both indicating the address space with the same function, but its value is not necessarily the same, that is, if the address space of the "initial data storage address B" is always valid, it remains unchanged, otherwise it will be replaced by a certain address of the "backup storage address"). If it is invalid, initialize the index address space with the initial value of the data storage address in the above-mentioned "storage space division and management" step.

[0061] While the main loop is processing tasks normally, it also updates the device's operating status parameters in real time, temporarily storing these values ​​in SRAM. Specifically, after the device is powered on, the energy storage circuit stores energy, the power-off detection and alarm circuit (operating normally) monitors the device's power status in real time, and the software timer (operating normally) keeps track of data storage. Of course, after initialization, it's necessary to determine whether the power-off save flag is valid. If so, other tasks are disabled, allowing only data storage. Otherwise, the SRAM is updated in real time (i.e., the data to be stored is updated in real time in the processor's SRAM), and other tasks are processed.

[0062] In addition, during the normal operation of the main loop device, it is also necessary to check in real time whether the power-off data save flag and the scheduled data save flag are valid, so as to determine whether to perform the subsequent data save operation to the non-volatile memory (i.e., execute the power-off data save step or the scheduled data save step operation). Specifically, if the scheduled save flag is valid, it is further determined whether the power-off save flag is valid. When the power-off data save flag is also valid, normal working tasks are not processed and the device status parameters are not updated. Only when the power-off save flag is invalid, data is stored to the non-volatile memory. This is because the power-off storage has a higher priority. Therefore, if the power-off mark signal is also valid after the scheduled time expires, the scheduled storage is no longer executed, and the power-off storage is executed instead.

[0063] Among them, the timed data is saved as follows: after the timed data save timing expires (i.e., the timed storage timing expires), the timer interrupt processing module sets the timed save flag (or timed data save flag) to be valid. When the main program detects that the timed save flag is valid in the main loop, it starts the storage of the device working status parameters and determines whether the power-off data storage flag is valid before storage. If it is invalid, the main program performs the data storage operation to the non-volatile memory. The power-off data is saved as follows: when the power-off detection circuit detects that the device is powered off, it triggers the software to enter an interrupt, that is, the power-off save flag is set to be valid in the power-off interrupt processing module. When the main program detects that the power-off data save flag is valid in the main loop, the main program closes (shields) other work tasks of the processor software engineering and only performs the power-off data storage work to reduce time consumption.

[0064] The present invention first determines whether the current data storage space is valid before data storage. If the storage space is valid, the data is stored. Otherwise, the software automatically searches for a new valid data storage space for data writing and updates the new data storage address to the index address space. The specific storage space validity detection is to first write the data into the current data storage space, then immediately read the data, and determine whether the read data is consistent with the written data. If so, the data storage space is determined to be valid (that is, the first data storage operation of the scheduled data storage or power-off data storage is valid, and the data writing operation is no longer repeated until the next scheduled storage time arrives or the power-off signal is valid). Otherwise, if the data storage space is determined to be invalid, the memory is searched for available storage space again, and the data writing and reading operations are repeated (while judging the validity of the data writing). After a certain number of repetitions (a maximum of 3 repetitions), if the storage is invalid, the current storage is abandoned, and the updated data storage address B' is rewritten into the index address space to ensure that the correct storage address can be found when the power is turned on next time.

[0065] Furthermore, since other tasks of the processor are blocked after a power failure signal is detected, when the power failure is caused by an unstable power supply (i.e., a false power failure), other processing tasks of the processor need to be resumed when the power supply stabilizes. The present invention determines whether the current power failure is a false power failure (or false power failure) signal by starting a timer to count the power failures after detecting the power failure signal. If the device is still in normal working state after a period of time (5 seconds), the power failure is determined to be a false power failure, and the power failure data preservation flag can be cleared (i.e., the power failure preservation flag is set to invalid), and the normal operating state of the processor is restored, that is, other tasks of the software project are restored to normal operation.

[0066] In summary, during normal operation of the device, the present invention maintains real-time updates and maintenance of data stored in the non-volatile memory in the processor's SRAM, with the latest data written to the non-volatile memory only after a set timer expires. When the device loses power, the latest data is written to the non-volatile memory, and data is preserved using a combination of scheduled and power-off storage. The present invention also incorporates a storage space validity detection mechanism, requiring the validity of the storage space to be checked before and after data is stored, thereby ensuring effective data storage. Furthermore, the present invention includes a storage space balancing mechanism, replacing the current data storage space with a new one when invalid data storage space is detected. When a power-off signal is detected, all operations other than the data storage function are disabled. Furthermore, a false power-off detection mechanism is implemented, along with a power-off monitoring alarm circuit and an energy storage circuit. Thus, by combining a data storage method with a memory space balancing allocation and utilization method, the present invention can extend the service life of the storage device while ensuring reliable storage of important parameter information, thus possessing high practical value. Of course, the present invention is applicable to all storage devices with lifespan requirements, and is not limited to civil aviation equipment; it can also be applied to other airborne equipment or equipment on vehicles and ships.

[0067] The above description is merely one embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that the present invention is susceptible to various modifications and variations. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. A device for extending the life of a storage device suitable for civil aviation airborne equipment, characterized in that: include: Energy storage circuits, used to provide power to the device when external power is lost; A power-off monitoring and alarm circuit is used to monitor the device power status in real time and issue an interruption alarm signal when the external power supply is lost or when the energy in the energy storage circuit is about to be exhausted. The energy storage circuit includes a voltage stabilization circuit, a DC / DC conversion module, and an isolation circuit connected in sequence. The power-off monitoring and alarm circuit includes a power acquisition circuit and a processor. The power acquisition circuit is connected to both sides of the isolation circuit. The two voltage signals output by the power acquisition circuit are connected to the IO pins of the processor. These two voltage signals are the external power loss alarm signal and the device power-off alarm signal. After the processor detects the external power loss alarm signal output by the power acquisition circuit, it sets the power-off saving flag to be valid; after the processor detects the device power-off alarm signal output by the power acquisition circuit, it does not perform any operation until the power is cut off; A power-off interrupt processing module, configured to trigger power-off storage of data; the power-off storage is configured to set a power-off save flag to be valid in the power-off interrupt processing module when the power-off monitoring alarm circuit detects a loss of external power supply. When the power-off save flag is valid, only power-off data storage is performed; A timer interrupt processing module is configured to trigger the timed storage of data; the timed storage is configured to enable the timed storage flag after the timer data storage timer expires. When the timed storage flag is enabled, the storage of the device operating status parameters is initiated. Before the storage is performed, the module determines whether the power-off save flag is enabled. If the power-off save flag is disabled, the module performs the data storage operation in the non-volatile memory. A non-volatile memory space division module is used to initialize and update and maintain the data storage address and its index address; the storage space of the non-volatile memory is divided into an index address space, a data storage space, and a backup storage space, the index address space is used to store the address value of the data storage space; the data storage space is used to store real-time updated data; the backup storage space is used to serve as a new data storage space when the current data storage space fails, and updates the value in the index address space; The memory access space validity detection module is used to perform validity detection on the data storage space.

2. The device according to claim 1, characterized in that When the device is powered on, the signal of the external power supply passes through the voltage stabilizing circuit to obtain a stable power signal, and then passes through the DC / DC conversion module to obtain a secondary regulated power signal. The secondary regulated power signal charges the components with energy storage function in the isolation circuit; When the device loses power, the isolation circuit begins to discharge and provide power to other loads in the device.

3. The device according to claim 1, characterized in that When the power signal is lost or drops below the threshold voltage, the output voltage of the power acquisition circuit changes from a high level to a low level, and triggers the processor to generate an interrupt alarm signal, which includes the external power loss alarm signal and the device power-off alarm signal.

4. The device according to claim 1, characterized in that Also includes: The update and maintenance module of the data to be saved in SRAM is used to save the parameter status values ​​during the operation of the equipment in real time; The data storage module is used to start when it detects that the timing time has expired or the power-off saving flag is valid, extract the data stored in the SRAM and save it to the non-volatile memory, and judge the reliability of the data storage each time the data is stored.

5. A method for extending the life of a storage device applicable to civil aviation airborne equipment using the device according to any one of claims 1 to 4, comprising the following steps: (a) When the device is powered on, the energy storage circuit stores electricity, the power failure monitoring and alarm circuit monitors the power status of the device in real time, and the software timer counts the data in real time; (b) Determine whether the power-off save flag is valid. If the power-off save flag is invalid, update the storage information in SRAM in real time and process other tasks; (c) Determine whether the timer save flag is valid. If the timer save flag is valid, determine whether the power-off save flag is valid. If the power-off save flag is invalid, store the data in the non-volatile memory.

6. The method according to claim 5, characterized in that After the timing data saving time is up, the timer interrupt processing module sets the timing saving flag to be valid; When the power-off monitoring alarm circuit detects that the external power supply is lost, the power-off saving flag is set to be valid in the power-off interrupt processing module, and other tasks are shielded, and only the power-off data storage work is performed.

7. The method according to claim 5, characterized in that When the power-off saving flag is valid, determine whether the current power-off is a false power-off. If so, set the power-off saving flag to invalid and resume other tasks; Before storing data in the non-volatile memory, it is determined whether the current data storage space in the non-volatile memory is valid. If so, the data is stored. Otherwise, a new valid data storage space is found and the new data storage address is updated to the index address space.

8. The method according to claim 7, characterized in that When determining a false power outage, a timer is started to count the power outages after a power loss alarm signal is detected. If the device is still in normal working condition after a period of time, the power outage is determined to be a false power outage. When judging the validity of the data storage space, data is first written into the current data storage space, and then the data is read to determine whether the read data is consistent with the written data. If so, the current data storage space is determined to be valid; otherwise, it is determined to be invalid, and the available storage space in the non-volatile memory is searched again and the writing and reading of data are repeated. If the data storage space is determined to be invalid after a certain number of repetitions, the current storage is abandoned.

9. The method according to claim 5, characterized in that In said step (a), an initialization step is also included, including: storage space division and management, initialization configuration of timer parameters and acquisition of data storage address; The specific operations of storage space division and management are as follows: setting the memory index address A and the initial data storage address B. When setting, a certain address space is reserved before the initial data storage address B for storing configuration parameter information. The address space after the initial data storage address B is used as a backup storage address space. When the current data storage space is invalid, the backup storage address is searched in a forward-to-backward order. The specific operations of initializing the configuration of timer parameters are: starting the timer, setting the IO level interrupt trigger mode, and enabling all interrupts, including timer interrupts and IO interrupts; When obtaining the data storage address, read the content of the index address space, and determine whether the data is valid based on the parameter value and check value in the read content. If so, extract the value of the data storage address B, otherwise initialize the index address space with the initial value of the data storage address.

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