Integrated chip and method of forming the same

Abstract

Various embodiments of the present invention relate to an integrated chip. The integrated chip includes an interconnect structure located over a semiconductor substrate and including a conductive line. A passivation structure is located over the interconnect structure. An upper conductive structure is located over the passivation structure and includes a first conductive layer, a dielectric layer, and a second conductive layer. The first conductive layer is disposed between the dielectric layer and the passivation structure. The second conductive layer extends along a top surface of the dielectric layer and penetrates the first conductive layer and the passivation structure to the conductive line. Embodiments of the present application provide an integrated chip and a method of forming the same.

Description

Technical Field

[0001] The implementation of this application relates to integrated chips and methods for forming the same. Background Technology

[0002] Semiconductor chips are used in electronics and other devices, and are well-known for this. The widespread use of these chips today, along with consumer demand for more powerful and compact devices, requires chip manufacturers to continuously reduce the physical size of these chips and increase their functionality. This scaling down process typically provides benefits by increasing production efficiency and reducing associated costs. However, as part sizes continue to shrink, manufacturing processes continue to become more difficult to execute. Therefore, forming reliable semiconductor devices in increasingly smaller sizes remains a challenge. Summary of the Invention

[0003] In some embodiments, this application provides an integrated chip, comprising: an interconnect structure located above a semiconductor substrate and including conductive lines; a passivation structure located above the interconnect structure; and an upper conductive structure located above the passivation structure and including a first conductive layer, a dielectric layer, and a second conductive layer, wherein the first conductive layer is disposed between the dielectric layer and the passivation structure, and wherein the second conductive layer extends along the top surface of the dielectric layer and penetrates the first conductive layer and the passivation structure to the conductive lines.

[0004] In some embodiments, this application provides an integrated chip, comprising: a dielectric structure located above a semiconductor substrate; a conductive line disposed within the dielectric structure, wherein the top surface of the conductive line is aligned with the top surface of the dielectric structure; a passivation structure disposed above the dielectric structure and including opposing sidewalls defining a trench above the conductive line; and an upper conductive structure disposed within the trench and electrically coupled to the conductive line, wherein the upper conductive structure includes a first conductive layer, a dielectric layer, and a second conductive layer, wherein the first conductive layer and the dielectric layer are disposed along the top surface of the passivation structure, wherein the second conductive layer liner the trench and directly contacts the top surface of the conductive line, and wherein the top surface of the second conductive layer is located above the dielectric layer.

[0005] In some embodiments, this application provides a method for forming an integrated chip, the method comprising: depositing a passivation structure above a conductive line; depositing a first conductive layer above the passivation structure; depositing a dielectric layer above the first conductive layer; performing a patterning process on the passivation structure, the first conductive layer, and the dielectric layer to form an opening above the conductive line, wherein the patterning process forms a metal oxide along the top surface of the conductive line; performing a cleaning process on the dielectric layer and the conductive line to remove the metal oxide from the top surface along the conductive line; depositing a second conductive layer above the dielectric layer and the conductive line such that the second conductive layer liner the opening and contacts the conductive line; and etching the second conductive layer, the dielectric layer, and the first conductive layer to form an upper conductive structure above the conductive line.

[0006] Embodiments of this application provide an upper conductive structure with multi-layer stacked components to reduce manufacturing costs and improve performance. Attached Figure Description

[0007] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 Cross-sectional views of some embodiments of an integrated chip including an upper conductive structure having a multilayer stack covering and electrically coupled to an interconnect structure are shown.

[0009] Figures 2A to 2E Cross-sectional views of some embodiments of an integrated chip are shown, the integrated chip including a bonding structure with an upper conductive structure covering an interconnect structure.

[0010] Figure 3 Cross-sectional views of some embodiments of an integrated chip are shown, the integrated chip including a redistribution structure covering the interconnect structure and an upper conductive structure covering the redistribution structure.

[0011] Figures 4A to 4B Cross-sectional views of some embodiments of an integrated chip are shown, the integrated chip having a light-emitting structure vertically positioned above a corresponding upper conductive structure.

[0012] Figures 5 to 13 Cross-sectional views of some embodiments of a method for forming an integrated chip having an upper conductive structure covering an interconnect structure are shown.

[0013] Figures 14 to 16 Cross-sectional views of some embodiments of a method for forming an integrated chip having an upper conductive structure covering an interconnect structure are shown.

[0014] Figures 17 to 19 A cross-sectional view is shown of yet another embodiment of a method for forming an integrated chip having an upper conductive structure covering an interconnect structure.

[0015] Figure 20 Flowcharts illustrating some embodiments of a method for forming an integrated chip with an overlying conductive structure covering interconnect structures are shown. Detailed Implementation

[0016] The following disclosure provides numerous different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0018] Integrated chip technology continues to improve. These improvements typically involve shrinking geometry to achieve lower manufacturing costs, higher device integration density, higher speeds, and better performance. Due to device scaling, the negative effects of contamination along the sidewalls of the processing chamber (e.g., reduced etching rates, inconsistent etching processes, inability to accurately remove contaminants and / or byproducts from the substrate, etc.) are amplified.

[0019] For example, a workpiece comprising an interconnect structure located above a semiconductor substrate can be loaded into the processing chamber of a plasma etching system. A passivation structure covers the top conductive line of the interconnect structure (e.g., tantalum, aluminum, copper, etc.), and a first conductive layer (i.e., a metal hard mask layer) covers the passivation structure. The plasma processing system forms a first plasma within the processing chamber to selectively etch the first conductive layer and the passivation structure, thereby forming an opening that exposes the top surface of the top conductive line. During this process, the first plasma and / or oxygen atoms within the processing chamber react with the top conductive line, resulting in the formation of a metal oxide (e.g., tantalum oxide, aluminum oxide, copper oxide, etc.) along the top surface of the top conductive line. The metal oxide may have a high lattice energy (e.g., greater than about 5,000 kJ / mol) that is difficult to remove by current cleaning processes. Subsequently, a cleaning process (e.g., a plasma etching process) is performed on the workpiece within the processing chamber to remove the metal oxide. During the cleaning process, the plasma processing system forms a second plasma within the processing chamber that bombards the first conductive layer and the metal oxide, thereby promoting the removal of the metal oxide along the top conductive line. However, bombarding the first conductive layer with a second plasma causes conductive material from the first conductive layer to be redeposited onto the sidewalls and / or top of the processing chamber. The plasma processing system may include a radio frequency (RF) antenna disposed along and / or within the sidewalls of the processing chamber, wherein the RF antenna is configured to generate electromagnetic waves that react with a processing gas (e.g., argon) inside the processing chamber to form a second plasma. However, the conductive material redeposited along the sidewalls and / or top of the processing chamber may adversely affect subsequent processing steps as the workpiece (or subsequent workpiece) undergoes subsequent processing in the processing chamber. For example, the redeposited conductive material may cause metal-insulator-metal (MIM) capacitance / metal shielding effects, thereby blocking and / or weakening the intensity of the electromagnetic waves generated by the RF antenna within the processing chamber. Therefore, the plasma processing system may fail to properly separate the plasma from the processing chamber, resulting in a significant reduction in the etch rate of subsequent etching processes. A fabless automated cleaning (WAC) process can be performed to remove conductive material from the sidewalls and / or top of the processing chamber. The WAC process may increase the time and cost associated with manufacturing integrated chips. Furthermore, the WAC process may not be able to effectively remove the redeposited conductive material from the sidewalls and / or top of the processing chamber due to the lack of physical bombardment of the conductive material, thereby increasing the yield loss of the integrated chip.

[0020] Furthermore, after forming an opening within the first conductive layer and passivation structure, a second conductive layer is formed above the passivation structure and liner-enclosed by the opening. The second conductive layer directly covers the topmost conductive line and is etched to define the upper conductive structure. The upper conductive structure is configured to electrically couple other semiconductor devices and / or another integrated chip to the interconnect structure. However, the re-deposited conductive material from the first conductive layer may degrade the performance of the cleaning process (e.g., may reduce the rate of etching metal oxide during the cleaning process), leaving at least a portion of the metal oxide along the top surface of the topmost conductive line. This increases the resistance between the upper conductive structure and the topmost conductive line, thereby increasing the resistive-capacitive (RC) delay in the integrated chip.

[0021] In some embodiments, the present invention relates to an upper conductive structure (and related manufacturing methods) having a multilayer stack, the upper conductive structure reducing redeposition of conductive material along the sidewalls and / or over the processing chamber. A method for forming the upper conductive structure includes forming a first conductive layer (e.g., a metal hard mask layer) over a passivation structure disposed along a topmost conductive line within an interconnect structure. The interconnect structure covers a semiconductor substrate. A dielectric layer (e.g., a dielectric hard mask layer) is formed along the first conductive layer. The semiconductor substrate is loaded into a processing chamber of a plasma etching system. A patterning process is performed to selectively etch the dielectric layer, the first conductive layer, and the passivation structure to form an opening above the topmost conductive line. During the patterning process, a metal oxide is formed along the top surface of the topmost conductive layer. Subsequently, a cleaning process is performed on the topmost conductive layer, and the cleaning process includes forming plasma (e.g., argon-based plasma) inside the processing chamber. The plasma bombards the dielectric layer and the metal oxide, thereby removing the metal oxide along the topmost conductive layer and reducing the thickness of the dielectric layer. The dielectric layer is configured to prevent or suppress plasma from reaching and / or bombarding the first conductive layer. By means of the dielectric layer covering the first conductive layer, metal oxides can be accurately removed while suppressing the re-deposition of conductive material from the first conductive layer to the sidewalls and / or on top of the processing chamber. This reduces the number of multiple WAC processes performed in the processing chamber and suppresses adverse effects on subsequent processing steps performed within the processing chamber.

[0022] Furthermore, a second conductive layer is formed above the dielectric layer and an opening is added. Multiple etching processes (e.g., within a processing chamber) are performed on the first conductive layer, dielectric layer, and second conductive layer to form an upper conductive structure. The upper conductive structure comprises a multilayer stack including the first and second conductive layers and the dielectric layer. Accurate removal of metal oxides ensures good electrical connection (e.g., ohmic contact) between the upper conductive structure and the topmost conductive line, thereby reducing RC delay in the integrated chip. Furthermore, by preventing the conductive material from re-depositing from the first conductive layer, the etch rate of the multiple etch processes is not adversely affected. This reduces the time and cost associated with forming the integrated chip.

[0023] Figure 1 Cross-sectional views of some embodiments of an integrated chip 100 having an upper conductive structure 121 covering an interconnect structure 110 are shown.

[0024] The integrated chip 100 includes an interconnect structure 110 covering a semiconductor substrate 102. A semiconductor device 104 is disposed above and / or on the semiconductor substrate 102. For example, the semiconductor device 104 may be a transistor or other suitable device. In some embodiments, the semiconductor device 104 includes a source / drain region 103 disposed in the semiconductor substrate 102, a gate dielectric layer 105 disposed between the source / drain regions 103, a gate electrode 106 covering the gate dielectric layer 105, and sidewall spacers 108 disposed around the sidewalls of the gate electrode 106 and the gate dielectric layer 105.

[0025] Interconnect structure 110 includes a plurality of conductive vias 114, a plurality of conductive lines 116, and an interconnect dielectric structure 112. The plurality of conductive vias 114 and the plurality of conductive lines 116 are disposed within the interconnect dielectric structure 112 and are configured to electrically couple semiconductor device 104 to the upper conductive structure and / or another semiconductor device (not shown). In addition, the plurality of conductive lines 116 includes a topmost conductive line 116a located directly below the upper conductive structure 121.

[0026] A passivation structure 118 is disposed along the top surface of the interconnect structure 110. An upper conductive structure 121 extends from the top surface of the passivation structure 118 to the topmost conductive line 116a. In various embodiments, the upper conductive structure 121 includes a multilayer stack comprising a first conductive layer 120, a dielectric layer 122, and a second conductive layer 124. The first conductive layer 120 is disposed along the top surface of the passivation structure 118 and between the passivation structure 118 and the dielectric layer 122. Furthermore, the second conductive layer 124 includes a central conductive portion 126 and peripheral conductive portions 128 continuously extending outward from the central conductive portion 126. The central conductive portion 126 extends continuously from the dielectric layer 122 through the passivation structure 118 to the topmost conductive line 116a. The upper conductive structure 121 is electrically coupled to the topmost conductive line 116a through the central conductive portion 126. In various embodiments, the upper conductive structure 121 is configured to electrically couple the semiconductor device 104 to another integrated chip (not shown) and / or another semiconductor device (not shown).

[0027] In various embodiments, the first conductive layer 120 is configured as a metallic hard mask layer, and the dielectric layer 122 is configured as a dielectric hard mask layer. The first conductive layer 120 and the dielectric layer 122 are in direct contact with the outer wall of the central conductive portion 126 of the first conductive layer 120, respectively. In yet another embodiment, the first conductive layer 120 and / or the dielectric layer 122 are both annular in plan view, such that the first conductive layer 120 and / or the dielectric layer 122 continuously laterally surround the central conductive portion 126. In another embodiment, when viewed from above, the peripheral conductive portion 128 of the second conductive layer 124 is annular and continuously laterally surrounds the central conductive portion 126. In some embodiments, the first conductive layer 120 and the second conductive layer 124 comprise the same material (e.g., titanium nitride).

[0028] By providing a dielectric layer 122 between the first conductive layer 120 and the second conductive layer 124, the redeposition of conductive material from the first conductive layer 120 onto one or more surfaces of the processing chamber and / or processing tool is suppressed during the fabrication of the integrated chip 100. By reducing the redeposition of conductive material from the first conductive layer 120, the resistance between the upper conductive structure 121 and the topmost conductive line 116a is reduced. For example, suppressing the redeposition of conductive material facilitates the proper execution of cleaning processes (e.g., plasma etching processes) for removing metal oxides along the top surface of the topmost conductive line 116a prior to the formation of the second conductive layer 124, and reduces the need for WAC processes performed on the processing chamber and / or processing tool to remove the redeposited conductive material. This partially reduces resistive-capacitive (RC) delay in the integrated chip 100 and reduces yield losses, time, and costs associated with the fabrication of the integrated chip 100.

[0029] Figure 2A Cross-sectional views of some embodiments of an integrated chip 200a having an upper conductive structure 121 covering the topmost conductive line 116a are shown.

[0030] The topmost conductive line 116a is disposed within the interconnect dielectric structure 112 and covers the semiconductor substrate 102. In various embodiments, the topmost conductive line 116a and the interconnect dielectric structure 112 are interconnect structures covering the semiconductor substrate 102 (e.g., Figure 1 As part of 110). In some embodiments, the interconnect dielectric structure 112 may be, for example, silicon dioxide, a low-k dielectric material, another suitable dielectric material, or any combination of the foregoing materials. As used herein, a low-k dielectric material is a dielectric material with a dielectric constant less than 3.9. In yet another embodiment, the topmost conductive line 116a may be, for example, aluminum, titanium, tantalum, ruthenium, zirconium, molybdenum, another conductive material, or any combination of the foregoing materials.

[0031] A passivation structure 118 is disposed along the top surface of the interconnect dielectric structure 112 and includes opposing sidewalls defining a trench within the passivation structure 118. In various embodiments, the opposing sidewalls of the passivation structure 118 are inclined relative to the top surface of the top conductive line 116a. In various embodiments, the passivation structure 118 may be, for example, silicon dioxide, silicon glass, undoped silicon glass, another dielectric material, etc. An upper conductive structure 121 is disposed within the trench of the passivation structure 118 and directly covers the top conductive line 116a. The upper conductive structure 121 includes a first conductive layer 120, a dielectric layer 122, and a second conductive layer 124. The first conductive layer 120 is disposed along the top surface of the passivation structure 118, and the dielectric layer 122 is disposed along the top surface of the first conductive layer 120. In various embodiments, the second conductive layer 124 extends from the top surface of the dielectric layer 122 along the opposing sidewalls of the first conductive layer 120 and the passivation structure 118 to the top conductive line 116a.

[0032] In various embodiments, the first conductive layer 120 and the second conductive layer 124 may, for example, be titanium nitride, aluminum, copper, tantalum nitride, another suitable conductive material, or any combination of the foregoing materials. In yet another embodiment, the first conductive layer 120 and the second conductive layer 124 comprise the same conductive material (e.g., titanium nitride) and each have a columnar wafer. In yet another embodiment, the dielectric layer 122 may, for example, be silicon dioxide, silicon nitride, aluminum oxide, silicon oxynitride, another suitable dielectric material, or any combination of the foregoing materials.

[0033] In some embodiments, the first conductive layer 120 has a density between approximately to approximately The first thickness t1 is within the range of or another suitable value. In some embodiments, if the first thickness t1 is relatively low (e.g., less than approximately...), If the passivation structure 118 is damaged by an etching process (e.g., plasma etching) that forms trenches in the passivation structure 118, then the passivation structure 118 may be damaged. In yet another embodiment, if the first thickness t1 is relatively large (e.g., greater than approximately...), the passivation structure 118 may be damaged by an etching process (e.g., plasma etching). If the etching process used to form trenches in the passivation structure 118 fails, it may not expose a sufficient portion of the top conductive line 116a. This will increase the resistance between the upper conductive structure 121 and the top conductive line 116a.

[0034] In yet another embodiment, the dielectric layer 122 has a dielectric layer with a dielectric layer approximately... to approximately The second thickness t2 is within the range of or another suitable value. In yet another embodiment, by means of the second thickness t2 and / or the arrangement of the dielectric layer 122, the re-deposition of conductive material from the first conductive layer 120 onto one or more surfaces of the processing chamber and / or processing tool used to manufacture the integrated chip 200a is reduced. Furthermore, the dielectric layer 122 protecting the first conductive layer 120 facilitates a cleaning process on the surface of the top conductive line 116a before the deposition of the second conductive layer 124 to remove metal oxides formed along the surface of the top conductive line 116a during previous processing steps. This partially reduces the resistance between the upper conductive structure 121 and the top conductive line 116a. In various embodiments, if the second thickness t2 is relatively low (e.g., less than approximately If the first conductive layer 120 and / or passivation structure 118 are damaged by the etching process that forms trenches in the passivation structure 118, then the first conductive layer 120 and / or passivation structure 118 may be damaged. In yet another embodiment, if the second thickness t2 is relatively large (e.g., greater than approximately...), the first conductive layer 120 and / or passivation structure 118 may be damaged by the etching process that forms trenches in the passivation structure 118. If the etching process used to form trenches in the passivation structure 118 fails, it may not expose a sufficient portion of the top conductive line 116a. This increases the resistance between the upper conductive structure 121 and the top conductive line 116a. In some embodiments, the first thickness t1 of the first conductive layer 120 is less than the second thickness t2 of the dielectric layer 122.

[0035] In various embodiments, the third thickness t3 of the second conductive layer 124 is between to approximately Within the range, or another suitable value. In some embodiments, if the third thickness t3 is relatively low (e.g., less than approximately...), If the third thickness t3 is relatively large (e.g., greater than approximately...), then the resistance between the second conductive layer 124 and the topmost conductive line 116a increases. In yet another embodiment, if the third thickness t3 is relatively large (e.g., greater than approximately...), then the resistance between the second conductive layer 124 and the topmost conductive line 116a increases. If the etching process used to form the upper conductive structure 121 is not performed, the etching process may over-etch into the underlying layers and / or structures. In some embodiments, the third thickness t3 is greater than the first thickness t1 and greater than the second thickness t2. In yet another embodiment, the third thickness t3 is greater than the second thickness t2, and the second thickness t2 is greater than the first thickness t1.

[0036] In yet another embodiment, the upper conductive structure 121 is configured to engage with a bonding pad and is part of a bonding structure 208. In such an embodiment, the bonding structure 208 includes: an upper conductive structure 121 extending through a passivation structure 118 and contacting a topmost conductive line 116a; a bonding bump structure 204 disposed above the upper conductive structure 121; and solder balls 206 disposed along the bonding bump structure 204. In some embodiments, the bonding structure 208 is configured to electrically couple an integrated chip 200a to another semiconductor structure (not shown). In yet another embodiment, the second conductive layer 124 of the upper conductive structure 121 may be configured as an upper conductive via structure. Furthermore, an opening 202 is laterally disposed adjacent to the upper conductive structure 121, wherein the opening exposes the top surface of the passivation structure 118. Furthermore, the upper conductive structure 121 is laterally offset and / or electrically isolated from the peripheries of the first conductive layer 120, the dielectric layer 122, and the second conductive layer 124. Furthermore, in some embodiments, the outer walls of the first conductive layer 120, the outer walls of the dielectric layer 122, and the outer walls of the second conductive layer 124 of the upper conductive structure 121 are substantially straight and aligned with each other.

[0037] Figure 2B Showing the corresponding Figure 2A Cross-sectional views of some embodiments of integrated chip 200a and integrated chip 200b.

[0038] like Figure 2B As shown, the first conductive layer 120 of the conductive structure 121 has a first width w1 defined between opposing sidewalls 120sw1, 120sw2 of the first conductive layer 120. The dielectric layer 122 of the conductive structure 121 has a second width w2 defined between opposing sidewalls 122sw1, 122sw2 of the dielectric layer 122. The second conductive layer 124 of the conductive structure 121 has a third width w3 defined between opposing sidewalls 124sw1, 124sw2 of the second conductive layer 124. In various embodiments, the first width w1 is smaller than the second width w2 and larger than the third width w3. In some embodiments, the first width w1 is smaller than the second width w2 because the upper conductive structure 121 is formed by one or more wet etching processes that bevele and / or recess the opposing sidewalls 120sw1, 120sw2 of the first conductive layer 120 and / or the opposing sidewalls 124sw1, 124sw2 of the second conductive layer 124.

[0039] Figure 2C Showing the corresponding Figure 2A Cross-sectional views of some embodiments of integrated chip 200a and integrated chip 200c.

[0040] like Figure 2CAs shown, in some embodiments, the first width w1 of the first conductive layer 120 is equal to the second width w2 of the dielectric layer 122. In such embodiments, the opposite sidewalls 120sw1, 120sw2 of the first conductive layer 120 are aligned with the opposite sidewalls 122sw1, 122sw2 of the dielectric layer 122. In yet another embodiment, the third width w3 of the second conductive layer 124 is greater than the first width w1 and the second width w2.

[0041] Figure 2D Showing the corresponding Figure 2A Cross-sectional views of some embodiments of integrated chip 200a and integrated chip 200d.

[0042] like Figure 2D As shown, in some embodiments, the opposing sidewalls 120sw1, 120sw2 of the first conductive layer 120, the opposing sidewalls 122sw1, 122sw2 of the dielectric layer 122, and the opposing sidewalls 124sw1, 124sw2 of the second conductive layer 124 are each bent, recessed, and / or sunken in a direction toward the center of the upper conductive structure 121.

[0043] Figure 2E Showing the corresponding Figure 2A Cross-sectional views of some embodiments of integrated chip 200a and integrated chip 200e.

[0044] like Figure 2E As shown, in some embodiments, the opposing sidewalls 120sw1, 120sw2 of the first conductive layer 120 are straight and can be tilted relative to the top surface of the passivation structure 118. In yet another embodiment, the opposing sidewalls 122sw1, 122sw2 of the dielectric layer 122 and the opposing sidewalls 124sw1, 124sw2 of the second conductive layer 124 are bent and / or recessed in a direction toward the center of the upper conductive structure 121.

[0045] Figure 3 Cross-sectional views of some embodiments of an integrated chip 300 are shown, the integrated chip including a redistribution structure 304 covering an interconnect structure 110 and a plurality of upper conductive structures 121 covering the redistribution structure 304.

[0046] The integrated chip 300 includes an interconnect structure 110 covering a semiconductor substrate 102 and a redistribution structure 304 disposed above the interconnect structure 110. In some embodiments, the semiconductor substrate 102 may be, for example, or include a bulk substrate (e.g., a bulk silicon substrate), a silicon-on-insulator (SOI) substrate, etc. A plurality of semiconductor devices 104 are disposed along and / or within the front surface of the semiconductor substrate 102. In various embodiments, each of the plurality of semiconductor devices 104 may be configured as a transistor, another semiconductor device, etc. Furthermore, the interconnect structure 110 includes a plurality of conductive vias 114 and a plurality of conductive lines 116 disposed within the interconnect dielectric structure. In various embodiments, the interconnect dielectric structure includes a plurality of interconnect dielectric layers 302, for example, each interconnect dielectric layer may be or include an interlayer dielectric (ILD) layer, an intermetallic dielectric (IMD) layer, a dielectric protective layer, another suitable layer, etc. The conductive vias 114 and conductive lines 116 are configured to electrically couple the semiconductor devices 104 to the redistribution structure 304.

[0047] The redistribution structure 304 includes a lower passivation layer 306, a plurality of redistribution vias 308, and a plurality of redistribution lines 310. The lower passivation layer 306 is disposed between the passivation structure 118 and the interconnect structure 110. The redistribution vias 308 and redistribution lines 310 are disposed within the lower passivation layer 306 and configured to electrically couple the interconnect structure 110 to a plurality of bonding structures 208 covering the redistribution structure 304. In various embodiments, the plurality of redistribution vias 308 may be, for example, or include aluminum, copper, titanium nitride, tantalum nitride, tungsten, another conductive material, or any combination of the foregoing materials. In other embodiments, the plurality of redistribution lines 310 may be, for example, or include aluminum, titanium, tantalum, ruthenium, zirconium, molybdenum, another conductive material, or any combination of the foregoing materials.

[0048] In various embodiments, multiple bonding structures 208 cover the redistribution 310 and are configured to electrically couple the interconnect structure 110 to another integrated chip (not shown). Each of the multiple bonding structures 208 includes an upper conductive structure 121, a bonding bump structure 204 covering the upper conductive structure 121, and solder balls 206 covering the bonding bump structure 204. In various embodiments, the upper conductive structure 121 includes a multilayer stack comprising a first conductive layer 120, a dielectric layer 122, and a second conductive layer 124. In various embodiments, although... Figure 3 The upper conductive structure 121 is shown as Figure 2A The conductive structure 121, but it should be understood that, Figure 3 The upper conductive structure 121 can each be configured as follows: Figure 2B , Figure 2C , Figure 2D or Figure 2E The upper conductive structure 121.

[0049] Figure 4ACross-sectional views of some embodiments of integrated chip 400a are shown, which has a light-emitting structure 406 vertically positioned above a corresponding upper conductive structure 121.

[0050] In some embodiments, the integrated chip 400a includes a plurality of light-emitting devices 402 covering a passivation structure 118. Dielectric spacers 408 laterally surround the sidewalls of each light-emitting device 402. In various embodiments, the plurality of light-emitting devices 402 each includes a light-emitting structure 406 covering an electrode 404. Each light-emitting device 402 is laterally adjacent to and vertically positioned above a corresponding upper conductive structure 121. In some embodiments, each upper conductive structure 121 is configured to electrically couple the corresponding light-emitting device 402 to a plurality of semiconductor devices 104.

[0051] In yet another embodiment, each light-emitting structure 406 directly covers the corresponding redistribution line 310 within the redistribution structure 304. In some embodiments, each redistribution structure 304 may be configured as a reflector, and each light-emitting structure 406 may be configured as a light-emitting diode (LED), an organic light-emitting diode (OLED), or some other suitable light-emitting device. The redistribution line 310 is electrically coupled to a control circuit (e.g., a semiconductor device 104), and the control circuit is configured to selectively apply an electrical signal (e.g., a voltage) to the redistribution line 310, causing the light-emitting structure 406 to generate light (e.g., visible light). In some embodiments, the light-emitting structure 406 generates light due to electron-hole recombination between the electrode 404 and the light-emitting structure 406 caused by the electrical signal. Some of the light generated by the light-emitting structure 406 is reflected off the corresponding reflector (e.g., the corresponding redistribution line 310) through the corresponding electrode 404 toward the passivation structure 118, and reflected back toward the light-emitting structure 406. The light reflected back toward the light-emitting structure 406 can be combined with other light generated by the light-emitting structure 406, and light with a specific wavelength is emitted from each light-emitting device 402 due to constructive and / or deconstructive interference.

[0052] In various embodiments, the first conductive layer 120 is configured as a metal hard mask layer that prevents damage to the passivation structure 118 during the fabrication of the integrated chip 400a. For example, the first conductive layer 120 prevents plasma from one or more etching processes from damaging the lattice of the passivation structure 118, and / or prevents plasma injection within the passivation structure 118 that could interfere with light reflection between the multiple light-emitting devices 402 and the underlying reflector (e.g., redistribution 310). This partially enhances the performance of the light-emitting structure 406. In yet another embodiment, the light-emitting structure 406 may be formed and / or disposed within the passivation structure 118. Figures 2A to 2E Within the opening 202. In such embodiments, the engagement bump structure may be omitted (e.g., Figure 2A 204) and solder balls (e.g., Figure 2A206), and the topmost conductive line (e.g., Figure 2A 116a) can be configured as a reflector.

[0053] Figure 4B Showing the corresponding Figure 4A A cross-sectional view 400b of some embodiments shows that each light-emitting device 402 directly covers the corresponding upper conductive structure 121.

[0054] like Figure 4B As shown, the electrode 404 of each light-emitting device 402 is in direct contact with the corresponding upper conductive structure 121. In various embodiments, the electrode 404 is in direct contact with the inner and outer sidewalls of the second conductive layer 124 of the upper conductive structure 121, the outer sidewall of the dielectric layer 122 of the upper conductive structure 121, and the outer sidewall of the first conductive layer 120 of the upper conductive structure 121. In yet another embodiment, the dielectric spacer 408 is configured as a dielectric grid structure laterally disposed between each light-emitting device 402. In another embodiment, the light-emitting structure 406 may be directly formed on... Figures 2A to 2E Above the conductive structure 121. In such embodiments, the joining bump structure may be omitted (e.g., Figure 2A 204) and solder balls (e.g., Figure 2A 206), and the topmost conductive line (e.g., Figure 2A 116a) can be configured as a reflector.

[0055] In various embodiments, although Figure 4A and Figure 4B The upper conductive structure 121 is shown as Figure 2A The conductive structure 121, but it should be understood that, Figure 4A and Figure 4B The upper conductive structure 121 can each be configured as follows: Figure 2B , Figure 2C , Figure 2D or Figure 2E The upper conductive structure 121.

[0056] Figures 5 to 13 Cross-sectional views 500 to 1300 illustrate some embodiments of a method for forming an integrated chip according to aspects of the present invention, the integrated chip having an upper conductive structure covering an interconnect structure. Although Figures 5 to 13 The cross-sectional views 500 to 1300 shown are described using a reference method, but it should be understood that... Figures 5 to 13 The structure shown is not limited to this method, but can be separated from it independently. Furthermore, although Figures 5 to 13The actions are described as a series of actions, but it should be understood that these actions are not limiting, as the order of the actions may be changed in other embodiments, and the disclosed methods are also applicable to other structures. In other embodiments, some of the actions shown and / or described may be omitted in whole or in part.

[0057] like Figure 5 As shown in cross-sectional view 500, an interconnect dielectric structure 112 is formed above the semiconductor substrate 102, and a topmost conductive line 116a is formed within the interconnect dielectric structure 112. In various embodiments, the topmost conductive line 116a may be an interconnect structure (e.g., as shown in cross-sectional view 500). Figure 1 It may be part of the topmost conductive layer shown and / or described, or it may be a redistributed structure (e.g., configured as shown) Figure 3 or Figures 4A to 4B (The redistribution shown and / or described). Furthermore, a passivation structure 118 is formed above the topmost conductive line 116a, a first conductive layer 120 is formed above the passivation structure 118, and a dielectric layer 122 is formed above the first conductive layer 120. In various embodiments, the passivation structure 118 and the dielectric layer 122 can be formed by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermal oxidation, another suitable deposition or growth process, or any combination thereof. Furthermore, the first conductive layer 120 can be formed by, for example, CVD, PVD, sputtering, electroplating, electroless plating, other suitable growth or deposition processes, or any combination thereof.

[0058] In some embodiments, the topmost conductive line 116a may be or include a first conductive material, such as, for example, aluminum, titanium, tantalum, ruthenium, zirconium, molybdenum, another conductive material, or any combination of the foregoing materials. The passivation structure 118 may be, for example, silicon dioxide, silicon glass, undoped silicon glass, another dielectric material, or any combination of the foregoing materials. In another embodiment, the first conductive layer 120 may be or include a second conductive material, such as, for example, titanium nitride, aluminum, copper, tantalum nitride, another suitable conductive material, or any combination of the foregoing materials. The first conductive layer 120 is formed with a dielectric material... to approximately The first thickness t1 is within the range of or another suitable value. In various embodiments, the first conductive material of the topmost conductive line 116a is different from the second conductive material of the first conductive layer 120. Since the first conductive layer 120 includes a first conductive material having a first thickness t1, the first conductive layer 120 can be used during subsequent processing steps (e.g., in...). Figure 6 Patterning process and / or Figure 7During the cleaning process, the passivated structure 118 is protected. Furthermore, during subsequent processing steps, the first conductive layer 120 may be configured to have a hard mask layer (e.g., a metal hard mask layer). The dielectric layer 122 is formed with a dielectric layer between... to approximately The second thickness t2 is within the range of or another suitable value. The dielectric layer 122 may be, for example, or include silicon dioxide, silicon nitride, aluminum oxide, silicon oxynitride, another suitable dielectric material, or any combination of the foregoing materials. The dielectric layer 122 may be referred to as a dielectric mask layer.

[0059] like Figure 6 As shown in cross-sectional view 600, a photoresist mask 602 is formed above the dielectric layer 122. Furthermore, a first patterning process is performed on the dielectric layer 122, the first conductive layer 120, and the passivation structure 118 based on the photoresist mask 602 to form an opening 604 above the top conductive line 116a. In various embodiments, the first patterning process may stop on and / or expose the top surface of the top conductive line 116a. In yet another embodiment, the first patterning process may form a metal oxide 606 along the top surface of the top conductive line 116a. Additionally, the first patterning process may form trenches within the passivation structure 118 defined by opposing sidewalls of the passivation structure 118.

[0060] In some embodiments, the first patterning process is performed by anisotropic and / or dry etching and may be performed in a processing chamber 608. In some embodiments, the first patterning process includes: loading a semiconductor substrate 102 into the processing chamber 608, wherein a radio frequency (RF) power generator 610 is coupled to an RF antenna 612, which may be disposed along and / or within a sidewall of the processing chamber 608 (wherein the semiconductor substrate 102 is laterally spaced between the sidewalls of the processing chamber 608); allowing a first process gas to flow into the processing chamber 608; applying an RF signal (e.g., having a potential) to the RF antenna 612 via the RF power generator 610 to form and / or generate a first plasma from the first process gas within the processing chamber 608; and bombarding a dielectric layer 122, a first conductive layer 120, and a passivation structure 118 with the first plasma to define an opening 604. In various embodiments, a first plasma and / or oxygen atoms within the processing chamber 608 react with the top conductive line 116a to form a metal oxide 606 along the top surface of the top conductive line 116a. In various embodiments, the metal oxide 606 may be, for example, an oxide of aluminum oxide, titanium oxide, tantalum oxide, ruthenium oxide, zirconium oxide, molybdenum oxide, or the first conductive material of the top conductive line 116a. In various embodiments, the first processing gas may be, for example, or include argon, helium, hydrogen, some other suitable gas, or any combination of the foregoing. In various embodiments, the metal oxide 606 has a relatively high lattice energy (e.g., greater than about 5,000 kJ / mol), which may make it difficult to react with a reducing agent (e.g., hydrogen) during a chemical reduction process (i.e., the relatively high lattice energy may inhibit the removal of the metal oxide 606 from a dry etching process that exposes the metal oxide 606 to hydrogen-based plasma).

[0061] like Figure 7 As shown in the cross-sectional view 700, for Figure 6 The structure is subjected to a cleaning process (e.g., plasma etching). In some embodiments, the cleaning process reduces the second thickness t2 of the dielectric layer 122 and / or removes metal oxides along the top surface of the topmost conductive line 116a. Figure 6 (606).

[0062] In some embodiments, the cleaning process is performed by anisotropic and / or dry etching and can be carried out in the processing chamber 608. In some embodiments, the cleaning process includes: loading a semiconductor substrate 102 into the processing chamber 608; allowing a second processing gas to flow into the processing chamber 608; applying an RF signal (e.g., having a potential) to an RF antenna 612 via an RF power generator 610 to form and / or generate a second plasma from the second processing gas within the processing chamber 608; and bombarding the dielectric layer 122 and the metal oxide with the second plasma. Figure 6 606) to remove metal oxides ( Figure 6(606). In various embodiments, the second processing gas may be, for example, or include argon, helium, some other suitable gas, or any combination of the foregoing. Furthermore, the cleaning process is carried out at a sufficiently high power (e.g., in the range of 250 watts to about 1250 watts) to overcome metal oxides ( Figure 6 The high lattice energy of 606 ensures the removal of metal oxides ( Figure 6 (606). Due to the thickness and layout of the dielectric layer 122, the second plasma is suppressed from reaching and / or bombarding the first conductive layer 120, thereby suppressing or preventing the redeposition of conductive material from the first conductive layer 120 onto one or more surfaces of the processing chamber 608. Furthermore, by suppressing the redeposition of conductive material from the first conductive layer 120 during the cleaning process, sufficient electromagnetic waves can be generated by the RF antenna 612 to react with the process gas in the processing chamber 608 to form or generate plasma without hindering the process. Therefore, the etching rate of the cleaning process can be increased to facilitate the removal of most and / or all metal oxides along the top surface of the top conductive line 116a. Figure 6 (606). Furthermore, multiple WAC processes performed in processing chamber 608 are suppressed, and adverse effects on subsequent processing steps performed within processing chamber 608 are suppressed. In another embodiment, the cleaning process includes an inductively coupled plasma (ICP) reactive ion etching (RIE) process, comprising allowing a second processing gas to flow into processing chamber 608.

[0063] like Figure 8 As shown in cross-sectional view 800, a second conductive layer 124 is formed above the dielectric layer 122 and the top conductive line 116a. The second conductive layer 124 extends along the top surface of the dielectric layer 122 and is lined with an opening 604. In various embodiments, the second conductive layer 124 can be formed in the deposition chamber 802 by, for example, CVD, PVD, sputtering, electroplating, electroless plating, other suitable growth or deposition processes, or any combination thereof. Furthermore, the second conductive layer 124 may be or include a second conductive material (e.g., titanium nitride, aluminum copper, tantalum nitride, another suitable conductive material, or any combination thereof). In some embodiments, the second conductive layer 124 is formed with a layer between to approximately The thickness t3 is within the range of another suitable value. Due to the metal oxide ( Figure 6 606) was Figure 7 The cleaning process removes the second conductive layer 124, allowing it to form a good electrical contact (e.g., an ohmic contact) with the topmost conductive line 116a. This reduces RC delay and device yield loss to some extent.

[0064] like Figure 9As shown in the cross-sectional view 900, the photoresist mask layer 904 is formed above the second conductive layer 124 and fills the opening ( Figure 8 (604). Subsequently, a first etching process is performed on the second conductive layer 124 to remove the unmasked portion of the second conductive layer 124. In various embodiments, the first etching process defines a conductive via in the second conductive layer 124 that directly covers the topmost conductive line 116a. In another embodiment, the first etching process is performed within a first etching chamber 902 and includes performing a first wet etching that exposes the second conductive layer 124 to one or more first wet etchants (e.g., hydrogen peroxide). The photoresist mask layer 904 may be, for example, a polymer or another suitable material.

[0065] like Figure 10 As shown in cross-sectional view 1000, a second etching process is performed on dielectric layer 122 to remove unmasked portions of dielectric layer 122. In various embodiments, the second etching process is performed within a second etching chamber 1002 and includes performing a second wet etching that exposes dielectric layer 122 to one or more second wet etchants (e.g., hydrofluoric acid, dilute hydrofluoric acid, etc.).

[0066] like Figure 11 As shown in cross-sectional view 1100, a third etching process is performed on the first conductive layer 120 to define the upper conductive structure 121 and an opening 202 laterally adjacent to the upper conductive structure 121, which exposes the upper surface of the passivation structure 118. In some embodiments, the third etching process removes unmasked portions of the first conductive layer 120. In another embodiment, the third etching process is performed within a third etching chamber 1102 and includes performing a third etching that exposes the first conductive layer 120 to one or more first wet etchants (e.g., hydrogen peroxide). The upper conductive structure 121 includes the first conductive layer 120, a dielectric layer 122, and a second conductive layer 124. In yet another embodiment, the process for forming the upper conductive structure 121 includes... Figures 6 to 11 The process steps shown and / or described are shown in the document.

[0067] implement Figures 9 to 11The first, second, and third etching processes cause the first conductive layer 120 of the upper conductive structure 121 to have a first width w1 defined between opposite sidewalls 120sw1 and 120sw2 of the first conductive layer 120; the dielectric layer 122 of the upper conductive structure 121 to have a second width w2 defined between opposite sidewalls 122sw1 and 122sw2 of the dielectric layer 122; and the second conductive layer 124 of the upper conductive structure 121 to have a third width w3 defined between opposite sidewalls 124sw1 and 124sw2 of the second conductive layer 124. In various embodiments, the first width w1 is smaller than the second width w2, the second width w2 is larger than the third width w3, and the third width w3 is larger than the first width w1 (e.g., as shown in the figure). Figure 2B (shown and / or described in the text). In various embodiments, this may occur because... Figure 9 The first etching process gives the second conductive layer 124 of the upper conductive structure 121 an initial width, and then the second etching process and / or the third etching process further reduce the width of the second conductive layer 124. In yet another embodiment, by means of Figures 9 to 11 Each includes a first etching process, a second etching process, and a third etching process using wet etching. The opposing sidewalls of the first conductive layer 120, the dielectric layer 122, and the second conductive layer 124, and the sidewalls of the upper conductive structure 121, can be beveled and / or recessed, such that the opposing sidewalls are each curved, recessed, and / or concave, as... Figure 2D Show and / or describe.

[0068] In various embodiments, processing chamber 608, deposition processing chamber 802, first etching processing chamber 902, second etching processing chamber 1002, and third etching processing chamber 1102 are identical. Thus, the semiconductor substrate 102 is subjected to... Figure 6 The beginning of the first patterning process Figure 11 The third etching process concludes in the same processing chamber. Therefore, it is performed in situ. Figures 6 to 11 The processing steps. For example, this can be used to prevent moisture from entering the same processing chamber and / or to prevent oxidation of the conductive layer and / or structure above the semiconductor substrate 102. Furthermore, by performing in-situ... Figures 6 to 11 The processing steps can reduce the time and / or cost associated with moving the semiconductor substrate 102 between different processing chambers.

[0069] like Figure 12 As shown in the cross-sectional view 1200, a removal process is performed to remove the photoresist mask layer from above the second conductive layer 124. Figure 11 (904). In various embodiments, the removal process includes performing a wet etching process, a dry etching process, or other suitable removal process.

[0070] like Figure 13As shown in cross-sectional view 1300, a bonding bump structure 204 is formed above the second conductive layer 124 of the upper conductive structure 121. Furthermore, solder balls 206 are formed above the bonding bump structure 204.

[0071] Figures 14 to 16 Showing alternatives Figures 9 to 11 Cross-sectional views 1400 to 1600 show some embodiments of the actions performed at the location, making it possible to... Figures 5 to 13 The method can optionally be from Figures 5 to 8 Progressing to Figures 14 to 16 , and then from Figures 16 to 12 to Figure 13 (i.e., skip) Figures 9 to 11 ).

[0072] like Figure 14 As shown in cross-sectional view 1400, a photoresist mask layer 904 is formed over the second conductive layer 124. Subsequently, a first etching process is performed on the second conductive layer 124 to remove the unmasked portion of the second conductive layer 124. In another embodiment, the first etching process is performed within a first etching chamber 902 and includes performing a first dry etching process (e.g., a first ICP RIE process) that exposes the second conductive layer 124 to one or more first dry etchants (e.g., chlorine-based etchants).

[0073] like Figure 15 As shown in cross-sectional view 1500, a second etching process is performed on dielectric layer 122 to remove unmasked portions of dielectric layer 122. In various embodiments, the second etching process is performed within a second etching chamber 1002 and includes performing a second dry etching process (e.g., a second ICP RIE process) that exposes dielectric layer 122 to one or more second dry etchants (e.g., fluorine-based etchants).

[0074] like Figure 16 As shown in cross-sectional view 1600, a third etching process is performed on the first conductive layer 120 to define the upper conductive structure 121 and an opening 202 laterally adjacent to the upper conductive structure 121, which exposes the upper surface of the passivation structure 118. In some embodiments, the third etching process removes unmasked portions of the first conductive layer 120. In another embodiment, the third etching process is performed within a third etching chamber 1102 and includes performing a third dry etching process (e.g., a third ICP RIE process) to expose the first conductive layer 120 to one or more first dry etchants (e.g., chlorine-based etchants). In yet another embodiment, the process for forming the upper conductive structure 121 includes... Figures 6 to 8 and Figures 14 to 16 The process steps shown and / or described are shown in the document.

[0075] In some embodiments, execute Figures 14 to 16The first, second, and third etching processes ensure that the first width w1 of the first conductive layer 120, the second width w2 of the dielectric layer 122, and the third width w3 of the second conductive layer 124 are equal to each other. In yet another embodiment, the etching process is performed... Figures 14 to 16 The first, second, and third etching processes ensure that the opposing sidewalls 120sw1 and 120sw2 of the first conductive layer 120, the opposing sidewalls 122sw1 and 122sw2 of the dielectric layer 122, and the opposing sidewall 124sw1 are substantially straight (e.g., vertical relative to the top surface of the passivation structure 118) and aligned with each other, such as... Figure 2A The following is shown and / or described.

[0076] Figures 17 to 19 Showing alternatives Figures 9 to 11 Cross-sectional views 1700 to 1900 show some embodiments of the actions performed at the location, making it possible to... Figures 5 to 13 The method can optionally be from Figures 5 to 8 Progressing to Figures 17 to 19 , and then from Figures 19 to 12 to Figure 13 (i.e., skip) Figures 9 to 11 ).

[0077] like Figure 17 As shown in cross-sectional view 1700, a photoresist mask layer 904 is formed over the second conductive layer 124. Subsequently, a first etching process is performed on the second conductive layer 124 to remove the unmasked portion of the second conductive layer 124. In some embodiments, the first etching process is performed within a first etching chamber 902 and includes performing a first wet etching that exposes the second conductive layer 124 to one or more first wet etchants (e.g., hydrogen peroxide).

[0078] like Figure 18 As shown in cross-sectional view 1800, a second etching process is performed on dielectric layer 122 to remove unmasked portions of dielectric layer 122. In various embodiments, the second etching process is performed within a second etching chamber 1002 and includes performing a second wet etching that exposes dielectric layer 122 to one or more second wet etchants (e.g., hydrofluoric acid, dilute hydrofluoric acid, etc.).

[0079] like Figure 19As shown in cross-sectional view 1900, a third etching process is performed on the first conductive layer 120 to define the upper conductive structure 121 and an opening 202 laterally adjacent to the upper conductive structure 121, which exposes the upper surface of the passivation structure 118. In some embodiments, the third etching process removes unmasked portions of the first conductive layer 120. In another embodiment, the third etching process is performed within a third etching chamber 1102 and includes performing a first dry etching process (e.g., ICP RIE process) to expose the first conductive layer 120 to one or more first dry etchants (e.g., chlorine-based etchants). In yet another embodiment, the process for forming the upper conductive structure 121 includes... Figures 6 to 8 and Figures 17 to 19 The process steps shown and / or described in the figure.

[0080] In some embodiments, execute Figures 17 to 19 The first, second, and third etching processes make the first width w1 of the first conductive layer 120 equal to the second width w2 of the dielectric layer 122, and the third width w3 of the second conductive layer 124 is greater than the first width w1 and the second width w2 (e.g., as shown in the image). Figure 2C (shown and / or described in the text). In yet another embodiment, by means of Figure 17 and Figure 18 Each includes a first etching process and a second etching process using wet etching technology. The opposing sidewalls 124sw1, 124sw2 of the second conductive layer 124 and the opposing sidewalls 122sw1, 122sw2 of the dielectric layer 122 can be beveled and / or recessed, such that the opposing sidewalls are each curved, recessed, and / or concave, as shown below. Figure 2E The following are shown and / or described. In some embodiments, by means of a dry etching process... Figure 19 In the third etching process, the opposing sidewalls 120sw1 and 120sw2 of the first conductive layer 120 can be tilted relative to the top surface of the passivation structure 118, such as... Figure 2E The following is shown and / or described.

[0081] Figure 20 A method 2000 for forming an integrated chip with an overlying conductive structure having an overlying interconnect structure according to the present invention is illustrated. Although method 2000 is shown and / or described as a series of actions or events, it should be understood that the method is not limited to the shown sequence or actions. Therefore, in some embodiments, actions may be performed in a different order than shown, and / or actions may be performed simultaneously. Furthermore, in some embodiments, the shown actions or events may be subdivided into multiple actions or events that may be performed at a separate time or simultaneously with other actions or sub-actions. In some embodiments, some shown actions or events may be omitted, and other actions or events not shown may be included.

[0082] At action 2002, an interconnect structure including the topmost conductive line is formed above the semiconductor substrate. Figure 5 Cross-sectional view 500 is shown, corresponding to some embodiments of action 2002.

[0083] At action 2004, a passivation structure is formed above the topmost conductive line. Figure 5 Cross-sectional view 500 is shown, corresponding to some embodiments of action 2004.

[0084] In action 2006, a first conductive layer is formed over the passivation structure. Figure 5 Cross-sectional view 500 is shown, corresponding to some embodiments of action 2006.

[0085] At action 2008, a dielectric layer is formed above the first conductive layer. Figure 5 Cross-sectional view 500 is shown, corresponding to some embodiments of action 2008.

[0086] At step 2010, a patterning process is performed on the dielectric layer, the first conductive layer, and the passivation structure to form an opening above the top conductive line. The patterning process forms a metal oxide along the top conductive line. Figure 6 A cross-sectional view 600 is shown, corresponding to some embodiments of action 2010.

[0087] At action 2012, a cleaning process is performed on the dielectric layer and the top conductive line to remove metal oxides. Figure 7 Cross-sectional view 700 is shown, corresponding to some embodiments of action 2012.

[0088] At action 2014, a second conductive layer is formed above the dielectric layer and the top conductive line, wherein the second conductive layer has an opening. Figure 8 Cross-sectional view 800 is shown, corresponding to some embodiments of action 2014.

[0089] At step 2016, a first etching process is performed on the second conductive layer, a second etching process is performed on the dielectric layer, and a third etching process is performed on the first conductive layer, thereby forming an upper conductive structure on the top conductive line. Figures 9 to 11 Cross-sectional views 900 to 1100 are shown corresponding to some embodiments of action 2016. Figures 14 to 16 Cross-sectional views 1400 to 1600 are shown corresponding to some embodiments of action 2016. Figures 17 to 19 Cross-sectional views 1700 to 1900 are shown corresponding to another embodiment of action 2016.

[0090] Therefore, in some embodiments, the present invention relates to an upper conductive structure disposed within a passivation structure and covering the topmost conductive line. The upper conductive structure includes a multilayer stack comprising a first conductive layer disposed along the passivation structure, a dielectric layer covering the first conductive layer, and a second conductive layer covering the dielectric layer and extending through the passivation structure to contact the topmost conductive line.

[0091] In some embodiments, this application provides an integrated chip, comprising: an interconnect structure located above a semiconductor substrate and including conductive lines; a passivation structure located above the interconnect structure; and an upper conductive structure located above the passivation structure and including a first conductive layer, a dielectric layer, and a second conductive layer, wherein the first conductive layer is disposed between the dielectric layer and the passivation structure, and wherein the second conductive layer extends along the top surface of the dielectric layer and penetrates the first conductive layer and the passivation structure to the conductive lines. In an embodiment, the first conductive layer and the second conductive layer include a first conductive material. In an embodiment, the conductive lines include a second conductive material different from the first conductive material. In an embodiment, a first thickness of the first conductive layer is less than a second thickness of the second conductive layer. In an embodiment, the second conductive layer includes a central conductive portion and a peripheral conductive portion extending outward from the central conductive portion, wherein the peripheral conductive portion continuously and laterally surrounds the central conductive portion and directly contacts the top surface of the dielectric layer. In an embodiment, the central conductive portion directly contacts the top surface of the conductive lines, and wherein the central conductive portion contacts the inner sidewall of the dielectric layer, the inner sidewall of the first conductive layer, and the inner sidewall of the passivation structure. In one embodiment, the conductive lines of the interconnect structure are disposed in the topmost conductive layer of the interconnect structure. In another embodiment, the outermost wall of the first conductive layer, the outermost wall of the dielectric layer, and the outermost wall of the first conductive layer are all straight and aligned with each other. In yet another embodiment, the outermost walls of the second conductive layer and the outermost walls of the dielectric layer are bent inward toward the center of the upper conductive structure.

[0092] In some embodiments, this application provides an integrated chip, comprising: a dielectric structure located above a semiconductor substrate; a conductive line disposed within the dielectric structure, wherein the top surface of the conductive line is aligned with the top surface of the dielectric structure; a passivation structure disposed above the dielectric structure and including opposing sidewalls defining a trench above the conductive line; and an upper conductive structure disposed within the trench and electrically coupled to the conductive line, wherein the upper conductive structure includes a first conductive layer, a dielectric layer, and a second conductive layer, wherein the first conductive layer and the dielectric layer are disposed along the top surface of the passivation structure, wherein the second conductive layer liner the trench and directly contacts the top surface of the conductive line, and wherein the top surface of the second conductive layer is located above the dielectric layer. In an embodiment, both the first conductive layer and the dielectric layer laterally surround the center portion of the second conductive layer. In an embodiment, the integrated chip further comprises: a bonding bump structure located above the second conductive layer and filling the trench, wherein the bottom surface of the bonding bump structure is disposed below the bottom surface of the first conductive layer; and solder balls disposed along the top surface of the bonding bump structure. In one embodiment, the integrated chip further includes a light-emitting device located above the passivation structure, wherein the light-emitting device is laterally adjacent to the upper conductive structure, and wherein the light-emitting device includes a light-emitting structure above an electrode. In one embodiment, along the inner sidewall of the second conductive layer, the electrode extends continuously from above the second conductive layer to a point below the top surface of the passivation structure, wherein the light-emitting structure is located directly above the upper conductive structure. In one embodiment, the electrode is in direct contact with the outer sidewall of the first conductive layer, the outer sidewall of the dielectric layer, and the outer sidewall of the second conductive layer.

[0093] In some embodiments, this application provides a method for forming an integrated chip, the method comprising: depositing a passivation structure above a conductive line; depositing a first conductive layer above the passivation structure; depositing a dielectric layer above the first conductive layer; performing a patterning process on the passivation structure, the first conductive layer, and the dielectric layer to form an opening above the conductive line, wherein the patterning process forms a metal oxide along the top surface of the conductive line; performing a cleaning process on the dielectric layer and the conductive line to remove the metal oxide from the top surface along the conductive line; depositing a second conductive layer above the dielectric layer and the conductive line such that the second conductive layer liner the opening and contacts the conductive line; and etching the second conductive layer, the dielectric layer, and the first conductive layer to form an upper conductive structure above the conductive line. In an embodiment, etching the second conductive layer, the dielectric layer, and the first conductive layer comprises: forming an upper mask layer above the second conductive layer such that the upper mask layer fills the remaining portion of the opening; performing a first etching process on the second conductive layer; performing a second etching process on the dielectric layer; and performing a third etching process on the first conductive layer. In one embodiment, the first etching process includes exposing the second conductive layer to a first wet etchant, the third etching process includes exposing the first conductive layer to the first wet etchant, and wherein the second etching process includes exposing the dielectric layer to a second wet etchant different from the first wet etchant. In another embodiment, the cleaning process is an inductively coupled plasma (ICP) reactive ion etching (RIE) process that exposes the metal oxide to argon-based plasma. In yet another embodiment, the metal oxide comprises a material with a lattice energy greater than about 5,000 kJ / mol.

[0094] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. An integrated chip, comprising: An interconnect structure located above a semiconductor substrate and including conductive lines; A passivation structure is located above the interconnect structure; as well as An upper conductive structure, located above the passivation structure, includes a first conductive layer, a dielectric layer, and a second conductive layer. The first conductive layer is disposed between the dielectric layer and the passivation structure. The second conductive layer extends along the top surface of the dielectric layer and penetrates the first conductive layer and the passivation structure to the conductive line. The second conductive layer includes a central conductive portion that extends continuously through the passivation structure to the conductive line. The central conductive portion is in contact with the inner sidewall of the dielectric layer, the inner sidewall of the first conductive layer, and the inner sidewall of the passivation structure. Furthermore, the outer sidewall of the first conductive layer is inclined inward toward the central conductive portion.

2. The integrated chip according to claim 1, wherein, The first conductive layer and the second conductive layer comprise a first conductive material.

3. The integrated chip according to claim 2, wherein, The conductive wire includes a second conductive material that is different from the first conductive material.

4. The integrated chip according to claim 1, wherein, The first thickness of the first conductive layer is less than the second thickness of the second conductive layer.

5. The integrated chip according to claim 1, wherein, The second conductive layer includes a peripheral conductive portion extending outward from the central conductive portion, wherein the peripheral conductive portion continuously and laterally surrounds the central conductive portion and is in direct contact with the top surface of the dielectric layer.

6. The integrated chip according to claim 5, wherein, The central conductive part is in direct contact with the top surface of the conductive wire.

7. The integrated chip according to claim 1, wherein, The conductive lines of the interconnect structure are disposed in the topmost conductive layer of the interconnect structure.

8. The integrated chip according to claim 1, wherein, The outer walls of the dielectric layer and the outer walls of the second conductive layer are straight and aligned with each other.

9. The integrated chip according to claim 1, wherein, The outer wall of the second conductive layer and the outer wall of the dielectric layer are bent inward toward the center of the upper conductive structure.

10. An integrated chip, comprising: Dielectric structure, located above the semiconductor substrate; A conductive wire is disposed within the dielectric structure, wherein the top surface of the conductive wire is aligned with the top surface of the dielectric structure; A passivation structure, disposed above the dielectric structure and including opposing sidewalls defining a trench above the conductive line; and An upper conductive structure is disposed within the trench and electrically coupled to the conductive wire. The upper conductive structure includes a first conductive layer, a dielectric layer, and a second conductive layer. The first conductive layer and the dielectric layer are disposed along the top surface of the passivation structure. The second conductive layer lining the trench and directly contacts the top surface of the conductive wire. The top surface of the second conductive layer is located above the dielectric layer. The second conductive layer includes a portion that extends continuously through the passivation structure to the center of the conductive line. The center portion is in contact with the inner sidewall of the dielectric layer, the inner sidewall of the first conductive layer, and the inner sidewall of the passivation structure. The outer sidewall of the first conductive layer is inclined inward toward the center portion.

11. The integrated chip according to claim 10, wherein, Both the first conductive layer and the dielectric layer laterally surround the central portion of the second conductive layer.

12. The integrated chip according to claim 10, further comprising: A bonding bump structure is located above the second conductive layer and fills the trench, wherein the bottom surface of the bonding bump structure is disposed below the bottom surface of the first conductive layer; and Solder balls are disposed along the top surface of the engagement bump structure.

13. The integrated chip according to claim 10, further comprising: A light-emitting device is located above the passivation structure, wherein the light-emitting device is laterally adjacent to the upper conductive structure, and wherein the light-emitting device includes a light-emitting structure above the electrode.

14. The integrated chip according to claim 13, wherein, Along the inner wall of the second conductive layer, the electrode extends continuously from above the second conductive layer to a point below the top surface of the passivation structure, wherein the light-emitting structure is located directly above the upper conductive structure.

15. The integrated chip according to claim 14, wherein, The electrode is in direct contact with the outer wall of the first conductive layer, the outer wall of the dielectric layer, and the outer wall of the second conductive layer.

16. A method for forming an integrated chip, the method comprising: Deposit a passivation structure above the conductive line; A first conductive layer is deposited over the passivated structure; A dielectric layer is deposited above the first conductive layer; A patterning process is performed on the passivation structure, the first conductive layer, and the dielectric layer to form an opening on the conductive line, wherein the patterning process forms a metal oxide along the top surface of the conductive line; A cleaning process is performed on the dielectric layer and the conductive lines to remove the metal oxide from the top surface along the conductive lines; A second conductive layer is deposited above the dielectric layer and the conductive line, such that the second conductive layer liner the opening and contacts the conductive line; and Etch the second conductive layer, the dielectric layer and the first conductive layer to form an upper conductive structure above the conductive line; The second conductive layer includes a central conductive portion that extends continuously through the passivation structure to the conductive line. The central conductive portion is in contact with the inner sidewall of the dielectric layer, the inner sidewall of the first conductive layer, and the inner sidewall of the passivation structure. Furthermore, the outer sidewall of the first conductive layer is inclined inward toward the central conductive portion.

17. The method according to claim 16, wherein, Etching the second conductive layer, the dielectric layer, and the first conductive layer includes: An upper mask layer is formed above the second conductive layer, such that the upper mask layer fills the remaining portion of the opening; A first etching process is performed on the second conductive layer; A second etching process is performed on the dielectric layer; and A third etching process is performed on the first conductive layer.

18. The method according to claim 17, wherein, The first etching process includes exposing the second conductive layer to a first wet etchant, the third etching process includes exposing the first conductive layer to the first wet etchant, and wherein the second etching process includes exposing the dielectric layer to a second wet etchant different from the first wet etchant.

19. The method of claim 17, wherein, The cleaning process is an inductively coupled plasma (ICP) reactive ion etching (RIE) process that exposes the metal oxide to argon-based plasma.

20. The method of claim 17, wherein, The metal oxides include materials with a lattice energy greater than about 5,000 kJ / mol.

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