A dc-dc converter module

Abstract

The application discloses a DC-DC converter module, comprising a Buck circuit network, a Boost circuit network, an inductor and a sampling resistor; the Buck circuit network comprises a Buck bridge arm, an input capacitor, a voltage input positive electrode port and a voltage input ground port; the Boost circuit network comprises a Boost bridge arm, an output capacitor, a voltage output positive electrode port and a voltage output ground port; the inductor is electrically connected with a PWM voltage port of the Buck bridge arm and a PWM voltage port of the Boost bridge arm at two ends; and the sampling resistor is electrically connected with the voltage input ground port and the voltage output ground port at two ends. The application realizes high-precision, low-loss, simple and practical full-current information sampling while saving cost, and provides a basic condition for ZVS control, period-by-period overcurrent protection, output and / or input current estimation of the converter.

Description

Technical Field

[0001] This invention belongs to the field of non-isolated power supply technology, and particularly relates to a DC-DC converter module. Background Technology

[0002] In non-isolated power conversion applications requiring both boost and buck voltage conversion, four-switch Buck-Boost DC-DC converters are widely used, such as in battery charging, photovoltaic grid connection, and power factor correction. Figure 1A As shown, this DC-DC converter includes four switching transistors Q1-Q4, inductor L1, input capacitor Cin, and output capacitor Co. During operation, the input voltage Vin can be less than or greater than or equal to the output voltage Vo, thus possessing buck-boost conversion functionality.

[0003] One existing technology for controlling this converter is to use partitioned mode switching control: when V in >V o When Q3 is normally open and Q4 is normally closed, Q1 and Q2 are complementary switches operating in Buck mode, with Q1 as the main switch and Q2 as the synchronous rectifier; when V in <V o In normal operation, Q1 is normally open, Q2 is normally off, and Q3 and Q4 are complementary switches operating in Boost mode, with Q4 as the main switch and Q3 as the synchronous rectifier. When Vin and Vo are close, it operates in a special transition mode. Except under very light load conditions, the inductor typically operates in continuous current mode (CCM). Although the synchronous rectifiers Q2 and Q3 can achieve zero-voltage switching (ZVS), the main switches Q1 and Q4 operate in hard-turn-on mode, resulting in higher switching losses and limiting the increase in switching frequency. To reduce the inductor size, it is usually necessary to increase the switching frequency; however, this hard-switching control method cannot meet this requirement. Furthermore, this type of control method inherently suffers from the lack of smoothness in operating mode switching, making the controller implementation more complex to solve the smooth switching problem.

[0004] Another existing control method involves enabling all four switching transistors to switch at high frequency. By controlling the inductor current to reverse in a timely manner, the main switching transistors Q1 and Q4 can also achieve ZVS (Zero-Voltage Switching), thus allowing all four transistors to achieve soft switching. Since soft switching results in low switching losses, especially when using silicon carbide (SiC) or gallium nitride (GaN) semiconductor devices, which have extremely low turn-off energy, controlling them to operate at ZVS further reduces switching losses and allows for a significant increase in switching frequency, thereby improving the converter's conversion efficiency and power density. However, this results in a larger inductor current ripple, leading to a higher effective current value for the same output power and increasing the circuit's conduction losses.

[0005] Current detection is the foundation for implementing the above control methods. Existing typical current detection schemes include... Figures 1B to 1D As shown in the diagram. To achieve ZVS control of switching transistors Q1 and Q4, it is necessary to detect that the inductor current at the turn-off moment of Q2 or Q3 is negative. Typically, a resistor R is connected in series between the source of transistor Q2 and ground. sens Perform current detection, such as Figure 1B As shown. Because the current on Q2 cannot fully reflect the inductor current information, for example, when Q2 is off and operating in Boost mode, it cannot provide timely overcurrent protection or current limiting for the inductor current. Therefore, Figure 1C Another current sensing scheme is proposed, which involves connecting R in series between the source parallel connection point of Q2 and Q4 and ground. sens Whether operating in Buck or Boost mode, the peak inductor current can be detected, enabling both ZVS control and timely cycle-by-cycle overcurrent protection. However, the separation of the source and ground hinders heat dissipation for Q2 and Q4. Additionally, a resistor R is typically connected in series at the output port to sample the output current. sens ,like Figure 1B As shown, this will increase throughput loss and hardware cost. Figure 1D Another current sensing scheme is proposed, namely, inserting R in series in the inductor branch. sens It can detect the complete inductor current, enabling both ZVS control and cycle-by-cycle overcurrent protection. However, due to R... sens The voltages at both ends are PWM high-frequency switching voltages, which place high demands on the differential operational amplifier and also result in higher costs.

[0006] Therefore, how to achieve high-precision, low-loss, and easily implemented full current information sampling in DC-DC converter modules while saving costs is an urgent problem to be solved. Summary of the Invention

[0007] In view of this, the purpose of this invention is to provide a DC-DC converter module that, while saving costs, achieves high-precision, low-loss, simple and practical full current information sampling, providing basic conditions for converter ZVS control, cycle-by-cycle overcurrent protection, and output and / or input current estimation.

[0008] To achieve the above objectives, the present invention provides a DC-DC converter module, comprising:

[0009] Buck circuit network, Boost circuit network, inductor and sampling resistor;

[0010] The Buck circuit network includes Buck bridge arms, input capacitors, a positive voltage input port, and a ground voltage input port.

[0011] The Boost circuit network includes a Boost bridge arm, an output capacitor, a voltage output positive port, and a voltage output ground port.

[0012] The two ends of the inductor are electrically connected to the PWM voltage port of the Buck bridge arm and the PWM voltage port of the Boost bridge arm, respectively.

[0013] The two ends of the sampling resistor are electrically connected to the voltage input ground port and the voltage output ground port, respectively.

[0014] Preferably, the Buck bridge arm and the input capacitor are connected in parallel, and the positive voltage input port and the voltage input ground port are electrically connected to the two ends of the input capacitor, respectively.

[0015] The Buck bridge arm includes a first switch and a second switch connected in series, with the source of the second switch electrically connected to the voltage input ground port;

[0016] The Boost bridge arm and the output capacitor are connected in parallel, and the positive voltage output port and the ground voltage output port are electrically connected to the two ends of the output capacitor, respectively.

[0017] The Boost bridge arm includes a third switch and a fourth switch connected in series, with the source of the fourth switch electrically connected to the voltage output ground port.

[0018] Preferably, the DC-DC converter module further includes: a Buck driver chip and a Boost driver chip;

[0019] The Buck driver chip is electrically connected to the gate of the first switch and the gate of the second switch, respectively, and the Buck driver chip is used to drive the first switch and the second switch.

[0020] The Boost driver chip is electrically connected to the gate of the third switch and the gate of the fourth switch, respectively; the Boost driver chip is used to drive the third switch and the fourth switch.

[0021] Preferably, the Buck driver chip has a drive output ground pin and a signal ground pin, wherein the drive output ground pin is electrically connected to the voltage input ground port, and the signal ground pin is electrically connected to the voltage output ground port.

[0022] Preferably, the Buck driver chip includes a level conversion unit and a drive signal unit. The level conversion unit is electrically connected to a signal ground pin, the drive signal unit is electrically connected to the level conversion unit, and the drive signal unit is electrically connected to a drive output ground pin.

[0023] Preferably, the DC-DC converter module further includes:

[0024] The control chip module outputs PWM signals to the driver chip.

[0025] Preferably, the DC-DC converter module further includes:

[0026] An operational amplifier unit amplifies and outputs the voltage differential signal across the sampling resistor to the control chip module.

[0027] Preferably, the control chip module integrates an operational amplifier unit, which amplifies the voltage differential signal across the sampling resistor.

[0028] Preferably, the control chip module obtains inductor current information by sampling the voltage across the sampling resistor.

[0029] Preferably, the control chip module controls the zero-voltage turn-on of the first and fourth switching transistors through inductor current information.

[0030] Preferably, the control chip module implements cycle-by-cycle protection using inductor current information.

[0031] Preferably, the control chip module estimates the average value of the output and / or input current using inductor current information.

[0032] Preferably, the DC-DC converter module further includes:

[0033] An electrical connection circuit board has an upper surface and a lower surface, and the Buck bridge arm, input capacitor, Boost bridge arm, output capacitor and sampling resistor are all disposed on the upper surface of the electrical connection circuit board.

[0034] Preferably, the Buck bridge arm and the Boost bridge arm are respectively disposed on both sides of the sampling resistor.

[0035] Preferably, one end of the input capacitor is electrically connected to the Buck bridge arm via the lower surface of the electrical connection circuit board;

[0036] One end of the output capacitor is electrically connected to the Boost bridge arm via the lower surface of the electrical connection circuit board.

[0037] Preferably, the lower surface of the electrical connection circuit board has a large area of ​​copper plating.

[0038] Preferably, the sampling resistor has a long side and a short side, and the electrical connection terminal of the sampling resistor is disposed on the long side.

[0039] The present invention has the following beneficial effects:

[0040] (1) The current flowing through the sampling resistor is equal in magnitude and opposite in direction to the current flowing through the inductor. Therefore, the complete current information in the inductor can be obtained based on the voltage across the sampling resistor, which can realize both ZVS control and cycle-by-cycle overcurrent protection. Furthermore, by combining the inductor current information and the switching state, the output and / or input current can be estimated, thus eliminating the need for additional input or output current sampling resistors and operational amplifiers. Compared with the multiple sampling resistor schemes in the prior art, this reduces conduction losses and saves hardware costs.

[0041] (2) The present invention sets the sampling resistor between the input ground and the output ground, rather than between the PWM voltage ports of the two bridge arms. Compared with the existing technology, it is easier to implement, has lower requirements for differential operational amplifiers, and is also cheaper. Or, under the same hardware conditions, higher sampling accuracy can be obtained.

[0042] (3) The present invention adjusts the traditional sampling resistor electrodes from the two ends of the long side of the rectangle to the two ends of the short side, which greatly reduces the parasitic inductance of the sampling resistor body, and makes the two power grounds of the present invention, namely the voltage input ground port and the voltage output ground port, closer together, making the current path wider, and further reducing the parasitic inductance between the power grounds, which is more than twice as small as that of the prior art.

[0043] (4) The Buck driver chip is electrically connected to both the voltage input ground port and the signal ground pin. In the case where the sampling resistor separates the voltage input ground port and the voltage output ground port, it can effectively receive signals and ensure driving capability. Attached Figure Description

[0044] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figures 1A to 1D This is a circuit diagram of a DC-DC converter in the prior art;

[0046] Figure 2 This is a circuit diagram of the DC-DC converter module disclosed in the embodiments of the present invention;

[0047] Figure 3 This is a driving circuit diagram of a DC-DC converter module disclosed in an embodiment of the present invention;

[0048] Figure 4 This is another driving circuit diagram of the DC-DC converter module disclosed in the embodiments of the present invention;

[0049] Figure 5 This is a schematic diagram of the Buck driver chip of the DC-DC converter module disclosed in the embodiments of the present invention;

[0050] Figure 6A and Figure 6B This is a schematic diagram of the DC-DC converter module disclosed in the embodiments of the present invention disposed on an electrical connection circuit board;

[0051] Figure 7 This is a schematic diagram of the sampling resistor of the DC-DC converter module disclosed in the embodiments of the present invention;

[0052] Figures 8A to 8F This is a schematic diagram illustrating the calculation of the output current estimate / input current estimate of the DC-DC converter module disclosed in the embodiments of the present invention. Detailed Implementation

[0053] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0054] This embodiment discloses a DC-DC converter module, such as Figure 2 As shown, it includes a Buck circuit network, a Boost circuit network, an inductor L1, and a sampling resistor R. sens The Buck circuit network includes the Buck bridge arm and the input capacitor C. in Voltage input positive terminal and voltage input ground terminal V in - The Boost circuit network includes the Boost bridge arm and the output capacitor C. o The voltage output positive port and voltage output ground port PGND are connected. The two ends of inductor L1 are electrically connected to the PWM voltage ports of the Buck bridge arm and the PWM voltage ports of the Boost bridge arm, respectively. The sampling resistor R sens respectively connected to the voltage input grounding port V in - Connect the voltage output grounding port PGND electrically.

[0055] compared to Figure 1C As shown in the prior art, since the sources of Q2 and Q4 are directly electrically connected to the voltage input and output ground ports respectively, their heat can be discharged through the source pads via a large area of ​​ground plane copper pouring. Therefore, the heat dissipation effect of Q2 and Q4 in the embodiment of the present invention is better.

[0056] In this embodiment, the sampling resistor R sens Set at voltage input ground port V in- Between the voltage output ground port PGND, rather than between the PWM voltage ports of the two bridge arms, compared to Figure 1D The existing technology shown is easier to implement, has lower requirements for differential operational amplifiers, and is less expensive, or can achieve higher sampling accuracy under the same hardware conditions.

[0057] In this embodiment, the Buck bridge arm and the input capacitor C in Parallel connection, voltage input positive terminal and voltage input ground terminal V in - respectively with input capacitor C in The two ends are electrically connected. The Buck bridge arm includes a first switch Q1 and a second switch Q2 connected in series. The source of the second switch Q2 is connected to the voltage input ground port V. in - Electrical connection;

[0058] Boost bridge arm and output capacitor C o In parallel connection, the positive terminal of the voltage output and the voltage output ground terminal PGND are respectively connected to the output capacitor C. o The two ends are electrically connected. The Boost bridge arm includes a third switch Q3 and a fourth switch Q4 connected in series. The source of the fourth switch Q4 is electrically connected to the voltage output ground port PGND.

[0059] Sampling resistor R sens The two ends are electrically connected to the source of the second switch Q2 and the source of the fourth switch Q4, respectively.

[0060] Furthermore, the DC-DC converter module disclosed in this embodiment also includes a Buck driver chip and a Boost driver chip, such as... Figure 3 As shown, Buck driver IC1 is electrically connected to the gate of the first switch Q1 and the gate of the second switch Q2, respectively. Buck driver IC1 is used to drive the first switch Q1 and the second switch Q2. Boost driver IC2 is electrically connected to the gate of the third switch Q3 and the gate of the fourth switch Q4, respectively. Boost driver IC2 is used to drive the third switch Q3 and the fourth switch Q4.

[0061] Furthermore, such as Figure 3 As shown, the Buck driver chip Driver IC1 has a driver output ground pin DGND and a signal ground pin SGND. The driver output ground pin DGND is connected to the voltage input ground port V. in- Electrical connection: The signal ground pin SGND is electrically connected to the voltage output ground port PGND. The driver output ground pin DGND of the Buck driver chip Driver IC1 is separate from the signal ground pin SGND, and it has a certain degree of internal voltage isolation capability, i.e., it has an internal level shift function. Specifically, as shown... Figure 5 As shown, the Buck driver chip includes a level conversion unit and a drive signal unit. The level conversion unit is electrically connected to the signal ground pin SGND, the drive signal unit is electrically connected to the level conversion unit, and the drive signal unit is electrically connected to the drive output ground pin DGND. This effectively receives signals while ensuring driving capability. Figure 3 and Figure 5 The meanings of the symbols are as follows: R1 to R4 are voltage detection voltage divider resistors, NTC is temperature detection resistor, Isens+ and Isens- are voltage differential signals across the sampling resistor, PWM1 to PWM4 are the PWM signals of Q1 to Q4 respectively, VD is the power supply pin, and Driver is the drive output pin.

[0062] Furthermore, such as Figure 3 As shown, the DC-DC converter module disclosed in this embodiment also includes a control chip module, which outputs PWM signals to the Buck driver chip Driver IC1 and the Boost driver chip Driver IC2.

[0063] In a preferred embodiment, an operational amplifier unit is integrated within the control chip module, which amplifies the voltage differential signal across the sampling resistor. In other embodiments, such as Figure 4 As shown, the above-mentioned operational amplifier unit can also be set independently outside the control chip module, which amplifies the voltage differential signal across the sampling resistor and outputs it to the control chip module.

[0064] The control chip module samples the sampling resistor R. sens The voltage across the terminals is used to obtain the inductor current information. Specifically, according to circuit principles, R... sens With the current flowing through L1 (i L The magnitudes are equal and the directions are opposite, therefore R sens The voltage across L1 can reflect complete current information, and its functions include:

[0065] 1) ZVS control is achieved using inductor valley current information;

[0066] 2) Utilize inductor peak current information to achieve cycle-by-cycle overcurrent protection;

[0067] 3) By combining the switch status and inductor current sampling signal, the average value of the input or output port current can be estimated for feedback control or external reporting of converter operating status information, without the need for additional input or output current sampling resistors and operational amplifiers. Compared with existing technologies, this can reduce conduction losses and save hardware costs.

[0068] In this context, feedback control or reporting of the converter's operating status requires output current and / or input current information. Existing technologies generally use resistors to directly detect the output current and / or input current, which has relatively high accuracy. However, this increases conduction losses and hardware costs. In this embodiment, the output current and / or input current are calculated from the inductor current waveform, reducing the need for additional sampling resistors in traditional current measurement schemes. Figures 8A to 8F The output current estimate I is shown in this embodiment. out_est and / or input current estimate I in_est The principle. I out_est The current flowing through transistor Q3 is the average value after being filtered by the output capacitor. Similarly, I in_est The current flowing through transistor Q1 is the average value after being filtered by the input capacitor. Below, we only use I... out_est Let's take an example to illustrate. (By...) Figure 8A and Figure 8B As can be seen, due to the transient switching process, the actual current of Q3 contains oscillations, making it difficult to detect accurately. Therefore, this embodiment uses the principle of area equivalence to calculate the estimated output current I based on the inductor current and the switching state. out_est Specifically, ignoring the switching process, the average current i flowing through transistor Q3 when PWM3 is turned on is... Q3 =i L When PWM3 is turned off, i Q3 =0, while I out_est For i Q3 The average value after filtering by the output capacitor, according to the principle of area equivalence, i Q3 The average value over one switching cycle is the estimated value of the output current. Similarly, refer to Figure 8E and Figure 8F An estimate of the input current can be calculated. Where I1 and I2 are the inductor currents at the end of time periods T1 and T2, respectively, which are the inductor currents at the turn-off times of Q4 and Q1.

[0069] In some other embodiments, such as Figure 8B As shown, to avoid the impact of oscillating current generated during device switching on sampling accuracy, the sampling time T of I1 is... s1 It occurs before the Q4 shutdown and allows sufficient time T for sampling between the shutdown time and the shutdown time. sample That is, Ts1 =T Q4off -T sample I2 sampling time T s2 It occurs before Q1 is turned off and within the time interval T required for sampling is allowed between the turn-off time and the turn-off time. sample That is, T s2 =T Q1off -T sample The error in current due to the advance sampling can be compensated by calculating the advance time, inductance, and inductor voltage drop. The calculation of this compensation is a known technique and will not be elaborated upon here.

[0070] To improve the accuracy of current estimation, the sampled values ​​I1 and I2 or the estimated value I can be calculated over multiple switching cycles. out_est and I in_est Perform digital filtering, such as low-pass filtering and moving average.

[0071] In the prior art, because the sampling resistor R sens It is connected in series with the power inductor L1 in a circuit, therefore, R sens Parasitic inductance on, or due to the increase of R sens This results in the voltage input to the ground port V. in - The current path between the voltage output ground port PGND, i.e., R s The longer path leads to parasitic inductance L gnd When it increases, it will have (L) when Q1 / Q3 is turned on. gnd / L)*V sw1 voltage (V) sw1 (where L is the voltage at the midpoint of bridge arm Q1 / Q2 relative to the voltage input ground port), when Q2 / Q4 is turned on, we have (L gnd / L)*V sw2 voltage (V) sw2 (This refers to the voltage at the midpoint of bridge arms Q3 / Q4 relative to the output ground port). Clearly, L... gnd The larger the voltage, the higher the high-frequency voltage between the two grounds, the greater the input and output common-mode voltage, and the more severe the electromagnetic interference.

[0072] like Figure 6A As shown, in this embodiment, C is first... in The close proximity of Q1 and Q2 forms a low-loop Buck bridge arm, enabling V... sw1 Voltage spikes should be minimized; similarly, C o The Boost bridge arm, positioned close to Q3 and Q4, forms another low-loop configuration, enabling V... sw2 Minimize voltage spikes to reduce common-mode voltage at the source.

[0073] Figure 6BThis diagram illustrates a DC-DC converter module as disclosed in an embodiment of the present invention, mounted on an electrical connection board. The electrical connection board (i.e., PCB board) has an upper surface and a lower surface, a Buck bridge arm, and an input capacitor C. in Boost bridge arm, output capacitor C o and sampling resistor R sens Both are mounted on the upper surface of the electrical connection circuit board. The Buck bridge arm and the Boost bridge arm are respectively mounted on the sampling resistor R. sens On both sides, sampling resistor R sens The two ends are electrically connected to the source of the second switch Q2 and the source of the fourth switch Q4, respectively, and the input capacitor C in One end of the output capacitor Co is electrically connected to the Buck bridge arm via the lower surface of the electrical connection board, and the other end of the output capacitor Co is electrically connected to the Boost bridge arm via the lower surface of the electrical connection board.

[0074] The two ends of the series bridge arm are connected to a high DC potential and a low DC potential, respectively. The innermost copper layer closest to the PCB board is set to either a high or low potential, and overlaps with at least half of the projected area of ​​the two switching elements. A pad is then created on the lower surface of the PCB board along with the other potential. These two potential pads are used to set the DC decoupling capacitor, forming a low-loop circuit together with the overlapping copper layer. The insulation layer thickness between two adjacent copper layers should be less than 0.1 mm to reduce the loop size. In this embodiment, the bridge arm loop inductance circuit starts from... Figure 6A The 2D shape shown is adjusted to Figure 6B The 3D shape shown has reduced parameters by more than 2 times and Rs path by more than 2 times, resulting in a significant improvement in high-frequency characteristics.

[0075] In this embodiment, as Figure 7 As shown, the sampling resistor R sens It has a long side and a short side, and a sampling resistor R. sens The electrical connection terminals are located on the long side. In this embodiment, the traditional sampling resistor electrodes are changed from the two ends of the long side of the rectangle to the two ends of the short side, which significantly reduces the parasitic inductance of the sampling resistor body and helps the two power grounds (V) in By placing the power grounds (PGND) closer to each other and widening the current path, the parasitic inductance between the two power grounds is reduced to an extreme level, more than twice that of existing technologies. This layout makes the parasitic inductance caused by Rsens almost negligible.

[0076] In a preferred embodiment, the lower surface of the electrical connection board has a large copper area, and the adjacent inner layers of the MOS of the Buck bridge arm and the Boost bridge arm each have a large copper area for Vin- and voltage output ground port PGND for heat dissipation, which compensates for the insufficient heat dissipation caused by Rsens separating the traditional large ground area.

[0077] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A DC-DC converter module, characterized in that, include: Buck circuit network, Boost circuit network, inductor and sampling resistor; The Buck circuit network includes Buck bridge arms, input capacitors, a positive voltage input port, and a ground voltage input port. The Boost circuit network includes a Boost bridge arm, an output capacitor, a voltage output positive port, and a voltage output ground port. The two ends of the inductor are electrically connected to the PWM voltage port of the Buck bridge arm and the PWM voltage port of the Boost bridge arm, respectively. The two ends of the sampling resistor are electrically connected to the voltage input ground port and the voltage output ground port, respectively; It also includes: control chip module, Buck driver chip and Boost driver chip; The Buck bridge arm includes a first and a second switch connected in series, and the Boost bridge arm includes a third and a fourth switch connected in series. The Buck driver chip is electrically connected to the gate of the first switch and the gate of the second switch, respectively, and the Buck driver chip is used to drive the first switch and the second switch. The Boost driver chip is electrically connected to the gate of the third switch and the gate of the fourth switch, respectively; the Boost driver chip is used to drive the third switch and the fourth switch. The control chip module outputs the PWM signal to the driver chip; The Buck driver chip has a drive output ground pin and a signal ground pin. The drive output ground pin is electrically connected to the voltage input ground port, and the signal ground pin is electrically connected to the voltage output ground port. The Buck driver chip has voltage isolation capability, which is used between the drive output ground pin and the signal ground pin.

2. The DC-DC converter module according to claim 1, characterized in that, The Buck bridge arm and the input capacitor are connected in parallel, and the positive voltage input port and the voltage input ground port are electrically connected to the two ends of the input capacitor, respectively; the source of the second switching transistor is electrically connected to the voltage input ground port. The Boost bridge arm and the output capacitor are connected in parallel, and the positive voltage output port and the ground voltage output port are electrically connected to the two ends of the output capacitor, respectively; the source of the fourth switch is electrically connected to the ground voltage output port.

3. The DC-DC converter module according to claim 1, characterized in that, The Buck driver chip includes a level conversion unit and a drive signal unit. The level conversion unit is electrically connected to the signal ground pin, the drive signal unit is electrically connected to the level conversion unit, and the drive signal unit is electrically connected to the drive output ground pin.

4. The DC-DC converter module according to claim 1, characterized in that, Also includes: An operational amplifier unit amplifies and outputs the voltage differential signal across the sampling resistor to the control chip module.

5. The DC-DC converter module according to claim 1, characterized in that, The control chip module integrates an operational amplifier unit, which amplifies the voltage differential signal across the sampling resistor.

6. The DC-DC converter module according to claim 1, characterized in that, The control chip module obtains inductor current information by sampling the voltage across the sampling resistor.

7. The DC-DC converter module according to claim 6, characterized in that, The control chip module controls the zero-voltage turn-on of the first and fourth switching transistors using inductor current information.

8. The DC-DC converter module according to claim 6, characterized in that, The control chip module implements cycle-by-cycle protection using inductor current information.

9. The DC-DC converter module according to claim 6, characterized in that, The control chip module estimates the average value of the output and / or input current using inductor current information.

10. The DC-DC converter module according to claim 1, characterized in that, Also includes: An electrical connection circuit board has an upper surface and a lower surface, and the Buck bridge arm, input capacitor, Boost bridge arm, output capacitor and sampling resistor are all disposed on the upper surface of the electrical connection circuit board.

11. The DC-DC converter module according to claim 10, characterized in that, The Buck bridge arm and the Boost bridge arm are respectively positioned on both sides of the sampling resistor.

12. The DC-DC converter module according to claim 10, characterized in that, One end of the input capacitor is electrically connected to the Buck bridge arm via the lower surface of the electrical connection circuit board; One end of the output capacitor is electrically connected to the Boost bridge arm via the lower surface of the electrical connection circuit board.

13. The DC-DC converter module according to claim 10, characterized in that, The lower surface of the electrical connection circuit board has a large area of ​​copper plating.

14. The DC-DC converter module according to claim 1, characterized in that, The sampling resistor has a long side and a short side, and the electrical connection terminal of the sampling resistor is located on the long side.

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