Metrology method

Abstract

A metrology method includes: performing a first exposure on a substrate to form a first patterned layer including a plurality of first target units, each first target unit including first target features; performing a second exposure on the substrate to form a second patterned layer including a plurality of second target units that are overlayed with respective ones of the first target units, each second target unit having second target features, wherein ones of the plurality of second target units have the second target features positioned at different offsets, respectively, relative to a reference location; imaging the second target units overlayed on the first target units; and determining edge placement errors based on positions of edges of the second target features in the second target units relative to edges of the first target features of the underlying first target units.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to European patent application 19219624.4, filed on 24 December 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to measurement methods and targets, particularly for devices manufactured using photolithography apparatus. Background Technology

[0004] A photolithography apparatus is a machine that applies a desired pattern onto a substrate, typically onto a target portion of the substrate. Photolithography apparatuses can be used, for example, in the fabrication of integrated circuits (ICs). In this case, a patterning apparatus, alternatively referred to as a mask or photomask, can be used to generate circuit patterns to be formed on individual layers of the IC. This pattern can be transferred onto a target portion (e.g., comprising a portion, one or more dies) on a substrate (e.g., a silicon wafer). The transfer of the pattern is typically achieved by imaging onto a radiation-sensitive material layer (resist) provided on the substrate. Generally, a single substrate will contain a network of continuously patterned adjacent target portions.

[0005] Most semiconductor devices require multiple patterned layers to be formed and transferred into a substrate. For proper device operation, there is typically a limit to the tolerable error in edge positioning, known as edge placement error or EPE. EPE can arise from relative positioning errors between successive layers (known as overlay) or from errors in feature size (especially critical dimensions or CD). As photolithography continues to strive to reduce the size of features that can be formed (shrink), the limitations on EPE are becoming increasingly stringent.

[0006] Overlap can be caused by a variety of factors in the photolithography process, such as errors in substrate positioning during exposure and aberrations in the projected image. Overlap can also occur during process steps (such as etching) used to transfer the pattern onto the substrate. Some of these process steps introduce stress within the substrate, which can lead to localized or overall deformation of the substrate. Forming three-dimensional structures on the substrate, such as those required for recently developed memory types and MEMS, can also result in significant substrate deformation. CD variations can also originate from a variety of causes, including dose or focus errors. Summary of the Invention

[0007] This disclosure aims to provide improved measurement methods, for example, for use in photolithography device manufacturing processes.

[0008] According to one embodiment, an inspection tool is provided, comprising:

[0009] An imaging system is configured to image a target formed on a substrate, the target comprising a plurality of first target units formed in a first patterned layer and a plurality of second target units formed in a second patterned layer, the plurality of second target units being overlaid with corresponding portions of the first target units, each first target unit including a first target feature, each second target unit having a second target feature, wherein some of the plurality of second target units have second target features positioned with different offsets relative to a reference position; and

[0010] The image analysis system is configured to determine edge placement based on the position of the edge of a second target feature in a second target unit relative to the edge of a first target feature in a first target unit below.

[0011] According to one embodiment, a measurement method is provided, comprising:

[0012] A first exposure is performed on a substrate to form a first patterning layer comprising a plurality of first target units, each first target unit comprising a first target feature;

[0013] A second exposure is performed on the substrate to form a second patterned layer, the second patterned layer including a plurality of second target units overlaid with corresponding first target units, each second target unit having a second target feature, wherein some of the plurality of second target units have second target features positioned with different offsets relative to a reference position.

[0014] Imaging the second target unit engraved on the first target unit; and

[0015] The edge placement error is determined based on the position of the edge of the second target feature in the second target unit relative to the edge of the first target feature in the first target unit below. Attached Figure Description

[0016] Embodiments will now be described by way of example with reference to the accompanying drawings, in which:

[0017] Figure 1 The image depicts a photolithography apparatus that, together with other devices, forms a production facility for semiconductor devices.

[0018] Figures 2A to 2C The steps in the process of forming the cutting line are described;

[0019] Figures 3A to 3F The effect of positional variations in cutting features within the target and device characteristics is depicted;

[0020] Figures 4A to 4C The effect of the opposite offset of the position of the cutting feature is depicted;

[0021] Figure 5 The equivalence of the reverse deviation characteristics under rotation is described;

[0022] Figure 6 An example of a SEM image depicting a target feature in an embodiment;

[0023] Figure 7 An example arrangement of a composite target including sub-targets with different deviations is depicted;

[0024] Figures 8A to 8C The effect of the positional variation of the contact hole relative to the lines in the plan view and cross-sectional view is depicted;

[0025] Figures 9A to 9C The effects of the arrangement and positional errors of the vertically aligned channel holes are depicted; and

[0026] Figure 10 A flowchart illustrating the method according to an embodiment is provided. Detailed Implementation

[0027] Electronic devices consist of circuits formed on silicon wafers called substrates. Many circuits can be formed together on the same silicon wafer and are called integrated circuits or ICs. The size of these circuits has been reduced significantly so that more circuits can be fitted onto the substrate. For example, an IC chip in a smartphone can be as small as a thumbnail but can include more than 2 billion transistors, each less than 1 / 1000th the size of a human hair.

[0028] Manufacturing these extremely small ICs is a complex, time-consuming, and expensive process, typically involving hundreds of individual steps. Even an error in one step can lead to a defective IC, rendering it unusable. Therefore, one goal of the manufacturing process is to avoid such defects in order to maximize the number of functional ICs manufactured in the process; that is, to improve the overall yield of the process.

[0029] A key component of improving yield is monitoring the chip manufacturing process to ensure it produces a sufficient number of functional integrated circuits. One way to monitor the process is to inspect the chip's circuit structure at various stages of its formation. This can be done using scanning electron microscopy (SEM), optical inspection systems, and the like. Such systems can be used to image these structures—essentially taking "photographs" of the wafer structure—with SEM capable of imaging the smallest structures within them. The images can be used to determine if the structure is correctly formed in the correct location. If defects are found, the process can be adjusted to make them less likely to recur.

[0030] To control errors in photolithography manufacturing processes, such as errors in the relative positions of features in different layers (called overlay) and feature sizes (called CD variations), it is necessary to measure these errors, such as by using SEM, optical inspection systems, etc., before applying corrections. It is difficult to directly measure the features of devices formed by photolithography. Therefore, special targets are formed simultaneously with the device features. Targets are designed to be easier to image, for example, by scanning electron microscopy, and to be represented in the same way as the device features; for example, if the device features suffer overlay errors, the target will also suffer the same errors. However, although targets are easier to image than device features, it is still difficult to accurately measure the absolute distances in those images, especially when using different imaging equipment or when features are measured at different stages of the manufacturing process. Among other things, a novel method and arrangement of targets are disclosed below, which makes it possible to determine the absolute value of errors such as overlay without direct measurement in SEM images.

[0031] In the example of the new target, each target has multiple target sub-units, all of which have the same two features, but in different target sub-units, one feature is located at a different position relative to the other. Due to the range of relative positions of the two features, the positional error will cause the edges of the two features to overlap in at least one target. Knowing the initial positional changes, the magnitude of the positional error can be determined by identifying which target the edges of the two features overlap in. In other examples, the positional error can be determined by comparing images of different sub-units, perhaps after cropping, rotating, and / or reflecting an image. Therefore, it is no longer necessary to directly measure the positions of the two features, and the magnitude of the error can be determined more accurately.

[0032] Before describing the embodiments in detail, it is helpful to present an example environment in which the techniques disclosed herein can be implemented.

[0033] Figure 1 The illustration depicts a typical layout of a semiconductor manufacturing facility. A photolithography apparatus 100 applies a desired pattern onto a substrate. Photolithography apparatuses are used, for example, in the manufacture of integrated circuits (ICs). In this case, a patterning apparatus MA, alternatively referred to as a mask or mask plate, includes a circuit pattern of features (often referred to as "product features") to be formed on individual layers of the IC. This pattern is transferred to a target portion (e.g., including a portion, one or more dies) on the substrate "W" (e.g., a silicon wafer) via exposure 104 on a radiation-sensitive material layer (resist) provided on the substrate. Generally, a single substrate will contain a network of continuously patterned adjacent target portions.

[0034] Known photolithography apparatuses irradiate each target portion by illuminating a patterning apparatus, simultaneously positioning the target portion of the substrate at the image position of the patterning apparatus. The irradiated target portion of the substrate is called the "exposure field" or simply the "field". The layout of the field on the substrate is typically a network of adjacent rectangles or other shapes aligned according to a Cartesian two-dimensional coordinate system (e.g., aligned along the X and Y axes, which are orthogonal to each other).

[0035] The requirement for a photolithography apparatus is to accurately replicate the desired pattern onto a substrate. The position and size of the applied product features must be within certain tolerances. Positional errors can lead to overlay errors (commonly referred to as "overlay"). Overlay is the error in placing a first product feature in a first layer relative to a second product feature in a second layer. Photolithography apparatuses reduce overlay errors by accurately aligning each wafer to a reference before patterning. This is done by measuring the position of alignment marks applied to the substrate. Based on the alignment measurements, the substrate position is controlled during the patterning process to prevent overlay errors that exceed tolerances. Alignment marks are typically created as part of the product image, thus forming a reference for measuring overlay. Alternatively, alignment marks from previously formed layers can be used.

[0036] When the dose applied associated with exposure 104 is outside the specifications, critical dimension (CD) errors in the product features may occur. Therefore, the lithography apparatus 100 must be able to accurately control the dose of radiation applied to the substrate. CD errors can also occur when the substrate is not correctly positioned with respect to the focal plane associated with the pattern image. Focal position errors are typically associated with the non-planarity of the substrate surface. The lithography apparatus reduces these focal position errors by measuring the substrate surface topography using a level sensor before patterning. Substrate height correction is applied in subsequent patterning processes to ensure that the patterning apparatus is correctly imaged (focused) onto the substrate.

[0037] To verify overlay and CD errors associated with the photolithography process, the patterned substrate is examined using metrology apparatus 140. Common examples of metrology apparatuses are scatterometers and scanning electron microscopes. Scatterometers are traditionally used to measure the characteristics of dedicated metrology targets. These metrology targets represent product features, except that they are typically larger to allow for accurate measurement. Scatterometers measure overlay by detecting asymmetry in the diffraction pattern associated with the overlay metrology target. Critical dimensions are measured by analyzing the diffraction pattern associated with critical dimension metrology targets. CD metrology targets are used to measure the results of the most recently exposed layer. Overlay targets are used to measure the difference between the positions of the previous and most recent layers. Electron beam-based inspection tools, such as scanning electron microscopes (SEM), often provide excellent results when measuring small overlay and CD values.

[0038] Within a semiconductor manufacturing facility, lithography apparatus 100 and metrology apparatus 140 form part of a "lithography unit" or "lithography cluster." The lithography cluster also includes a coating apparatus 108 for applying photoresist to a substrate W, a baking apparatus 110, a developing apparatus 112 for developing an exposed pattern into a physical resist pattern, an etching station 122, an apparatus 124 for performing a post-etch annealing step, and possibly other processing apparatus 126, etc. The metrology apparatus is configured to inspect the substrate after developing 112 or after other processes (e.g., etching). The various apparatuses within the lithography unit are controlled by a supervisory control system (SCS), which issues control signals 166 to control the lithography apparatus via a lithography apparatus control unit (LACU) 106 to execute a configuration scheme R. The SCS allows different apparatuses to be operated to deliver maximum throughput and product yield. An important control mechanism is the feedback 146 from metrology apparatus 140 (via the SCS) to various apparatuses, particularly to lithography apparatus 100. Based on the characteristics of the metrology feedback, corrective actions are determined to improve the processing quality of subsequent substrates. The SCS can be one or more computers that may or may not communicate. A configuration scheme R can be implemented as one configuration scheme or multiple independent configuration schemes. For example, a configuration scheme for a process step such as etching may be completely independent of a configuration scheme used to examine the results of that process step (e.g., etching). For example, two or more configuration schemes for an individual step can be correlated to allow adjusting one configuration scheme to account for the results of another configuration scheme performed on the same or different substrates.

[0039] The performance of lithography apparatuses is typically controlled and calibrated using methods such as Advanced Process Control (APC), as described, for example, in US2012008127A1. APC techniques utilize measurements applied to a metrological target on the substrate. The Manufacturing Execution System (MES) schedules APC measurements and transmits the results to a data processing unit. The data processing unit converts the characteristics of the measurement data into a configuration scheme that includes instructions for the lithography apparatus. This approach is highly effective in suppressing drift phenomena associated with lithography apparatuses.

[0040] The processing of measurement data into calibration actions by the processing device is crucial for semiconductor manufacturing. In addition to measurement data, characteristics of individual patterning apparatuses, substrates, processing devices, and other contextual data may be needed to further optimize the manufacturing process. The framework in which available measurement and contextual data are used to optimize the lithography process holistically is often referred to as part of holistic lithography. For example, contextual data related to CD errors on a mask can be used to control various devices (lithography apparatus, etching station) so that the CD errors do not affect the yield of the manufacturing process. Subsequent measurement data can be used to verify the effectiveness of the control strategy and to determine further calibration actions.

[0041] To qualify the process window, separate CD and overlay measurements are performed using one or more existing tools, and then combined into an edge placement error (EPE) budget. Typically, one measurement step may be performed after development (ADI) and another after etching (AEI), and there are inherent difficulties in calibrating two such different measurements to give equivalent results.

[0042] EPE (Extended Physical Surface) is crucial for ensuring the proper functioning of semiconductor devices; for example, it can affect the availability of sufficient electrical contacts at the back end of a line module. This makes EPE measurement invaluable for ensuring that the process window accommodates a sufficient EPE budget and for controlling the process to remain within that window.

[0043] Targeted designs that facilitate EPE determination are suggested, such as post-etching measurements. Post-etching measurements are likely desirable because they better represent the final patterned structure. Furthermore, post-etching measurements can reveal the contribution of the etching machine and other tools (such as deposition and CMP) to the final pattern. Post-development (pre-pattern transfer) measurements are also desirable because they may allow defective exposures to be reworked rather than scrapped.

[0044] The target corresponds to the pattern of interest, but a portion of the pattern has a displacement or deviation. For overlay measurement, the target has components (features) in the same two layers as the pattern of interest, and the target feature in each layer corresponds to a device feature in the corresponding layer. Device features may also be referred to as product features or pattern features. In one embodiment, one or both features of the target completely correspond to the device feature of interest. If optical proximity correction (OPC) features are applied to the device features, they are ideally also applied to the target features. Ideally, the target features have the same pitch as the device features (e.g., dense, semi-dense, or isolated). Ideally, the target features have the same CD as the device features. In particular, if the device features are elongated (such as line features), the target features do not need to be as long as the device features, but the target features are ideally long enough to behave similarly to the device features. If the device has an array of features, such as parallel lines or a mesh of contact holes, the target does not need to have the same extent as the array of device features, but ideally it has at least two unit cells of the array.

[0045] The target has multiple parts, referred to herein as target units. Various target units provide a range of different offsets between two features. This allows for self-calibration of the measurement by designing multiple displacement offsets on the mask plane, thus enabling direct determination of the configuration accuracy. Ideally, all sub-units of the target are fitted within the field of view of the measurement tool to be used to measure the target. For example, the target can be smaller than 40 μm x 40 μm. The various target units do not need to be structurally divided. For example, if the first target feature comprises elongated lines and the second target feature is a slit feature, then several target units can be formed by slit features positioned along a continuous set of lines.

[0046] Now refer to Figures 2A to 2C , Figures 3A to 3F as well as Figures 4A to 4C This describes an exemplary target for measuring edge placement error (EPE) in line layers and cut layers.

[0047] Device layout in Figures 2A to 2C It is shown in the middle: Figure 2A The three lines DL1-3 in the line layer are shown, and Figure 2B The cut feature C1 formed in a hard mask HM or photolithographic stack (e.g., resist, adhesion layer, BARC, etc.) is shown. Figure 2C The etched line layer is shown: line DL2 is divided into two lines, DL2A and DL2B. However, it is difficult to detect minute changes in CD-y and overlay-y during post-etching inspection. CD-y refers to the critical dimension in the y-direction, and overlay-y refers to the overlay in the y-direction. This is in Figures 3A to 3C The diagram shows the results after development (top portion) and after etching (bottom portion). It can be seen that the minute changes in the detectable location of the cut features during post-development inspection did not result in any detectable differences in the post-etching inspection results, because the cut features are larger than lines.

[0048] According to one embodiment, the target unit is Figure 3D The diagram is shown, with the top portion showing the result after development and the bottom portion showing the result after etching. It can be seen that the target unit corresponds to a device feature, except that the origin of the dicing layer is shifted in the y-direction by a line pitch / 2. This means that the target dicing feature CT1 is symmetrically but not completely overlaid with the two target line features TL1, TL2, so each target line is a half-cut. The edge of the target dicing feature CT1 falls within the target line features TL1, TL2. This has the following effect: the dicing CD-y is clearly detectable in the etched target layout. The target features are positioned so that their associated edges are detectable after processing.

[0049] Figure 3E and Figure 3FThe effects of overlay errors in the +y and -y directions are shown separately. The top portion again shows the situation after development, while the bottom portion shows the situation after etching. The effect of overlay error is that the half-cut of one target line increases while that of the other decreases. Therefore, the direction (positive or negative) of the overlay error can be determined without measuring the target image simply by considering which direction the target is asymmetrical. This can also be done in... Figures 4A to 4C As seen in the middle, Figures 4A to 4C The left side shows a plan view of the etched features and the right side shows a cross-section of the etched features. Figure 4A In the middle, the centerline TL2 is completely cut off, while Figure 4B and Figure 4C Residual material remains, the location of which depends on the direction of the cutting feature offset. It can be understood that actual SEM images (examples of which are shown in...) Figure 6 The diagram shown is quite different from the idealized illustration presented here, but the location of the cutting features is still easily identifiable.

[0050] To determine the magnitude of positional errors (such as overlay, CD, or edge placement errors), any symmetry within the target can be utilized. Figure 5 In the case of the target shown, a target image with an overlay of –A nm -y, rotated 180°, looks like an image of a target with an overlay of +A nm -y. In this example, the same effect can be achieved by reflecting one of the images. Therefore, the actual overlay magnitude can be determined by providing multiple targets with different deviations (displacement of the second target feature at the mask plane) and checking for symmetry pairs. For example, if an array of targets with ±n nm deviations is printed, where n = 1, 2, 3, etc., and the rotated etched image of a target with a +1 nm deviation matches the etched image of a target with a -3 nm deviation, then there is an overlay of +1 nm. This is because the actual position of the second feature in the target with a +1 nm deviation is +2 nm (deviation + actual overlay = 1 + 1 = 2), and the actual position of the second feature in the target with a -3 nm deviation is -2 nm (deviation + actual overlay = -3 + 1 = -2). Similar techniques can be applied to determine CD or edge placement errors (a combination of CD and overlay), optionally by considering only one edge of the target feature. In other target modes, different symmetry operations or combinations of symmetry operations can be used before comparing target units. In some cases, image transformation and comparison can be performed only on a portion of the target unit's image.

[0051] The method described above does not require measuring absolute distances in the image provided by the measurement tool, and therefore can be considered self-calibrated. This method can also be applied to non-imaging measurement tools, such as scatterometers. The desired measurement range and resolution can be set by appropriately selecting the number of targets and the magnitude of the deviation variation (e.g., ±n*0.5nm, ±n*1nm, ±n*2nm).

[0052] In an example where the target includes lines and cut features, the cut feature is offset by a distance D in each target unit, where D = ±n * 1 nm, and n = 1, 2, 3, etc. Ideally, the value of n is such that the offset range in each direction is equivalent to the distance between the nominal positions of adjacent edges of two target features (ideally, it corresponds to the distance between the nominal positions of the edges of two device features). In other words, |Dmax| ≥ |pattern 1 edge – pattern 2 edge|. If correctly imaged, the nominal position of a feature or edge is its location and can also be referred to as the design position.

[0053] Figure 7 An example array of target units TU1, TU2, ... TUn is shown. Each target unit can have a size smaller than approximately 5μm x 5μm, for example, 2μm x 2μm. An array of nine or more target units can be easily fitted into the field of view of the measurement tool, enabling the determination of overlay and / or CD in a single measurement. If suitable, the target unit array can be easily fitted into the scribing area or the product area.

[0054] Although a target with lines extending in the x-direction for measuring CD and overlay in the y-direction has been illustrated, it should be understood that the entire arrangement can be rotated 90° to measure overlay and CD in the x-direction. Composite targets may include target units with two orientations. However, in device layers that have only or primarily lines extending along the x or y direction, measuring overlay and CD in only one direction may be sufficient.

[0055] Figures 8A to 8C Another set of target units is shown for use with the pattern of the contact hole (through hole) to be contacted. In each case, the top portion is a plan view, and the bottom portion is the corresponding cross-section. In the first target unit ( Figure 8A In the second target unit (), the contact hole CH is aligned with the center of the target line feature TL (which extends in the y direction in this example). Figure 8B In the third target unit (), the contact hole feature CH has a predetermined offset in the -ve x direction, while in the third target unit ( Figure 8CIn this model, the contact hole feature CH has a predetermined offset in the +ve x direction. The size of the contact hole and the offset in the second and third target units are chosen such that, under perfectly correct imaging and patterning (i.e., good overlay and CD within the process window), the edge of the underlying line is not visible in the first target unit, but is visible in the second and third target units. If there is a sufficient amount of overlay error to offset the contact hole target feature relative to the line feature in the +ve x direction, then the edge of the line feature will become visible in the contact hole of the first target unit and disappear from the contact hole target feature of the second target unit. Conversely, an overlay error in the -x direction will cause the edge of the line feature to appear in the first target unit and disappear in the third target unit. A sufficient amount of -ve CD error will cause the edge to appear in the first target unit and move in the second and third target units. A +ve CD error will cause the edge of the line feature to disappear from both the second and third target units. Therefore, different types of errors can be distinguished by considering in which target units the edge is visible. Providing additional target units with different offsets enables the detection of different types and magnitudes of errors over a wider range and / or at higher resolution.

[0056] In another embodiment, a target array with a deviation of ±n nm is printed, where n = 1, 2, 3, etc. Advantageously, based on such an array, the EPE can be determined without any precise measurements. In some cases, the EPE is the positional error between the edge of the first target and the edge of the second target. In an example illustrating this concept, the target for the cut hole is placed on a metal line, with the outer edge of the cut located 3 nm from the edge of the metal line. In one case, the metal line size is 1 nm too large, and the cut hole is placed 1 nm too close to the line edge. In this case, the EPE is zero because the two errors cancel each other out. In another case, the metal line size is 1 nm too large, and the cut hole is 1 nm too far from the line edge. In this case, the EPE is 2 nm because the two errors are additive. In an example where the EPE can be determined without any precise measurements, a target array with the aforementioned deviation is printed. In one of the targets, the cut edge is aligned with the edge of the metal (including overlay error and CD error). This is determined by examining the target array, where the cut can be seen getting closer and closer to the edge of the metal line, such as where the upper edge of CT1 is located in the middle of TL1. Figure 3D The upper edge of CT1 is closer to the upper edge of TL1. Figure 3EThe two are visible. In such a target array, the upper edge of CD1 will be closer to the upper edge of TL1, and at one of the deviations, the two edges will align. As the target array continues, the upper edge of CT1 will extend beyond the top of TL1. Based on the first target in the target array that CT1 cuts through TL1, the EPE can be determined simply by knowing the deviation of that particular target.

[0057] Figures 9A to 9C The diagram illustrates the application of, for example Figure 9A This illustration shows an embodiment of a pattern for placing an upper channel hole CH2 (e.g., a memory channel hole in a 3D-NAND device) above a lower channel hole CH1. Accurate alignment of the two channel holes is desirable to ensure a good electrical connection. Figure 9B This is a schematic diagram of a target unit including an array of channel hole features in the etched state with good alignment. Figure 9C The corresponding view in the misaligned example is shown: only a portion of the edge of the lower contact hole is visible. Targets used with this pattern include multiple target holes in the upper layer, which have various offsets relative to the channel holes in the lower layer. Offsets can include offsets in the x-direction, y-direction, and / or both x and y-directions.

[0058] exist Figure 10 An exemplary method is depicted, which is a flowchart. The first layer L1 is exposed (S1), then developed and processed (e.g., by etching) (S2) of the first layer L1. Figure 3D to Figure 3F as well as Figures 8A to 8C In the example, line features are formed in these steps. Figures 9A to 9C In the example, a lower channel hole is formed. The second layer L2 is exposed (S2), then developed and processed (e.g., by etching) (S4). Figure 3D to Figure 3F In the example, cutting features are formed during these steps. Figures 8A to 8C In the example, the contact hole feature is formed in these steps. Figures 9A to 9C In the example, an upper contact hole is formed. Therefore, the first layer L1 includes first target features of multiple target units, and the second layer L2 includes second target features of multiple target units.

[0059] Then, for example, using a scanning electron microscope, the target unit S5 is measured. Ideally, all target units are imaged in a single image generated by the measurement tool. Based on the measurement results, any edge placement error (EPE) is detected and characterized, for example, by detecting the presence and / or location of edges in the target unit(s) images, or by considering the symmetry of processed (e.g., cropped, rotated, and / or reflected) images and normal images of different target units. In the event of an edge placement error exceeding the budget, appropriate process corrections are determined in S7, and the appropriate process corrections are fed back to the exposure and development / process steps S1-S4.

[0060] Therefore, it can be seen that the techniques disclosed herein can provide self-calibration targets, for example, for detecting edge placement errors using scanning electron microscopy or scattering-based measurement tools. These self-calibration targets can provide higher accuracy and avoid the need for reference tools.

[0061] The techniques disclosed in this paper enable the extraction of multiple EPE parameters in a single measurement step, which improves processing cycle time.

[0062] The techniques disclosed in this paper can reduce the need for very high voltage SEM, thus making the measurement less destructive.

[0063] The techniques disclosed in this article can reduce the complexity of the SEM process.

[0064] Voltage comparison methods require a metal that can be used to measure EPE, while the technique disclosed in this paper does not require a metal that can be used to measure EPE, thus increasing flexibility.

[0065] The techniques disclosed herein can be used in online measurements of control loops and wafer placement.

[0066] The techniques disclosed in this article can be applied in particular to:

[0067] 1D and 2D patterns in FEOL (front-end production line), MOL (middle production line), and BEOL (back-end production line).

[0068] ·Block layers in BEOL

[0069] • Photolithography Etching - Photolithography Etching (LELE)

[0070] Although specific techniques have been described above, it should be understood that this disclosure can be practiced in ways other than those described.

[0071] The embodiments may include a computer program containing one or more machine-readable instruction sequences configured to instruct as follows: Figure 1The various devices depicted perform measurement and optimization steps and control the subsequent exposure process as described above. For example, the computer program can... Figure 1 The computer program is executed within a control unit (LACU) or a supervisory control system (SCS), or a combination of both. A data storage medium (e.g., semiconductor memory, magnetic disk, or optical disk) in which such a computer program is stored may also be provided.

[0072] While specific references to optical lithography may have been made above, it should be understood that the techniques disclosed herein can be used in other applications such as imprint lithography. In imprint lithography, the morphology within the patterning apparatus defines the pattern produced on the substrate. The morphology of the patterning apparatus can be pressed into a resist layer supplied to the substrate, and then the resist is cured by applying electromagnetic radiation, heat, pressure, or a combination thereof. After the resist has cured, the patterning apparatus is removed from the resist, leaving the pattern therein.

[0073] As used herein, the terms “radiation” and “beam” encompass all types of electromagnetic radiation, including ultraviolet (UV) radiation (e.g., wavelengths of approximately 365, 355, 248, 193, 157, or 126 nm) and extreme ultraviolet (EUV) radiation (e.g., wavelengths in the range of 1–100 nm), as well as particle beams such as ion beams or electron beams. The implementation of scatterometers and other inspection devices can be performed using suitable sources at UV and EUV wavelengths, and this disclosure is by no means limited to systems using IR and visible radiation.

[0074] Where the context permits, the term "lens" can refer to any one or a combination of various types of optical elements, including refractive, reflective, magnetic, electromagnetic, and electrostatic optical elements. Reflective components are likely to be used in devices operating in the UV and / or EUV range.

[0075] As used herein, unless otherwise expressly stated, the term "or" covers all possible combinations unless impractical. For example, if a component is declared to include A or B, then unless otherwise expressly stated or impractical, the component may include A, or B, or A and B. As a second example, if a component is declared to include A, B, or C, then unless otherwise expressly stated or impractical, the component may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0076] The various aspects of this disclosure are set forth in the following numbered clauses:

[0077] 1. A measurement method, comprising:

[0078] A first exposure is performed on a substrate to form a first patterning layer comprising a plurality of first target units, each first target unit comprising a first target feature;

[0079] A second exposure is performed on the substrate to form a second patterned layer, the second patterned layer including a plurality of second target units overlaid with corresponding first target units, each second target unit having a second target feature, wherein the second target units among the plurality of second target units have second target features positioned with different offsets relative to a reference position;

[0080] Imaging the second target unit engraved on the first target unit; and

[0081] The edge placement error is determined based on the position of the edge of the second target feature in the second target unit relative to the edge of the first target feature in the first target unit below.

[0082] 2. The method according to Clause 1, wherein imaging is performed using a scanning electron microscope.

[0083] 3. The method according to Clause 1 or 2, wherein different offsets vary within the range of the distance between the nominal position of the edge of the first target feature and the nominal position of the edge of the second target feature, which is greater than or equal to that between the two sides.

[0084] 4. The method according to any one of the preceding clauses, wherein the second target unit comprises at least a pair of second target units, and the corresponding second target features in the at least pair of second target units have opposite offsets.

[0085] 5. The method according to any one of the preceding clauses, wherein the offset of the second target feature in the second target unit is oriented in one direction.

[0086] 6. The method according to any one of clauses 1 to 4, wherein the offset of the second target feature in the second target unit includes an offset oriented in more than one direction.

[0087] 7. The method according to any one of the preceding clauses, wherein there are at least 5, at least 7, or at least 9 first target units and second target units.

[0088] 8. The method according to any one of the preceding clauses, wherein imaging obtains a single image of a plurality of second target units overlaid on a first target unit.

[0089] 9. The method according to any one of the preceding clauses, wherein the first patterning layer includes a plurality of first device features; the second patterning layer includes a plurality of second device features; the first target feature corresponds to the first device feature; and the second target feature corresponds to the second device feature.

[0090] 10. The method according to Clause 9, wherein the position of the second target feature relative to the first target feature is different from the position of the second device feature relative to the first device feature.

[0091] 11. The method according to any one of the preceding clauses, wherein the first target unit and the second target unit are configured such that the magnitude of the position error can be determined by detecting a predetermined positional relationship in which feature edges exist.

[0092] 12. The method according to any one of the preceding clauses, wherein the first device feature and the second device feature are respectively selected from the group consisting of free lines, cut features, block features and holes.

[0093] 13. The method according to any one of Clauses 1 to 12, wherein the first device feature and the second device feature are features of a continuous exposure of a photolithography-etching-photolithography-etching pattern.

[0094] 14. The method according to any one of the preceding clauses, wherein the first and second target units are formed in the lane.

[0095] 15. The method according to any one of the preceding clauses, wherein imaging is performed after the development of the second patterned layer.

[0096] 16. The method according to any one of the preceding clauses, wherein imaging is performed after the pattern transfer step of the second patterned layer.

[0097] 17. A device manufacturing method comprising performing a measurement method according to any one of the preceding clauses; determining a process correction based at least in part on edge placement error; and repeating a first exposure and a second exposure while applying the process correction.

[0098] 18. A mask assembly for use in a photolithography apparatus to form a first patterned layer comprising a plurality of first target units, each first target unit including a first target feature; and a second patterned layer comprising a plurality of second target units overlaid with corresponding first target units, each second target unit having a second target feature, wherein some of the plurality of second target units have second target features positioned with different offsets relative to a reference position.

[0099] 19. The mask set according to Clause 18, wherein different offsets vary within a range of distances greater than or equal to the nominal positions of the edges of the first target feature and the nominal positions of the edges of the second target feature.

[0100] 20. A mask set according to any one of Clauses 18 or 19, wherein the second target unit comprises at least a pair of second target units, and corresponding second target features in the at least pair of second target units have opposite offsets.

[0101] 21. The mask set according to any one of Clauses 18 to 19, wherein a plurality of second target units overlaid on a first target unit are positioned to be captured in a single image.

[0102] 22. The mask set according to any one of Clauses 18 to 21, wherein the first patterning layer includes a plurality of first device features; the second patterning layer includes a plurality of second device features; the first target feature corresponds to the first device feature; and the second target feature corresponds to the second device feature.

[0103] 23. The mask set according to Clause 22, wherein the position of the second target feature relative to the first target feature is different from the position of the second device feature relative to the first device feature.

[0104] 24. The mask group according to any one of clauses 18 to 23, wherein the first device feature and the second device feature are selected from the group consisting of free lines, cut features, block features and holes, respectively.

[0105] 25. The mask set according to any one of Clauses 18 to 23, wherein the first device feature and the second device feature are features of a continuous exposure of a photolithography-etching-photolithography-etching pattern.

[0106] 26. The mask assembly according to any one of clauses 18 to 25, wherein the first target unit and the second target unit are formed in the scribe line.

[0107] 27. The mask set according to any one of clauses 18 to 26, wherein the first target unit and the second target unit are configured such that the magnitude of the positional error can be determined by detecting a predetermined positional relationship in which a feature edge exists.

[0108] 28. A substrate having: a first patterned layer including a plurality of first target units, each first target unit including a first target feature; and a second patterned layer including a plurality of second target units overlaid with corresponding first target units, each second target unit having a second target feature, wherein the second target units among the second target units have second target features positioned with different offsets relative to a reference position.

[0109] 29. The substrate according to Clause 28, wherein the first and second target units are configured such that the magnitude of the positional error can be determined by detecting a predetermined positional relationship in which a feature edge exists.

[0110] 30. A computer program including code components that, when executed by a supervisory control system, instruct one or more lithography tools to perform the method according to any one of clauses 1 to 17.

[0111] 31. An inspection method, comprising:

[0112] Imaging a target formed on a substrate, the target comprising a plurality of first target units formed in a first patterned layer and a plurality of second target units formed in a second patterned layer, the plurality of second target units being overlaid with corresponding first target units, each first target unit including a first target feature, each second target unit having a second target feature, wherein some of the plurality of second target units have second target features positioned with different offsets relative to a reference position; and

[0113] The edge placement error is determined based on the position of the edge of the second target feature in the second target unit relative to the edge of the first target feature in the first target unit below.

[0114] 32. An inspection tool, comprising:

[0115] An imaging system is configured to image a target formed on a substrate, the target comprising a plurality of first target units formed in a first patterned layer and a plurality of second target units formed in a second patterned layer and overlaid with corresponding first target units, each first target unit including a first target feature, each second target unit having a second target feature, wherein the second target units among the second target units have second target features positioned with different offsets relative to a reference position; and

[0116] The image analysis system is configured to determine edge placement based on the position of the edge of the second target feature in the second target unit relative to the edge of the first target feature of the underlying first target unit.

[0117] 33. The inspection tool according to Clause 32, wherein the image analysis system is configured to determine the magnitude of the positional error by detecting a predetermined positional relationship of feature edges in which target unit exists.

[0118] 34. The inspection tool as described in clause 32 or 33, wherein the imaging system includes a scanning electron microscope.

[0119] 35. The inspection tool according to clauses 32, 33 or 34, wherein the imaging system is configured to image the target, wherein different offsets vary within a range of distances greater than or equal to the nominal position of the edge of a first target feature and the nominal position of the edge of a second target feature.

[0120] 36. An inspection tool according to any one of clauses 32 to 35, wherein the imaging system is configured to image a target, wherein the second target unit comprises at least a pair of second target units, and corresponding second target features in the at least pair of second target units have opposite offsets.

[0121] 37. An inspection tool according to any one of clauses 32 to 36, wherein the imaging system is configured to image a target, wherein the offset of a second target feature in a second target unit is oriented in one direction.

[0122] 38. An inspection tool according to any one of clauses 32 to 37, wherein the imaging system is configured to image a target, wherein the offset of a second target feature in a second target unit includes an offset oriented in more than one direction.

[0123] 39. An inspection tool according to any one of clauses 32 to 38, wherein the imaging system is configured to image a target, wherein there are at least 5, at least 7, or at least 9 first target units and second target units.

[0124] 40. An inspection tool according to any one of clauses 32 to 39, wherein the imaging system is configured to obtain a single image of a plurality of second target units overlaid on a first target unit.

[0125] 41. An inspection tool according to any one of clauses 32 to 40, wherein the imaging system is configured to image a target, wherein a first patterning layer includes a plurality of first device features; a second patterning layer includes a plurality of second device features; a first target feature corresponds to a first device feature; and a second target feature corresponds to a second device feature.

[0126] 42. The inspection tool according to Clause 41, wherein the imaging system is configured to image a target, wherein the position of the second target feature relative to the first target feature is different from the position of the second device feature relative to the first device feature.

[0127] 43. An inspection tool according to any one of clauses 32 to 42, wherein the imaging system is configured to image a target, wherein the first device feature and the second device feature are selected from the group consisting of free lines, cutting features, block features and holes, respectively.

[0128] 44. An inspection tool according to any one of clauses 32 to 42, wherein the imaging system is configured to image a target, wherein the first device feature and the second device feature are features of a continuous exposure of a photolithography-etching-photolithography-etching pattern.

[0129] 45. An inspection tool according to any one of clauses 32 to 44, wherein the imaging system is configured to image a target formed in a scribbling path.

[0130] 46. ​​An inspection tool according to any one of clauses 32 to 45, wherein the imaging system is configured to perform imaging after the development of the second patterned layer.

[0131] The breadth and scope of the technology disclosed herein should not be limited by any of the exemplary embodiments described above, but should be defined solely by the following claims and their equivalents.

Claims

1. An inspection tool, comprising: An imaging system configured to image a target formed on a substrate, the target including a plurality of first target units formed in a first patterned layer and a plurality of second target units formed in a second patterned layer, the plurality of second target units being overlaid with corresponding first target units, each first target unit including a first target feature, each second target unit having a second target feature, wherein some of the plurality of second target units have second target features positioned with different offsets relative to a reference position; and An image analysis system configured to determine edge placement based on the position of the edge of a second target feature in a second target unit relative to the edge of a first target feature in a lower first target unit and based on the symmetry between a first part of the target and a second part of the target.

2. The inspection tool according to claim 1, wherein the image analysis system is configured to determine the magnitude of the positional error by detecting a predetermined positional relationship of feature edges in which target unit.

3. The inspection tool according to claim 1, wherein the imaging system comprises a scanning electron microscope.

4. The inspection tool of claim 1, wherein the imaging system is configured to image a target, wherein the different offsets vary within a range of a distance greater than or equal to the nominal position of the edge of the first target feature and the nominal position of the edge of the second target feature.

5. The inspection tool of claim 1, wherein the imaging system is configured to image a target, wherein the second target unit comprises at least a pair of second target units, and corresponding second target features in the at least pair of second target units have opposite offsets.

6. The inspection tool of claim 1, wherein the imaging system is configured to image a target, and the offset of the second target feature in the second target unit is oriented in one direction.

7. The inspection tool of claim 1, wherein the imaging system is configured to image a target, and wherein the offset of the second target feature in the second target unit includes an offset oriented in more than one direction.

8. The inspection tool of claim 1, wherein the imaging system is configured to image a target, wherein at least five first target units and second target units are present.

9. The inspection tool of claim 8, wherein the imaging system is configured to image a target, wherein at least seven first target units and second target units are present.

10. The inspection tool of claim 9, wherein the imaging system is configured to image a target, wherein at least nine first target units and second target units are present.

11. The inspection tool of claim 1, wherein the imaging system is configured to obtain a single image of a plurality of second target units overlaid on the first target unit.

12. The inspection tool of claim 1, wherein the imaging system is configured to image a target, wherein the first patterning layer includes a plurality of first device features; the second patterning layer includes a plurality of second device features; the first target feature corresponds to the first device feature; and the second target feature corresponds to the second device feature.

13. The inspection tool of claim 12, wherein the imaging system is configured to image a target, wherein the position of the second target feature relative to the first target feature is different from the position of the second device feature relative to the first device feature.

14. The inspection tool of claim 12, wherein the imaging system is configured to image a target, wherein the first device feature and the second device feature are selected from the group consisting of free lines, cut features, block features and holes, respectively.

15. The inspection tool of claim 12, wherein the imaging system is configured to image a target, wherein the first device feature and the second device feature are features of a continuous exposure of a photolithography-etching-photolithography-etching pattern.

16. The inspection tool of claim 1, wherein the imaging system is configured to image a target formed in a scribing pattern.

17. A non-transitory computer-readable medium storing a set of instructions executable by one or more processors of an inspection tool to cause the inspection tool to perform methods comprising: A first exposure is performed on a substrate to form a first patterning layer comprising a plurality of first target units, each first target unit comprising a first target feature; A second exposure is performed on the substrate to form a second patterned layer, the second patterned layer including a plurality of second target units overlaid with corresponding first target units, each second target unit having a second target feature, wherein some of the plurality of second target units have second target features positioned with different offsets relative to a reference position; Image the second target unit that is overlaid on the first target unit; as well as The edge placement error is determined based on the position of the edge of the second target feature in the second target unit relative to the edge of the first target feature in the first target unit below, and based on the symmetry between the first part of the target including the plurality of first target units and the plurality of second target units and the second part of the target.

18. The computer-readable medium of claim 17, wherein imaging is performed using a scanning electron microscope.

19. The computer-readable medium of claim 17, wherein the different offsets vary within a range of distances greater than or equal to the nominal position of the edge of the first target feature and the nominal position of the edge of the second target feature.

20. The computer-readable medium of claim 17, wherein the second target unit comprises at least a pair of second target units, and corresponding second target features in the at least pair of second target units have opposite offsets.

21. The computer-readable medium of claim 17, wherein the offset of the second target feature in the second target unit is oriented in one direction.

22. The computer-readable medium of claim 17, wherein the offset of the second target feature in the second target unit includes an offset oriented in more than one direction.

Images