Cold electron erase in thin film memory transistor

Abstract

A memory transistor has a tunneling dielectric layer and a charge trapping layer between a channel region and a gate electrode, wherein the charge trapping layer has a conduction band step below a low point of a tunneling barrier in the tunneling dielectric layer such that electrons tunnel directly into the charge trapping layer when a write voltage is applied. The conduction band step of the charge trapping layer is between -1.0 electron volts and 2.3 electron volts. The memory transistor can include a barrier layer between the tunneling dielectric layer and the charge trapping layer, the barrier layer having a conduction band step that is less than the conduction band step of the charge trapping layer.

Description

TECHNICAL FIELD

[0001] The present invention relates to a write and erase system in a thin film memory transistor. In particular, the present invention utilizes cold electron erase in a thin film transistor for fast write and erase operation, and also provides the added advantage of high endurance. BACKGROUND

[0002] U.S. Publication Patent No. 2019 / 0006015 ("Halali"), entitled "Capacitive-coupled non-volatile thin film transistor strings in three-dimensional arrays," published on January 3, 2019, discloses thin film memory transistors that form a NOR memory string. The thin film memory transistors of Halali can be written and erased in 100 nanoseconds (ns) or less, making them suitable for a variety of applications of typical volatile memory devices, such as dynamic random access memory (DRAM) devices. The thin film memory transistors of Halali also have the advantage of several minutes of retention time, compared to the few milliseconds of typical conventional DRAM devices. Thus, the thin film memory transistors of Halali can also be considered as quasi-volatile memory transistors. In many applications, such quasi-volatile memory transistors are preferably to have high endurance (e.g., in the range of 1011 cycles) and are preferably to be written or erased using a voltage of about 8-9 volts or less.

[0003] Fast write and fast erase operation requires relatively high current through the gate stack of the memory transistor. Figure 1 A band diagram for a portion of a memory transistor, including various sub-layers of dielectric material and stored charge between a channel region and a gate electrode. Figure 1 As shown, the various materials 120 between the channel region 110 and the gate electrode 114 allow data to be stored in the memory transistor. These materials include a tunneling dielectric sub-layer 111, a charge trapping sub-layer 112 (e.g., silicon nitride), and a blocking dielectric sub-layer 113 (e.g., silicon oxide). The charge trapping sub-layer 112 and the blocking dielectric sub-layer 113 can each be, for example, 4 nanometers thick. The tunneling dielectric sub-layer 111 can be, for example, 2 nanometers thick. Figure 1 In the middle, line 101 depicts the lowest energy state in the conduction bands of the various materials, and line 102 depicts the highest energy state in the valence bands of the various materials. In such a system, to change the threshold voltage of the memory transistor by 1 volt in 100 nanoseconds, approximately 5.0 amps per square centimeter (5.0 amps / cm2) of current is required. 2). Using silicon dioxide as the tunneling dielectric sublayer 111, high current densities can be achieved at moderate electric fields in the range of 10.0 MV / cm by a direct tunneling mechanism.

[0004] Figure 2 Typical direct tunneling current densities (gate current) for various thicknesses of silicon dioxide for different bias conditions. As shown in Figure 2 Figure 2, even at voltages through the silicon dioxide layer lower than 1.5 volts, high current densities (e.g., 5.0 amps / cm 2 ) can be achieved for silicon dioxide thicknesses less than 1.5 nanometers.

[0005] Figures 3(a) and 3(b) depict the direct tunneling of electrons into and out of the charge-trapping sublayer 112 during write and erase operations, respectively. As shown in Figure 3(a), the application of a write voltage through the gate electrode 114 and the channel region 110 lowers the conduction band of the tunneling dielectric sublayer 111, the charge-trapping sublayer 112, and the blocking dielectric sublayer 113 relative to the channel region 110. In particular, the lowest energy level in the conduction band of the charge-trapping sublayer 112 is slightly lower than the lowest energy level in the conduction band of the channel region 110, so that an electron having energy at the lowest energy level in the conduction band of the channel region 110 tunnels directly into the charge-trapping sublayer 112, as shown by arrow 301 in Figure 3(a).

[0006] Likewise, as shown in Figure 3(b), the application of an erase voltage through the gate electrode 114 and the channel region 110 raises the lowest energy level in the conduction band of the tunneling dielectric sublayer 111, the charge-trapping sublayer 112, and the blocking dielectric sublayer 113 relative to the channel region 110. The electric field imparts energy to an electron in the charge-trapping site in the charge-trapping sublayer 112 at the allowed energy level to tunnel directly into the channel region 110, as shown by arrow 302 in Figure 3(b).

[0007] The direct tunneling mechanism of electrons as depicted in Figures 3(a) and 3(b) enables fast write and erase. In contrast, erase by holes is a slow mechanism. In a floating-substrate quasi-volatile memory cell (e.g., the thin-film memory transistor of Halai), for example, holes in the channel region 110 are not sufficient to provide a proper hole current into the charge-trapping sublayer 112; likewise, the erase mechanism of such a memory transistor pulls electrons out of the charge-trapping sublayer 112.

[0008] In a memory transistor, the voltage difference between the threshold voltage of the memory transistor in the erased state and the programmed state is called the "programming window." The programming window shrinks or closes as the number of program-erase cycles to which the memory transistor is subjected increases. This shrinkage of the programming window is due to, for example, interface state formation that causes interface deterioration between the channel region 110 and the tunneling dielectric 111. The shrinkage of the programming window can also be due to charge trapping at other material interfaces, for example, between the charge-trapping sublayer 112 and the blocking dielectric sublayer 113. The endurance of a memory transistor refers to the number of program-erase cycles before which an acceptable programming window cannot be maintained. As shown in Figure 3(a), electrons that tunnel directly from the channel region 110 to the charge-trapping sublayer 112 have low energy to enter the charge-trapping sublayer 112, and thus they only lose a small fraction of their energy at the lowest allowed energy state in the charge-trapping sublayer 112. (That is, the lowest energy level in the conduction band of the channel region 110 and the charge-trapping sublayer 112 is very close in the presence of the programming voltage.) This energy loss does not cause any significant harm to the charge-trapping sublayer 112. In contrast, as depicted in Figure 3(b), the energy loss by the electrons entering the channel region 110 during an erase operation is significantly greater. The large energy loss creates energetic holes, "hot holes," in the channel region 110 that are driven by the electric field of the erase voltage toward the gate electrode 114. These hot holes create interface traps at the interface between the channel region 110 and the tunneling dielectric sublayer 111. These interface traps are detrimental to the endurance of the memory transistor and, in fact, can be the primary cause of closing the programming window. Those skilled in the art can also know that the hot hole phenomenon, known as the "anodic hot hole injection mechanism," provides a model for dielectric breakdown.

[0009] Figure 4 The evolution of the programming window in a memory transistor beyond 109 program and erase cycles is depicted, which illustrates the programmed state threshold voltage 401 and the erased state threshold voltage 402. SUMMARY

[0010] According to one embodiment of the present application, a memory transistor has a tunneling dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-trapping layer has a conduction band step (relative to an n-type silicon conduction band) that is lower than the bottom of a tunneling barrier in the tunneling dielectric layer, such that electrons tunnel directly into the charge-trapping layer when a write voltage is applied. The conduction band step of the charge-trapping layer is selected from a value between -1.0 electron volts and 2.3 electron volts. In some embodiments, the charge-trapping layer comprises one or more of hafnium oxide (HfO2), yttrium oxide (Y2O3), silicon nitride (Si3N4), zirconium dioxide (ZrO2), zirconium silicate (ZrSiO4), lanthanum oxide (La2O3), tantalum pentoxide (Ta2O5), cerium dioxide (CeO2), titanium dioxide (TiO2), strontium titanate (SrTiO3), other semiconductors, and metal nanodots (e.g., silicon, ruthenium, platinum, and cobalt nanodots).

[0011] According to one embodiment of the present application, the memory transistor can further comprise a barrier layer between the tunneling dielectric layer and the charge-trapping layer, the barrier layer having a conduction band step that is less than the conduction band step of the charge-trapping layer. The barrier layer can also comprise a material having a conduction band step between -1.00 electron volts and 2.3 electron volts, preferably between -1.00 electron volts and 1.5 electron volts, such as one or more of hafnium oxide (HfO2), yttrium oxide (Y2O3), silicon nitride (Si3N4), zirconium dioxide (ZrO2), zirconium silicate (ZrSiO4), tantalum pentoxide (Ta2O5), cerium dioxide (CeO2), titanium dioxide (TiO2), strontium titanate (SrTiO3), other semiconductors, and metal nanodots (e.g., silicon, ruthenium, platinum, and cobalt nanodots).

[0012] In one embodiment, when a voltage substantially less than the write voltage is applied between the channel region and the gate electrode, electrons tunnel into the charge-trapping layer through a barrier (energy barrier) that is wider than the thickness of the tunneling dielectric layer by Fowler-Nordheim tunneling.

[0013] In one embodiment, the tunneling dielectric layer can be as thin as 5-40 Angstroms and can be formed from silicon oxide (e.g., SiO2) or silicon nitride (SiN). Silicon oxide tunnel dielectric layers can be formed using conventional oxidation techniques (e.g., high temperature oxidation), chemical synthesis (e.g., atomic layer deposition (ALD)), or any suitable combination of the foregoing. An active oxygen (O2) process can include ozone for precise control of thickness and improved oxide quality (e.g., reduced leakage due to defect sites). Silicon nitride tunnel dielectric layers can be formed using conventional nitridation, direct synthesis, chemical synthesis (e.g., atomic layer deposition (ALD)), or any suitable combination of the foregoing. Plasma processes can be used for precise control of thickness and improved dielectric quality (e.g., reduced leakage due to defect sites).

[0014] The tunnel dielectric layer can also include an additional thin layer of aluminum oxide (Al2O3) (e.g., 1-5 A) or less. The aluminum oxide layer in the tunnel dielectric layer can be synthesized in an amorphous phase to reduce leakage due to defect sites.

[0015] A more complete understanding of the present application can be had by reference to the following detailed description when taken in connection with the accompanying drawings, wherein: BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 A band diagram for a typical memory transistor including various sublayers of dielectric material and stored charge between a channel region and a gate electrode.

[0017] Figure 2 Typical direct tunneling current densities (gate current) for various thicknesses of silicon dioxide under different bias conditions.

[0018] FIGS. 3(a) and 3(b) depict direct tunneling of electrons into and out of the charge-trapping sublayer 112 during write and erase operations, respectively.

[0019] Figure 4 An evolution plot for a write window of more than 109 write and erase cycles in a memory transistor depicting a write state threshold voltage 401 and an erase state threshold voltage 402.

[0020] Figure 5 A band diagram for an exemplary memory transistor including a conduction band edge 511 and a valence band edge 512 having a substrate 501, a tunnel dielectric layer 502, and a charge-trapping layer 503.

[0021] Figures 6(a)-6(c) ​These are (i) the lowest energy level of the conduction band of the substrate 501, the tunneling dielectric layer 502 and the charge trapping layer 503 in the storage transistor; (ii) the lowest energy level of the conduction band of the aforementioned layers in the storage transistor when no voltage is applied; and (iii) the electron energy shift 515 between the substrate 501 and the charge trapping layer 503 when an erase voltage is applied.

[0022] Figures 7(a)-7(c) These are (i) the relative conduction band offsets of the substrate 601, tunneling dielectric layer 602, barrier layer 603 with a low conduction band step, and charge trapping layer 604 of the storage transistor; (ii) the energy band diagram of the aforementioned layers in the storage transistor without an applied voltage; and (iii) the electron energy offset 615 between the substrate 601 and the charge trapping layer 604 when an erase voltage is applied.

[0023] Figures 8(a)-8(c) Depicting Figures 7(a)-7(c) Conductor step parameters of dielectric layers 602-604.

[0024] Figure 9(a) shows direct tunneling in the memory transistor of Figure 7(a), and Figures 9(b) and 9(c) respectively show... Figures 7(b)-7(c) MFN tunneling in the storage transistor.

[0025] Figures 10(a) and 10(b) are energy band diagrams of the structure during write and erase operations based on a one-volt voltage drop across the tunneling dielectric layer 602 (i.e., b = 1 eV during a write operation and b' = 1 eV during an erase operation).

[0026] Figures 11(a)-11(d) These are various simulation results of the storage transistors in this invention.

[0027] Figure 12(a) is an energy band diagram of the conduction band of the gate stack in a storage transistor during an erase operation.

[0028] Figure 12(b) is an energy band diagram of the conduction band of the gate stack in a storage transistor during an erase operation. According to an embodiment of the invention, the storage transistor has an additional high-k dielectric layer 607 (e.g., an aluminum oxide layer) in the barrier dielectric layer 610. Detailed Implementation

[0029] This invention utilizes a device structure to ensure that electrons tunnel through a charge trapping layer into the channel region of the storage transistor within a desired low energy range (referred to as "cold electrons") (e.g., during an erase operation). This ensures that the final hole generation is also low-energy, thus reducing damage to the write window and improving the durability of the storage transistor, exceeding 10. 11 One write-erase cycle. The device architecture provides a large direct tunneling write current density, exceeding 1.0 amps / cm².2 (e.g. 5.0 amps / cm 2 The present invention is particularly advantageous for use in forming a memory layer of thin film memory transistors in a three dimensional memory structure, such as the quasi-volatile memory transistors disclosed by Harari in the above-mentioned reference in a three dimensional array of NOR gate memory strings.

[0030] An embodiment of the present invention is depicted by the model of Figure 5 Fig. 5, which shows the conduction band edge 511 and the valence band edge 512 of an exemplary memory transistor, having a substrate 501, a tunneling dielectric layer 502 and a charge trapping layer 503. As shown in Fig. 5, the arrow 514 represents an electron tunneling directly from the charge trapping layer 503 to the substrate 501. The energy difference between the lowest energy level in the conduction band of the charge trapping layer 503 and the lowest energy level in the conduction band of the substrate 501 ("conduction band offset"), as indicated by the symbol 515, is the energy loss expected for an electron tunneling. Figure 5

[0031] The present invention achieves the required conduction band offset in the layers relative to the semiconductor substrate (i.e. channel region) of the memory transistor by carefully selecting a combination of a tunneling dielectric material and a charge trapping dielectric material. Fig. 6(a) is a graph of the lowest energy level in the conduction band of the substrate 501, the tunneling dielectric layer 502 and the charge trapping layer 503 in a memory transistor. Fig. 6(b) is a graph of the lowest energy level in the conduction band of the aforementioned layers in a memory transistor without an applied voltage. Fig. 6(c) is a graph of the electron energy shift 515 between the substrate 501 and the charge trapping layer 503 when an erase voltage is applied. The electron energy shift 515 depends on the conduction band offset between each of the substrate 501 and the tunneling dielectric layer 502 and the charge trapping layer 503, as well as on the voltage applied for the erase operation. As shown in Fig. 6(c), using a different charge trapping material for the charge trapping layer 503 has a different conduction band offset relative to the substrate 501 for the tunneling dielectric layer 502, resulting in a greater or lesser energy loss for the tunneling electron to reach the substrate 501. Similarly, using a different tunneling dielectric material for the tunneling dielectric layer 502 has a different conduction band offset relative to the substrate 501 for the charge trapping layer 503, also resulting in a greater or lesser energy loss for the tunneling electron to reach the substrate 501.

[0032] The tunneling dielectric layer 502 can be as thin as 5-40 Angstroms ​and can be formed from silicon oxide (e.g., SiO2), silicon nitride (SiN), or silicon oxynitride (SiON). The silicon oxide tunnel dielectric layer can be formed using conventional oxidation techniques (e.g., high temperature oxidation), chemical synthesis (e.g., atomic layer deposition (ALD)), or any suitable combination of the foregoing. An active oxygen (O2) process can include an ozone step (e.g., using pulsed ozone) for precise control of thickness and improved oxide quality (e.g., reduced leakage due to defect sites). The ozone step enhances the oxide cure in a conformal manner, which is particularly advantageous for three-dimensional transistor structures. An anneal step (e.g., a hydrogen (H2) anneal, an ammonia (NH3) anneal, or a rapid thermal anneal) can also strengthen the tunnel dielectric layer 502. The silicon nitride tunnel dielectric layer can be formed using conventional nitridation, direct synthesis, chemical synthesis (e.g., atomic layer deposition (ALD)), or any suitable combination of the foregoing. A plasma process can be used for precise control of thickness and improved dielectric quality (e.g., reduced leakage due to defect sites).

[0033] The tunnel dielectric layer 502 can also include an additional thin layer of aluminum oxide (AI2O3) (e.g., 1-5 A) or thinner. The additional aluminum oxide layer in the tunnel dielectric layer can be synthesized in an amorphous phase to reduce leakage due to defect sites.

[0034] The following materials can be used to provide the tunnel dielectric layer 502 and the charge trapping layer 503:

[0035]

[0036]

[0037] The use of a low conduction band step in the charge trapping layer is effective to increase the tunnel barrier in the tunnel dielectric layer, thereby improving data retention.

[0038] Alternatively, a barrier material of the low conduction band step can be introduced between the tunnel dielectric layer and the charge trapping layer in the memory transistor. Figures 7(a)-7(c) The band diagram for this structure is shown in FIG. 7. FIG. 7(a) shows the relative conduction band offsets of the substrate 601, the tunnel dielectric layer 602, the barrier layer 603 of the low conduction band step, and the charge trapping layer 604 in the memory transistor. FIG. 7(b) shows the band diagram of the foregoing layers in the memory transistor without an applied voltage. FIG. 7(c) shows the electron energy offset 615 between the substrate 601 and the charge trapping layer 604 when a erase voltage is applied. The electron energy offset 615 depends on the conduction band step between the substrate 601 and each of the tunnel dielectric layer 602, the barrier layer 603 of the low conduction band step, and the charge trapping layer 604, as well as the voltage applied for the erase operation. As shown in FIG. 7(c), the electron energy offset 615 is greater than the conduction band step of the barrier layer 603 of the low conduction band step. This results in a lower tunnel barrier in the tunnel dielectric layer 602, which improves data retention. Figures 7(a)-7(c) ​As shown, the barrier layer 603 with a low conduction band offset (LCBO) preferably has a conduction step that is smaller than that of the tunneling dielectric layer 602 and the charge trapping layer 604 with respect to the substrate 601. By carefully selecting the materials of the tunneling dielectric layer 602, the barrier layer 603 with a low conduction band offset, and the charge trapping layer 604, direct cold electron tunneling can be achieved during both write and erase operations, enabling the storage transistor to have high endurance.

[0039] Figures 8(a)-8(c) depicts Figures 7(a)-7(c) the conduction band step parameters of the dielectric layers 602 - 604. As shown in Fig. 8(a), (i) parameter B represents the conduction step of the tunneling dielectric layer 602 with respect to the substrate 601, (ii) parameter a represents the conduction band step of the LCBO barrier layer 603 with respect to the conduction band step of the tunneling dielectric layer 602, (iii) parameter d represents the conduction step of the LCBO barrier layer 603 with respect to the substrate 601, and (iv) parameter c represents the conduction step of the charge trapping layer 604 with respect to the substrate 601. According to an embodiment of the present invention, the conduction step of the LCBO barrier layer 603 should not be greater than the conduction step of the charge trapping layer 604 (i.e., d ≤ c), such that a large direct tunneling write current density exceeds 1.0 amps / cm 2 (e.g., 5.0 amps / cm 2 ).

[0040] Fig. 8(b) shows the energy levels that are inclined at the bottom of the conduction band of the tunneling dielectric layer 602 due to the write voltage. Through the thickness of the tunneling dielectric layer 602, the sloping reduces the energy level of the tunneling dielectric layer 602 by parameter b. To achieve the write operation through direct tunneling, parameter b should be greater than or equal to the value of parameter c (i.e., b ≥ c). The value of parameter b (in electron volts eV) is the product of the voltage drop across the tunneling dielectric layer 602 and the charge q (i.e., 1.6 × 10 -19 Coulomb).

[0041] When the voltage drop of the tunneling dielectric layer 602 is less than the conduction step of the charge trapping layer 604 (i.e., b < c), the tunneling barrier becomes wider because at least a portion of the LCBO barrier layer 603 maintains a tunneling barrier. In that case, direct tunneling can be replaced by the modified Fowler - Nordheim (MFN) mechanism to provide a current that is much smaller than that of direct tunneling (e.g., less than 0.1 amps / cm 2 ).

[0042] In Figures 7(a)-7(c)Figure 9(a) is direct tunneling under a write voltage, Figure 9(b) and Figure 9(c) are MFN tunneling under a low voltage (mid voltage) and a lower voltage, respectively. It is recognized that during operation of the memory transistor, MFN tunneling can occur in the region of low voltage perturbation. However, for the memory transistor of the depicted structure, such MFN tunneling current can be very low under the range of applied voltages. The materials and thicknesses of the charge trapping layer 604 and the barrier layer 603 are chosen such that the read disturb voltages, the programming inhibit voltages, or the erase inhibit voltages fall within the range of low or mid voltages that limit tunneling to the MFN mechanism. Figures 7(a)-7(c)

[0043] Thus, the memory transistor of the present application has the important advantage of having high current due to direct tunneling under a write voltage, while having only low MFN tunneling current when under a low voltage. This characteristic reduces the perturbation under read, programming inhibit, or erase inhibit operations, and improves data retention and endurance, particularly for the quasi-volatile memory transistor of the present application that utilizes direct tunneling for fast programming and erase operations. In this regard, since the holes generated in the channel region are of low energy, the LCBO barrier layer 603 improves endurance by allowing cold electron erase operation, reducing device degradation.

[0044] Since read disturb, programming inhibit disturb, or erase inhibit disturb all occur under a low voltage, the LCBO barrier layer 603 also improves data retention and endurance, as well as reducing read disturb, programming inhibit disturb, or erase inhibit disturb, by limiting tunneling to MFN tunneling under a low voltage. For example, programming inhibit disturb or erase inhibit disturb occurs under a half-select or a voltage lower than that used for programming and erase operations, respectively. All advantages are realized when the memory transistor is biased at a low voltage, while at the same time maintaining the advantage of high efficiency of direct tunneling when the memory transistor is biased at a higher read, program, or erase voltage.

[0045] ​Figure 8(c) shows the sloping of the conduction band bottom of the tunnel dielectric layer 602 during an erase operation. The sloping raises the energy level of the tunnel dielectric layer 602 by a parameter b' as the electron tunnels through the thickness of the tunnel dielectric layer 602. During the erase operation, an electron tunnels directly from the charge trapping layer 604 to the substrate 601, losing an energy of parameter A, where A = b' + c. Note that the conduction band step of the charge trapping layer 604 should be larger than the difference between the energy level of the charge trapping site and the conduction band of the energy level, so that an electron at the charge trapping site can be included in the direct tunneling current.

[0046] According to one embodiment of the present application, the substrate 601 can be implemented by a P-doped silicon, the tunnel dielectric layer 602 can be implemented by a 1 nm thick silicon dioxide layer (B = 3.15 eV), the low-conductivity step barrier layer 603 can be implemented by a 2 nm thick titanium dioxide layer (d = 0.3 eV), the charge trapping layer 604 can be implemented by a 4 nm thick silicon-rich silicon nitride (i.e., SiN:Si, c = 1.35 eV), and another 4 nm thick silicon dioxide layer can be used as the blocking dielectric layer. Unlike silicon nitride (stoichiometric Si3N4), silicon-rich silicon nitride contains silicon as an impurity, which lowers the bandgap of the silicon nitride from 4.6 eV to about 3.6 eV. In addition, the refractive index of silicon nitride is 2.0, while the refractive index of silicon-rich silicon nitride is in the range of 2.1-2.3. The gate electrode 606 can be implemented by a highly doped P-type polysilicon. Figure 10(a) and 10(b) The energy band diagram of the structure during a write operation (i.e., b = 1 eV) and an erase operation (i.e., b' = 1 eV) based on a one volt voltage drop across the tunnel dielectric layer 602 is shown in Figure 10(b). As shown by arrow 1001 in Figure 10(b), during an erase operation, an electron tunnels directly to the substrate 601, losing about 1.4 eV of energy. The dispersion in the LCBO barrier layer 603, as indicated by arrow 1002, can further reduce this energy loss.

[0047] According to another embodiment of the present application, the substrate 601 can be implemented by a P-doped silicon, the tunnel dielectric layer 602 can be implemented by a 1 nm thick silicon dioxide layer (B = 3.15 eV), the low-conductivity step barrier layer 603 can be implemented by a 2 nm thick cerium dioxide layer (d = 0.6 eV), the charge trapping layer 604 can be implemented by a 4 nm thick silicon-rich silicon nitride (Si3N4:Si, c = 1.35 eV), and another 5 nm thick silicon dioxide layer can be used as the blocking dielectric layer. The gate electrode 606 can be implemented by a highly doped P-type polysilicon.

[0048] Figures 11(a)-11(d) Various simulation results of the memory transistor of the present application.

[0049] Figure 11(a) is a simulation of a memory transistor having a 0.8 nm thick tunneling dielectric of silicon dioxide, a 2.0 nm thick LCBO barrier layer of zirconium dioxide, and a 5 nm thick trapping layer of silicon-rich silicon nitride. Figure 11(a) shows that a direct tunneling current density of over 1.0 amps / cm 2 may be achieved at a write voltage of about 3.1 volts.

[0050] Figure 11(b) is a simulation of a memory transistor having a 1.0 nm thick tunneling dielectric of silicon dioxide, a 2.0 nm thick LCBO barrier layer of cerium dioxide, and a 4.0 nm thick trapping layer of silicon-rich silicon nitride. Figure 11(b) shows that a direct tunneling current density of over 1.0 amps / cm 2 may be achieved at a write voltage of about 1.6 volts.

[0051] Figure 11(c) is a simulation of a memory transistor having a 1.0 nm thick tunneling dielectric of silicon dioxide, a 2.0 nm thick LCBO barrier layer of tantalum pentoxide, and a 4.0 nm thick trapping layer of silicon-rich silicon nitride. Figure 11(c) shows that a direct tunneling current density of over 1.0 amps / cm 2 may be achieved at a write voltage of about 1.8 volts.

[0052] Figure 11(d) is a simulation of a memory transistor having a 1.0 nm thick tunneling dielectric of silicon nitride, a 2.0 nm thick LCBO barrier layer of cerium dioxide, and a 4.0 nm thick trapping layer of silicon-rich silicon nitride. Figure 11(d) shows that a direct tunneling current density of over 1.0 amps / cm 2 may be achieved at a write voltage of about 2.1 volts.

[0053] Figure 12(a) depicts a phenomenon of "reverse injection of electrons" that can occur during an erase operation. Reverse injected electrons can have an adverse effect on endurance. Figure 12(a) is an energy band diagram of a gate stack in a memory transistor during an erase operation. As shown in Figure 12(a), the gate stack includes a substrate 601, a tunneling dielectric layer 602, an LCBO barrier layer 603, a charge trapping layer 604, a blocking dielectric layer 605, and a gate electrode 606. (The blocking dielectric layer 605 can be, for example, silicon dioxide (SiO2)). During an erase operation, a relatively high electric field across the blocking dielectric layer 605 can cause high energy electrons, as indicated by arrow 1201 in Figure 12(a), to tunnel from the gate electrode into the charge trapping layer 604, or even into the tunneling dielectric layer 602. These reverse injected electrons can damage these layers, and have an adverse effect on the endurance of the memory transistor.

[0054] According to one embodiment of the present application, the back injection of electrons can be significantly reduced or substantially eliminated by including a layer of material having a high dielectric constant (high-k material), such as aluminum oxide (AI2O3) in the blocking dielectric layer (e.g., blocking dielectric layer 605 in Figure 10(a)). In this embodiment, the gate electrode can use a high work function metal (e.g., greater than 3.8 eV, preferably not less than 4.0 eV). The high-k material can provide the same required transistor characteristics (e.g., gate capacitance) at a thickness t H An equivalent oxide thickness t EOT is provided as: where κ ox and κ H are the relative dielectric constants of silicon dioxide and the high-k material, respectively. Thus, the high-k material can provide the same required transistor characteristics (e.g., gate capacitance) at a thickness t H that is substantially less than the equivalent thickness t EOT of its silicon dioxide layer counterpart without causing the undesirable leakage of the silicon dioxide layer.

[0055] Figure 12(b) is a band diagram of the conduction band of the gate stack in a storage transistor during an erase operation, according to one embodiment of the present application, in which the storage transistor has an additional high-k dielectric layer 607 (e.g., aluminum oxide layer) in the blocking dielectric layer 610. In Figure 12(b), the blocking dielectric layer 610 includes the high-k dielectric layer 607 (e.g., aluminum oxide layer) and the silicon dioxide layer 608. In a practical aspect, the equivalent oxide thickness of the blocking dielectric layer 610 is substantially the same as the blocking dielectric layer 605 in Figure 12(a). However, since the relative dielectric constant of aluminum oxide is 9.0 and the relative dielectric constant of silicon dioxide is 3.9, the actual combined physical thickness of the high-k dielectric layer 607 (e.g., aluminum oxide layer) and the silicon dioxide 608 in Figure 12(b) is greater than the thickness of the blocking dielectric layer 605 in Figure 12(a). Since the relative dielectric constant of the high-k dielectric layer 607 is greater than the relative dielectric constant of the silicon dioxide layer 608, the electric field in the high-k dielectric layer 607 is lower than the electric field in the silicon dioxide layer 608. The larger combined physical thickness of the blocking dielectric layer 610 in Figure 12(b) (providing a wider tunnel barrier between the gate electrode 606 and the charge trapping layer 604) and the lower electric field at the interface between the gate electrode 606 and the high-k dielectric layer 607 reduces or eliminates back electron injection, resulting in an improved endurance. In conjunction with the high-k dielectric layer 607 (e.g., aluminum oxide), a high work function metal is preferably used as the gate electrode 606. The high work function metal creates a high barrier (as indicated by barrier height 1202 in Figure 12(b)) at the gate electrode-aluminum oxide interface, significantly reducing back electron injection during erase operations. Suitable high work function metals include tungsten (W), tantalum nitride (TaN), and tantalum silicon nitride (TaSiN).

[0056] The above detailed description provides specific examples of the present application, but is not limiting thereof. Various modifications and changes can be made within the scope of the present application. The following claims set forth the scope of the application.

Claims

1. A memory transistor, comprising: a tunneling dielectric layer, a charge trapping layer, and a barrier layer, all located between a channel region and a gate electrode; wherein (i) the barrier layer is located between the tunneling dielectric layer and the charge trapping layer; (ii) the charge trapping layer has a conduction band step below a low point of a tunneling barrier in the tunneling dielectric layer such that electrons tunnel directly into the charge trapping layer when a write voltage is applied; and (iii) the barrier layer has a conduction band step that is less than the conduction band step of the charge trapping layer, wherein the barrier layer comprises a material having a conduction band step between -1.00 electron volts and 1.5 electron volts.

2. The memory transistor of claim 1, wherein the conduction band step of the charge trapping layer is between -1.0 electron volts and 2.3 electron volts.

3. The memory transistor of claim 1, wherein the charge trapping layer comprises a material selected from the group consisting of hafnium oxide (Hf02), yttrium oxide (Y203), zirconium dioxide (Zr02), zirconium silicate (ZrSi04), lanthanum oxide (La203), tantalum pentoxide (Ta205), cerium dioxide (Ce02), titanium dioxide (Ti02), strontium titanate (SrTi03), silicon nanodots, ruthenium nanodots, platinum nanodots, and cobalt nanodots.

4. The memory transistor of claim 1, wherein the conduction band step of the charge trapping layer is greater than an energy difference between a charge trapping point of the charge trapping layer and a conduction band edge of the charge trapping layer.

5. The memory transistor of claim 1, wherein the direct tunneling provides a current in excess of 1.0 ampere (amps / cm2. 2 ) per square centimeter.

6. The memory transistor of claim 1, wherein the tunneling dielectric layer has a thickness to allow write and erase operations to be accomplished primarily through the direct tunneling.

7. The memory transistor of claim 1, wherein the tunneling dielectric layer comprises one or more of silicon oxide, silicon nitride, and silicon oxynitride.

8. The memory transistor of claim 1, wherein the tunneling dielectric layer comprises stoichiometric silicon nitride.

9. The memory transistor of claim 7, wherein the tunneling dielectric layer comprises silicon oxide formed using an ozone step.

10. The memory transistor of claim 7, wherein the tunneling dielectric layer is formed using a pulsed ozone step, a hydrogen (H2) anneal, an ammonia (NH3) anneal, a rapid thermal anneal, or any combination of the foregoing.

11. The memory transistor of claim 7, further comprising an aluminum oxide layer in the tunneling dielectric layer.

12. The memory transistor of claim 11, wherein the aluminum oxide layer has a thickness no greater than 1 nanometer.

13. The memory transistor of claim 1, wherein when a voltage is applied between the channel region and the gate electrode and the voltage is less than the write voltage, electrons tunnel into the charge trapping layer through Fowler-Nordheim tunneling or a modified Fowler-Nordheim tunneling.

14. The memory transistor of claim 13, wherein the applied voltage corresponds to a write inhibit voltage or an erase inhibit voltage, and wherein electrons tunneling into the charge trapping layer provide a current density of less than 0.1 amp per square centimeter.

15. The memory transistor of claim 1 having an average endurance of more than 10 11 write-erase cycles.

16. The memory transistor of claim 1, wherein the barrier layer is selected from a group consisting of hafnium oxide (Hf02), yttrium oxide (Y203), zirconium dioxide (Zr02), zirconium silicate (ZrSi04), tantalum pentoxide (Ta205), cerium dioxide (Ce02), titanium dioxide (Ti02), silicon-rich silicon nitride (SiN:Si), strontium titanate (SrTi03), silicon nanodots, ruthenium nanodots, platinum nanodots, and cobalt nanodots.

17. The memory transistor of claim 13, wherein the tunneling dielectric layer comprises silicon oxide, the barrier layer comprises titanium pentoxide, and the charge trapping layer comprises silicon-rich silicon nitride.

18. The memory transistor of claim 13, wherein the tunneling dielectric layer comprises silicon oxide, the barrier layer comprises cerium dioxide, and the charge trapping layer comprises silicon-rich silicon nitride.

19. The memory transistor of claim 13, wherein the tunneling dielectric layer comprises silicon nitride, the barrier layer comprises cerium dioxide, and the charge trapping layer comprises silicon-rich silicon nitride.

20. The memory transistor of claim 13, wherein the tunneling dielectric layer comprises silicon oxide, the barrier layer comprises zirconium dioxide, and the charge trapping layer comprises silicon-rich silicon nitride.

21. The memory transistor of claim 13, wherein when a voltage substantially less than the write voltage is applied between the channel region and the gate electrode, electrons tunnel into the charge trapping layer by Fowler-Nordheim tunneling or modified Fowler-Nordheim tunneling.

22. The memory transistor of claim 1, further comprising a blocking dielectric layer between the charge trapping layer and the gate electrode.

23. The memory transistor of claim 22, wherein the blocking dielectric layer further comprises an aluminum oxide layer.

24. The memory transistor of claim 23, wherein the aluminum oxide layer has a thickness between 2 nanometers and 5 nanometers.

25. The memory transistor of claim 1, wherein the memory transistor is a quasi-volatile memory transistor.

26. The memory transistor of claim 25, wherein the memory transistor is one of a plurality of thin film transistors formed in a not-or-gate (NOR) memory string.

27. The memory transistor of claim 26, wherein the not-or-gate memory string is one of a plurality of not-or-gate memory strings in a three-dimensional array.

28. The memory transistor of claim 1, wherein the memory transistor is a quasi-volatile memory transistor.

29. The memory transistor of claim 28, wherein the memory transistor is one of a plurality of thin film memory transistors formed in a not-or-gate memory string.

30. The memory transistor of claim 29, wherein the NOR gate memory string is one of a plurality of NOR gate memory strings in a three-dimensional array.

31. A memory transistor having a gate electrode layer, a channel region, and a charge storage layer between the gate electrode and the channel region, wherein the charge storage layer includes a tunneling dielectric layer, a charge trapping layer, a barrier layer between the tunneling dielectric layer and the charge trapping layer, and a barrier dielectric layer including a silicon dioxide or silicon nitride layer and a high-k dielectric material having a relative dielectric constant in excess of 4.0, wherein the barrier layer includes a material having a conduction band offset between -1.00 electron volts and 1.5 electron volts.

32. The memory transistor of claim 31, wherein the gate electrode layer includes P-type polysilicon.

33. The memory transistor of claim 31, wherein the high-k dielectric material includes aluminum oxide.

34. The memory transistor of claim 33, wherein the gate electrode layer includes a metal having a work function in excess of 3.8 eV.

35. The memory transistor of claim 34, wherein the metal includes one or more of: tungsten, tantalum nitride, and tantalum silicon nitride.

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