An automatic level tracking circuit, method, device and medium

Abstract

The present application discloses an automatic level tracking circuit, method, device and medium, relating to the field of electronic information technology. The circuit includes a dual-integral circuit, an oscillation circuit, a counting circuit, a DAC conversion circuit and a controlled amplification circuit; the dual-integral circuit receives a sensor signal and a reference voltage, and outputs a level signal to the counting circuit; the oscillation circuit outputs a pulse signal to the counting circuit; the counting circuit counts according to the level signal and the pulse signal, and outputs a digital signal to the DAC conversion circuit; the DAC conversion circuit converts the digital signal into an analog voltage signal and outputs it to the controlled amplification circuit; the controlled amplification circuit outputs a voltage signal according to the sensor signal, the analog voltage signal and the reference voltage. By adopting the dual-integral circuit and using the first mean value theorem of integration, the DC noise in the effective signal of the sensor signal is removed; and by changing the counting condition of the counting circuit to adjust the output level, the tracking of the effective signal is realized, and the working performance of the amplifier is improved.

Description

Technical Field

[0001] The present application relates to the field of electronic information technology, and in particular to an automatic level tracking circuit, method, device and medium. Background Art

[0002] When detecting trace voltage signals, it's common to encounter situations where the effective signal is very small but superimposed on a large amount of stray noise. When the effective signal and DC noise of similar frequency are superimposed and fed together into the op amp input, the DC operating point of the op amp drifts, preventing high-power amplification. To address this issue, existing automatic level control (ALC) methods activate when the effective signal level exceeds a threshold. When the signal level exceeds the threshold, a peak detector is used to isolate the peak of the output signal. This is then followed by level detection using an RC filter circuit with a time constant τ much greater than the noise level period. The control signal is then inversely superimposed on the input signal to attenuate the noise.

[0003] However, in the above circuit, if the RC filter circuit is not set properly, it will cause the circuit to oscillate and damage the input system.

[0004] In view of the above problems, designing an automatic level tracking circuit is an issue that needs to be urgently solved by technicians in this field. Summary of the Invention

[0005] The purpose of this application is to provide an automatic level tracking circuit, method, device and medium to solve the problem that improper setting of the RC filter circuit may cause circuit oscillation and damage the input system.

[0006] In order to solve the above technical problems, the present application provides an automatic level tracking circuit, comprising: a dual integration circuit 10, an oscillation circuit 11, a counting circuit 12, a DAC conversion circuit 13 and a controlled amplifier circuit 14;

[0007] The output end of the dual integration circuit 10 is connected to the first input end of the counting circuit 12, for receiving the sensor signal and the reference voltage, and outputting a level signal to the counting circuit 12 according to the sensor signal and the reference voltage;

[0008] The first output terminal of the oscillation circuit 11 is connected to the second input terminal of the counting circuit 12 for outputting a pulse signal to the counting circuit 12;

[0009] The output end of the counting circuit 12 is connected to the input end of the DAC conversion circuit 13, and is used for counting according to the level signal and the pulse signal, and outputting a digital signal to the DAC conversion circuit 13;

[0010] The output end of the DAC conversion circuit 13 is connected to the first input end of the controlled amplifier, and is used to convert the digital signal into an analog voltage signal and output it to the controlled amplifier circuit 14;

[0011] The second input end of the controlled amplifier circuit 14 receives a reference voltage, and is used to output a voltage signal according to the sensor signal, the analog voltage signal and the reference voltage.

[0012] Preferably, the dual-integral circuit 10 includes: a first amplifier, a second amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a first diode, a second diode, a first capacitor and a second capacitor;

[0013] The positive power supply end of the first amplifier is connected to the power supply, the negative power supply end of the first amplifier is grounded, the non-inverting input end of the first amplifier is connected to the first end of the first resistor, the inverting input end of the first amplifier is connected to the first end of the second resistor, and the output end of the first amplifier is connected to the first end of the fourth resistor;

[0014] The positive power supply end of the second amplifier is connected to the power supply, the negative power supply end of the second amplifier is grounded, the non-inverting input end of the second amplifier is connected to the second end of the second resistor, the inverting input end of the second amplifier is connected to the first end of the third resistor, the second end of the third resistor is connected to the second end of the first resistor, and the output end of the second amplifier is connected to the first end of the fifth resistor;

[0015] The anode of the first diode is grounded, and the cathode of the first diode is connected to the first end of the second resistor and the first end of the first capacitor; the second end of the first capacitor is connected to the first end of the sixth resistor; the second end of the sixth resistor is connected to the second end of the fourth resistor;

[0016] The anode of the second diode is grounded, and the cathode of the second diode is connected to the first end of the third resistor and the first end of the second capacitor; the second end of the second capacitor is connected to the first end of the seventh resistor; the second end of the seventh resistor is connected to the second end of the fifth resistor;

[0017] Wherein, the common end formed by the second end of the first resistor and the second end of the third resistor serves as the first input end of the dual-integral circuit 10; the second end of the second resistor serves as the second input end of the dual-integral circuit 10; the common end formed by the second end of the fourth resistor and the second end of the sixth resistor serves as the first output end of the dual-integral circuit 10; the common end formed by the second end of the fifth resistor and the second end of the seventh resistor serves as the second output end of the dual-integral circuit 10.

[0018] Preferably, the counting circuit 12 includes: a first NAND gate, a second NAND gate, a first counter, and a second counter;

[0019] The output terminals of the first NAND gate and the second NAND gate are respectively connected to the first counter;

[0020] The first counter is connected to the second counter;

[0021] Wherein, the first input terminals of the first NAND gate and the second NAND gate together serve as the first input terminal of the counting circuit 12; the common terminal formed by the second input terminal of the first NAND gate and the second input terminal of the second NAND gate serves as the second input terminal of the counting circuit 12; the output terminals of the first counter and the second counter together serve as the output terminal of the counting circuit 12.

[0022] Preferably, it further includes: a third NAND gate, a fourth NAND gate, a fifth NAND gate, and a sixth NAND gate;

[0023] The first input terminal and the second input terminal of the third NAND gate are respectively connected to the first output terminal of the dual-slope integrating circuit 10; the first input terminal and the second input terminal of the fourth NAND gate are respectively connected to the output terminal of the third NAND gate; the output terminal of the fourth NAND gate is connected to the first input terminal of the first NAND gate;

[0024] The first input terminal and the second input terminal of the fifth NAND gate are respectively connected to the second output terminal of the dual-slope integrating circuit 10; the first input terminal and the second input terminal of the sixth NAND gate are respectively connected to the output terminal of the fifth NAND gate; the output terminal of the sixth NAND gate is connected to the first input terminal of the second NAND gate.

[0025] Preferably, it further includes: a discharge circuit; wherein, the discharge circuit includes a signal shaping circuit 15, a seventh NAND gate, an eighth NAND gate, an eighth resistor, a ninth resistor, a first discharge tube, and a second discharge tube;

[0026] The input terminal of the signal shaping circuit 15 is connected to the second output terminal of the oscillation circuit 11; the common terminal formed by the first input terminal and the second input terminal of the seventh NAND gate is connected to the output terminal of the signal shaping circuit 15; the common terminal formed by the first input terminal and the second input terminal of the eighth NAND gate is connected to the output terminal of the signal shaping circuit 15;

[0027] The output terminal of the seventh NAND gate is connected to the first end of the eighth resistor, the second end of the eighth resistor is connected to the first end of the first discharge tube; the second end of the first discharge tube is connected to the second end of the sixth resistor; the third end of the first discharge tube is grounded;

[0028] The output terminal of the eighth NAND gate is connected to the first end of the ninth resistor, and the second end of the ninth resistor is connected to the first end of the second discharge tube; the second end of the second discharge tube is connected to the second end of the seventh resistor; the third end of the second discharge tube is grounded.

[0029] Preferably, the DAC conversion circuit 13 includes: 8 resistor combinations, a third amplifier, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, and a third capacitor;

[0030] Each of the resistor combinations includes two resistors; wherein, the first end of the first resistor in the two resistors serves as the first end of the resistor combination, the second end of the first resistor is connected to the first end of the second resistor, and the second end of the second resistor serves as the second end of the resistor combination;

[0031] The first ends of the resistor combinations are sequentially connected to the common end formed by the second end of the first resistor and the first end of the second resistor in the previous resistor combination; wherein, the first end of the first resistor combination is grounded, and the common end formed by the second end of the first resistor and the first end of the second resistor in the last resistor combination is connected to the first end of the tenth resistor, and the second end of the tenth resistor is grounded; the second ends of the resistor combinations are respectively used as the input terminals of the DAC conversion circuit 13;

[0032] The positive power supply terminal of the third amplifier is connected to the power supply, the negative power supply terminal of the third amplifier is grounded, the non-inverting input terminal of the third amplifier is connected to the first end of the tenth resistor, the inverting input terminal of the third amplifier is connected to the first ends of the eleventh resistor and the twelfth resistor, and the output terminal of the third amplifier is connected to the second end of the twelfth resistor and the first end of the thirteenth resistor; the second end of the thirteenth resistor is connected to the first end of the third capacitor; the second end of the third capacitor and the second end of the eleventh resistor are grounded; the first end of the tenth resistor serves as the output terminal of the DAC conversion circuit 13.

[0033] Preferably, the controlled amplification circuit 14 includes: a fourth amplifier, a fourteenth resistor, and a fifteenth resistor;

[0034] The positive power supply terminal of the fourth amplifier is connected to the power supply, the negative power supply terminal of the fourth amplifier is grounded, the inverting input terminal of the fourth amplifier is connected to the first ends of the fourteenth resistor and the fifteenth resistor, and the output terminal of the fourth amplifier is connected to the second end of the fifteenth resistor;

[0035] Among them, the non-inverting input terminal of the fourth amplifier serves as the first input terminal of the controlled amplification circuit 14; the second terminal of the fourteenth resistor serves as the second input terminal of the controlled amplification circuit 14, and the output terminal of the fourth amplifier serves as the output terminal of the controlled amplification circuit 14.

[0036] To solve the above technical problems, the present application also provides an automatic level tracking method, which is applied to the above-mentioned automatic level tracking circuit and includes:

[0037] Obtain a level signal and a pulse signal;

[0038] Perform counting according to the level signal and the pulse signal to obtain a count value;

[0039] Output a digital signal of the count value to the DAC conversion circuit 13 for converting the digital signal into an analog voltage signal and outputting it to the controlled amplification circuit 14;

[0040] Among them, the controlled amplification circuit 14 outputs a voltage signal according to the sensor signal, the analog voltage signal, and the reference voltage.

[0041] To solve the above technical problems, the present application also provides an automatic level tracking device, which is applied to the above-mentioned automatic level tracking circuit and includes:

[0042] A memory for storing a computer program;

[0043] A processor for implementing the steps of the above-mentioned automatic level tracking method when executing the computer program.

[0044] To solve the above technical problems, the present application also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the above-mentioned automatic level tracking method are implemented.

[0045] The automatic level tracking circuit provided by this application includes a dual-integral circuit, an oscillation circuit, a counting circuit, a DAC conversion circuit, and a controlled amplification circuit; the output end of the dual-integral circuit is connected to the first input end of the counting circuit, and is used to receive a sensor signal and a reference voltage, and output a level signal to the counting circuit according to the sensor signal and the reference voltage; the first output end of the oscillation circuit is connected to the second input end of the counting circuit, and is used to output a pulse signal to the counting circuit; the output end of the counting circuit is connected to the input end of the DAC conversion circuit, and is used to count according to the level signal and the pulse signal, and output a digital signal to the DAC conversion circuit; the output end of the DAC conversion circuit is connected to the first input end of the controlled amplifier, and is used to convert the digital signal into an analog voltage signal and output it to the controlled amplification circuit; the second input end of the controlled amplification circuit receives the reference voltage, and is used to output a voltage signal according to the sensor signal, the analog voltage signal, and the reference voltage. It can be seen that in the above solution, by adopting a dual-integral circuit and using the first mean value theorem for integrals, the DC noise in the effective signal is removed from the sensor signal through the dual-integral circuit; and by changing the counting situation of the counting circuit to adjust the output level, the tracking of the effective signal is realized, so as to amplify the effective signal and improve the working performance of the amplifier.

[0046] In addition, the embodiment of this application also provides an automatic level tracking method and device, and the effect is the same as above. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of this application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of this application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0048] Figure 1 It is a schematic structural diagram of an automatic level tracking circuit provided by an embodiment of this application;

[0049] Figure 2 It is a schematic structural diagram of a dual-integral circuit provided by an embodiment of this application;

[0050] Figure 3 It is a schematic structural diagram of a counting circuit provided by an embodiment of this application;

[0051] Figure 4 It is a schematic structural diagram of an oscillation circuit provided by an embodiment of this application;

[0052] Figure 5 It is a schematic structural diagram of another dual-integral circuit provided by an embodiment of this application;

[0053] Figure 6Schematic diagram of the connection between a discharge circuit and a dual-integral circuit provided by an embodiment of the present application;

[0054] Figure 7 Schematic diagram of the structure of a DAC conversion circuit provided by an embodiment of the present application;

[0055] Figure 8 Schematic diagram of the structure of a controlled amplification circuit provided by an embodiment of the present application;

[0056] Figure 9 Flowchart of an automatic level tracking method provided by an embodiment of the present application;

[0057] Figure 10 Schematic diagram of the structure of an automatic level tracking device provided by an embodiment of the present application.

[0058] Among them, 10 is a dual-integral circuit, 11 is an oscillation circuit, 12 is a counting circuit, 13 is a DAC conversion circuit, 14 is a controlled amplification circuit, and 15 is a signal shaping circuit. Detailed implementation manners

[0059] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0060] The core of the present application is to provide an automatic level tracking circuit, method, device and medium.

[0061] In order to enable those skilled in the art to better understand the solution of the present application, the present application will be further described in detail below in conjunction with the accompanying drawings and specific implementation manners.

[0062] In the detection process of some micro-voltage signals, it is often encountered that the effective signal is very small, but superimposed on a large amount of stray noise. When the effective signal is superimposed with a DC noise with a similar frequency and input to the input end of the operational amplifier together, it will cause the DC operating point of the operational amplifier to drift and the problem of inability to perform high-magnification amplification. The existing ALC method is that when the effective signal level exceeds the threshold, the ALC circuit is started. When the signal level exceeds the threshold, the peak value of the output signal is separated by a peak detector, and then the level is detected through an RC filter circuit with a time constant τ much larger than the noise level period. Then the control signal is superimposed on the input signal in the reverse direction to attenuate the noise. However, in the above circuit, if the RC filter circuit is set improperly, the circuit will oscillate and damage the input system. Therefore, the embodiments of the present application provide an automatic level tracking circuit.Figure 1 This is a schematic diagram of the structure of an automatic level tracking circuit provided by an embodiment of the present application. As Figure 1 shown, the circuit includes: a dual-integral circuit 10, an oscillation circuit 11, a counting circuit 12, a DAC conversion circuit 13, and a controlled amplification circuit 14;

[0063] The output end of the dual-integral circuit 10 is connected to the first input end of the counting circuit 12, and is used to receive a sensor signal and a reference voltage, and output a level signal to the counting circuit 12 according to the sensor signal and the reference voltage;

[0064] The first output end of the oscillation circuit 11 is connected to the second input end of the counting circuit 12, and is used to output a pulse signal to the counting circuit 12;

[0065] The output end of the counting circuit 12 is connected to the input end of the DAC conversion circuit 13, and is used to count according to the level signal and the pulse signal, and output a digital signal to the DAC conversion circuit 13;

[0066] The output end of the DAC conversion circuit 13 is connected to the first input end of the controlled amplifier, and is used to convert the digital signal into an analog voltage signal and output it to the controlled amplification circuit 14;

[0067] The second input end of the controlled amplification circuit 14 receives the reference voltage, and is used to output a voltage signal according to the sensor signal, the analog voltage signal, and the reference voltage.

[0068] It can be understood that in this embodiment, the dual-integral circuit 10 is used to receive the sensor signal and the reference voltage, and output a corresponding level signal to the counting circuit 12 by comparing the voltage magnitudes of the sensor signal and the reference signal, so that the counting circuit 12 can count according to the level signal. In the present application, the specific structure of the dual-integral circuit 10 is not limited and is determined according to specific implementation situations.

[0069] The first input terminal of the counting circuit 12 receives the level signal transmitted by the dual-integral circuit 10, and the second input terminal of the counting circuit 12 receives the pulse signal transmitted by the oscillation circuit 11. The counting circuit 12 can perform counting according to the above-mentioned level signal and pulse signal. Specifically, when the bias point of the controlled amplifier circuit 14 drifts upward, the counting circuit 12 can perform counting according to the level signal and pulse signal received at this time, and the counter therein is incremented by 1; when the bias point of the controlled amplifier circuit 14 drifts downward, the counting circuit 12 can perform counting according to the level signal and pulse signal received at this time, and the counter therein is decremented by 1, so as to implement the counting operation and output corresponding digital signals according to different counting situations. There is no limitation on the specific structure of the counting circuit 12, nor on the specific counting process, which depends on the specific implementation situation. In addition, in this embodiment, there is no limitation on the specific structure of the oscillation circuit 11, which depends on the specific implementation situation.

[0070] After the counting circuit 12 performs counting, since the counting circuit 12 finally outputs the digital signal of the count, the digital signal after counting also needs to be output to the DAC conversion circuit 13, and the DAC conversion circuit 13 converts the digital signal into an analog voltage signal as an analog signal for voltage feedback. In this embodiment, there is no limitation on the specific structure of the DAC conversion circuit 13, which depends on the specific implementation situation.

[0071] The first input terminal of the controlled amplifier circuit 14 receives the analog voltage signal transmitted by the DAC conversion circuit 13 and can also receive the sensor signal. The controlled amplifier can output a voltage signal according to the sensor signal, the analog voltage signal, and the reference voltage received at its second input terminal. Specifically, the controlled amplifier circuit 14 can achieve the purpose of removing the DC bias in the signal through the feedback voltage and adjusting the reference voltage, and the output voltage signal points to the level center. In this embodiment, there is no limitation on the specific structure of the controlled amplifier circuit 14, which depends on the specific implementation situation.

[0072] In this embodiment, the automatic level tracking circuit includes a dual-integral circuit, an oscillation circuit, a counting circuit, a DAC conversion circuit, and a controlled amplification circuit; the output end of the dual-integral circuit is connected to the first input end of the counting circuit, and is used to receive the sensor signal and the reference voltage, and output a level signal to the counting circuit according to the sensor signal and the reference voltage; the first output end of the oscillation circuit is connected to the second output end of the counting circuit, and is used to output a pulse signal to the counting circuit; the output end of the counting circuit is connected to the input end of the DAC conversion circuit, and is used to count according to the level signal and the pulse signal, and output a digital signal to the DAC conversion circuit; the output end of the DAC conversion circuit is connected to the first input end of the controlled amplifier, and is used to convert the digital signal into an analog voltage signal and output it to the controlled amplification circuit; the second input end of the controlled amplification circuit receives the reference voltage, and is used to output a voltage signal according to the sensor signal, the analog voltage signal, and the reference voltage. It can be seen that the above solution uses a dual-integral circuit and the integral first mean value theorem to remove the DC noise in the effective signal of the sensor signal through the dual-integral circuit; and adjusts the output level by changing the counting situation of the counting circuit, realizes the tracking of the effective signal, so as to amplify the effective signal and improve the working performance of the amplifier.

[0073] Figure 2 FIG. is a schematic structural diagram of a dual-integral circuit provided by an embodiment of the present application. On the basis of the above embodiment, as a preferred embodiment, as Figure 2 shown, in this embodiment, the dual-integral circuit 10 includes: a first amplifier U1, a second amplifier U2, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, a first diode D1, a second diode D2, a first capacitor C1, and a second capacitor C2;

[0074] The positive power supply terminal of the first amplifier U1 is connected to the power supply, the negative power supply terminal of the first amplifier U1 is grounded, the non-inverting input terminal of the first amplifier U1 is connected to the first end of the first resistor R1, the inverting input terminal of the first amplifier U1 is connected to the first end of the second resistor R2, and the output terminal of the first amplifier U1 is connected to the first end of the fourth resistor R4;

[0075] The positive power supply terminal of the second amplifier U2 is connected to the power supply, the negative power supply terminal of the second amplifier U2 is grounded, the non-inverting input terminal of the second amplifier U2 is connected to the second end of the second resistor R2, the inverting input terminal of the second amplifier U2 is connected to the first end of the third resistor R3, the second end of the third resistor R3 is connected to the second end of the first resistor R1, and the output terminal of the second amplifier U2 is connected to the first end of the fifth resistor R5;

[0076] The anode of the first diode D1 is grounded, and the cathode of the first diode D1 is connected to the first end of the second resistor R2 and the first end of the first capacitor C1; the second end of the first capacitor C1 is connected to the first end of the sixth resistor R6; the second end of the sixth resistor R6 is connected to the second end of the fourth resistor R4;

[0077] The anode of the second diode D2 is grounded, and the cathode of the second diode D2 is connected to the first end of the third resistor R3 and the first end of the second capacitor C2; the second end of the second capacitor C2 is connected to the first end of the seventh resistor R7; the second end of the seventh resistor R7 is connected to the second end of the fifth resistor R5;

[0078] Wherein, the common end formed by the second end of the first resistor R1 and the second end of the third resistor R3 serves as the first input end of the dual-slope integrating circuit 10; the second end of the second resistor R2 serves as the second input end of the dual-slope integrating circuit 10; the common end formed by the second end of the fourth resistor R4 and the second end of the sixth resistor R6 serves as the first output end of the dual-slope integrating circuit 10; the common end formed by the second end of the fifth resistor R5 and the second end of the seventh resistor R7 serves as the second output end of the dual-slope integrating circuit 10.

[0079] It can be understood that the above devices together form the dual-slope integrating circuit 10. Among them Figure 2 the common end formed by the first end of the first resistor R1 and the second end of the third resistor R3 is Vin, that is, the input end of the sensor signal, and the second end of the second resistor R2 is Vref, that is, the input end of the reference voltage. In this embodiment, there is no limitation on the model selection of the above amplifier, resistor, diode, and capacitor, which is determined according to the specific implementation situation. The working state of the dual-slope integrating circuit 10 is as follows:

[0080] When the bias point of the controlled amplification circuit 14 does not drift, both the first output end and the second output end of the dual-slope integrating circuit 10 output low levels; when the bias point of the controlled amplification circuit 14 drifts upward, the first output end of the dual-slope integrating circuit 10 outputs a high level and the second output end outputs a low level; when the bias point of the controlled amplification circuit drifts downward, the first output end of the dual-slope integrating circuit 10 outputs a low level and the second output end outputs a high level;

[0081] It should be noted that the specific parameters of the first capacitor C1, the sixth resistor R6, the second capacitor C2, and the seventh resistor R7 determine the integration sensitivity and response time of the dual-slope integrating circuit 10; the specific parameters set are determined according to the specific implementation situation and are not limited in this embodiment.

[0082] In this embodiment, through the dual-slope integrating circuit, different level signals can be generated according to the sensor signal and the reference voltage, so as to output the level signal to the counting circuit for counting.

[0083] Figure 3A structural schematic diagram of a counting circuit provided by an embodiment of the present application. On the basis of the above embodiment, as a preferred embodiment, in this embodiment, the counting circuit 12 includes: a first NAND gate U3, a second NAND gate U4, a first counter U5, and a second counter U6;

[0084] The output terminals of the first NAND gate U3 and the second NAND gate U4 are respectively connected to the first counter U5;

[0085] The first counter U5 is connected to the second counter U6;

[0086] Among them, the first input terminals of the first NAND gate U3 and the second NAND gate U4 together serve as the first input terminal of the counting circuit 12; the common terminal formed by the second input terminal of the first NAND gate U3 and the second input terminal of the second NAND gate U4 serves as the second input terminal of the counting circuit 12; the output terminals of the first counter U5 and the second counter U6 together serve as the output terminal of the counting circuit 12.

[0087] It can be understood that in Figure 3 the first input terminals of the first NAND gate U3 and the second NAND gate U4 are Vup and Vdw respectively; Vup is connected to the first output terminal of the dual-slope integration circuit 10, and Vdw is connected to the second output terminal of the dual-slope integration circuit 10, and is used to receive two level signals transmitted by the dual-slope integration circuit 10 respectively. The common terminal formed by the second input terminal of the first NAND gate U3 and the second input terminal of the second NAND gate U4 is used to receive the pulse signal transmitted by the oscillation circuit 11.

[0088] Figure 4 A structural schematic diagram of an oscillation circuit provided by an embodiment of the present application. As Figure 4 shown, the oscillation circuit 11 mainly consists of a timing chip U20, a resistor R30, a capacitor C10, and a capacitor C11, and its connection method is as Figure 4 shown. Among them, the first end of the resistor R30 is connected to the first end of the capacitor C10, and the second end of the resistor R30 is the first output terminal of the oscillation circuit 11, which can output the pulse signal generated by the oscillation circuit 11 to the counting circuit 12. There is no limitation on the selected models of the components in the oscillation circuit 11, which is determined according to specific implementation situations. The working state of the counting circuit 12 is as follows:

[0089] When the bias point of the controlled amplifier circuit 14 drifts upward, Vup is at a high level, Vdw is at a low level, the first NAND gate U3 is turned on, the oscillation circuit 11 outputs a pulse, and the first counter U5 increments by 1; when the bias point of the controlled amplifier circuit 14 drifts downward, Vup is at a low level, Vdw is at a high level, the second NAND gate U4 is turned on, the oscillation circuit 11 outputs a pulse, and the second counter U6 decrements by 1, and this cycle continues until approaching the center of the level. The obtained count value is output to the DAC conversion circuit 13 through the d0, d1, d2, and d3 output terminals of the first counter U5, and the d4, d5, d6, and d7 output terminals of the second counter U6.

[0090] In this embodiment, a counting circuit is formed by the first NAND gate, the second NAND gate, the first counter, the second counter, and their connection methods, realizing the counting function of the counting circuit, so as to adjust the output level by changing the counting situation of the counting circuit and achieving the tracking of the effective signal.

[0091] Figure 5 FIG. shows a schematic structural diagram of another dual-integral circuit provided by an embodiment of the present application. On the basis of the above embodiment, as a preferred embodiment, in this embodiment, it further includes: a third NAND gate U7, a fourth NAND gate U8, a fifth NAND gate U9, and a sixth NAND gate U10;

[0092] The first input terminal and the second input terminal of the third NAND gate U7 are respectively connected to the first output terminal of the dual-integral circuit 10; the first input terminal and the second input terminal of the fourth NAND gate U8 are respectively connected to the output terminal of the third NAND gate U7; the output terminal of the fourth NAND gate U8 is connected to the first input terminal of the first NAND gate U3;

[0093] The first input terminal and the second input terminal of the fifth NAND gate U9 are respectively connected to the second output terminal of the dual-integral circuit 10; the first input terminal and the second input terminal of the sixth NAND gate U10 are respectively connected to the output terminal of the fifth NAND gate U9; the output terminal of the sixth NAND gate U10 is connected to the first input terminal of the second NAND gate U4.

[0094] It can be understood that since the voltage output at the output terminal of the dual-integral circuit 10 is relatively high, to protect the subsequent connected counting circuit 12, as Figure 5 shown, by respectively connecting the third NAND gate U7 and the fourth NAND gate U8, as well as the fifth NAND gate U9 and the sixth NAND gate U10 after the two output terminals of the dual-integral circuit 10, the step-down isolation of the output voltage of the dual-integral circuit 10 is realized. Then, the output terminal of the fourth NAND gate U8 is connected to the first input terminal of the first NAND gate U3 of the counting circuit 12, that is, Vup; at this time, the output terminal of the sixth NAND gate U10 is connected to the first input terminal of the second NAND gate U4 of the counting circuit 12, that is, Vdw.

[0095] In this embodiment, by adding the third NAND gate, the fourth NAND gate, the fifth NAND gate, and the sixth NAND gate between the dual-integral circuit and the counting circuit, the step-down isolation of the output voltage of the dual-integral circuit is achieved, protecting the counting circuit.

[0096] Figure 6 FIG. is a schematic connection diagram of a discharge circuit and a dual-integral circuit provided by an embodiment of the present application. On the basis of the above embodiment, as a preferred embodiment, in this embodiment, the automatic level tracking circuit further includes: a discharge circuit; wherein, the discharge circuit includes a signal shaping circuit 15, a seventh NAND gate U11, an eighth NAND gate U12, an eighth resistor R8, a ninth resistor R9, a first discharge tube Q1, and a second discharge tube Q2;

[0097] The input end of the signal shaping circuit 15 is connected to the second output end of the oscillation circuit 11; the common end formed by the first input end and the second input end of the seventh NAND gate U11 is connected to the output end of the signal shaping circuit 15; the common end formed by the first input end and the second input end of the eighth NAND gate U12 is connected to the output end of the signal shaping circuit 15;

[0098] The output end of the seventh NAND gate U11 is connected to the first end of the eighth resistor R8, the second end of the eighth resistor R8 is connected to the first end of the first discharge tube Q1; the second end of the first discharge tube Q1 is connected to the second end of the sixth resistor R6; the third end of the first discharge tube Q1 is grounded;

[0099] The output end of the eighth NAND gate U12 is connected to the first end of the ninth resistor R9, the second end of the ninth resistor R9 is connected to the first end of the second discharge tube Q2; the second end of the second discharge tube Q2 is connected to the second end of the seventh resistor R7; the third end of the second discharge tube Q2 is grounded.

[0100] It can be understood that after the dual-integral circuit 10 finishes integrating one cycle, since there will still be some remaining charges in the first capacitor C1 and the second capacitor C2, in order to clear the remaining charges of the two capacitors for the next cycle of integration, a discharge circuit is provided in this embodiment to clear the remaining charges of the two capacitors.

[0101] In the discharge circuit, the function of the signal shaping circuit 15 is to convert the triangular wave signal output by the oscillation circuit 11 into a square wave signal. Its components include an amplifier U21, a resistor R31, a resistor R32, and a resistor R33, and their connection method is as Figure 6As shown, the first end of resistor R33 is grounded, and the second end of resistor R33 is the output end of signal shaping circuit 15; there is no limitation on the specific model of the above-mentioned devices, which is determined according to the specific implementation situation. The signal shaping circuit 15 outputs the square wave signal to the seventh NAND gate U11 and the eighth NAND gate U12 respectively, and conducts the first discharge tube Q1 and the second discharge tube Q2 through the eighth resistor R8 and the ninth resistor R9 respectively, so that the first discharge tube Q1 and the second discharge tube Q2 respectively discharge the electric charges in the first capacitor C1 and the second capacitor C2.

[0102] In this embodiment, the remaining electric charges in the first capacitor and the second capacitor in the dual-integral circuit are emptied by setting a discharge circuit, so as to facilitate the integration in the next cycle.

[0103] Figure 7 It is a schematic structural diagram of a DAC conversion circuit provided by an embodiment of the present application. On the basis of the above embodiment, as a preferred embodiment, in this embodiment, the DAC conversion circuit 13 includes: 8 resistor combinations, a third amplifier U13, a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, a thirteenth resistor R13, and a third capacitor C3;

[0104] Each resistor combination contains two resistors; among them, the first end of the first resistor in the two resistors is used as the first end of the resistor combination, the second end of the first resistor is connected to the first end of the second resistor, and the second end of the second resistor is used as the second end of the resistor combination;

[0105] The first ends of each resistor combination are sequentially connected to the common end formed by the second end of the first resistor and the first end of the second resistor in the previous resistor combination; among them, the first end of the first resistor combination is grounded, and the common end formed by the second end of the first resistor and the first end of the second resistor in the last resistor combination is connected to the first end of the tenth resistor R10, and the second end of the tenth resistor R10 is grounded; the second ends of each resistor combination are respectively used as the input ends of the DAC conversion circuit 13;

[0106] The positive power supply end of the third amplifier U13 is connected to the power supply, the negative power supply end of the third amplifier U13 is grounded, the non-inverting input end of the third amplifier U13 is connected to the first end of the tenth resistor R10, the inverting input end of the third amplifier U13 is connected to the first ends of the eleventh resistor R11 and the twelfth resistor R12, and the output end of the third amplifier U13 is connected to the second end of the twelfth resistor R12 and the first end of the thirteenth resistor R13; the second end of the thirteenth resistor R13 is connected to the first end of the third capacitor C3; the second end of the third capacitor C3 and the second end of the eleventh resistor R11 are grounded; the first end of the tenth resistor R10 is used as the output end of the DAC conversion circuit 13.

[0107] It can be understood that inFigure 7 Among them, the two resistors in the combination of 8 resistors are resistor R34 and resistor R35, resistor R36 and resistor R37, resistor R38 and resistor R39, resistor R40 and resistor R41, resistor R42 and resistor R43, resistor R44 and resistor R45, resistor R46 and resistor R47, resistor R48 and resistor R49. Among them, the second ends of resistor R35, resistor R37, resistor R39, resistor R41, resistor R43, resistor R45, resistor R47, and resistor R49 are respectively the input ends of the DAC conversion circuit 13, and are correspondingly connected to the output end of the counting circuit 12, and the corresponding manner is as Figure 7 shown.

[0108] In this embodiment, the DAC conversion circuit can convert the digital signal transmitted by the counting circuit into an analog voltage signal for voltage feedback to the controlled amplifier circuit.

[0109] Figure 8 It is a schematic structural diagram of a controlled amplifier circuit provided by an embodiment of the present application. On the basis of the above embodiment, as a preferred embodiment, in this embodiment, the controlled amplifier circuit 14 includes: a fourth amplifier U14, a fourteenth resistor R14, and a fifteenth resistor R15;

[0110] The positive power supply terminal of the fourth amplifier U14 is connected to the power supply, the negative power supply terminal of the fourth amplifier U14 is grounded, the inverting input terminal of the fourth amplifier U14 is connected to the first ends of the fourteenth resistor R14 and the fifteenth resistor R15, and the output terminal of the fourth amplifier U14 is connected to the second end of the fifteenth resistor R15;

[0111] Among them, the non-inverting input terminal of the fourth amplifier U14 is used as the first input terminal of the controlled amplifier circuit 14; the second end of the fourteenth resistor R14 is used as the second input terminal of the controlled amplifier circuit 14, and the output terminal of the fourth amplifier U14 is used as the output terminal of the controlled amplifier circuit 14.

[0112] It can be understood that Figure 8 the controlled amplifier circuit 14 in is a subtractor structure. The first input terminal of the circuit receives the sensor signal Vin and the feedback voltage transmitted by the DAC conversion circuit 13; the second input terminal of the circuit receives the reference voltage, so as to achieve the effect of subtracting the DC bias by adjusting the reference voltage, so that the bias point of the fourth amplifier U14 gradually returns, and the output level signal tends to the level center.

[0113] In this embodiment, the controlled amplifier circuit is a subtractor structure, which realizes the effect of subtracting the DC bias, so as to amplify the effective signal and improve the working performance of the amplifier.

[0114] Figure 9The flowchart of an automatic level tracking method provided by an embodiment of the present application. The method is applied to the above automatic level tracking circuit, such as Figure 9 shown, the method includes:

[0115] S10: Obtain a level signal and a pulse signal.

[0116] S11: Perform counting according to the level signal and the pulse signal to obtain a count value.

[0117] S12: Output the digital signal of the count value to the DAC conversion circuit 13 for converting the digital signal into an analog voltage signal and outputting it to the controlled amplification circuit 14;

[0118] wherein, the controlled amplification circuit 14 outputs a voltage signal according to the sensor signal, the analog voltage signal and the reference voltage.

[0119] The automatic level tracking method provided by this embodiment is applied to the above automatic level tracking circuit. By obtaining the level signal and the pulse signal, performing counting according to the level signal and the pulse signal to obtain a count value, and outputting the digital signal of the count value to the DAC conversion circuit for converting the digital signal into an analog voltage signal and outputting it to the controlled amplification circuit; wherein, the controlled amplification circuit outputs a voltage signal according to the sensor signal, the analog voltage signal and the reference voltage. The level signal is obtained through a dual-integral circuit. By using the first mean value theorem for integrals, the sensor signal is passed through the dual-integral circuit to remove the DC noise in the effective signal; and by changing the counting situation of the counting circuit to adjust the output level, the tracking of the effective signal is realized, so as to amplify the effective signal and improve the working performance of the amplifier.

[0120] Figure 10 The structural schematic diagram of an automatic level tracking device provided by an embodiment of the present application, such as Figure 10 shown, the automatic level tracking device includes:

[0121] A memory 20 for storing a computer program;

[0122] A processor 21 for implementing the steps of the automatic level tracking method mentioned in the above embodiment when executing the computer program.

[0123] The automatic level tracking device provided by this embodiment may include but is not limited to a smart phone, a tablet computer, a notebook computer or a desktop computer, etc.

[0124] Among them, the processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 21 may be implemented in at least one of the following hardware forms: Digital Signal Processor (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 21 may also include a main processor and a coprocessor. The main processor is a processor used to process data in the wake state, also known as the Central Processing Unit (CPU); the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 21 may be integrated with a Graphics Processing Unit (GPU), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 21 may also include an Artificial Intelligence (AI) processor, which is used to process computational operations related to machine learning.

[0125] The memory 20 may include one or more computer-readable storage media, and the computer-readable storage media may be non-transitory. The memory 20 may also include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash storage devices. In this embodiment, the memory 20 is at least used to store the following computer program 201. After the computer program is loaded and executed by the processor 21, it can implement the relevant steps of the automatic level tracking method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 may also include an operating system 202 and data 203, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system 202 may include Windows, Unix, Linux, etc. The data 203 may include, but is not limited to, the data involved in the automatic level tracking method.

[0126] In some embodiments, the automatic level tracking device may further include a display screen 22, an input / output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.

[0127] Those skilled in the art can understand that Figure 10 the structure shown in

[0128] Finally, the present application also provides an embodiment corresponding to a computer-readable storage medium. A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps recorded in the above method embodiments are implemented.

[0129] It can be understood that if the method in the above embodiments is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods described in various embodiments of the present application. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs that can store program codes.

[0130] The above has introduced in detail an automatic level tracking circuit, method, device, and medium provided by the present application. The embodiments in the specification are described in a progressive manner, and the key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method part. It should be noted that for those of ordinary skill in the art in this technical field, without departing from the principle of the present application, several improvements and modifications can still be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

[0131] It should also be noted that in this specification, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including", or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article, or device including a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article, or device. Without further limitation, an element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, article, or device including the said element.

Claims

1. An automatic level tracking circuit, characterized in that, Including: A dual-slope integrating circuit (10), an oscillation circuit (11), a counting circuit (12), a DAC conversion circuit (13), and a controlled amplification circuit (14); The output end of the dual-slope integrating circuit (10) is connected to the first input end of the counting circuit (12), and is used for receiving a sensor signal and a reference voltage, and outputting a level signal to the counting circuit (12) according to the sensor signal and the reference voltage; The first output end of the oscillation circuit (11) is connected to the second input end of the counting circuit (12), and is used for outputting a pulse signal to the counting circuit (12); The output end of the counting circuit (12) is connected to the input end of the DAC conversion circuit (13), and is used for counting according to the level signal and the pulse signal, and outputting a digital signal to the DAC conversion circuit (13); The output end of the DAC conversion circuit (13) is connected to the first input end of the controlled amplification circuit (14), and is used for converting the digital signal into an analog voltage signal and outputting it to the controlled amplification circuit (14); The second input end of the controlled amplification circuit (14) receives a reference voltage, and is used for outputting a voltage signal according to the sensor signal, the analog voltage signal, and the reference voltage; Wherein, when the bias point of the controlled amplification circuit (14) does not drift, both the first output end and the second output end of the dual-slope integrating circuit (10) output low levels; when the bias point of the controlled amplification circuit (14) drifts upward, the first output end of the dual-slope integrating circuit (10) outputs a high level, and the second output end outputs a low level; when the bias point of the controlled amplification circuit (14) drifts downward, the first output end of the dual-slope integrating circuit (10) outputs a low level, and the second output end outputs a high level.

2. The automatic level tracking circuit according to claim 1, wherein The dual-slope integrating circuit (10) includes: a first amplifier, a second amplifier, a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a first diode, a second diode, a first capacitor, and a second capacitor; The positive power supply end of the first amplifier is connected to a power supply, the negative power supply end of the first amplifier is grounded, the non-inverting input end of the first amplifier is connected to the first end of the first resistor, the inverting input end of the first amplifier is connected to the first end of the second resistor, and the output end of the first amplifier is connected to the first end of the fourth resistor; The positive power supply end of the second amplifier is connected to a power supply, the negative power supply end of the second amplifier is grounded, the non-inverting input end of the second amplifier is connected to the second end of the second resistor, the inverting input end of the second amplifier is connected to the first end of the third resistor, the second end of the third resistor is connected to the second end of the first resistor, and the output end of the second amplifier is connected to the first end of the fifth resistor; The anode of the first diode is grounded, the cathode of the first diode is connected to the first end of the second resistor and the first end of the first capacitor; the second end of the first capacitor is connected to the first end of the sixth resistor; the second end of the sixth resistor is connected to the second end of the fourth resistor; The anode of the second diode is grounded, and the cathode of the second diode is connected to the first end of the third resistor and the first end of the second capacitor; the second end of the second capacitor is connected to the first end of the seventh resistor; the second end of the seventh resistor is connected to the second end of the fifth resistor; Wherein, the common end formed by the second end of the first resistor and the second end of the third resistor serves as the first input end of the dual-integrating circuit (10); the second end of the second resistor serves as the second input end of the dual-integrating circuit (10); the common end formed by the second end of the fourth resistor and the second end of the sixth resistor serves as the first output end of the dual-integrating circuit (10); the common end formed by the second end of the fifth resistor and the second end of the seventh resistor serves as the second output end of the dual-integrating circuit (10).

3. The automatic level tracking circuit according to claim 2, wherein The counting circuit (12) includes: a first NAND gate, a second NAND gate, a first counter, and a second counter; The output ends of the first NAND gate and the second NAND gate are respectively connected to the first counter; The first counter is connected to the second counter; Wherein, the first input ends of the first NAND gate and the second NAND gate together serve as the first input end of the counting circuit (12); the common end formed by the second input end of the first NAND gate and the second input end of the second NAND gate serves as the second input end of the counting circuit (12); the output ends of the first counter and the second counter together serve as the output end of the counting circuit (12).

4. The automatic level tracking circuit according to claim 3, wherein It further includes: A third NAND gate, a fourth NAND gate, a fifth NAND gate, and a sixth NAND gate; The first input end and the second input end of the third NAND gate are respectively connected to the first output end of the dual-integrating circuit (10); the first input end and the second input end of the fourth NAND gate are respectively connected to the output end of the third NAND gate; the output end of the fourth NAND gate is connected to the first input end of the first NAND gate; The first input end and the second input end of the fifth NAND gate are respectively connected to the second output end of the dual-integrating circuit (10); the first input end and the second input end of the sixth NAND gate are respectively connected to the output end of the fifth NAND gate; the output end of the sixth NAND gate is connected to the first input end of the second NAND gate.

5. The automatic level tracking circuit according to claim 2, wherein It further includes: A discharge circuit; wherein, the discharge circuit includes a signal shaping circuit (15), a seventh NAND gate, an eighth NAND gate, an eighth resistor, a ninth resistor, a first discharge tube, and a second discharge tube; The input end of the signal shaping circuit (15) is connected to the second output end of the oscillation circuit (11); the common end formed by the first input end and the second input end of the seventh NAND gate is connected to the output end of the signal shaping circuit (15); the common end formed by the first input end and the second input end of the eighth NAND gate is connected to the output end of the signal shaping circuit (15); The output terminal of the seventh NAND gate is connected to the first end of the eighth resistor, and the second end of the eighth resistor is connected to the first end of the first discharge tube; the second end of the first discharge tube is connected to the second end of the sixth resistor; the third end of the first discharge tube is grounded; The output terminal of the eighth NAND gate is connected to the first end of the ninth resistor, and the second end of the ninth resistor is connected to the first end of the second discharge tube; the second end of the second discharge tube is connected to the second end of the seventh resistor; the third end of the second discharge tube is grounded.

6. The automatic level tracking circuit according to claim 1, wherein The DAC conversion circuit (13) includes: eight resistor combinations, a third amplifier, a tenth resistor, an eleventh resistor, a twelfth resistor, a thirteenth resistor, and a third capacitor; Each of the resistor combinations includes two resistors; wherein, the first end of the first resistor in the two resistors is used as the first end of the resistor combination, the second end of the first resistor is connected to the first end of the second resistor, and the second end of the second resistor is used as the second end of the resistor combination; The first ends of the resistor combinations are sequentially connected to the common end formed by the second end of the first resistor and the first end of the second resistor in the previous resistor combination; wherein, the first end of the first resistor combination is grounded, and the common end formed by the second end of the first resistor and the first end of the second resistor in the last resistor combination is connected to the first end of the tenth resistor, and the second end of the tenth resistor is grounded; the second ends of the resistor combinations are respectively used as the input terminals of the DAC conversion circuit (13); The positive power supply terminal of the third amplifier is connected to the power supply, the negative power supply terminal of the third amplifier is grounded, the non-inverting input terminal of the third amplifier is connected to the first end of the tenth resistor, the inverting input terminal of the third amplifier is connected to the first ends of the eleventh resistor and the twelfth resistor, and the output terminal of the third amplifier is connected to the second end of the twelfth resistor and the first end of the thirteenth resistor; the second end of the thirteenth resistor is connected to the first end of the third capacitor; the second end of the third capacitor and the second end of the eleventh resistor are grounded; the first end of the tenth resistor is used as the output terminal of the DAC conversion circuit (13).

7. The automatic level tracking circuit according to claim 1, wherein The controlled amplification circuit (14) includes: a fourth amplifier, a fourteenth resistor, and a fifteenth resistor; The positive power supply terminal of the fourth amplifier is connected to the power supply, the negative power supply terminal of the fourth amplifier is grounded, the inverting input terminal of the fourth amplifier is connected to the first ends of the fourteenth resistor and the fifteenth resistor, and the output terminal of the fourth amplifier is connected to the second end of the fifteenth resistor; Wherein, the non-inverting input terminal of the fourth amplifier is used as the first input terminal of the controlled amplification circuit (14); the second end of the fourteenth resistor is used as the second input terminal of the controlled amplification circuit (14), and the output terminal of the fourth amplifier is used as the output terminal of the controlled amplification circuit (14).

8. An automatic level tracking method, characterized in that, Applied to the automatic level tracking circuit according to any one of claims 1 to 7, comprising: Obtain a level signal and a pulse signal; Count according to the level signal and the pulse signal to obtain a count value; Outputting the digital signal of the count value to a DAC conversion circuit (13) for converting the digital signal into an analog voltage signal and outputting the analog voltage signal to a controlled amplifier circuit (14); The controlled amplifying circuit (14) outputs a voltage signal according to the sensor signal, the analog voltage signal and the reference voltage.

9. An automatic level tracking device, characterized in that, The automatic level tracking circuit according to any one of claims 1 to 7, comprising: memory for storing computer programs; A processor, configured to implement the steps of the automatic level tracking method according to claim 8 when executing the computer program.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the automatic level tracking method according to claim 8 are implemented.

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