A sampling and transmission monitoring circuit, module, communication chip, vehicle and method

Abstract

The present invention belongs to the technical field of electronic control of intelligent vehicles. An embodiment thereof discloses a sampling and transmission monitoring circuit, a module, a communication chip, a vehicle, and a signal acquisition and transmission method. Under the scheduling of the signal conditioning circuit, signals from the system are sampled or transmitted according to the control instructions of the main system, so as to improve the overall security level of the system. The related circuit uses multiple interconnected processing units to achieve hierarchical signal sampling and transmission monitoring. The high-level main control circuit is connected to the low-level circuit through a communication line or channel, enabling the low-security-level slave circuits distributed on different boards, chips, or products to have the same security level or design level as the main control circuit.

Description

Technical Field

[0001] The present invention belongs to the technical field of intelligent vehicle electronic control, and in particular relates to a sampling and transmission monitoring circuit, a module, a communication chip, a vehicle and a method. Background Art

[0002] The electronic circuits of smart products are becoming increasingly complex, and higher requirements are placed on their fault diagnosis and maintenance; especially for some systems with human involvement, such as smart vehicles, the safety of the system plays a vital role. Smart products often include multiple boards, modules or subsystems with processors, and the subsystems are often connected by communication networks; how to achieve global high-level security based on existing high-level subsystems, thereby reducing the probability of systematic failures and random hardware failures, is a technical problem that needs to be improved urgently. Summary of the invention

[0003] The present invention discloses a sampling and transmission monitoring circuit, module, communication chip, vehicle and method; the relevant circuit adopts multiple processing units interconnected by a network to realize hierarchical signal sampling and transmission monitoring; wherein, the high-level monitoring circuit is connected to the low-level circuit through a communication line or channel, and under the circuit structure disclosed in the embodiment of the present invention, the low-security level circuits distributed on different boards, chips or products and the circuits distributed on the main control unit have the same security level or design level.

[0004] The signal sampling and transmission monitoring circuit disclosed in the embodiment of the present invention includes a first processing unit, a first communication unit, a second processing unit and a first conditioning unit.

[0005] The first processing unit and the second processing unit located on different boards, chips or devices establish a signal transmission channel via the first communication unit; the second processing unit includes at least one group of signal acquisition control circuits; the signal acquisition control circuit responds to the instructions sent by the first processing unit via the first communication unit, and sends a first monitoring signal to the first conditioning unit.

[0006] Furthermore, the first conditioning unit includes at least one group of signal conditioning circuits; the signal conditioning circuits respond to the first monitoring signal and return a second monitoring signal to the signal acquisition control circuit.

[0007] Specifically, its signal acquisition control circuit is electrically and / or communicatively connected to at least one group of input signal terminals under the scheduling of the second monitoring signal; thereby, the first processing unit and the second processing unit located on different boards, chips or devices are interconnected into an associated whole via the first communication unit.

[0008] Further, the second processing unit may further include at least one set of first signal acquisition circuits; and the input signal terminal of the system is electrically connected and / or communicatively connected to the first signal acquisition circuits.

[0009] Further, the second processing unit may further include at least one set of first scheduling circuits; the first scheduling circuits respond to instructions sent by the first processing unit via the first communication unit and send first monitoring signals to the first conditioning unit.

[0010] Further, the input signal terminal may include at least a first port and a second port or further include a third port; among them, the signals that the third port can be connected to may include a ground signal, a zero-level signal or other reference signals.

[0011] Further, the second port can receive the redundant signal of the first port, providing guarantee for further improving the reliability of the system.

[0012] Further, the signal acquisition control circuit may further include at least one set of second communication units; the first signal acquisition circuits acquire signals from the input signal terminal via the second communication units and / or are electrically connected and / or communicatively connected to the input signal terminal.

[0013] Further, the first signal acquisition circuits may include at least one set of analog-to-digital conversion circuits, i.e., ADC (Analog to Digital Converter); and the ADC is electrically connected and / or communicatively connected to the input signal terminal.

[0014] Further, the first scheduling circuits may further include at least one set of PWM (Pulse Width Modulation) pulse width modulation circuits; and the PWM circuits are electrically connected and / or communicatively connected to the signal conditioning circuits.

[0015] Further, the first scheduling circuits may further include at least two sets of PWM circuits; and the PWM circuits are controlled with different duty cycle DCL (Duty Cycle) time sequences.

[0016] Among them: the above PWM circuits may include a first PWM circuit and a second PWM circuit; and the width of the duty cycle DCL time sequence of the first PWM circuit is successively 10%, 20%, 30%... 100% of the maximum pulse width over time; or the width of the duty cycle DCL time sequence of the second PWM circuit is successively 100%, 80%, 70%... 10% of the maximum pulse width over time.

[0017] Further, the safety level of the first processing unit may conform to a preset first standard; the safety level of the second processing unit may conform to a preset second standard or is not restricted by a preset standard.

[0018] Furthermore, the signal transmission channels established by the first communication unit and / or the second communication unit can be selected in accordance with at least one communication standard and / or protocol among Controller Area Network (CAN), Serial Peripheral Interface (SPI), and Universal Asynchronous Receiver / Transmitter (UART).

[0019] Furthermore, the above-mentioned first standard and second standard can be selected to conform to the relevant standards of ISO26262 ASIL (Automotive Safety Integrity Level); and the first standard can be made at least one level higher than the second standard.

[0020] Furthermore, an embodiment of the present invention also discloses a signal acquisition module, including any one of the above-mentioned monitoring circuits; wherein the first processing unit and the second processing unit are integrated on different circuit boards or different chips.

[0021] Furthermore, the above-mentioned monitoring circuit outputs the signals, reference data, reference voltage, and / or instructions collected by at least one of the input signal terminals to a preset port.

[0022] In addition, an embodiment of the present invention also discloses a communication chip and an intelligent vehicle; the chip includes a chip body; the chip body can be lithographed or prepared with any one of the above-mentioned circuits; and / or a signal acquisition module.

[0023] Furthermore, the processing process of the above-mentioned communication chip body can include at least one of processes or products such as a single-chip / multi-chip microprocessor or programmable unit MCU (Microprogrammed Control Unit or MicroController Unit), a field-programmable gate array (FPGA), a complex programmable logic device (CPLD), and a digital signal processor (DSP).

[0024] The circuit, module, chip, or vehicle disclosed in the embodiment of the present invention adopts a distributed signal sampling and transmission monitoring structure, and under the scheduling of the signal conditioning circuit, samples or transmits signals from the system according to the control instructions of the main system, so as to improve the overall safety level of the system.

[0025] An embodiment of the present invention also discloses a sampling transmission monitoring method, which obtains at least one first scheduling signal from a first processing unit and feeds the first scheduling signal back to a second processing unit after passing through a conditioning circuit; meanwhile, the signal to be collected and the conditioned signal are jointly sent to the first processing unit for verification processing.

[0026] Among them, the first scheduling signal is a voltage-controlled signal that changes with time; the first scheduling signal is transmitted to the conditioning circuit to generate a second monitoring signal; by feeding back or loading the second monitoring signal to the second processing unit, the monitoring signal of the first processing unit is superimposed on the second processing unit.

[0027] Further, the second processing unit includes at least one signal acquisition control circuit; at least one group of redundant signal pairs is acquired and sent to the first processing unit together with the second monitoring signal; among them, the redundant signal pair includes a first signal and a second signal, and the second signal is a redundant signal of the first signal.

[0028] Further, an auxiliary reference signal is provided for the verification process by superimposing a grounding signal as the input of the first signal acquisition circuit; among them, the first scheduling signal includes a PWM signal with a duty cycle that changes with time or a controllable voltage signal dominated by the first processing unit; the second processing unit also includes at least one group of first scheduling circuits; the first scheduling circuit responds to an instruction sent by the first processing unit via a first communication unit and sends a first monitoring signal to the first conditioning unit; the input signal terminal includes at least a first port and a second port, which are respectively used to receive the first signal and the second signal.

[0029] Further, the input signal terminal further includes a third port; the signal connected to the third port includes a grounding signal, a zero-level signal or other reference signals; the second port receives the redundant signal of the first port; the signal acquisition control circuit further includes at least one group of second communication units; the first signal acquisition circuit acquires signals from the input signal terminal via the second communication unit and / or is electrically connected and / or communicatively connected to the input signal terminal, and feeds back relevant signals to the first processing unit for verification;

[0030] Further, the first signal acquisition circuit includes at least one group of AD conversion circuits; the AD conversion circuit is electrically connected and / or communicatively connected to the input signal terminal; the first scheduling circuit includes at least one group of PWM circuits; the PWM circuit is electrically connected and / or communicatively connected to the signal conditioning circuit; similarly, through the conditioning circuit, the instruction of the first processing unit is superimposed on the input end of signal acquisition and fed back to the second processing unit.

[0031] It should be noted that the terms such as "first" and "second" used in this text are only for describing the components in the technical solution, and do not constitute a limitation to the technical solution, nor can they be understood as an indication or implication of the importance of the corresponding elements; the elements with terms such as "first" and "second" indicate that in the corresponding technical solution, there is at least one such element. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solution of the present invention and facilitate a further understanding of the technical effects, technical features and objectives of the present invention, the present invention will be described in detail below with reference to the drawings. The drawings form an essential part of the specification and are used together with the embodiments of the present invention to illustrate the technical solution of the present invention, but do not constitute a limitation to the present invention.

[0033] The same reference numerals in the drawings represent the same components. Specifically:

[0034] Figure 1 It is a schematic diagram of the composition structure and signal connection in the embodiment of the present invention: when there is a single slave system;

[0035] Figure 2 It is a schematic diagram of the composition structure and signal connection in the embodiment of the present invention: when there are two or more slave systems;

[0036] Figure 3 It is a schematic diagram of the sampling of the inter-board safety signal in the embodiment of the present invention;

[0037] Figure 4 It is a schematic diagram of multiple ADC sampling groups (using the same PWM signal) in the embodiment of the present invention;

[0038] Figure 5 It is a schematic diagram of multiple ADC sampling groups (using PWM signals with different variation rules) in the embodiment of the present invention;

[0039] Figure 6 It is a schematic diagram of the sampling and transmission monitoring structure involving multiple single-chip microcomputers in the embodiment of the present invention;

[0040] Figure 7 It is a schematic diagram of the sampling and transmission monitoring structure using non-PWM (such as Digital Output) in the embodiment of the present invention;

[0041] Figure 8 It is a schematic diagram of the sampling and transmission monitoring structure when the reference voltage output is dynamically loaded to the signal to be sampled in the embodiment of the present invention;

[0042] Figure 9 It is a schematic diagram of the sampling and transmission monitoring structure when an independent sampling device replaces the ADC in the embodiment of the present invention;

[0043] Figure 10 For the embodiment of the present invention: Composition and structure schematic diagram of the input signal terminal;

[0044] Figure 11 For the method embodiment of the present invention: Flow schematic diagram.

[0045] Among them:

[0046] 11 - Host computer instruction synchronous transmission step, 22 - Lower computer synchronous conditioning feedback step,

[0047] 33 - Lower computer composite sampling conversion step, 44 - Host computer comprehensive verification step,

[0048] 100 - First processing unit (UH); 200 - First communication unit; 300 - Second processing unit,

[0049] 301, 302, 30N - Signal acquisition control circuit,

[0050] 311, 312, 31N - First scheduling circuit (PL1, PL2, MCU, CHIP),

[0051] 321, 32N - Second communication unit, 331, 332, 33N - First signal acquisition circuit;

[0052] 401, 402, 40N - First monitoring signal, 411, 412, 41N - Second monitoring signal;

[0053] 500 - First conditioning unit, 501, 502, 50N - Signal conditioning circuit (CC1, CCN);

[0054] 601, 602, 60N - Input signal terminal,

[0055] 611, 612 - First port, 621, 622 - Second port, 631, 632 - Third port. Specific implementation manner

[0056] The present invention will be further described in detail below with reference to the drawings and embodiments. Of course, the specific embodiments described below are only for explaining the technical solution of the present invention, rather than limiting the present invention.

[0057] In addition, the parts described in the embodiments or drawings are only examples of relevant parts of the present invention, rather than the whole of the present invention.

[0058] Such as Figure 1 And Figure 2As shown, it is a schematic diagram of the composition structure and signal connection of the embodiment of the present invention in a single or two or more subordinate systems; wherein, the signal sampling and transmission monitoring circuit includes a first processing unit 100, a first communication unit 200, a second processing unit 300, and a first conditioning unit 500.

[0059] Specifically, the first processing unit 100 and the second processing unit 300 establish a signal transmission channel via the first communication unit 200; in the working state, the second processing unit 300 will perform relevant signal acquisition and transmission under the monitoring of the first processing unit 100.

[0060] Among them, the second processing unit 300 includes at least one group of signal acquisition control circuits 301, 302, 30N; the signal acquisition control circuits 301, 302, 30N respond to the instructions sent by the first processing unit 100 via the first communication unit 200, and send first monitoring signals 401, 402, 40N to the first conditioning unit 500.

[0061] Specifically, the first conditioning unit 500 includes at least one group of signal conditioning circuits 501, 502, 50N; in the working state, the signal conditioning circuits 501, 502, 50N respond to the first monitoring signals 401, 402, 40N and return second monitoring signals 411, 412, 41N to the signal acquisition control circuits 301, 302, 30N.

[0062] Among them, the signal acquisition control circuits 301, 302, 30N are electrically connected and / or communicatively connected to at least one group of input signal terminals 601, 602, 60N under the scheduling of the second monitoring signals 411, 412, 41N.

[0063] Furthermore, the second processing unit 300 may further include at least one group of first signal acquisition circuits 331, 332, 33N; the input signal terminals 601, 602, 60N are electrically connected and / or communicatively connected to the first signal acquisition circuits 331, 332, 33N, and then relevant signals are acquired and transmitted by the input signal terminals 601, 602, 60N.

[0064] Furthermore, the second processing unit 300 may further include at least one group of first scheduling circuits 311, 312, 31N; the first scheduling circuits 311, 312, 31N respond to the instructions sent by the first processing unit 100 via the first communication unit 200, and send first monitoring signals 401, 402, 40N to the first conditioning unit 500.

[0065] Furthermore, the input signal terminals 601, 602, 60N may at least include a first port 611, 612 and a second port 621, 622; which are respectively used to acquire different or the same signals.

[0066] Furthermore, the input signal terminals 601, 602, 60N may further include third ports 631, 632; the signals connected to the third ports 631, 632 include ground signals, zero-level signals or other reference signals, and the signals passing through the third ports 631, 632 can provide reference signals to relevant circuits.

[0067] Specifically, the second ports 621, 622 can be used to receive redundant signals from the first ports 611, 612, and are used to verify or ensure the stable and reliable acquisition and transmission of relevant signals, improving the robustness of the system.

[0068] Among them, the signal acquisition control circuits 301, 302, 30N further include at least one group of second communication units 321, 32N; the applicable range of relevant circuits is further expanded, and the second processing unit can be either an intelligent system distributed on different boards or chips, or a more extensive system connected through communication.

[0069] Specifically, the first signal acquisition circuits 331, 332, 33N acquire signals from the input signal terminals 601, 602, 60N via the second communication units 321, 32N and / or are electrically connected and / or communicatively connected to the input signal terminals 601, 602, 60N.

[0070] Furthermore, the first signal acquisition circuits 331, 332, 33N may include at least one group of AD conversion circuits; the AD conversion circuits are electrically connected and / or communicatively connected to the input signal terminals 601, 602, 60N.

[0071] Furthermore, the first scheduling circuits 311, 312, 31N may at least include one group of PWM circuits; the PWM circuits are electrically connected and / or communicatively connected to the signal conditioning circuits 501, 502, 50N.

[0072] Among them, the first scheduling circuits 311, 312, 31N may at least include two groups of PWM circuits; the PWM circuits are controlled using different duty cycle DCL timings.

[0073] Specifically, the PWM circuit may include a first PWM circuit and a second PWM circuit; the width of the duty cycle DCL timing of the first PWM circuit is successively 10%, 20%, 30%... 100% of the maximum pulse width over time; the width of the duty cycle DCL timing of the second PWM circuit is successively 100%, 80%, 70%... 10% of the maximum pulse width over time.

[0074] Further, in a specific application scenario or industry background, the security level of the first processing unit 100 needs to comply with a preset first standard; the security level of the second processing unit 300 can also optionally comply with a preset second standard or be not restricted by the preset standard.

[0075] Specifically, the signal transmission channels established by the first communication unit 200 and / or the second communication units 321, 32N can optionally comply with at least one communication standard and / or protocol among CAN, SPI, and UART.

[0076] Among them, the first standard and the second standard can be the ISO26262 ASIL standard; in particular, the first standard can be at least one level higher than the second standard.

[0077] Further, if the above circuit is used in a signal acquisition module, a communication chip, an intelligent vehicle, or other application fields, the relevant circuit can obtain a circuit acquisition, transmission, monitoring, security, or protection level based on a higher security level.

[0078] Specifically, in the scenarios of the above signal acquisition module, communication chip, intelligent vehicle, or other application fields, the first processing unit 100 and the second processing unit 300 are integrated on different boards or different chips; the monitoring circuit outputs signals, reference data, reference voltages, and / or instructions collected by at least one of the input signal terminals 601, 602, 60N to a preset port.

[0079] At this time, the security level or reliability of the entire system will be improved and guaranteed according to the standard that the first processing system can achieve as follows:

[0080] Such as Figure 3 , which is a schematic diagram of inter-board safe signal sampling in an embodiment of the present invention; among them, for the system (microcontroller) MCU, a low-cost hardware solution can be selected, so that the slave MCU only meets a lower ASIL automotive safety integrity level, or even is not rated; at this time, as long as the main MCU meets the ASIL level required by the entire controller or system, the safety indicators of the entire controller or system can be achieved.

[0081] Specifically, the main MCU of the first processing unit 100 with a high security level HA (High ASIL) sends a PWM duty cycle DCL output request to the slave MCU with a low security level LA (Low ASIL) or not rated for security through the first communication unit 200 to implement signal sampling and transmission monitoring.

[0082] Among them, in order to improve the diagnostic coverage rate, this PWM duty cycle DCL request changes over time, for example: 10%, 20%, 30%... 100%. When the MCU (Low ASIL) receives the PWM duty cycle DCL request, it sends out a PWM wave with the corresponding duty cycle DCL through the single-chip microcomputer PWM module. The output signal of this PWM channel is connected to the sampling group ADC-G (ADC Group) of the analog-to-digital converter ADC331 where the safety signal is located after passing through the conditioning circuit 501.

[0083] In addition, one pin 631 in the above sampling group ADC-G can be selected to be grounded as a reference; finally, send the Figure 3 four ADC sampling values to the high safety level HA (High ASIL) for range and rationality verification.

[0084] Through this solution, not only can the failure modes such as Stuck, drift, and non-linear of the ADC where the MCU (Low ASIL) safety signal is located be covered, but also the hardware resources such as the power supply, clock, instruction set, and memory of the MCU (Low ASIL) involved in ADC sampling and transmission are covered.

[0085] For the communication path between the MCU (Low ASIL) and the MCU (High ASIL), due to the existence of the PWM signal that changes over time, even without adding other safety mechanisms additionally, a relatively high diagnostic coverage rate can be achieved.

[0086] If CAN communication is adopted, a standard E2E (End-To-End) check, such as the algorithm recommended by AUTOSARE2ELibrary, can be additionally added to further improve the diagnostic coverage rate.

[0087] In order to cover the failure of the sensor itself, the signals (Signal) of the first ports 611 and 612 and the redundant signals (Signal_Redundant) of the second ports 621 and 622 can adopt the SC (Sensor Correlation) sensor error correction method recommended by the ISO26262 standard: by adding a hardware operational amplifier circuit, two different slope conversion relationships between the Raw value and the physical value are obtained to avoid the influence of common cause failures caused by the environment and the like on the two-way sampling.

[0088] Such as Figure 4 , an embodiment of the present invention: schematic diagram of multiple ADC sampling groups (using the same PWM signal); among them, the slave MCU (Low ASIL) can also be other types of control chips, such as FPGA, CPLD, DSP or other similar chips CHIP (Low ASIL) in other forms.

[0089] If there are many sampling signals from the subordinate MCU (Low ASIL) and multiple ADC sampling groups are required, the above solution can be extended: for example Figure 4 As shown, in the case of two ADC sampling groups, the main MCU (High ASIL) sends a request for the duty cycle DCL of the PWM wave, and the two ADC sampling groups can use the same PWM signal as the monitoring reference.

[0090] For example Figure 5 , in order to further improve the diagnostic coverage rate and prevent the adhesion of hardware such as memories, it is also possible to send requests for the duty cycle DCL of two PWM waves, and the duty cycle DCL of the reference PWM signals corresponding to the two ADC sampling groups can adopt different change rules: for example, for the ADC1 sampling group, the change rule of the PWM signal can be 10%, 20%, 30%... 100%; while for the ADC2 sampling group, the change rule of the PWM signal can be 100%, 80%, 70%... 10%.

[0091] In addition, it is also possible to implement a sampling and transmission monitoring solution as shown Figure 6 among multiple slave microcontrollers. The working principle is similar and will not be elaborated here.

[0092] Again, as shown Figure 7 in this solution, the PWM hardware resource of the chip CHIP (Low ASIL) can also be other voltage-controllable hardware resources P (Part). For example: it can be DO (Digital Output) or similar P resources; by sending a request from the main MCU, the reference voltage change can be controlled by the DO.

[0093] Moreover, as shown Figure 8 : Combining the characteristics of the sampled signal itself, the reference voltage output can also be dynamically loaded onto the sampled signal, and the rationality verification is performed through the software of the main MCU (High ASIL) to cover the failures in the signal sampling and transmission paths.

[0094] For example Figure 9 , the ADC digital-to-analog conversion unit located within CHIP (Low ASIL) can also be a sampling device 331 independent of CHIP (Low ASIL), and the collected signals 611, 621, etc. are transmitted to CHIP (Low ASIL) through communication methods 321 such as CAN / SPI / UART.

[0095] For example Figure 11 , the sampling transmission monitoring method includes the host computer instruction synchronous transmission step 11, the slave computer synchronous conditioning feedback step 22, the slave computer composite sampling conversion step 33, and the host computer comprehensive verification step 44.

[0096] In step 11, the host computer and the slave computer work synchronously. By obtaining at least one first scheduling signal from the first processing unit 100 of the host computer, the synchronization of the host computer to the slave computer is realized; wherein, the first scheduling signal is a voltage-controlled signal that changes with time.

[0097] In step 22, the first scheduling signal is transmitted to the conditioning circuit to generate second monitoring signals 411, 412, 41N; at the same time, the second monitoring signals 411, 412, 41N are fed back or loaded to the second processing unit 300; wherein, the second processing unit 300 of the slave computer includes at least one signal acquisition control circuit 301, 302, 30N.

[0098] In steps 33 and 44, at least one set of redundant signal pairs is collected and sent to the first processing unit 100 of the host computer together with the second monitoring signals 411, 412, 41N for verification; wherein, the redundant signal pair includes a first signal and a second signal, and the second signal is a redundant signal of the first signal.

[0099] Further, in step 33, a grounding signal can also be superimposed as the input of the first signal acquisition circuits 331, 332, 33N; wherein, the first scheduling signal includes a PWM signal with a time-varying duty cycle or a controllable voltage signal dominated by the first processing unit 100 of the host computer; wherein, the second processing unit 300 of the slave computer further includes at least one set of first scheduling circuits 311, 312, 31N; the first scheduling circuits 311, 312, 31N respond to the instructions sent by the first processing unit 100 of the host computer via the first communication unit 200 and send first monitoring signals 401, 402, 40N to the first conditioning unit 500; the input signal terminals 601, 602, 60N include at least a first port 611, 612 and a second port 621, 622.

[0100] Specifically, the input signal terminals 601, 602, 60N may further include third ports 631, 632; the signals connected to the third ports 631, 632 include ground signals, zero-level signals or other reference signals; the second ports 621, 622 receive redundant signals from the first ports 611, 612; the signal acquisition control circuits 301, 302, 30N further include at least one group of second communication units 321, 32N; the first signal acquisition circuits 331, 332, 33N acquire signals from the input signal terminals 601, 602, 60N and / or are electrically connected and / or communicatively connected to the input signal terminals 601, 602, 60N via the second communication units 321, 32N; the first signal acquisition circuits 331, 332, 33N include at least one group of AD conversion circuits; the AD conversion circuits are electrically connected and / or communicatively connected to the input signal terminals 601, 602, 60N; the first scheduling circuits 311, 312, 31N include at least one group of PWM circuits; the PWM circuits are electrically connected and / or communicatively connected to the signal conditioning circuits 501, 502, 50N to achieve signal synchronization and control.

[0101] The input signal serves as the given information of the control system, and its ASIL level will directly affect the ASIL level of the entire system. Therefore, it is crucial for the design of safety-critical systems.

[0102] In the context of reducing costs and improving integration, the trend of "multiple functions in one" for controllers is becoming increasingly obvious. When there are multiple MCUs on-board and between boards in a product, it is particularly important and complex to ensure the ASIL level of the entire sampling path.

[0103] By adopting the solution disclosed in the embodiments of the present invention, under the monitoring or management of a high-level main MCU, the ASIL level required by the entire controller can be achieved. For a slave MCU, even if it only has a lower ASIL level or no safety level is set, when the master and slave MCUs communicate via CAN, SPI, or UART, a higher ASIL level can still be achieved according to the above technical solution.

[0104] It should be noted that the above embodiments are only for more clearly illustrating the technical solutions of the present invention. Those skilled in the art can understand that the implementation manners of the present invention are not limited to the above content. Obvious changes, substitutions or replacements based on the above content do not exceed the scope covered by the technical solutions of the present invention; without departing from the concept of the present invention, other implementation manners will also fall within the scope of the present invention.

Claims

1. A sampling and transmission monitoring circuit, comprising: A first processing unit (100), a first communication unit (200), a second processing unit (300), and a first conditioning unit (500); The first processing unit (100) and the second processing unit (300) establish a signal transmission channel via the first communication unit (200); The second processing unit (300) includes at least one set of signal acquisition control circuits (301, 302, 30N); The signal acquisition control circuits (301, 302, 30N) respond to instructions sent by the first processing unit (100) via the first communication unit (200), and send first monitoring signals (401, 402, 40N) to the first conditioning unit (500); The first conditioning unit (500) includes at least one set of signal conditioning circuits (501, 502, 50N); The signal conditioning circuits (501, 502, 50N) respond to the first monitoring signals (401, 402, 40N) and return second monitoring signals (411, 412, 41N) to the signal acquisition control circuits (301, 302, 30N); The signal acquisition control circuits (301, 302, 30N) are electrically connected and / or communicatively connected to at least one set of input signal terminals (601, 602, 60N) under the scheduling of the second monitoring signals (411, 412, 41N).

2. The monitoring circuit according to claim 1, wherein: The second processing unit (300) further includes at least one set of first signal acquisition circuits (331, 332, 33N); The input signal terminals (601, 602, 60N) are electrically connected and / or communicatively connected to the first signal acquisition circuits (331, 332, 33N).

3. The monitoring circuit according to claim 2, wherein: The second processing unit (300) further includes at least one set of first scheduling circuits (311, 312, 31N); The first scheduling circuits (311, 312, 31N) respond to instructions sent by the first processing unit (100) via the first communication unit (200), and send first monitoring signals (401, 402, 40N) to the first conditioning unit (500).

4. The monitoring circuit according to claim 2 or 3, wherein: The input signal terminals (601, 602, 60N) include at least a first port (611, 612) and a second port (621, 622).

5. The monitoring circuit according to claim 4, wherein: The input signal terminals (601, 602, 60N) further include a third port (631, 632); The signals connected to the third port (631, 632) include a ground signal, a zero-level signal, or other reference signals.

6. The monitoring circuit according to claim 5, wherein: The second port (621, 622) receives redundant signals from the first port (611, 612).

7. The monitoring circuit according to claim 3, wherein: The signal acquisition control circuit (301, 302, 30N) further includes at least one set of second communication units (321, 32N); The first signal acquisition circuit (331, 332, 33N) acquires signals from the input signal terminals (601, 602, 60N) and / or is electrically connected and / or communicatively connected to the input signal terminals (601, 602, 60N) via the second communication units (321, 32N).

8. The monitoring circuit according to claim 3, wherein: The first signal acquisition circuit (331, 332, 33N) includes at least one set of AD conversion circuits; The AD conversion circuit is electrically connected and / or communicatively connected to the input signal terminals (601, 602, 60N); The first scheduling circuit (311, 312, 31N) includes at least one set of PWM circuits; The PWM circuit is electrically connected and / or communicatively connected to the signal conditioning circuit (501, 502, 50N).

9. The monitoring circuit according to claim 3, wherein: The first scheduling circuit (311, 312, 31N) includes at least two sets of PWM circuits; The PWM circuits are controlled with different duty cycle timings.

10. The monitoring circuit according to claim 9, wherein: The PWM circuit includes a first PWM circuit and a second PWM circuit; The duty cycle timings of the first PWM circuit have widths that are successively 10%, 20%, 30%... 100% of the maximum pulse width over time; The duty cycle timings of the second PWM circuit have widths that are successively 100%, 80%, 70%... 10% of the maximum pulse width over time.

11. The monitoring circuit according to claim 1, wherein: The safety level of the first processing unit (100) conforms to a preset first standard; The safety level of the second processing unit (300) is not subject to a preset standard.

12. The monitoring circuit according to claim 7, wherein: The signal transmission channels established by the first communication unit (200) and / or the second communication units (321, 32N) conform to at least one communication standard and / or protocol among CAN, SPI, and UART.

13. The monitoring circuit according to claim 1, wherein: The safety level of the first processing unit (100) conforms to a preset first standard; The safety level of the second processing unit (300) conforms to a preset second standard; The first standard and the second standard are ISO26262 ASIL standards; The first standard is at least one level higher than the second standard.

14. A signal acquisition module, comprising: Any one of the monitoring circuits according to claims 1, 2, 3, 5, 6, 8, 10, 13; The first processing unit (100) and the second processing unit (300) are integrated on different circuit boards or different chips; The monitoring circuit outputs signals, reference data, reference voltage, and / or instructions acquired from at least one of the input signal terminals (601, 602, 60N) to a preset port.

15. A communication chip, comprising a chip body; The chip body is lithographed or prepared with a monitoring circuit as described in any one of claims 1, 2, 3, 5, 6, 8, 10, 13; and / or a signal acquisition module as described in claim 14; The processing process of the communication chip body includes single-chip / board MCU, FPGA, CPLD, DSP process or product.

16. An intelligent vehicle, comprising: The communication chip as described in claim 15.

17. A sampling and transmission monitoring method, characterized in that Comprising: The second processing unit (300) obtains at least one first scheduling signal from the first processing unit (100), and the first scheduling signal is a voltage-controlled signal that changes with time; The second processing unit (300) transmits the first scheduling signal to the conditioning circuit to generate second monitoring signals (411, 412, 41N); Feed back or load the second monitoring signals (411, 412, 41N) to the second processing unit (300); wherein the second processing unit (300) includes at least one signal acquisition control circuit (301, 302, 30N); Acquire at least one set of redundant signal pairs and send them to the first processing unit (100) together with the second monitoring signals (411, 412, 41N) for verification; wherein, the redundant signal pair includes a first signal and a second signal, and the second signal is a redundant signal of the first signal.

18. The method as described in claim 17, further comprising: The second processing unit (300) further includes at least one set of first signal acquisition circuits (331, 332, 33N); Superimpose a ground signal as the input of the first signal acquisition circuits (331, 332, 33N); wherein, The first scheduling signal includes a PWM signal with a duty cycle that changes with time or a controllable voltage signal dominated by the first processing unit (100); the second processing unit (300) further includes at least one set of first scheduling circuits (311, 312, 31N); the first scheduling circuits (311, 312, 31N) respond to instructions sent by the first processing unit (100) via the first communication unit (200) and send first monitoring signals (401, 402, 40N) to the first conditioning unit (500); the input signal terminals (601, 602, 60N) include at least a first port (611, 612) and a second port (621, 622).

19. The method as described in claim 18, wherein, The input signal terminals (601, 602, 60N) further include a third port (631, 632); the signals connected to the third port (631, 632) include a ground signal, a zero-level signal or other reference signals; the second port (621, 622) receives the redundant signals of the first port (611, 612); The signal acquisition control circuits (301, 302, 30N) further include at least one set of second communication units (321, 32N); the first signal acquisition circuits (331, 332, 33N) acquire signals from the input signal terminals (601, 602, 60N) and / or are electrically connected and / or communicatively connected to the input signal terminals (601, 602, 60N) via the second communication units (321, 32N). The first signal acquisition circuits (331, 332, 33N) include at least one set of AD conversion circuits; the AD conversion circuits are electrically connected and / or communicatively connected to the input signal terminals (601, 602, 60N); the first scheduling circuits (311, 312, 31N) at least include one set of PWM circuits; the PWM circuits are electrically connected and / or communicatively connected to the signal conditioning circuits (501, 502, 50N).

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