Method of operating a host and a memory system connected to the host

Abstract

A method of operating a host that communicates with a memory system including a log area and a data area is provided. The method of operating the host includes determining to update old data stored in the memory system, transmitting a write command to the memory system for writing log data and meta log data for updating the old data to the log area, and in response to a write completion of the meta log data and the log data received from the memory system, transmitting a write command to the memory system for writing new data corresponding to the log data to the data area. Each of the meta log data and the log data includes a descriptor identifier (ID) indicating a same write transaction.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority to Korean Patent Application No. 10-2021-0016972, filed on February 5, 2021, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] This disclosure relates to an electronic device, and more particularly, to a method of operating a host computer and a memory system connected to the host computer. Background Technology

[0004] The host computer can communicate with and control the operation of the memory system. The memory system may include semiconductor memory devices and controllers.

[0005] Semiconductor memory devices can be formed as a two-dimensional structure arranged horizontally on a semiconductor substrate, or as a three-dimensional structure stacked vertically on a semiconductor substrate. Three-dimensional semiconductor memory devices are designed to address the limited integration density of two-dimensional semiconductor memory devices and can include multiple memory cells stacked vertically on a semiconductor substrate.

[0006] A controller can control the operation of a semiconductor memory device. Summary of the Invention

[0007] Embodiments of this disclosure provide a host computer and its operating method that can improve the write speed of a memory system.

[0008] According to embodiments of this disclosure, a method for operating a host that communicates with a memory system including a log area and a data area includes: determining old data stored in the memory system to be updated; transmitting a write command to the memory system for writing log data and meta-log data used to update the old data into the log area; and, in response to the completion of writing meta-log data and log data received from the memory system, transmitting a write command to the memory system for writing new data corresponding to the log data into the data area. Each of the meta-log data and the log data includes a descriptor identifier (ID) indicating the same write transaction.

[0009] In embodiments of this disclosure, the method may further include: in response to the completion of writing new data received from the memory system, controlling the memory system to invalidate old data stored in the data area.

[0010] In an embodiment of the disclosure, the method can further include detecting a sudden power failure of the memory system, reading meta log data and log data stored in the log area, and controlling the memory system to recover a write operation before the sudden power failure based on the meta log data and the log data.

[0011] In an embodiment of the disclosure, controlling the memory system to recover the write operation before the sudden power failure based on the meta log data and the log data can include comparing a descriptor ID of the meta log data with a descriptor ID of the log data, and when the descriptor ID of the meta log data is identical to the descriptor ID of the log data, controlling the memory system to write the log data of the log area to a data area.

[0012] According to another embodiment of the disclosure, a method of operating a host that communicates with a memory system including a log area and a data area, the method includes detecting a sudden power failure of the memory system, reading meta log data and log data stored in the log area, and controlling the memory system to recover a write operation before the sudden power failure based on the meta log data and the log data. Each of the meta log data and the log data includes a descriptor identifier (ID) that identifies a transaction including corresponding data.

[0013] In an embodiment of the disclosure, controlling the memory system to recover the write operation before the sudden power failure based on the meta log data and the log data can include determining whether a descriptor ID of the meta log data and a descriptor ID of the log data are identical to each other.

[0014] In an embodiment of the disclosure, controlling the memory system to recover the write operation before the sudden power failure based on the meta log data and the log data can further include, in response to determining that the descriptor ID of the meta log data and the descriptor ID of the log data are identical to each other, controlling the memory system to write the log data of the log area to a data area.

[0015] In an embodiment of the disclosure, controlling the memory system to recover the write operation before the sudden power failure based on the meta log data and the log data can further include, in response to determining that the descriptor ID of the meta log data and the descriptor ID of the log data are different from each other, controlling the memory system to delete or invalidate the meta log data and the log data in the log area.

[0016] In embodiments of the present disclosure, the log data can include first page data and second page data, the first page data can include first partial data and first parity data, and the second page data can include second partial data and second parity data. The first parity data can be generated based on the first partial data, and the second parity data can be generated based on the first partial data and the second partial data. Controlling the memory system to recover the write operation before the sudden power failure based on the meta log data and the log data can include determining whether the parity of the log data has passed.

[0017] In embodiments of the present disclosure, controlling the memory system to recover the write operation before the sudden power failure based on the meta log data and the log data can further include, in response to determining that the parity of the log data has passed, controlling the memory system to write the log data of the log area to the data area.

[0018] In embodiments of the present disclosure, controlling the memory system to recover the write operation before the sudden power failure based on the meta log data and the log data can further include, in response to determining that the parity of the log data has not passed, controlling the memory system to delete or invalidate the meta log data and the log data of the log area.

[0019] According to still another embodiment of the present disclosure, a method of operating a memory system including a log area and a data area includes receiving write data and a write command from a host and writing log data generated based on the write data to the log area. The write data includes first to Nth partial data, and the log data includes first to Nth page data. The i-th page data among the first to Nth page data includes the i-th partial data among the first to Nth partial data and the i-th parity data among first to Nth parity data. The i-th parity data is generated based on at least one of the first to (i-1)th partial data and the i-th partial data. Here, N is a natural number greater than 1, and i is a natural number greater than or equal to 1 and less than or equal to N.

[0020] In embodiments of the present disclosure, the i-th parity data can be generated by a cyclic redundancy check method with respect to at least one of the first to (i-1)th partial data and the i-th partial data.

[0021] In embodiments of the present disclosure, the i-th parity data can be generated based on the first to i-th partial data.

[0022] In embodiments of the present disclosure, the i-th parity data can be generated by a cyclic redundancy check method with respect to the first to i-th partial data.

[0023] The present technology can provide a host and an operating method thereof capable of improving the write speed of a memory system.

[0024] According to another embodiment of this disclosure, a data processing system includes a host and a memory system coupled to the host. The memory system includes a controller and a memory device coupled to the controller. The memory device includes a log area and a data area. The controller is configured to: control the memory device to write log data and meta-log data into the log area, wherein each of the log data and meta-log data includes a descriptor; read the log data and meta-log data from the log area when a sudden power failure is detected; determine whether the descriptor of the meta-log data is the same as the descriptor of the log data; and when it is determined that the descriptor of the meta-log data is the same as the descriptor of the log data, write the log data from the log area into the data area.

[0025] In embodiments of this disclosure, the controller may be configured to: control the memory device to delete log data in the log region when it is determined that the descriptor of the meta log data is different from the descriptor of the log data. Attached Figure Description

[0026] FIG. 1 This is a block diagram illustrating a host and a memory system communicating with the host according to an embodiment of the present disclosure.

[0027] FIG. 2 This illustrates an embodiment according to the present disclosure. FIG. 1 A block diagram of the semiconductor memory devices included in the memory system.

[0028] FIG. 3 This illustrates an embodiment according to the present disclosure. FIG. 2 A diagram of a memory cell array.

[0029] FIG. 4 This illustrates an embodiment according to the present disclosure. FIG. 3 The circuit diagram of storage block BLKa in storage blocks BLK1 to BLKz.

[0030] FIG. 5 This illustrates an embodiment according to the present disclosure. FIG. 3 The circuit diagram of storage block BLKb in storage blocks BLK1 to BLKz.

[0031] FIG. 6 This illustrates an embodiment according to the present disclosure. FIG. 2 The circuit diagram of memory block BLKc among memory blocks BLK1 to BLKz included in the memory cell array 110.

[0032] FIG. 7 This illustrates an embodiment according to the present disclosure. FIG. 2 A diagram showing the log area and data area included in the memory cell array.

[0033] FIG. 8 FIG. 8 is a flowchart illustrating a method of operating a host according to an embodiment of the present disclosure.

[0034] FIG. 9A FIG. 9B FIG. 9C FIG. 9 is a diagram illustrating a method of operating a host according to an embodiment of the present disclosure. FIG. 8

[0035] FIG. 10A FIG. 10B FIG. 10C FIG. 10 is a diagram illustrating a structure of data written in a log area or a data area according to an embodiment of the present disclosure. FIG. 8

[0036] FIG. 11 FIG. 11 is a flowchart illustrating a method of operating a host according to another embodiment of the present disclosure.

[0037] FIG. 12A FIG. 12B FIG. 12 is a diagram illustrating a method of operating a host according to an embodiment of the present disclosure. FIG. 11

[0038] FIG. 13A FIG. 13B FIG. 13C FIG. 13 is a diagram illustrating a structure of data written in a log area or a data area according to an embodiment of the present disclosure. FIG. 11

[0039] FIG. 14 FIG. 14 is a flowchart illustrating a method of operating a host according to yet another embodiment of the present disclosure.

[0040] FIG. 15A FIG. 15B FIG. 15 is a diagram illustrating a method of writing data of a log area to a data area after a sudden power off (SPO) occurs according to an embodiment of the present disclosure. FIG. 14

[0041] FIG. 16A FIG. 16 is a flowchart illustrating a method of operating a host according to yet another embodiment of the present disclosure. FIG. 16B

[0042] FIG. 17A FIG. 17 is a diagram illustrating a method of writing data of a log area to a data area after a SPO occurs according to an embodiment of the present disclosure. FIG. 17B FIG. 16A

[0043] FIG. 18 FIG. 18 is a diagram illustrating a structure of data written in a log area or a data area according to an embodiment of the present disclosure. FIG. 1 ​​​​​​​​​​​​​​​​a block diagram of an example of the controller shown in FIG. 1.

[0044] FIG. 19 is a block diagram of a memory system 1000 according to an embodiment of the disclosure. FIG. 1

[0045] FIG. 20 is a block diagram of a computing system including the memory system described with reference to FIG. 19 FIG. 1 according to an embodiment of the disclosure. DETAILED DESCRIPTION

[0046] The specific structure or function descriptions shown according to embodiments of the concepts disclosed in this specification or application are only for describing embodiments according to the disclosure. Embodiments according to the disclosure can be implemented in various forms and should not be interpreted as being limited to the embodiments described in this specification.

[0047] FIG. 1 is a block diagram of a host 300 and a memory system 1000 in communication with the host 300 according to an embodiment of the disclosure.

[0048] With reference to FIG. 1 , the memory system 1000 includes a semiconductor memory device 100 and a controller 200. In addition, the memory system 1000 is in communication with the host 300. The controller 200 controls overall operations of the semiconductor memory device 100. In addition, the controller 200 controls operations of the semiconductor memory device 100 based on a command received from the host 300.

[0049] The host 300 can control operations of the memory system 1000. For example, the host 300 can transfer a write command and data to the memory system 1000. The memory system 1000 can store the data in the semiconductor memory device 100 based on the received write command. As another example, the host 300 can transfer a read command to the memory system 1000. The memory system 1000 can read data stored in the semiconductor memory device 100 based on the received read command. In addition, the memory system 1000 can transfer the read data to the host 300.

[0050] FIG. 2 is a block diagram of a semiconductor memory device 100 included in the memory system 1000 according to an embodiment of the disclosure. FIG. 1

[0051] With reference to FIG. 2 , the semiconductor memory device 100 includes a memory cell array 110, an address decoder 120, a read and write circuit 130, a control logic 140, and a voltage generator 150.

[0052] ​​The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to the address decoder 120 through word lines WL. The plurality of memory blocks BLK1 to BLKz are connected to the read and write circuit 130 through bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. In an embodiment, the plurality of memory cells are non-volatile memory cells, and can be configured by non-volatile memory cells having a vertical channel structure. The memory cell array 110 can be configured as a two-dimensional structure of memory cells. According to an embodiment, the memory cell array 110 can be configured as a three-dimensional structure of memory cells. Each of the plurality of memory cells included in the memory cell array can store at least one bit of data. In an embodiment, each of the plurality of memory cells included in the memory cell array 110 can be a single layer cell (SLC) storing one bit of data. In another embodiment, each of the plurality of memory cells included in the memory cell array 110 can be a multi layer cell (MLC) storing two bits of data. In yet another embodiment, each of the plurality of memory cells included in the memory cell array 110 can be a triple layer cell (TLC) storing three bits of data. In yet another embodiment, each of the plurality of memory cells included in the memory cell array 110 can be a quad layer cell (QLC) storing four bits of data. According to an embodiment, the memory cell array 110 can include a plurality of memory cells each storing five or more bits of data.

[0053] The address decoder 120, the read and write circuit 130, the control logic 140, and the voltage generator 150 operate as peripheral circuits that drive the memory cell array 110. The address decoder 120 is connected to the memory cell array 110 through the word lines WL. The address decoder 120 is configured to operate in response to control of the control logic 140. The address decoder 120 receives an address through an input / output buffer (not shown) inside the semiconductor memory device 100.

[0054] The address decoder 120 is configured to decode a block address among the received address. The address decoder 120 selects at least one memory block according to the decoded block address. In addition, during a read operation, the address decoder 120 applies a read voltage Vread generated by the voltage generator 150 to a selected word line of the selected memory block at a read voltage application operation, and applies a pass voltage Vpass to the remaining unselected word lines. In addition, during a program verify operation, the address decoder 120 applies a verify voltage generated by the voltage generator 150 to a selected word line of the selected memory block, and applies a pass voltage Vpass to the remaining unselected word lines.

[0055] The address decoder 120 is configured to decode a column address of a received address. The address decoder 120 transmits the decoded column address to the read and write circuit 130.

[0056] The read operation and the program operation of the semiconductor memory device 100 are performed in units of pages. An address received at a request for the read operation and the program operation includes a block address, a row address, and a column address. The address decoder 120 selects one memory block and one word line according to the block address and the row address. The column address is decoded by the address decoder 120 and is provided to the read and write circuit 130.

[0057] The address decoder 120 can include a block decoder, a row decoder, a column decoder, an address buffer, etc.

[0058] The read and write circuit 130 includes a plurality of page buffers PB1 to PBm. The read and write circuit 130 can operate as a "read circuit" during a read operation of the memory cell array 110 and can operate as a "write circuit" during a write operation of the memory cell array 110. The plurality of page buffers PB1 to PBm are connected to the memory cell array 110 through bit lines BL1 to BLm. During a read operation and a program verify operation, in order to sense a threshold voltage of a memory cell, the plurality of page buffers PB1 to PBm sense a change in an amount of current flowing according to a program state of a corresponding memory cell through a sense node while continuously supplying a sense current to a bit line connected to the memory cell, and latch the sensed change as sense data. The read and write circuit 130 operates in response to a page buffer control signal output from the control logic 140.

[0059] During a read operation, the read and write circuit 130 senses data of a memory cell, temporarily stores read data, and outputs the data DATA to an input / output buffer (not shown) of the semiconductor memory device 100. In an embodiment, the read and write circuit 130 can include a column selection circuit, etc., in addition to the page buffer (or page register).

[0060] The control logic 140 is connected to the address decoder 120, the read and write circuit 130, and the voltage generator 150. The control logic 140 receives a command CMD and a control signal CTRL through an input / output buffer (not shown) of the semiconductor memory device 100. The control logic 140 can be configured to control overall operations of the semiconductor memory device 100 in response to the control signal CTRL. In addition, the control logic 140 outputs a control signal for adjusting a sense node pre-charge potential level of the plurality of page buffers PB1 to PBm. The control logic 140 can control the read and write circuit 130 to perform a read operation of the memory cell array 110.

[0061] The voltage generator 150 generates the read voltage Vread and the pass voltage Vpass during the read operation in response to the control signal output from the control logic 140. To generate a plurality of voltages having various voltage levels, the voltage generator 150 can include a plurality of pump capacitors that receive an internal power supply voltage, and generate a plurality of voltages by selectively activating the plurality of pump capacitors in response to the control of the control logic 140. As described above, the voltage generator 150 can include a charge pump, and the charge pump can include the plurality of pump capacitors described above. The specific configuration of the charge pump included in the voltage generator 150 can be variously designed as needed.

[0062] The address decoder 120, the read and write circuit 130, and the voltage generator 150 can function as "peripheral circuits" that perform read, write, and erase operations on the memory cell array 110. The peripheral circuits perform the read, write, and erase operations on the memory cell array 110 based on the control of the control logic 140.

[0063] FIG. 3 is a diagram illustrating an embodiment of the memory cell array 110 according to an embodiment of the disclosure. FIG. 2

[0064] Referring to FIG. 3 , the memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. Each memory block can have a three-dimensional structure. Each memory block includes a plurality of memory cells stacked on a substrate. The plurality of memory cells are arranged in the +X direction, the +Y direction, and the +Z direction. Referring to FIG. 4 and FIG. 5 the structure of each memory block is described in more detail.

[0065] FIG. 4 is a circuit diagram illustrating a memory block BLKa among the memory blocks BLK1 to BLKz according to an embodiment of the disclosure. FIG. 3

[0066] Referring to FIG. 4 , the memory block BLKa includes a plurality of cell strings CS11 to CS1m and CS21 to CS2m. In an embodiment, each of the plurality of cell strings CS11 to CS1m and the cell strings CS21 to CS2m can be formed in a "U" shape. In the memory block BLKa, m cell strings are arranged in the row direction (i.e., the +X direction). In FIG. 4 , two cell strings are arranged in the column direction (i.e., the +Y direction). However, this is for convenience of description, and it can be understood that three or more cell strings can be arranged in the column direction.

[0067] ​​Each of the plurality of cell strings CS11 to CS1m and the cell strings CS21 to CS2m includes at least one source select transistor SST, first to nth memory cells MC1 to MCn, a pipe transistor PT, and at least one drain select transistor DST.

[0068] Each of the select transistors SST and DST and the memory cells MC1 to MCn can have a similar structure. In an embodiment, each of the select transistors SST and DST and the memory cells MC1 to MCn can include a channel layer, a tunnel insulating layer, a charge storage layer, and a blocking insulating layer. In an embodiment, a pillar for providing the channel layer can be provided in each cell string. In an embodiment, a pillar for providing at least one of the channel layer, the tunnel insulating layer, the charge storage layer, and the blocking insulating layer can be provided in each cell string.

[0069] The source select transistor SST of each cell string is connected between a common source line CSL and the memory cells MC1 to MCp.

[0070] In an embodiment, the source select transistors of the cell strings arranged in the same row are connected to a source select line extending in the row direction, and the source select transistors of the cell strings arranged in different rows are connected to different source select lines. In FIG. 4 In an embodiment, the source select transistors of the cell strings CS11 to CS1m of the first row are connected to a first source select line SSL1. The source select transistors of the cell strings CS21 to CS2m of the second row are connected to a second source select line SSL2.

[0071] In another embodiment, the source select transistors of the cell strings CS11 to CS1m and the cell strings CS21 to CS2m can be commonly connected to one source select line.

[0072] The first to nth memory cells MC1 to MCn of each cell string are connected between the source select transistor SST and the drain select transistor DST.

[0073] The first to n-th memory cells MC1 to MCn can be divided into first to p-th memory cells MC1 to MCp and (p+1) to n-th memory cells MCp+1 to MCn. The first to p-th memory cells MC1 to MCp are arranged continuously in a direction opposite to the +Z direction and connected in series between the source selection transistor SST and the pipe transistor PT. The (p+1) to n-th memory cells MCp+1 to MCn are arranged sequentially along the +Z direction and connected in series between the pipe transistor PT and the drain selection transistor DST. The first to p-th memory cells MC1 to MCp and the (p+1) to n-th memory cells MCp+1 to MCn are connected to each other through the pipe transistor PT. The gates of the first to n-th memory cells MC1 to MCn of each cell string are connected to the first to n-th word lines WL1 to WLn, respectively.

[0074] The gate of the pipe transistor PT of each cell string is connected to the pipeline PL.

[0075] The drain selection transistor DST of each cell string is connected between the corresponding bit line and the memory cells MCp+1 to MCn. The drain selection transistors DST of the cell strings arranged along the row direction are connected to the drain selection lines extending along the row direction. The drain selection transistors of the cell strings CS11 to CS1m of the first row are connected to the first drain selection line DSL1. The drain selection transistors of the cell strings CS21 to CS2m of the second row are connected to the second drain selection line DSL2.

[0076] The cell strings arranged along the column direction are connected to the bit lines extending along the column direction. In FIG. 4 , the cell strings CS11 and CS21 of the first column are connected to the first bit line BL1. The cell strings CS1m and CS2m of the m-th column are connected to the m-th bit line BLm.

[0077] The memory cells connected to the same word line among the cell strings arranged along the row direction constitute one page. For example, the memory cells connected to the first word line WL1 among the cell strings CS11 to CS1m of the first row constitute one page. The memory cells connected to the first word line WL1 among the cell strings CS21 to CS2m of the second row constitute another page. The cell strings arranged along one row direction can be selected by selecting any one of the drain selection lines DSL1 and DSL2. One page of the selected cell strings can be selected by selecting any one of the word lines WL1 to WLn.

[0078] In another embodiment, even-numbered bit lines and odd-numbered bit lines can be provided instead of the first through mth bit lines BL1 through BLm. In addition, even-numbered cell strings among the cell strings CS11 through CS1m or CS21 through CS2m arranged in the row direction can be connected to the even-numbered bit lines, respectively, and odd-numbered cell strings among the cell strings CS11 through CS1m or CS21 through CS2m arranged in the row direction can be connected to the odd-numbered bit lines, respectively.

[0079] In an embodiment, at least one of the first through nth memory cells MC1 through MCn can be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce an electric field between the source select transistor SST and the memory cells MC1 through MCp. Alternatively, at least one dummy memory cell is provided to reduce an electric field between the drain select transistor DST and the memory cells MCp+1 through MCn. As more dummy memory cells are provided, the reliability of the operation of the memory block BLKa is improved, but the size of the memory block BLKa increases. As fewer memory cells are provided, the size of the memory block BLKa can be reduced, but the reliability of the operation of the memory block BLKa can be degraded.

[0080] To effectively control the at least one dummy memory cell, each of the dummy memory cells can have a desired threshold voltage. A program operation can be performed on all or part of the dummy memory cells before or after an erase operation on the memory block BLKa. When the erase operation is performed after the program operation is performed, the dummy memory cells can have the desired threshold voltage by controlling a voltage applied to a dummy word line connected to each of the dummy memory cells.

[0081] FIG. 5 is a circuit diagram of a memory block BLKb among the memory blocks BLK1 through BLKz of a memory block BLKa according to an embodiment of the disclosure. FIG. 3 is a circuit diagram of a memory block BLKb among the memory blocks BLK1 through BLKz of a memory block BLKa according to an embodiment of the disclosure.

[0082] Referring to FIG. 5 The memory block BLKb includes a plurality of cell strings CS11' through CS1m' and CS21' through CS2m'. Each of the plurality of cell strings CS11' through CS1m' and CS21' through CS2m' extends in the +Z direction. Each of the plurality of cell strings CS11' through CS1m' and CS21' through CS2m' includes at least one source select transistor SST, first through nth memory cells MC1 through MCn, and at least one drain select transistor DST stacked on a substrate (not shown) under the memory block BLK1'.

[0083] The source select transistor SST of each cell string is connected between a common source line CSL and the memory cells MC1 to MCn. The source select transistors of the cell strings arranged in the same row are connected to the same source select line. The source select transistors of the cell strings CS11' to CS1m' arranged in the first row are connected to a first source select line SSL1. The source select transistors of the cell strings CS21' to CS2m' arranged in the second row are connected to a second source select line SSL2. In another embodiment, the source select transistors of the cell strings CS11' to CS1m' and the cell strings CS21' to CS2m' can be commonly connected to one source select line.

[0084] The first to nth memory cells MC1 to MCn of each cell string are connected in series between the source select transistor SST and the drain select transistor DST. The gates of the first to nth memory cells MC1 to MCn are connected to the first to nth word lines WL1 to WLn, respectively.

[0085] The drain select transistor DST of each cell string is connected between a corresponding bit line and the memory cells MC1 to MCn. The drain select transistors of the cell strings arranged in the row direction are connected to a drain select line extending in the row direction. The drain select transistors of the cell strings CS11' to CS1m' of the first row are connected to a first drain select line DSL1. The drain select transistors of the cell strings CS21' to CS2m' of the second row are connected to a second drain select line DSL2.

[0086] Thus, FIG. 5 The storage block BLKb has an equivalent circuit similar to that of the storage block BLKa, except that the pass transistor PT is excluded from each cell string. FIG. 4

[0087] In another embodiment, instead of the first to mth bit lines BL1 to BLm, even and odd bit lines can be provided. In addition, among the cell strings CS11' to CS1m' or the cell strings CS21' to CS2m' arranged in the row direction, the even numbered cell strings can be connected to the even bit lines, respectively, and among the cell strings CS11' to CS1m' or the cell strings CS21' to CS2m' arranged in the row direction, the odd numbered cell strings can be connected to the odd bit lines, respectively.

[0088] ​In an embodiment, at least one of the first to nth memory cells MC1 to MCn can be used as a dummy memory cell. For example, at least one dummy memory cell is provided to reduce an electric field between the source select transistor SST and the memory cells MC1 to MCn. Alternatively, at least one dummy memory cell is provided to reduce an electric field between the drain select transistor DST and the memory cells MC1 to MCn. When more dummy memory cells are provided, the reliability of the operation of the memory block BLKb is improved, but the size of the memory block BLKb increases. With fewer memory cells provided, the size of the memory block BLKb can be reduced, but the reliability of the operation of the memory block BLKb can be reduced.

[0089] To effectively control the at least one dummy memory cell, each of the dummy memory cells can have a desired threshold voltage. A program operation can be performed on all or part of the dummy memory cells before or after an erase operation on the memory block BLKb. When the erase operation is performed after the program operation is performed, the dummy memory cells can have the desired threshold voltage by controlling a voltage applied to a dummy word line connected to each of the dummy memory cells.

[0090] FIG. 6 is a circuit diagram of a memory cell array 110 included in a memory block BLKc among memory blocks BLK1 to BLKz according to an embodiment of the disclosure. FIG. 2

[0091] Referring to FIG. 6 The memory block BLKc includes a plurality of cell strings CS1 to CSm. The plurality of cell strings CS1 to CSm can be connected to a plurality of bit lines BL1 to BLm, respectively. Each of the cell strings CS1 to CSm includes at least one source select transistor SST, first to nth memory cells MC1 to MCn, and at least one drain select transistor DST.

[0092] Each of the select transistors SST and DST and the memory cells MC1 to MCn can have a similar structure. In an embodiment, each of the select transistors SST and DST and the memory cells MC1 to MCn can include a channel layer, a tunnel insulating layer, a charge storage layer, and a blocking insulating layer. In an embodiment, a pillar for providing the channel layer can be provided in each cell string. In an embodiment, a pillar for providing at least one of the channel layer, the tunnel insulating layer, the charge storage layer, and the blocking insulating layer can be provided in each cell string.

[0093] The source select transistor SST of each cell string is connected between a common source line CSL and the memory cells MC1 to MCn.

[0094] ​The first to nth memory cells MC1 to MCn of each cell string are connected between a source select transistor SST and a drain select transistor DST.

[0095] The drain select transistor DST of each cell string is connected between a corresponding bit line and the memory cells MC1 to MCn.

[0096] Memory cells connected to the same word line constitute one page. A cell string CS1 to CSm can be selected by selecting a drain select line DSL. A page in the selected cell string can be selected by selecting any one of the word lines WL1 to WLn.

[0097] In another embodiment, even and odd bit lines can be provided instead of the first to mth bit lines BL1 to BLm. Even-numbered cell strings among the cell strings CS1 to CSm can be connected to even bit lines, respectively, and odd-numbered cell strings can be connected to odd bit lines, respectively.

[0098] FIG. 7 is a diagram illustrating a memory cell array 110 of a semiconductor memory device 100 according to an embodiment of the disclosure. FIG. 2 is a diagram of a log area and a data area included in the memory cell array 110 of the semiconductor memory device 100.

[0099] Referring to FIG. 7 , FIG. 2 The memory cell array 110 of the semiconductor memory device 100 illustrated in FIG. 1 can be divided into a log area and a data area. In an embodiment, a file system of the host 300 can divide a data storage area of the memory system 1000 into the log area and the data area.

[0100] In some embodiments, the host 300 can drive the memory system 1000 based on a log technique. In the log technique or log file system, after a region called a log is reserved, when a specific write operation occurs, data or metadata is first stored in the log area, not immediately in a logical block address location in the memory system 1000. All data and metadata related to a write operation are stored in the log area, and a stream of the data and metadata is grouped into a unit called a transaction. In this method, after several transactions are written in the log area, a specific transaction of the log area is written in a location (i.e., a final location of the data area) where the specific transaction is to be stored in the storage (i.e., the memory system 1000) by a background operation. When all data is stored in the data area, the transaction is deleted from the log area to obtain a log area space required for a next write operation.

[0101] In the case of using the log technique as described above, data consistency of the memory system 1000 can be maintained even if power supplied to the memory system 1000 is suddenly cut off, i.e., when a sudden power off (SPO) occurs. For example, when a write operation is stopped due to the SPO during the write operation, the result can be retained in each of the data area and the log area. The operation that is stopped while writing the data area can be an operation that exists in the form of a transaction that completely writes the log area according to the file system of the host 300. When power is supplied to the memory system 1000 again, the controller 200 can scan the log area to complete the write operation that is stopped in a short time. Also, there can be an operation that is stopped while being stored in the log area. In this case, an incomplete transaction can be stored in the log area and then stay in the stopped form. When power is supplied to the memory system 1000 again, such a transaction is ignored, thereby bringing consistency to the file system. In other words, consistency can be maintained by taking an approach of ignoring the transaction, so that all situations that can occur during a power failure are not broken in recovery or consistency.

[0102] FIG. 8 is a flowchart illustrating a method of operating a host according to an embodiment of the disclosure.

[0103] Referring to FIG. 8 The method of operating the host 300 includes determining to update data stored in the memory system 1000 (S110), transmitting a write command for writing meta log data for data update and log data to the log area of the memory system 1000 to the memory system (S130), transmitting a flush command to the memory system (S140), in response to completion of writing of the log data, transmitting a write command for writing commit data to the log area to the memory system (S150), transmitting a flush command to the memory system (S160), in response to completion of writing of the commit data, transmitting a write command for writing write data corresponding to the log data to the data area to the memory system (S170).

[0104] According to FIG. 8In the illustrated embodiment, the log data and the meta log data corresponding thereto are written to the log area through operation S130 and operation S140. That is, as operation S140 of transmitting the flush command to the memory system is performed, the memory system can start to actually write the meta log data and the log data to the log area. After the operation of writing the meta log data and the log data to the log area is completed, the commit data is written to the log area through operation S150 and operation S160. That is, as operation S160 of transmitting the flush command to the memory system is performed, the memory system can start to actually write the commit data to the log area. After the operation of writing the commit data to the log area is completed, the write data is written to the data area. The write data can be substantially the same data as the log data.

[0105] Accordingly, when the SPO occurs, in the process of writing the write data to the data area, the write operation can be recovered by writing the log data written to the log area as the write data to the data area by checking the commit data written to the log area when the memory system recovers from the SPO.

[0106] When the SPO occurs before the operation of writing the commit data to the log area is completed, it can be checked that the commit data is not completely written to the log area or that the commit data is not written to the log area when the memory system recovers from the SPO. In this case, the log data written to the log area can be ignored, and the corresponding transaction can be re-executed under the control of the host 300.

[0107] FIG. 9A 、 FIG. 9B and FIG. 9C is a diagram illustrating a method of operations of a host according to an embodiment of the disclosure. FIG. 8

[0108] Referring to FIG. 9A , old data DATA_O is stored in the data area of the memory cell array 110. As illustrated in FIG. 8 , the host 300 can determine to update the old data DATA_O stored in the memory cell array 110 in the memory system 1000 (S110).

[0109] According to the determination of operation S110, the host 300 transmits meta log data JMDATA, log data JDATA, and a write command WCMD to the controller 200 of the memory system 1000 (S130). Thereafter, although not illustrated in FIG. 1, the controller 200 of the memory system 1000 can write the meta log data JMDATA and the log data JDATA to the log area 120 and write the write command WCMD to the memory cell array 110. FIG. 9A ​The host 300 can transmit the commit command to the controller 200 of the memory system 1000 (S140), although not shown in FIG. 14. The controller 200 can control the semiconductor memory device 100 to program the meta log data JMDATA' and the log data JDATA' generated based on the received meta log data JMDATA and the log data JDATA in the log area of the memory cell array 110 in response to the received write command WCMD and the commit command. At this time, the controller 200 can program the meta log data JMDATA' and the log data JDATA' in the log area in which parity is added to each of the meta log data JMDATA and the log data JDATA.

[0110] Although not shown in FIG. 9A and FIG. 9B , the controller 200 can transmit a completion message to the host 300 when the meta log data JMDATA' and the log data JDATA' are completely written in the log area. Referring to FIG. 9B , the host 300 transmits the commit data COMMIT and the write command WCMD to the controller 200 of the memory system 1000 (S150) in response to the completion message. Thereafter, although not shown in FIG. 9B , the host 300 can transmit the commit command to the controller 200 of the memory system 1000 (S160). The controller 200 can control the semiconductor memory device 100 to program the commit data COMMIT' generated based on the received commit data COMMIT in the log area of the memory cell array 110 in response to the write command WCMD and the commit command. At this time, the controller 200 can program the commit data COMMIT' to which parity is added in the log area.

[0111] Although not shown in FIG. 9C , the controller 200 can transmit a completion message to the host 300 when the commit data COMMIT' is completely written in the log area. Referring to FIG. 9C , the host 300 can transmit the write data DATA and the write command WCMD to the controller 200 of the memory system 1000 (S170) in response to the completion message. The write data DATA can be substantially the same data as the log data JDATA. The controller 200 can control the semiconductor memory device 100 to program the write data DATA received from the host 300 as new data DATA_N in the data area. Here, the new data DATA_N stored in the data area can be substantially the same as the log data JDATA' stored in the log area. As the new data DATA_N is stored in the data area, old data DATA_O can be invalidated. Accordingly, the update operation of the data is completed.

[0112] FIG. 10A 、 FIG. 10B and FIG. 10C is a diagram illustrating a structure of data written in a log area or a data area by a method shown in FIG. 8 .

[0113] Referring to FIG. 10A , meta log data JMDATA and log data JDATA are shown. More specifically, FIG. 10A an example in which log data JDATA included in one transaction includes a plurality of partial data PD1 to PD4 is shown. That is, FIG. 10A the partial data PD1 to PD4 shown in FIG. 9A to FIG. 9C may be included in the log data JDATA or the write data DATA shown in

[0114] As shown in FIG. 10A , each of the partial data PD1 to PD4 can include corresponding user data UD1 to UD4 and metadata MD1 to MD4. The user data UD1 to UD4 can be data for updating old data. The first partial data PD1 includes first user data UD1 and first metadata MD1, and the second partial data PD2 includes second user data UD2 and second metadata MD2. Meanwhile, the third partial data PD3 includes third user data UD3 and third metadata MD3, and the fourth partial data PD4 includes fourth user data UD4 and fourth metadata MD4.

[0115] As will be described later with reference to FIG. 10B , the controller 200 generates parity data PT1 to PT4 corresponding to the respective partial data PD1 to PD4, and controls the semiconductor memory device 100 to program page data PG1 to PG4 including the parity data PT1 to PT4 as log data JDATA' in the log area of the memory cell array 110.

[0116] As shown in FIG. 10A , the meta log data JMDATA can include information about the first to fourth partial data PD1 to PD4. For example, the meta log data JMDATA can include information that the log data JDATA is divided into four partial data PD1 to PD4. In addition, the meta log data JMDATA can include a descriptor identifier (ID) for distinguishing a transaction including the log data.

[0117] Further, the metadata MD1 to MD4 included in the first to fourth partial data PD1 to PD4, respectively, can further include a descriptor ID for distinguishing a transaction in which the metadata MD1 to MD4 are included. Accordingly, the journal data JDATA and the first to fourth metadata MD1 to MD4 can include the same descriptor ID.

[0118] Referring to FIG. 10B , the first parity data PT1 is generated from the first partial data PD1, and the second parity data PT2 is generated from the second partial data PD2. Further, the third parity data PT3 is generated from the third partial data PD3, and the fourth parity data PT4 is generated from the fourth partial data PD4. That is, the first to fourth parity data PT1 to PT4 can be generated based on the corresponding partial data PD1 to PD4, respectively.

[0119] For example, the parity data PT1 to PT4 can be generated through a cyclic redundancy check (CRC) method. However, this is merely an example, and the parity data PT1 to PT4 can be generated through various other methods.

[0120] Referring to FIG. 10C , the journal data JDATA' including FIG. 10B the parity data described above is illustrated. That is, the first page data PG1 can be generated by adding the first parity data PT1 to the first partial data PD1 including the first user data UD1 and the first metadata MD1, and the second page data PG2 can be generated by adding the second parity data PT2 to the second partial data PD2 including the second user data UD2 and the second metadata MD2. Also, the third page data PG3 can be generated by adding the third parity data PT3 to the third partial data PD3 including the third user data UD3 and the third metadata MD3, and the fourth page data PG4 can be generated by adding the fourth parity data PT4 to the fourth partial data PD4 including the fourth user data UD4 and the fourth metadata MD4. The first to fourth page data PG1 to PG4 can constitute the journal data JDATA'.

[0121] Further, the parity data PTM can be generated based on the meta-journal data JMDATA. The meta-journal data JMDATA' can be generated by adding the parity data PTM to the meta-journal data JMDATA.

[0122] FIG. 11 is a flowchart illustrating a method of operating the host 300 according to another embodiment of the disclosure.

[0123] Referring to FIG. 11The method of operating the host 300 includes: determining the data stored in the memory system 1000 to be updated (S115); transmitting a write command to the memory system for writing meta-log data and log data for data update to the log area of ​​the memory system 1000 (S135); transmitting a clear command to the memory system (S145); and in response to the completion of writing the meta-log data and log data, transmitting a write command to the memory system for writing write data corresponding to the log data to the data area (S175).

[0124] according to FIG. 11 The illustrated embodiment, and FIG. 8 The illustrated embodiment differs from the one shown in that the operation S150 of transmitting commit data to the memory system 1000 is not performed. However, instead of using commit data to determine whether a transaction can be completed, when writing log data to the log area, it can be done in a manner similar to... FIG. 10B The different methods shown execute the method for generating parity data (S135). See below for further details. FIG. 13A , FIG. 13B and FIG. 13C This describes a detailed method for generating parity data in operation S135.

[0125] FIG. 12A and FIG. 12B This illustrates a host 300 according to an embodiment of the present disclosure, such as... FIG. 11 A diagram illustrating the method of operation shown.

[0126] Reference FIG. 12A The old data DATA_O is stored in the data area of ​​memory cell array 110. For example... FIG. 11 As shown, host 300 can determine to update old data DATA_O stored in memory cell array 110 in memory system 1000 (S115).

[0127] Based on the determination in operation S115, the host 300 transmits the metadata JMDATA, the log data JDATA, and the write command WCMD to the controller 200 of the memory system 1000 (S135). Afterwards, although not in FIG. 12A As shown, however, the host 300 can transmit the clear command to the controller 200 of the memory system 1000 (S145). The controller 200 can, in response to the received write command WCMD and clear command, control the semiconductor memory device 100 to program the meta-log data JMDATA' and log data JDATA' generated based on the received meta-log data JMDATA and log data JDATA into the log area of ​​the memory cell array 110.

[0128] Although not in FIG. 12A andFIG. 12B As shown, however, when the meta-log data JMDATA' and the log data JDATA' are completely written to the log area, the controller 200 can send a completion message to the host 300. (See reference...) FIG. 12B In response to the completion message, the host 300 can transmit the write data DATA and the write command WCMD to the controller 200 of the memory system 1000 (S175). The write data DATA can be substantially the same as the log data JDATA. The controller 200 can control the semiconductor memory device 100 to program the write data DATA received from the host 300 as new data DATA_N in the data area. Here, the data programmed in the data area can be substantially the same as the log data JDATA' stored in the log area. As the new data DATA_N is stored in the data area, the old data DATA_O can be invalidated. Therefore, the data update operation is completed.

[0129] When FIG. 12A and FIG. 12B and FIG. 9A to FIG. 9C When making comparisons, in FIG. 12A and FIG. 12B The method shown can be omitted. FIG. 9B The operation shown illustrates writing and committing data. Therefore, the write speed of the memory system can be improved.

[0130] FIG. 13A , FIG. 13B and FIG. 13C This illustrates the implementation of embodiments according to this disclosure. FIG. 11 The diagram illustrates the structure of the data written to the log area or data area using the method shown.

[0131] Reference FIG. 13A This shows the metadata JMDATA and the log data JDATA. More specifically, FIG. 13A This example illustrates a transaction that includes multiple page portions of data, PD1 through PD4. In other words, FIG. 13A The data PD1 to PD4 shown can be included FIG. 12A and FIG. 12B The log data JDATA or the write data DATA shown are displayed.

[0132] like FIG. 13AAs illustrated, each of the partial data PD1 to PD4 can include respective user data UD1 to UD4 and metadata MD1 to MD4. The user data UD1 to UD4 can be data for updating old data. The first partial data PD1 includes first user data UD1 and first metadata MD1, and the second partial data PD2 includes second user data UD2 and second metadata MD2. Further, the third partial data PD3 includes third user data UD3 and third metadata MD3, and the fourth partial data PD4 includes fourth user data UD4 and fourth metadata MD4.

[0133] As will be described later with reference to FIG. 6, the controller 200 generates parity data PT1 to PT4 corresponding to the respective partial data PD1 to PD4, and controls the semiconductor memory device 100 to program the page data PG1 to PG4 including the parity data PT1 to PT4 as log data JDATA' in the log area of the memory cell array 110. FIG. 13B

[0134] The metadata MD1 to MD4 included in the first to fourth partial data PD1 to PD4, respectively, can further include a descriptor ID for distinguishing a transaction in which the metadata MD1 to MD4 are included. Accordingly, the meta log data JMDATA and the first to fourth metadata MD1 to MD4 can include the same descriptor ID.

[0135] Referring to FIG. 6, FIG. 13B The first parity data PT1' can be generated from the first partial data PD1. The second parity data PT2' can be generated from the first partial data PD1 and the second partial data PD2. In addition, the third parity data PT3' can be generated from the first to third partial data PD1 to PD3. Finally, the fourth parity data PT4' can be generated from the first to fourth partial data PD1 to PD4. That is, the parity data PT1' to PT4' included in the respective page data PG1 to PG4 are generated cumulatively based on the respective partial data PD1 to PD4 and previous partial data.

[0136] Referring to FIG. 6, FIG. 13C It is illustrated that the first to fourth partial data PD1 to PD4 are generated from the first to fourth user data UD1 to UD4 and the first to fourth metadata MD1 to MD4. FIG. 13B ​The described parity data is log data JDATA'. That is, the first page data PG1 can be generated by adding the first parity data PT1' to the first partial data PD1 including the first user data UD1 and the first metadata MD1, and the second page data PG2 can be generated by adding the second parity data PT2' to the second partial data PD2 including the second user data UD2 and the second metadata MD2. Also, the third page data PG3 can be generated by adding the third parity data PT3' to the third partial data PD3 including the third user data UD3 and the third metadata MD3, and the fourth page data PG4 can be generated by adding the fourth parity data PT4' to the fourth partial data PD4 including the fourth user data UD4 and the fourth metadata MD4. The first to fourth page data PG1 to PG4 can constitute the log data JDATA'.

[0137] Referring to FIG. 10B and FIG. 13B , the parity data PT1 to PT4 generated according to FIG. 10B is generated based on only the corresponding partial data PD1 to PD4. However, the parity data PT1' to PT4' generated according to FIG. 13B is generated based on the corresponding partial data PD1 to PD4 and the previous partial data cumulatively. Accordingly, when the controller 200 reads any one of the page data PG1 to PG4, the parity check operation is performed by referring to all the previous page data. For example, when the controller 200 receives the first page data PG1, the controller 200 can perform the parity check operation based on the first partial data PD1 and the first parity data PT1'. However, when the controller 200 receives the third page data PD3, the controller 200 can perform the parity check operation based on the first to third partial data PD1 to PD3 and the third parity data PT3'. Using this method, it is possible to determine whether a transaction is completed without the committed data of the log area. Hereinafter, a more detailed description will be given with reference to FIG. 14 to FIG. 17B .

[0138] Referring to FIG. 13B, showing embodiments in which the parity data PT1' to PT4' is generated based on the corresponding partial data PD1 to PD4 and all previous partial data cumulatively. However, the present disclosure is not limited thereto. In this example, the write data includes first to Nth partial data. The i-th parity data among the first to Nth parity data corresponding to the first to Nth partial data can be generated based on at least one of the first to (i-1)th partial data and the i-th partial data. For example, when the write data includes first to fourth partial data, the first parity data is generated based on the first partial data. Also, the second parity data is generated based on the first partial data and the second partial data. Also, the third parity data can be generated based on at least one of the first partial data and the second partial data and the third partial data. Also, the fourth parity data can be generated based on at least one of the first to third partial data and the fourth partial data.

[0139] FIG. 14 is a flowchart showing a method of operating a host according to yet another embodiment of the present disclosure.

[0140] Referring to FIG. 14 , the method of operating a host includes detecting power-on of the memory system 1000 and SPO (S210), reading journal metadata and commit data from a log area of the memory system 1000 (S230), and determining whether descriptors IDs of the journal metadata JMDATA and the commit data COMMIT are identical to each other (S240).

[0141] In an embodiment, the descriptor ID can be an identifier (ID) for identifying a transaction to which the journal metadata JMDATA and the commit data COMMIT belong. For example, the journal metadata JMDATA and the commit data COMMIT belonging to the same transaction can include the same descriptor ID. Thus, when the descriptor ID of the journal metadata JMDATA and the descriptor ID of the commit data COMMIT are identical to each other, the journal metadata JMDATA, the log data JDATA, and the commit data COMMIT can be included in the same transaction. Since the commit data COMMIT is written, it is guaranteed that the log data JDATA belonging to the corresponding transaction is also completely stored in the log area before the SPO occurs.

[0142] According to an embodiment, the method of operating the host 300 further includes, when the descriptor ID of the journal metadata JMDATA and the descriptor ID of the commit data COMMIT are identical to each other (S240: Yes), writing the log data JDATA of the log area to a data area (S250). Thus, the data update operation before the SPO occurs can be recovered.

[0143] According to an embodiment, the method of operating host 300 further includes: deleting the meta log data JMDATA, log data JDATA, and commit data COMMIT in the log area when the descriptor ID of the meta log data JMDATA and the descriptor ID of the commit data COMMIT are different from each other (S240: No) (S260). Therefore, data update operations prior to the SPO may not be recoverable, and the data update operations may have to start over.

[0144] In operation S240, the case where the descriptor ID of the meta log data JMDATA and the descriptor ID of the COMMIT data are the same means that the log data JDATA stored in the log area was written immediately before SPO, ensuring the integrity of the log data JDATA. Therefore, in this case, the log data JDATA in the log area can be used to complete the transaction. Thus, the operation proceeds to operation S250 and the log data JDATA in the log area is written to the data area. In the following text, reference will be made to... FIG. 15A and FIG. 15B Describe operation S250.

[0145] FIG. 15A and FIG. 15B This illustrates an embodiment of the present disclosure, such as... FIG. 14 The diagram illustrates the method for writing data from the log area to the data area after an SPO occurs. (Refer to...) FIG. 15A The host 300 detects the power-on of the memory system 1000 and the occurrence of SPO (S210), and in response to the power-on of the memory system 1000 and the occurrence of SPO, controls the memory system 1000 to read the commit data 'COMMIT' and the meta-log data 'JMDATA' written to the log area (S230). More specifically, the host 300 transmits a read command RCMD for reading the meta-log data 'JMDATA' and the commit data 'COMMIT' to the controller 200. In response to the received read command RCMD, the controller 200 controls the semiconductor memory device 100 to read the commit data 'COMMIT' and the meta-log data 'JMDATA' stored in the log area. The read meta-log data JMDATA and commit data 'COMMIT' are then transmitted to the host 300.

[0146] Host 300 compares the received log data with the committed data based on the read operation of memory system 1000. Meta-log data JMDATA and committed data COMMIT can include descriptor IDs, which distinguish transactions containing the corresponding data. Host 300 compares the descriptor ID of meta-log data JMDATA with the descriptor ID of committed data COMMIT. When the descriptor ID of meta-log data JMDATA and the descriptor ID of committed data COMMIT are the same, the log data JDATA written to the log area by the transaction immediately preceding SPO is complete. Therefore, in this case, as... FIG. 15B As shown, the host 300 can read the log data JDATA' stored in the log area and control the memory system 1000 to store the log data JDATA' as new data DATA_N in the data area (S250). To this end, the host 300 can transmit a write command WCMD to the memory system 1000 to control the memory system 1000 to store the log data JDATA' as new data DATA_N in the data area.

[0147] Although not in FIG. 15A and FIG. 15B As shown, however, when the descriptor ID of the meta-log data JMDATA and the descriptor ID of the commit data COMMIT are different from each other (S240: No), the host 300 can control the memory system 1000 to delete the meta-log data JMDATA', log data JDATA', and commit data COMMIT' written to the log area (S260). Optionally, in operation S260, instead of deleting the meta-log data JMDATA', log data JDATA', and commit data COMMIT' written to the log area, the meta-log data JMDATA', log data JDATA', and commit data COMMIT' can be made invalid.

[0148] In other words, FIG. 14 to FIG. 15B The recovery method shown corresponds to the reference. FIG. 8 to FIG. 10C The logging technology described. In the following text, the description will correspond to the reference. FIG. 11 to FIG. 13C The recovery method described is based on log technology.

[0149] FIG. 16A and FIG. 16B This is a flowchart illustrating a method of operating a host according to yet another embodiment of the present disclosure.

[0150] Reference FIG. 16AThe method of operating the host includes detecting power-on of the memory system 1000 and SPO (S210), reading meta log data JMDATA' and log data JDATA' from a log area of the memory system 1000 (S235), and determining whether the descriptor ID of the meta log data JMDATA and the descriptor ID of the log data JDATA are identical to each other (S245).

[0151] In an embodiment, the descriptor ID can be an ID for identifying a transaction to which the meta log data JMDATA and the log data JDATA belong. For example, the meta log data JMDATA and the log data JDATA belonging to the same transaction can include the same descriptor ID. For example, in an example where the first to fourth metadata MD1 to MD4 include the same descriptor ID, the meta log data JMDATA and the log data JDATA can belong to the same transaction. FIG. 13A

[0152] Accordingly, when the descriptor ID of the meta log data JMDATA and the descriptor ID of the log data JDTATA are identical to each other, the meta log data JMDATA and the log data JDATA can be included in the same transaction.

[0153] The meta log data JMDATA can contain information about the number of partial data included in the log data JDATA included in the corresponding transaction. In an example where the first to fourth metadata MD1 to MD4 include information that the log data JDATA included in the corresponding transaction is composed of four partial data PD1' to PD4', the meta log data JMDATA can contain information that the log data JDATA included in the corresponding transaction is composed of four partial data PD1' to PD4'. FIG. 13A

[0154] According to an embodiment, the method of operating the host 300 further includes, when the descriptor ID of the meta log data JMDATA and the descriptor ID of the log data JDATA are identical to each other (S245: Yes), writing the log data JDATA of the log area to a data area (S255). Accordingly, it is possible to restore the data update operation before the SPO occurs.

[0155] ​​According to an embodiment, the method of operating the host 300 further includes deleting the meta log data JMDATA' and the log data JDATA' of the log area when the descriptors ID of the meta log data JMDATA and the log data JDATA are different from each other (S245: No) (S265). Thus, it can be impossible to restore the data update operation before the SPO occurs, and it can be necessary to start the data update operation from the beginning.

[0156] Referring to FIG. 16B , the method of operating the host according to still another embodiment of the disclosure includes detecting power-on and SPO of the memory system 1000 (S210), reading the meta log data JMDATA' and the log data JDATA' from the log area of the memory system 1000 (S235), and determining whether the parity check of the log data passes (S247).

[0157] FIG. 16B The operations S210 and S235 of FIG. 16A are substantially the same as the operations S210 and S235 of

[0158] According to an embodiment of FIG. 16B , the method of operating the host 300 further includes writing the log data JDATA of the log area to the data area when the parity check of the log data passes (S247: Yes) (S255). According to an embodiment, the method of operating the host 300 further includes deleting the meta log data JMDATA' and the log data JDATA' of the log area when the parity check of the log data does not pass (S247: No) (S265).

[0159] In operation S247, the case where the parity check of the log data JDATA' passes means that the log data JDATA' stored in the log area is written immediately before the SPO, and the integrity of the log data in the transaction is ensured. As described above with reference to FIG. 13B , in this case, the parity check can be performed by referring to the partial data and the other partial data corresponding to the parity check data included in the same transaction.

[0160] In an embodiment, in determining whether the parity check of the log data passes (S247), the host 300 can receive the log data JDATA' stored in the log area, and directly perform the parity check operation on the corresponding log data JDATA'.

[0161] In another embodiment, the controller 200 can receive the log data JDATA' stored in the log area and perform a parity check operation on the corresponding log data JDATA'. The controller 200 can transmit whether the parity check operation has passed to the host 300, so that the host 300 can determine whether the parity check of the log data JDATA' has passed based on the result of the parity check operation received from the controller 200.

[0162] More specifically, the log data JDATA' read in operation S235 can include FIG. 13C the first to fourth page data PG1 to PG4 illustrated. The parity check operation of the first page data PG1 can be performed based on the first partial data PD1 and the first parity check data PT1'. The parity check operation of the second page data PG2 can be performed based on the first and second partial data PD1 to PD2 and the second parity check data PT2'. The parity check operation of the third page data PG3 can be performed based on the first to third partial data PD1 to PD3 and the third parity check data PT3'. The parity check operation of the fourth page data PG4 can be performed based on the first to fourth partial data PD1 to PD4 and the fourth parity check data PT4'. When all of the parity check operations on the first to fourth page data PG1 to PG4 pass, it can be determined that the parity check of the log data has passed (S245: Yes). When the parity check operation on at least one of the first to fourth page data PG1 to PG4 does not pass, it can be determined that the parity check of the log data has not passed (S245: No).

[0163] FIG. 17A and FIG. 17B is a diagram illustrating a method of writing data of a log area to a data area after the SPO occurrence in FIG. 16A is illustrated according to an embodiment of the disclosure. Referring to FIG. 17A , the host 300 detects the occurrence of the SPO of the memory system 1000 (S210). The host 300 controls the memory system 1000 to read the meta log data JMDATA' and the log data JDATA' written to the log area in response to the occurrence of the SPO (S235). More specifically, the host 300 transmits a read command RCMD for reading the meta log data JMDATA' and the log data JDATA' to the controller 200. The controller 200 controls the semiconductor memory device 100 to read the meta log data JMDATA' and the log data JDATA' stored in the log area in response to the received read command RCMD. The read meta log data JMDATA and the log data JDATA are transmitted to the host 300.

[0164] In an embodiment, as FIG. 16AAs shown, the host 300 determines whether the descriptor ID of the meta log data JMDATA and the descriptor ID of the log data JDATA received based on the read operation of the memory system 1000 are identical to each other (S245). When the descriptor ID of the meta log data JMDATA and the descriptor ID of the log data JDATA are identical to each other (S245: Yes), the log data JDATA' written in the log area by the write transaction immediately before the SPO can be complete. Thus, in this case, the host 300 can read the log data JDATA' stored in the log area, and control the memory system 1000 to store the log data JDATA' as new data DATA_N in the data area (S255). To this end, the host 300 can transmit a write command WCMD for controlling the memory system 1000 to store the log data JDATA' as new data DATA_N in the data area to the memory system 1000. FIG. 17B As shown, the host 300 can read the log data JDATA' stored in the log area, and control the memory system 1000 to store the log data JDATA' as new data DATA_N in the data area (S255). To this end, the host 300 can transmit a write command WCMD for controlling the memory system 1000 to store the log data JDATA' as new data DATA_N in the data area to the memory system 1000.

[0165] Although not shown, when the descriptor ID of the meta log data JMDATA and the descriptor ID of the log data JDATA are different from each other (S245: No), the host 300 can control the memory system 1000 to delete the meta log data JMDATA' and the log data JDATA' written in the log area (S265). Alternatively, instead of deleting the meta log data JMDATA' and the log data JDATA' written in the log area, the host 300 can invalidate the meta log data JMDATA' and the log data JDATA'. FIG. 17A FIG. 17B As shown, the host 300 can read the log data JDATA' stored in the log area, and control the memory system 1000 to store the log data JDATA' as new data DATA_N in the data area (S255). To this end, the host 300 can transmit a write command WCMD for controlling the memory system 1000 to store the log data JDATA' as new data DATA_N in the data area to the memory system 1000.

[0166] In another embodiment, the host 300 performs a parity check operation on the log data JDATA' received based on the read operation of the memory system 1000. When the parity check of the log data JDATA' is passed (S247: Yes), the log data written in the log area by the write transaction immediately before the SPO is complete. Thus, in this case, the host 300 can read the log data JDATA' stored in the log area, and control the memory system 1000 to store the log data JDATA' as new data DATA_N in the data area (S255). To this end, the host 300 can transmit a write command WCMD for controlling the memory system 1000 to store the log data JDATA' as new data DATA_N in the data area to the memory system 1000. FIG. 17B As shown, the host 300 can read the log data JDATA' stored in the log area, and control the memory system 1000 to store the log data JDATA' as new data DATA_N in the data area (S255). To this end, the host 300 can transmit a write command WCMD for controlling the memory system 1000 to store the log data JDATA' as new data DATA_N in the data area to the memory system 1000.

[0167] Although not shown, when the descriptor ID of the meta log data JMDATA and the descriptor ID of the log data JDATA are different from each other (S245: No), the host 300 can control the memory system 1000 to delete the meta log data JMDATA' and the log data JDATA' written in the log area (S265). Alternatively, instead of deleting the meta log data JMDATA' and the log data JDATA' written in the log area, the host 300 can invalidate the meta log data JMDATA' and the log data JDATA'. FIG. 17A FIG. 17B ​​The host 300 can control the memory system 1000 to delete the meta log data JMDATA' and the log data JDATA' written in the log area (S265) when the parity check of the log data JDATA' fails (S247: No), although it is not illustrated. Alternatively, in operation S265, instead of deleting the meta log data JMDATA' and the log data JDATA' written in the log area, the meta log data JMDATA' and the log data JDATA' can be invalidated.

[0168] According to FIG. 14 the method of operating the host 300 illustrated in FIG. 16, to recover the previous write transaction when the SPO is detected, the host 300 refers to the commit data COMMIT' stored in the log area. To this end, FIG. 8 the method of operating the host 300 illustrated in FIG. 16 requires an operation of writing the commit data COMMIT' to the log area in response to completion of the writing of the log data JDATA'. Therefore, after the meta log data JMDATA' and the log data JDATA' are written, a separate operation of writing the commit data COMMIT' is required. This requires a longer time to update the old data DATA_O stored in the memory system 1000 with the new data DATA_N.

[0169] On the other hand, according to the method of operating the host 300 illustrated in FIG. 16, to recover the previous write transaction when the SPO is detected, the host 300 refers to the commit data COMMIT' stored in the log area. To this end, FIG. 11 the method of operating the host 300 illustrated in FIG. 16 does not require an operation of writing the commit data COMMIT' to the log area in response to completion of the writing of the log data JDATA'. That is, since a separate operation of writing the commit data COMMIT' after the meta log data JMDATA' and the log data JDATA' are written is unnecessary, only a shorter time can be required to update the old data DATA_O stored in the memory system 1000 with the new data DATA_N. Therefore, the operation speed of the memory system 1000 can be improved.

[0170] FIG. 18 is a block diagram illustrating an example of the controller 200 according to an embodiment of the disclosure. FIG. 1 the controller 200 illustrated in FIG. 17.

[0171] Referring to FIG. 18 , the controller 200 is connected to the semiconductor memory device 100 and the host HOST. The semiconductor memory device 100 can be the semiconductor memory device described with reference to FIG. 2 .

[0172] The controller 200 is configured to access the semiconductor memory device 100 in response to a request from the host Host. For example, the controller 200 is configured to control a read operation, a write operation, an erase operation, and a background operation of the semiconductor memory device 100. The controller 200 is configured to provide an interface between the semiconductor memory device 100 and the host Host. The controller 200 is configured to drive firmware for controlling the semiconductor memory device 100.

[0173] The controller 200 includes a random access memory (RAM) 210, a processing unit 220, a host interface (I / F) 230, a memory interface 240, and an error correction block 250. The RAM 210 is used as at least one of a work memory of the processing unit 220, a cache memory between the semiconductor memory device 100 and the host Host, and a buffer memory between the semiconductor memory device 100 and the host Host.

[0174] The processing unit 220 controls the overall operation of the controller 200.

[0175] The host interface 230 includes a protocol for performing data exchange between the host Host and the controller 200. In an embodiment, the controller 200 is configured to communicate with the host Host through at least one of various communication standards or interfaces such as a universal serial bus (USB) protocol, a multimedia card (MMC) protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-e or PCIe) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an electronic integrated drive (IDE) protocol, and a proprietary protocol.

[0176] The memory interface 240 interfaces with the semiconductor memory device 100. For example, the memory interface 1240 includes a NAND interface or a NOR interface.

[0177] The error correction block 250 is configured to detect and correct errors of data received from the semiconductor memory device 100 by using an error correction code (ECC). The processing unit 220 can control the semiconductor memory device 100 to adjust a read voltage and perform a re-read according to an error detection result of the error correction block 250. In an embodiment, the error correction block can be provided as a component of the controller 200.

[0178] The controller 200 and the semiconductor memory device 100 can be integrated into one semiconductor device. In an embodiment, the controller 200 and the semiconductor memory device 100 can be integrated into one semiconductor device to form a memory card. For example, the controller 200 and the semiconductor memory device 100 can be integrated into one semiconductor device to form a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a compact flash card (CF), a smart media card (e.g., SM and SMC), a memory stick, a multimedia card (e.g., MMC, RS-MMC, or micro-SD), a secure digital (SD) card (e.g., SD, mini-SD, micro-SD, or SDHC), and a universal flash storage (UFS).

[0179] The controller 200 and the semiconductor memory device 100 can be integrated into one semiconductor device to form a semiconductor drive (solid state drive (SSD)). The semiconductor drive (SSD) includes a memory system 1000 configured to store data in a semiconductor memory. When the memory system 1000 including the controller 200 and the semiconductor memory device 100 is used as a semiconductor drive (SSD), the operating speed of a host connected to the memory system 1000 is significantly improved.

[0180] As another example, the memory system 1000 including the controller 200 and the semiconductor memory device 100 is disposed as one of various components of an electronic device such as a computer, an ultra mobile PC (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a web tablet, a wireless phone, a mobile phone, a smartphone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation device, a black box, a digital camera, a three-dimensional TV, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, one of various electronic devices constituting a computer network, one of various electronic devices constituting a telematics network, an RFID device, or one of various components constituting a computing system.

[0181] In an embodiment, the semiconductor memory device 100 or a memory system including the semiconductor memory device 100 can be mounted as various types of packages. For example, the semiconductor memory device 100 or the memory system can be packaged and mounted in a method such as a package on package (PoP), a ball grid array (BGA), a chip scale package (CSP), a plastic leaded chip carrier (PLCC), a plastic dual-in-line package (PDIP), a die in waffle pack, a die in wafer form, a chip on board (COB), a ceramic dual-in-line package (CERDIP), a plastic metric quad flat package (MQFP), a thin quad flat package (TQFP), a small outline integrated circuit (SOIC), a shrink small outline package (SSOP), a thin small outline package (TSOP), a system in package (SIP), a multi-chip package (MCP), a wafer level package (WFP), or a wafer level process package (WSP).

[0182] FIG. 19 is a block diagram illustrating an application example of a memory system according to an embodiment of the disclosure. FIG. 1

[0183] Referring to FIG. 19 , the memory system 2000 includes a semiconductor memory device 2100 and a controller 2200. The semiconductor memory device 2100 includes a plurality of semiconductor memory chips. The plurality of semiconductor memory chips is divided into a plurality of groups.

[0184] In FIG. 19 , the plurality of groups respectively communicates with the controller 2200 through first to k-th channels CH1 to CHk. The configuration and operation of each semiconductor memory chip are similar to those of the semiconductor memory chips of the semiconductor memory device 100 described with reference to FIG. 2 .

[0185] Each group is configured to communicate with the controller 2200 through one common channel. The controller 2200 is configured similarly to the controller 200 described with reference to FIG. 18 , and is configured to control the plurality of memory chips of the semiconductor memory device 2100 through the plurality of channels CH1 to CHk.

[0186] FIG. 20 is a block diagram illustrating a computing system 3000 including the memory system described with reference to FIG. 19 .

[0187] Referring to FIG. 20 ​The computing system 3000 includes a central processing device 3100, a random access memory (RAM) 3200, a user interface 3300, a power supply 3400, a system bus 3500, and the memory system 2000.

[0188] The memory system 2000 is electrically connected to the central processing device 3100, the RAM 3200, the user interface 3300, and the power supply 3400 through the system bus 3500. Data provided through the user interface 3300 or processed by the central processing device 3100 is stored in the memory system 2000.

[0189] In FIG. 20 , the semiconductor memory device 2100 is connected to the system bus 3500 through the controller 2200. However, the semiconductor memory device 2100 can be configured to be directly connected to the system bus 3500. At this time, the functions of the controller 2200 are performed by the central processing device 3100 and the RAM 3200.

[0190] In FIG. 20 , the memory system 2000 described with reference to FIG. 19 is provided. However, a memory system including the controller 200 and the semiconductor memory device 100 described with reference to FIG. 18 may be utilized instead of the memory system 2000.

[0191] The embodiments of the disclosure and the accompanying drawings are provided only with specific examples to easily describe the technical content of the disclosure and help understanding of the disclosure, and are not intended to limit the scope of the disclosure. It would be obvious to those of ordinary skill in the art that other modified examples based on the technical spirit of the disclosure can be implemented in addition to the embodiments disclosed herein.

[0192] The methods, processes, and / or operations described herein can be performed by code or instructions executed by a computer, a processor, a controller, or other signal processing device. The computer, the processor, the controller, or the other signal processing device can be one of those described herein or one other than the elements described herein. Since the algorithm forming the basis of the method (or the operation of the computer, the processor, the controller, or the other signal processing device) is described in detail, the code or the instructions for implementing the operations of the method embodiments can convert the computer, the processor, the controller, or the other signal processing device into a dedicated processor for performing the methods herein.

[0193] When implemented at least partially in software, the controllers, processors, managers, devices, modules, units, multiplexers, generators, logic, interfaces, decoders, drivers, and other signal generation and signal processing functions can include, for example, a memory or other storage for storing code or instructions, for example, executed by a computer, processor, microprocessor, controller, or other signal processing device. The computer, processor, microprocessor, controller, or other signal processing device can be one of those described herein or one in addition to the elements described herein. Since the algorithms that form the basis of the methods (or the operation of the computer, processor, microprocessor, controller, or other signal processing device) are described in detail, the code or instructions for implementing the operations of the method embodiments can transform the computer, processor, controller, or other signal processing device into a special purpose processor for performing the methods described herein.

[0194] While various embodiments of the disclosed technology have been described in specific detail with reference to particular details and different elements, it will be understood that various modifications, additions and substitutions can be made to the embodiments disclosed and illustrated in the present disclosure and appended claims without departing from the spirit and scope of the disclosed technology. Furthermore, embodiments can be combined to form additional embodiments.

Claims

1. A method of operating a host, the host being in communication with a memory system, the memory system including a log area and a data area, the method comprising: determining to update old data stored in the memory system; transmitting to the memory system a write command for writing log data and meta-log data for updating the old data to the log area; and in response to receiving from the memory system a write completion of the meta-log data and the log data, transmitting to the memory system a write command for writing new data corresponding to the log data to the data area, wherein the log data includes first page data and second page data, the first page data including first partial data and first parity data, the second page data including second partial data and second parity data, and the first parity data is generated based on the first partial data, and the second parity data is generated based on the first partial data and the second partial data.

2. The method of claim 1, further comprising: in response to receiving from the memory system a write completion of the new data, controlling the memory system to invalidate the old data stored in the data area.

3. The method of claim 1, further comprising: detecting a sudden power loss of the memory system; reading the meta-log data and the log data stored in the log area; and controlling the memory system to resume a write operation before the sudden power loss based on the meta-log data and the log data.

4. A method of operating a host, the host being in communication with a memory system, the memory system including a log area and a data area, the method comprising: detecting a sudden power loss of the memory system; reading meta-log data and log data stored in the log area; and controlling the memory system to resume a write operation before the sudden power loss based on the meta-log data and the log data, wherein the log data includes first page data and second page data, the first page data including first partial data and first parity data, the second page data including second partial data and second parity data, and the first parity data is generated based on the first partial data, and the second parity data is generated based on the first partial data and the second partial data.

5. The method of claim 4, wherein controlling the memory system to recover the write operation prior to the sudden power loss based on the meta log data and the log data comprises: determining whether parity of the log data has passed.

6. The method of claim 5, wherein controlling the memory system to recover the write operation prior to the sudden power loss based on the meta log data and the log data further comprises: in response to determining that parity of the log data has passed, controlling the memory system to write the log data of the log area to the data area.

7. The method of claim 5, wherein controlling the memory system to recover the write operation prior to the sudden power loss based on the meta log data and the log data further comprises: in response to determining that parity of the log data has not passed, controlling the memory system to delete or invalidate the meta-log data and the log data of the log area.

8. A method of operating a memory system, the memory system including a log area and a data area, the method comprising: receiving write data and a write command from a host; and writing log data generated based on the write data to the log area, wherein the write data includes first to Nth partial data, the log data includes first to Nth page data, i-th page data among the first to Nth page data includes i-th partial data among the first to Nth partial data and i-th parity data among first to Nth parity data, and the i-th parity data is generated based on at least one of the first to (i-1)th partial data and the i-th partial data, where N is a natural number greater than 1, and i is a natural number greater than or equal to 1 and less than or equal to N. 9.The method of claim 8, wherein the i-th parity data is generated by a cyclic redundancy check method for at least one of the first to (i-1)th partial data and the i-th partial data. 10.The method of claim 8, wherein the i-th parity data is generated based on the first to i-th partial data. 11.The method of claim 10, wherein the i-th parity data is generated by a cyclic redundancy check method for the first to i-th partial data. 12.A data processing system comprising: a host; and a memory system coupled to the host and including a controller and a memory device, the memory device coupled to the controller and including a log area and a data area, wherein the controller controls the memory device to: write log data and meta log data to the log area; read the log data and the meta log data from the log area when a sudden power loss is detected; determine whether a parity check of the log data passes; and write the log data of the log area to the data area when it is determined that the parity check of the log data passes, wherein the log data includes first and second page data, the first page data includes first partial data and first parity data, the second page data includes second partial data and second parity data, and the first parity data is generated based on the first partial data, and the second parity data is generated based on the first and second partial data.

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