Storage array, memory and writing, reading and erasing method thereof
By designing adjacent row memory cells to share memory tube word lines and adjacent column memory cells to share bit lines in SONOS memory, the problem of crowded metal traces in memory arrays is solved, improving integration and enhancing write speed and storage efficiency.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- SHANGHAI HUAHONG GRACE SEMICON MFG CORP
- Filing Date
- 2026-01-05
- Publication Date
- 2026-04-17
AI Technical Summary
In existing SONOS memories, as device size shrinks, the metal traces of the memory array become increasingly crowded, affecting the integration density of the memory array.
By connecting the same memory word line to adjacent memory cells in adjacent rows, adjacent memory cells in adjacent rows can share a single memory word line, and memory cells in the same memory cell can be connected to different bit lines. Adjacent memory cells in adjacent columns can share the same bit line, thus reducing the number of memory cells and bit lines.
It alleviates the congestion of the memory pipe word lines and bit lines, improves the integration of the memory array, and increases the write speed, reduces power consumption, and enhances the storage efficiency of the memory through hot carrier injection.
Smart Images
Figure CN121884883A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductors, and more particularly to a storage array, a memory, and methods for writing, reading, and erasing the same. Background Technology
[0002] Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) memory is a type of non-volatile memory. In SONOS memory, each memory cell includes two transistors and a select transistor connected in series between them. Write, erase, and read operations can be performed on the SONOS memory by applying specific voltage combinations to the metal traces connecting the memory cells.
[0003] However, as device size continues to shrink, the metal traces connecting the memory cells in existing SONOS memory are becoming increasingly congested, hindering further reduction in memory array size and impeding improvements in the integration density of memory arrays. Summary of the Invention
[0004] The technical problem solved by this invention is: how to reduce the size of the storage array in order to improve the integration of the storage array.
[0005] To address the aforementioned technical problems, embodiments of the present invention provide a storage array, comprising: a plurality of storage cells arranged in an array; each storage cell includes: a select transistor, a first storage transistor, and a second storage transistor, wherein the select transistor is connected in series between the first storage transistor and the second storage transistor; wherein the select transistors of storage cells in the same row are connected to the same word line, and the select transistors of storage cells in different rows are connected to different word lines; adjacent storage transistors of adjacent rows of storage cells are connected to the same storage transistor word line; and two storage transistors in the same row of storage cells are connected to different storage transistor word lines.
[0006] Optionally, the first storage tube of the nth row of storage units is connected to the first storage tube word line, the second storage tube of the nth row of storage units and the first storage tube of the (n+1)th row of storage units are connected to the second storage tube word line, and the second storage tube of the (n+1)th row of storage units is connected to the third storage tube word line, where n≥1 and n is an integer.
[0007] Optionally, the memory transistors in the same memory cell can be connected to different bit lines.
[0008] Optionally, adjacent column storage units can share the same bit line.
[0009] Optionally, each first memory tube in an adjacent column memory cell is connected to the same bit line, or each second memory tube in an adjacent column memory cell is connected to the same bit line.
[0010] Optionally, the first storage tube of each storage cell in the kth column and the second storage tube of each storage cell in the (k+1)th column are connected to the same bit line, or the second storage tube of the storage cell in the kth column and the first storage tube of the storage cell in the (k+1)th column are connected to the same bit line, where k ≥ 1 and k is an integer.
[0011] Accordingly, the present invention also provides a memory comprising: the memory array described above.
[0012] Optionally, the memory includes a writing unit connected to the memory array, adapted to perform a write operation on the target memory tube using a hot carrier injection method.
[0013] Optionally, the memory includes an erase unit connected to the memory array, adapted to perform erase operations on the row containing the target memory cell and adjacent row memory cells connected to the same memory pipe word line as the target memory cell using FN tunneling.
[0014] Optionally, the memory includes: a read unit adapted to be connected to the memory array and adapted to perform read operations on the target memory tube.
[0015] Accordingly, the present invention also provides a method for writing to a memory, comprising: when the target memory tube is the second memory tube of the memory cell, turning on the target memory tube, the first memory tube of the memory cell, and the select tube, turning off other memory cells, and causing the memory cell where the target memory tube is located to generate current, so as to realize writing to the target memory tube; when the target memory tube is the first memory tube of the memory cell, turning on the target memory tube, the second memory tube of the memory cell, and the select tube, turning off other memory cells, and causing the memory cell where the target memory tube is located to generate current, so as to realize writing to the target memory tube.
[0016] Accordingly, the present invention also provides a memory erasure method, comprising: applying a first erasure voltage to a memory pipe word line shared by a target memory cell and an adjacent row memory cell, and applying a second erasure voltage to other word lines and bit lines connected to the target memory cell and the adjacent row memory cell, wherein the first erasure voltage is greater than the second erasure voltage.
[0017] Accordingly, the present invention also provides a method for reading a memory, comprising: when the target memory tube is the second memory tube of the memory cell in which the target memory tube is located, opening the first memory tube and the selection tube of the memory cell in which the target memory tube is located, and closing the target memory tube and other memory cells, so as to realize reading the target memory tube; when the target memory tube is the first memory tube of the memory cell in which the target memory tube is located, opening the second memory tube and the selection tube of the memory cell in which the target memory tube is located, and closing the target memory tube and other memory cells, so as to realize reading the target memory tube.
[0018] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:
[0019] In the storage array provided by the technical solution of the present invention, adjacent storage tubes of adjacent row storage cells are connected to the same storage word line, which enables adjacent storage tubes of adjacent row storage cells to share a storage word line, thereby reducing the number of storage word lines in the storage array. This can alleviate the congestion of wiring between storage word lines, effectively reduce the array area, and thus help to increase the integration of the storage array.
[0020] Furthermore, in the storage array provided by the technical solution of the present invention, the storage tubes of the same storage cell are connected to different bit lines respectively, and adjacent column storage cells share the same bit line, so that the same bit line can alternately connect the storage tubes of different storage cells on both sides, reducing the number of bit lines, thereby reducing the congestion of bit lines in the column direction, which can further alleviate the congestion of word lines between storage tubes, further reduce the array area, and help to further improve the integration of the storage array.
[0021] Furthermore, the write unit adopts a hot carrier injection method to perform write operations on the target memory tube, which can improve the memory write speed and improve the memory storage efficiency. Attached Figure Description
[0022] Figure 1 This is a schematic diagram of a storage unit structure;
[0023] Figure 2 A schematic diagram of a storage array structure;
[0024] Figure 3 This is a schematic diagram of the structure of a storage array in one embodiment of the present invention;
[0025] Figure 4 This is a schematic diagram of the structure of a storage unit in one embodiment of the present invention;
[0026] Figure 5 This is a schematic diagram of the storage array structure in another embodiment of the present invention;
[0027] Figure 6 This is a schematic diagram of the structure of a storage unit in another embodiment of the present invention;
[0028] Figure 7 This is a schematic diagram of the structure of a storage array in another embodiment of the present invention;
[0029] Figure 8 This is a schematic diagram of the structure of a storage unit in another embodiment of the present invention. Detailed Implementation
[0030] It should be noted that the terms "surface" and "on" in this specification are used to describe the relative spatial position and are not limited to whether there is direct contact.
[0031] In current SONOS memories, the metal traces connecting memory cells are becoming increasingly crowded, hindering further reduction in memory array size. The reasons for this deficiency are analyzed below:
[0032] Figure 1 This is a schematic diagram of a storage unit. (Refer to...) Figure 1 The storage cell includes: a substrate 100; a selection gate 1012 located on the substrate 100; a first storage gate 1011 located on the substrate 100 on one side of the selection gate 1012; and a second storage gate 1013 located on the substrate 100 on the other side of the selection gate 1012.
[0033] The substrate 100 includes a well region 1001, a source / drain region 1002, and a lightly doped drain implantation region 1003. The lightly doped drain implantation region 1003 is located in the well region 1001 on the side of the first storage gate 1011 away from the select gate 1012, and in the well region 1001 on the side of the second storage gate 1013 away from the select gate 1012.
[0034] The first memory gate 1011 and the source / drain region 1002 form a first memory transistor, and the second memory gate 1013 and the source / drain region 1002 form a second memory transistor. The selection gate 1012 and the source / drain region 1002 form a selection transistor.
[0035] The select tube is connected to word line WL1 via select gate 1012, the first memory tube is connected to a memory tube word line WLS1 via first memory gate 1011, and the second memory tube is connected to another memory tube word line WLS2 via second memory gate 1013.
[0036] When a memory array is formed using the aforementioned memory cells, each select transistor in the same row of memory cells is connected to the same word line, each first memory transistor in the same row of memory cells is connected to a memory word line, and each second memory gate in the same row of memory cells is connected to another memory word line. The two memory word lines connected to any two rows of memory cells are not the same, which leads to increasingly crowded routing of the memory word lines within the memory array, hindering further reduction in the size of the memory array and ultimately resulting in a low integration density.
[0037] Figure 2 This is a schematic diagram of a storage array structure, with reference to... Figure 2The storage array includes a plurality of storage cells arranged in an array; each storage cell has the same structure. Each storage cell includes a select transistor S1, a first storage transistor M1, and a second storage transistor M2, wherein the select transistor S1 is connected in series between the first storage transistor M1 and the second storage transistor M2.
[0038] In this configuration, the select transistors of the same row of memory cells are connected to the same word line, while the select transistors of different rows of memory cells are connected to different word lines; the first and second memory transistors of the same row of memory cells are connected to different memory transistor word lines, and the second and first memory transistors of adjacent rows of memory cells are connected to different memory transistor word lines.
[0039] Taking a 3x4 storage array as an example, refer to... Figure 2 In the first storage cell 101 in the first row and fourth column, the first storage tube M1 is connected to the first storage tube word line WLS0, and the second storage tube M2 is connected to the second storage tube word line WLS1.
[0040] In the second storage cell 102 in the second row and fourth column, the first storage tube M1 is connected to the third storage tube word line WLS2, and the second storage tube M2 is connected to the fourth storage tube word line WLS3.
[0041] As can be seen, in the above-mentioned memory array, since the first and second memory transistors of the same row of memory cells are connected to different memory word lines, each row of memory cells is connected to two memory word lines, which increases the number of memory word lines. Moreover, as the device size continues to shrink, the traces of the memory word lines become more and more crowded, which affects the further reduction of the size of the memory array.
[0042] To address the aforementioned technical problems, this invention provides a storage array, a memory, and its writing, reading, and erasing methods, in which the same storage word line is connected to adjacent storage tubes of adjacent row storage cells, so that adjacent storage tubes of adjacent row storage cells share a single storage word line. This reduces the number of storage word lines in the storage array, reduces wiring congestion between storage word lines, and increases the integration of the storage array.
[0043] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
[0044] This invention provides a storage array comprising: a plurality of storage cells arranged in an array; each storage cell comprising: a select transistor, a first storage transistor, and a second storage transistor, wherein the select transistor is connected in series between the first storage transistor and the second storage transistor; wherein the select transistors of storage cells in the same row are connected to the same word line, and the select transistors of storage cells in different rows are connected to different word lines; adjacent storage transistors of adjacent rows of storage cells are connected to the same storage transistor word line; and two storage transistors of the same row of storage cells are connected to different storage transistor word lines.
[0045] The first and second storage tubes are used to store data, and their operating states include writing, erasing, and reading.
[0046] The selection tube is used to select the first storage tube and the second storage tube, and to isolate the first storage tube and the second storage tube.
[0047] In the storage array provided by this invention, adjacent storage transistors of adjacent row storage cells are connected to the same storage word line, which can reduce the number of storage word lines between adjacent storage transistors of adjacent row storage cells by one, thereby reducing the number of storage word lines in the storage array, alleviating the congestion between storage word lines, and improving the integration of the storage array.
[0048] In a specific embodiment, the storage array is an N*M storage array, where N is the number of rows in the storage array, M is the number of columns in the storage array, and N and M are both positive integers, n∈N. Taking the nth row of storage units as any row of storage units as an example, the first storage tube of the nth row of storage units can be connected to the first storage tube word line, the second storage tube of the nth row of storage units and the first storage tube of the (n+1)th row of storage units can be connected to the second storage tube word line, and the second storage tube of the (n+1)th row of storage units can be connected to the third storage tube word line, where n≥1 and n is an integer.
[0049] In this configuration, the second storage tube of the nth row storage unit and the first storage tube of the (n+1)th row storage unit are adjacent storage tubes of adjacent row storage units. The second storage tube of the nth row storage unit and the first storage tube of the (n+1)th row storage unit are connected to the same storage tube word line, that is, the adjacent storage tubes of adjacent row storage units are controlled by the same storage tube word line.
[0050] Figure 3 This is a schematic diagram of the structure of a storage array in one embodiment of the present invention, for reference. Figure 3 Taking a 3*4 storage array as an example, the storage array includes 3 rows and 4 columns.
[0051] Specifically, the first storage unit 201 in the first row and fourth column includes: a selection tube S1, a first storage tube M1 and a second storage tube M2, wherein the selection tube S1 is connected in series between the first storage tube M1 and the second storage tube M2.
[0052] The second storage unit 202 in the second row and fourth column includes: a selection tube S1, a first storage tube M1 and a second storage tube M2, wherein the selection tube S2 is connected in series between the first storage tube M1 and the second storage tube M2.
[0053] Figure 4 This is a schematic diagram of the structure of a storage unit in one embodiment of the present invention. Figure 3 Based on reference Figure 4 , Figure 4 Figure (a) is Figure 3 A schematic diagram of the cross-sectional structure of the first storage cell 201. Figure 4 Figure (b) is Figure 3 A schematic diagram of the cross-sectional structure of the second storage unit 202.
[0054] like Figure 4 As shown in Figure (a), the first memory cell 201 includes: a substrate; a substrate 200; a selection gate 2012 located on the substrate 200; a first memory gate 2011 located on the substrate 200 on one side of the selection gate 2012; and a second memory gate 2013 located on the substrate 200 on the other side of the selection gate 2012.
[0055] The substrate 200 includes a well region 2001, a source / drain region 2002, and a lightly doped drain implantation region 2003. The lightly doped drain implantation region 2003 is located in the well region 2001 on the side of the first memory gate 2011 away from the select gate 2012, and in the well region 2001 on the side of the second memory gate 2013 away from the select gate 2012.
[0056] The selection gate 2012 and the source / drain region 2002 are used to form the selection tube S1 of the first storage cell 201, the first storage gate 2011 and the source / drain region 2002 are used to form the first storage tube M1 of the first storage cell 201, and the second storage gate 2013 and the source / drain region 2002 are used to form the second storage tube M2 of the first storage cell 201.
[0057] like Figure 4As shown in Figure (b), the second memory cell 202 includes: a substrate; a substrate 200; a selection gate 2022 located on the substrate 200; a first memory gate 2021 located on the substrate 200 on one side of the selection gate 2022; and a second memory gate 2023 located on the substrate 200 on the other side of the selection gate 2022.
[0058] The selection gate 2012 and the source / drain region 2002 are used to form the selection tube S1 of the first memory cell 201, the first memory gate 2011 and the source / drain region 2002 are used to form the first memory tube M1 of the first memory cell 201, and the second memory gate 2013 and the source / drain region 2002 are used to form the second memory tube M2 of the first memory cell 201.
[0059] In the first storage cell 201, the select gate 2012 is connected to the first word line WL1 through a contact hole, and the first storage gate 2011 is connected to the second storage word line WLS0 through a contact hole. In the second storage cell 202, the select gate 2022 is connected to the second word line WL2 through a contact hole, and the first storage gate 2021 is connected to the second storage word line WLS1 through a contact hole.
[0060] In the first storage unit 201, the first storage tube M1 is connected to the first storage tube word line WLS0. In the first storage unit 201, the second storage tube M2 and the first storage tube M1 in the second storage unit 202 are connected to the second storage tube word line WLS1. In the second storage unit 202, the second storage tube M2 is connected to the third storage tube word line WLS2.
[0061] Therefore, in the first storage cell 201 and the second storage cell 202 of adjacent rows, the second storage transistor M2 in the first storage cell 201 and the first storage transistor M1 in the second storage cell 202 are both connected to the second storage word line WLS1, realizing the sharing of the second storage word line WLS1. Compared with adjacent storage transistors of adjacent rows of storage cells being connected to different storage word lines, the storage array of the present invention can reduce the number of storage word lines connecting adjacent rows of storage cells, thereby reducing the number of storage word lines in the storage array, alleviating the problem of wiring congestion between storage word lines, and improving the integration of the storage array. In addition, the reduction in the number of contact holes and storage word lines can reduce process costs.
[0062] In the prior art, reference Figure 2 The memory transistors in the same column of memory cells are connected to a bit line and a source line respectively, which makes the bit lines and source lines in the memory array increasingly crowded, resulting in a low integration density of the memory array.
[0063] Taking a 3x4 storage array as an example, refer to... Figure 2 In the third storage cell 103 of the first row and third column, the first storage tube M1 is connected to the third bit line BL3, and the second storage tube M2 is connected to the third source line SL3.
[0064] In the first storage cell 101 in the first row and fourth column, the first storage tube M1 is connected to the fourth bit line BL4, and the second storage tube M2 is connected to the fourth source line SL4.
[0065] The memory cells in the column where the third memory cell 103 and the first memory cell 101 are located need to be connected to four column-direction metal traces: the third bit line BL3, the third source line SL3, the fourth bit line BL4, and the fourth source line SL4. This makes the column-direction metal traces in the memory array increasingly crowded, affecting the integration of the memory array.
[0066] Therefore, in some embodiments of the present invention, in order to further reduce the number of metal traces in the column direction in the memory array, the memory tubes of the same memory cell are connected to different bit lines, but adjacent column memory cells share the same bit line.
[0067] Since adjacent column storage cells share the same bit line, the bit line can function as a bit line or a source line in different storage states. This reduces the number of metal traces in the column direction, thereby alleviating the congestion between bit lines and improving the integration of the storage array.
[0068] In practice, adjacent column storage units can share the same bit line in various ways, and no restrictions are imposed here.
[0069] Figure 5 This is a schematic diagram of the storage array structure in another embodiment of the present invention.
[0070] exist Figure 3 Based on reference Figure 5 As with the aforementioned embodiments, the present disclosure will not repeat the same features. In one embodiment, each first storage tube of the k-th column storage unit and each second storage tube of the (k+1)-th column storage unit are connected to the same bit line, or the second storage tube of the k-th column storage unit and the first storage tube of the (k+1)-th column storage unit are connected to the same bit line, where k ≥ 1 and k is an integer.
[0071] Specifically, taking a 3x4 storage array as an example, refer to... Figure 5 In the first storage cell 301 in the first row and third column, the first storage tube M1 is connected to the third bit line BL3, and the second storage tube M2 is connected to the fourth bit line BL4.
[0072] In the second storage cell 302 in the first row and fourth column, the first storage tube M1 is connected to the fourth bit line BL4, and the second storage tube M2 is connected to the fifth bit line BL5.
[0073] Figure 6 This is a schematic diagram of the structure of a storage unit in another embodiment of the present invention.
[0074] exist Figure 5 Based on reference Figure 6 , Figure 6 Figure (a) is Figure 5 A schematic diagram of the cross-sectional structure of the first storage cell 301. Figure 6 Figure (b) is Figure 5 A schematic diagram of the cross-sectional structure of the second storage unit 302.
[0075] like Figure 6 As shown in Figure (a), the first storage cell 301 includes: a substrate; a substrate 300; a selection gate 3012 located on the substrate 300; a first storage gate 3011 located on the substrate 300 on one side of the selection gate 3012; and a second storage gate 3013 located on the substrate 300 on the other side of the selection gate 3012.
[0076] The substrate 300 includes a well region 3001, a source / drain region 3002, and a lightly doped drain implantation region 3003. The lightly doped drain implantation region 3003 is located in the well region 3001 on the side of the first storage gate 3011 away from the select gate 3012, and in the well region 3001 on the side of the second storage gate 3013 away from the select gate 3012.
[0077] The selection gate 3012 and the source / drain region 3002 are used to form the selection tube of the first memory cell 301, the first memory gate 3011 and the source / drain region 3002 are used to form the first memory tube of the first memory cell 301, and the second memory gate 3013 and the source / drain region 3002 are used to form the second memory tube of the first memory cell 301.
[0078] like Figure 6 As shown in Figure (b), the second memory cell 302 includes: a substrate; a substrate 300; a selection gate 3022 located on the substrate 300; a first memory gate 3021 located on the substrate 300 on one side of the selection gate 3022; and a second memory gate 3023 located on the substrate 300 on the other side of the selection gate 3022.
[0079] The selection gate 3022 and the source / drain region 3002 are used to form the selection tube of the second memory cell 302, the first memory gate 3021 and the source / drain region 3002 are used to form the first memory tube of the second memory cell 302, and the second memory gate 3023 and the source / drain region 3002 are used to form the second memory tube of the second memory cell 302.
[0080] In the first memory cell 301, one end of the first memory gate 3011 is connected to the third bit line BL3 through a contact hole, and the second memory gate 3013 is connected to the fourth bit line BL4 through a contact hole. In the second memory cell 302, one end of the first memory gate 3021 is connected to the fourth bit line BL4 through a contact hole, and the second memory gate 3023 is connected to the fifth bit line BL5 through a contact hole.
[0081] Therefore, in the first storage cell 301 and the second storage cell 302 in adjacent columns, the second storage transistor M2 in the first storage cell 301 and the first storage transistor M1 in the second storage cell 302 are both connected to the fourth bit line BL4, realizing the sharing of the fourth bit line BL4. Compared with each storage cell being connected to a bit line and a source line respectively, the present invention can reduce the connection of one source line between the first storage cell 301 and the second storage cell 302, and the first storage cell 301 and the second storage cell 302 share the fourth bit line BL4, reducing the number of metal traces in the storage array, thereby alleviating the situation of trace congestion between bit lines and improving the integration of the storage array.
[0082] In a specific implementation, the first storage tube M1 of the first storage unit 301 can be connected to the fourth bit line BL4, and the second storage tube M2 of the first storage unit 301 can be connected to the third bit line BL3. The first storage tube M1 of the second storage unit 302 can be connected to the fifth bit line BL5, and the second storage tube M2 of the second storage unit 302 can be connected to the fourth bit line BL4. This can also reduce the number of metal traces in the column direction of the storage array and alleviate the problem of trace congestion between bit lines.
[0083] Figure 7 This is a schematic diagram of the structure of a storage array in another embodiment of the present invention.
[0084] exist Figure 3 Based on reference Figure 7 The similarities to the aforementioned embodiments will not be repeated here. The difference from the aforementioned embodiments is that each first memory tube in an adjacent column memory cell is connected to the same bit line, or each second memory tube in an adjacent column memory cell is connected to the same bit line.
[0085] Specifically, in the first storage cell 401 in the first row and third column, the first storage tube M1 is connected to the fourth bit line BL4, and the second storage tube M2 is connected to the third bit line BL3.
[0086] In the second storage cell 402 in the first row and fourth column, the first storage tube M1 is connected to the fourth bit line BL4, and the second storage tube M2 is connected to the fifth bit line BL5.
[0087] Figure 8 This is a schematic diagram of the structure of a storage unit in another embodiment of the present invention.
[0088] exist Figure 7 Based on reference Figure 8 , Figure 8 Figure (a) is Figure 7 A cross-sectional structural diagram of the first storage cell 401. Figure 8 Figure (b) is Figure 7 A schematic diagram of the cross-sectional structure of the second storage unit 402.
[0089] like Figure 8 As shown in Figure (a), the first storage cell 401 includes: a substrate; a substrate 400; a selection gate 4012 located on the substrate 400; a first storage gate 4011 located on the substrate 400 on one side of the selection gate 4012; and a second storage gate 4013 located on the substrate 400 on the other side of the selection gate 4012.
[0090] The substrate 400 includes a well region 4001, a source / drain region 4002, and a lightly doped drain implantation region 4003. The lightly doped drain implantation region 4003 is located in the well region 4001 on the side of the first storage gate 4011 away from the select gate 4012, and in the well region 4001 on the side of the second storage gate 4013 away from the select gate 4012.
[0091] The selection gate 4012 and the source / drain region 4002 are used to form the selection tube of the first memory cell 401, the first memory gate 4011 and the source / drain region 4002 are used to form the first memory tube of the first memory cell 401, and the second memory gate 4013 and the source / drain region 4002 are used to form the second memory tube of the first memory cell 401.
[0092] like Figure 8As shown in Figure (b), the second memory cell 402 includes: a substrate; a substrate 400; a selection gate 4022 located on the substrate 400; a first memory gate 4021 located on the substrate 400 on one side of the selection gate 4022; and a second memory gate 4023 located on the substrate 400 on the other side of the selection gate 4022.
[0093] The selection gate 4022 and the source / drain region 4002 are used to form the selection tube of the second memory cell 402, the first memory gate 4021 and the source / drain region 4002 are used to form the first memory tube of the second memory cell 402, and the second memory gate 4023 and the source / drain region 4002 are used to form the second memory tube of the second memory cell 402.
[0094] In the first memory cell 401, one end of the first memory gate 4011 is connected to the fourth bit line BL4 through a contact hole, and the second memory gate 4013 is connected to the third bit line BL3 through a contact hole. In the second memory cell 402, one end of the first memory gate 4021 is connected to the fourth bit line BL4 through a contact hole, and the second memory gate 4023 is connected to the fifth bit line BL5 through a contact hole.
[0095] Therefore, in the first storage cell 401 and the second storage cell 402 in adjacent columns, the first storage transistor M1 in the first storage cell 401 and the first storage transistor M1 in the second storage cell 402 are both connected to the fourth bit line BL4, realizing the sharing of the fourth bit line BL4. Compared with each storage cell being connected to a bit line and a source line respectively, the present invention can reduce the connection of one source line between the first storage cell 401 and the second storage cell 402, and the first storage cell 401 and the second storage cell 402 share the fourth bit line BL4, reducing the number of metal traces in the storage array, thereby reducing the congestion of traces between bit lines and increasing the integration of the storage array.
[0096] Accordingly, the present invention also provides a memory comprising the memory array described above.
[0097] In some embodiments, the memory includes a write unit connected to the memory array, adapted to perform a write operation on a target memory tube using a hot carrier injection method.
[0098] The write operation is characterized as writing data into the target storage tube.
[0099] This invention employs a hot carrier injection method to perform write operations on the target memory tube, which can improve the memory write speed, reduce memory power consumption, and improve memory storage efficiency.
[0100] Hot carrier injection refers to the process where, under the influence of a strong electric field, charge carriers (such as electrons or holes) acquire sufficient kinetic energy to far exceed their energy in thermal equilibrium. These high-energy charge carriers are called "hot carriers." After gaining sufficient energy, hot carriers can overcome the potential barrier and enter the storage gate or well region.
[0101] Specifically, by using hot carrier injection to perform write operations on the target memory tube, the write time can be reduced to 5 to 10 microseconds.
[0102] In some embodiments, the memory includes an erase unit connected to the memory array, adapted to perform erase operations on the row containing the target memory cell and adjacent row memory cells connected to the same memory pipe word line as the target memory cell in a tunneling manner.
[0103] The erasure operation is characterized by erasing data from the target storage tube. The tunneling refers to Fowler-Nordheim (FN) tunneling, which means that when an electron passes through a potential barrier under the influence of a high electric field, it can tunnel to the other side.
[0104] In some embodiments, the memory includes a read unit adapted to be connected to the memory array and adapted to perform read operations on a target memory tube.
[0105] The read operation is characterized as reading data from the target storage tube.
[0106] In some embodiments, the memory may further include a voltage supply circuit that provides the voltage required to perform various operations on the memory cells. Specifically, the voltage supply circuit may include a voltage source and multiple charge pumps, wherein the voltage output from the voltage source is pumped to output a voltage value matching the corresponding operation. Wherein, when the difference between the required voltage value and the voltage output from the voltage source is small, the charge pump may use a single-pump method to pump the charge output from the voltage source to the required voltage value. When the difference between the required voltage value and the voltage output from the voltage source is large, the charge pump may use a dual-pump method to pump the voltage output from the voltage source to the required voltage value.
[0107] The so-called dual-pump method is a bidirectional operation with both positive and negative voltages, which pumps the voltage output from the voltage source to the required voltage value.
[0108] Accordingly, the present invention also provides a method for writing to a memory, specifically, the method comprising:
[0109] When the target memory tube is the second memory tube in the memory cell, the target memory tube, the first memory tube and the select tube in the memory cell are turned on, and the other memory cells are turned off. The memory cell in which the target memory tube is located is then powered to enable writing to the target memory tube.
[0110] When the target memory tube is the first memory tube in the memory cell, the target memory tube, the second memory tube and the select tube in the memory cell are turned on, and the other memory cells are turned off. The memory cell in which the target memory tube is located is then powered to enable writing to the target memory tube.
[0111] The target storage tube is the storage tube on which data needs to be written. Correspondingly, the other storage tubes besides the target storage tube are non-target storage tubes, which are storage tubes on which no data is written.
[0112] In this embodiment, reference Figure 5 If the bit line connected to the target memory tube is located on the right side of the target memory cell, such as Figure 5 The voltage applied to the second storage transistor M2 in the second storage cell 302 in the first row and fourth column during a write operation is shown in Table 1:
[0113] Table 1
[0114]
[0115] In Table 1, the values in each column represent different voltage values on word lines, memory word lines, and bit lines connected to the target memory transistor and non-target memory transistors.
[0116] The following is combined Figure 5 Table 1 describes the writing method of the memory.
[0117] refer to Figure 5 According to Table 1, when the target storage tube is the second storage tube M2 in the second storage unit 302 in the first row and fourth column, the second storage tube M2 and the first storage tube M1 and the selection tube S1 in the second storage unit 302 are turned on, and a current is generated in the second storage unit 302 where the second storage tube M2 is located, so as to realize the writing of the second storage tube M2.
[0118] In one embodiment, when the target memory tube is the second memory tube M2 in the second memory cell 302 in the first row and fourth column, a word line voltage Vwl-p is applied to the first word line WL1 connected to the select tube S1, a first enable voltage Vso is applied to the first memory tube word line WLS0 connected to the first memory tube M1, a second enable voltage Vpos-p is applied to the second memory tube word line WLS1 connected to the second memory tube M2, a write ground voltage Vgnd1 is applied to the first bit line BL4 connected to the first memory tube M1, a write voltage Vbl-p is applied to the second bit line BL5 connected to the second memory tube M2, and a write ground voltage Vgnd is applied to the well region of the memory cell.
[0119] Specifically, the first bit line refers to the left bit line connected to the target memory cell, and the second bit line refers to the right bit line connected to the target memory cell.
[0120] Specifically, the first turn-on voltage Vso is greater than the threshold voltage of the first memory transistor M1, enabling the first memory transistor M1 to be turned on. A voltage difference exists between the write-to-ground voltage Vgnd1 on the first bit line BL4 and the write voltage Vbl-p on the second bit line BL5, causing carriers to be accelerated in a strong electric field. The second turn-on voltage Vpos-p is greater than the threshold voltage of the second memory transistor M2 and also greater than the minimum voltage required for hot carrier injection, attracting the carriers accelerated by the voltage difference between the first bit line BL4 and the second bit line BL5 into the second memory transistor M2.
[0121] The word line voltage Vwl-p is equal to the threshold voltage of the select transistor S1, or less than the threshold voltage of the select transistor S1 by 1V, so that the select transistor S1 can be weakly turned on. The word line voltage Vwl-p is less than the first turn-on voltage Vso and the second turn-on voltage Vpos-p.
[0122] In a specific embodiment, the word line voltage Vwl-p is any voltage value that enables the select transistor S1 to be weakly turned on, the first turn-on voltage Vso is any voltage value that enables the first memory transistor M1 to be turned on, the second turn-on voltage Vpos-p is any voltage value that enables the second memory transistor M2 to undergo hot carrier injection, and the voltage difference between the write ground voltage Vgnd and the write voltage Vbl-p can reach a write current that can generate hot carrier injection.
[0123] For example, the word line voltage Vwl-p can be 0.5V, the first turn-on voltage Vso can be 3V, the second turn-on voltage Vpos-p can be 7V, the write ground voltage Vgnd1 can be 0V, and the write voltage Vbl-p can be 4V.
[0124] Since the voltage difference between the write ground voltage Vgnd1 (0V) and the write voltage Vbl-p (4V) is 4V, the write current flows from the first storage tube M1 through the select tube S1 and is finally stored in the second storage tube M2.
[0125] When the target memory transistor is the second memory transistor M2 in the second memory cell 302 of the first row and fourth column, the other memory cells besides the target memory transistor are non-target memory transistors (e.g., the third memory cell 303 and the fourth memory cell 304). For memory transistors that share memory transistor word lines and word lines with the target cell, such as the second memory transistor M2 in the first memory cell 301, the voltage applied to the memory transistor word lines and word lines is the same as that applied to the target memory transistor (the second memory transistor M2 in the second memory cell 302). A first non-write voltage VblU-p is applied to the first bit line BL3 connected to the first memory transistor M1, a write ground voltage Vgnd1 is applied to the second bit line BL4 connected to the second memory transistor M2, and a write ground voltage Vgnd is applied to the well region of the memory cell. The voltage difference between the first bit line BL3 and the second bit line BL4 on both sides of 301 is the voltage difference between the first non-write voltage VblU-p and the write ground voltage Vgnd1, which is insufficient to generate a current that can cause hot carrier injection. Therefore, the second memory tube M2 of the first memory cell 301 will not be written. Similarly, referring to Table 1, the voltage difference between the first bit line BL2 and the second bit line BL3 on both sides of the memory cell on the left side of the first memory cell 301 is the voltage difference between the write voltage Vbl-p and the first non-write voltage VblU-p, which is insufficient to generate a current that can cause hot carrier injection. Referring to Table 1, the voltage applied to the first bit line and the second bit line on both sides of other memory cells is the write voltage Vbl-p, the voltage difference is 0, no write current is generated, and no hot carrier injection occurs.
[0126] Wherein, the first non-write voltage VblU-p is a voltage between the write ground voltage Vgnd1 and the write voltage Vbl-p, such that the voltage difference between the first non-write voltage VblU-p and the write ground voltage Vgnd1, and the voltage difference between the write voltage Vbl-p and the first non-write voltage VblU-p, are insufficient to generate a current that can cause hot carrier injection.
[0127] When the target memory transistor is the second memory transistor M2 in the second memory cell 302 in the first row and fourth column, for memory transistors that do not share a memory transistor word line with the target cell but do share a word line, such as the first memory transistor M1 in the first memory cell 301 and the first memory transistor M2 in the second memory cell 302, the voltage applied to the first word line WL1 is the same as that applied to the target memory transistor (the second memory transistor M2 in the second memory cell 302). A write ground voltage Vgnd1 is applied to the well region of the memory cell. The voltage applied to the first memory transistor word line WLS0 is the first turn-on voltage Vso, which is insufficient to generate hot carrier injection at the first memory transistor M1 in 301 and the first memory transistor M1 in the second memory cell 302, so no write will occur. Here, the first turn-on voltage Vso is a voltage greater than the threshold voltage of the first memory transistor M1 but less than the second turn-on voltage Vpos-p, which turns on the first memory transistor but does not cause hot carrier injection.
[0128] When the target memory transistor is the second memory transistor M2 in the second memory cell 302 in the first row and fourth column, for memory transistors that share a memory transistor word line with the target cell but do not share a word line, such as the first memory transistor M1 in the fourth memory cell 304 and the first memory transistor M1 in the third memory cell 303, the voltage applied to the second memory transistor word line WLS1 is the same as that applied to the target memory transistor (the second memory transistor M2 in the second memory cell 302). The write ground voltage Vgnd1 is applied to the well region of the memory cell, and the write ground voltage Vgnd1 is applied to the second word line WL2, so that the select transistor S1 in the fourth memory cell 304 and the select transistor S1 in the third memory cell 303 are in the off state. There is no write current in the fourth memory cell 304 and the third memory cell 303, and the first memory transistor M1 in the fourth memory cell 304 and the first memory transistor M1 in the third memory cell 303 will not be written.
[0129] When the target memory transistor is the second memory transistor M2 in the second memory cell 302 of the first row and fourth column, for memory transistors that do not share a memory transistor word line with the target cell, such as the second memory transistor M2 in the fourth memory cell 304 and the second memory transistor M2 in the third memory cell 303, a write ground voltage Vgnd1 is applied to the well region of the memory cell, a write ground voltage Vgnd1 is applied to the second word line WL2, and a non-selection voltage VposU is applied to the third memory transistor word line WLS2. The non-selection voltage VposU is insufficient to generate hot carrier injection, and the select transistor S1 in the fourth memory cell 304 and the select transistor S1 in the third memory cell 303 are in the off state with no write current. Therefore, the second memory transistor M2 in the fourth memory cell 304 and the second memory transistor M2 in the third memory cell 303 will not be written.
[0130] The unselected voltage VposU is a voltage less than the first turn-on voltage Vso, so that when this voltage is applied to the word line of any memory transistor, hot carrier injection will not occur.
[0131] In a specific embodiment, the first non-write voltage VblU-p can be 2.5V. The non-selection voltage VposU can be 1.1V, so as to increase the anti-interference capability of the non-target memory tube during write operations in the memory array.
[0132] Specifically, in the third storage unit 303, the first storage transistor M1 and the target storage transistor are connected to the same storage word line WLS1. That is, the voltage on the storage word line connected to the first storage transistor M1 in the third storage unit 303 is also 7V. However, since the selected transistors S1 in the third storage unit 303 are all in the off state, the current cannot flow to the first storage transistor M1 in the third storage unit 303. Therefore, the storage array of the present invention can select one of the storage transistors connected to the same storage word line for writing during the write operation by applying voltage.
[0133] In other embodiments, when the bit line connected to the target memory tube is located to the left of the target memory cell, such as... Figure 5 The second storage tube M2 in the fourth storage cell 304 in the second row and third column of the table differs from that in Table 1 only in that the voltages on the first and second bit lines are opposite. The voltage types on other voltage terminals are the same, which will not be described in detail here.
[0134] Accordingly, the present invention also provides a memory erasure method, comprising: applying a first erasure voltage to a memory pipe word line shared by a target memory cell and an adjacent row memory cell, and applying a second erasure voltage to other word lines and bit lines connected to the target memory cell and the adjacent row memory cell, wherein the first erasure voltage is greater than the second erasure voltage.
[0135] The target storage tube is the storage tube into which data needs to be written.
[0136] Correspondingly, the other storage tubes besides the target storage tube are non-target storage tubes, which are storage tubes on which no data is written.
[0137] In this embodiment, the voltage applied to the storage cell during the erase operation is shown in Table 2:
[0138] Table 2
[0139]
[0140] In Table 2, the values in each column represent different voltage values on word lines, memory word lines, and bit lines connected to the target memory transistor and non-target memory transistors.
[0141] The following is combined Figure 5 Table 2 describes the erasure method of the memory.
[0142] refer to Figure 5 And according to Table 2, when the target memory tubes are all the second memory tubes M2 in the first row of memory cells and all the first memory tubes M1 in the second row of memory cells, an erase ground voltage Vgnd2 is applied to the word line WLS1 of the second memory tube connected to the target memory tube, an erase voltage Vpos-e is applied to the well region of the memory cell and the word line connected to the selected tube in the first row of memory cells, and a floating voltage Float is applied to the bit line connected to the target memory tube.
[0143] Apply an erase voltage Vpos-e to the word line connected to the non-target memory transistor, apply the erase voltage Vpos-e to the word line connected to the selected transistor in the first row of memory cells, and apply a floating voltage Float to the bit line connected to the non-target memory transistor.
[0144] Wherein, the erase voltage Vpos-e is greater than the erase ground voltage Vgnd2, generating a voltage difference between the gate and the well region of the target memory tube. The voltage difference generates a strong vertical electric field, the direction of which is from the well region to the memory gate. The electric field can attract positively charged holes to tunnel upward from the well region into the ONO dielectric layer of the memory gate (that is, to erase the data from the memory tube).
[0145] In a specific embodiment, the erase voltage Vpos-e must be greater than the minimum voltage required to cause hole tunneling in the target memory transistor.
[0146] In a specific embodiment, the erasure grounding voltage Vgnd2 is 0V and the erasure voltage Vpos-e is 7V.
[0147] In another embodiment, the erasure ground voltage Vgnd2 is a negative voltage, and the erasure voltage Vpos-e is a positive voltage greater than 7V.
[0148] Since all memory transistors in the row containing the target memory transistor share the same memory word line, the same erase ground voltage Vgnd2 is applied to all memory transistors in the row containing the target memory transistor, and the same erase voltage Vpos-e is applied to all well regions. This allows for the parallel and simultaneous erasure of the entire row of memory transistors sharing the memory word line.
[0149] Accordingly, the present invention also provides a method for reading a memory, comprising: when the target memory tube is the second memory tube of the memory cell in which the target memory tube is located, turning on the first memory tube and the selection tube of the memory cell in which the target memory tube is located, and turning off the selection tubes of other rows so that the memory cells of other rows have no read current, so as to realize the reading of the target memory tube;
[0150] When the target memory tube is the first memory tube of the memory cell, the second memory tube and the selection tube of the memory cell containing the target memory tube are turned on, and the selection tubes of other rows are turned off so that there is no read current in the memory cells of other rows, so as to realize the reading of the target memory tube.
[0151] The target storage tube is the storage tube from which data needs to be read.
[0152] Correspondingly, the other storage tubes besides the target storage tube are non-target storage tubes, which are storage tubes that do not read data.
[0153] In this embodiment, when performing a read operation, refer to Figure 5 If the bit line connected to the target memory transistor is located to the right of the target memory cell, such as the second memory transistor M2 in the second memory cell 302 in the first row and fourth column, the voltage applied to the memory cell of the target memory transistor is shown in Table 3:
[0154] Table 3
[0155]
[0156] In Table 3, the values in each column represent different voltage values on word lines, memory word lines, and bit lines connected to the target memory transistor and non-target memory transistors.
[0157] The following is combined Figure 5 Table 3 describes the method for reading the memory.
[0158] refer to Figure 5 According to Table 3, when the target memory tube is the second memory tube M2 in the second memory cell 302 in the first row and fourth column, the first memory tube M1 and the select tube S1 in the memory cell 302 where the target memory tube is located are turned on. The read ground voltage Vgnd3 is applied to the gate of the second memory tube M2 and other memory cells. The read ground voltage Vgnd3 is applied to the well region. There is no obvious voltage difference in the vertical direction of the second memory tube M2, and the state of the second memory tube M2 is not changed, so as to realize the reading of the second memory tube M2.
[0159] In one embodiment, when the target memory tube is the second memory tube M2 in the second memory cell 302 in the first row and fourth column, a power supply voltage Vpwr is applied to the first word line WL1 connected to the selected transistor S1 in the second memory cell 302, an enable voltage Vso is applied to the first memory tube word line WLS0 connected to the first memory tube M1 in the second memory cell 302, a read ground voltage Vgnd3 is applied to the second memory tube word line WLS1 connected to the target memory tube, a read voltage Vlim is applied to the first bit line BL4 connected to the target memory tube, a read ground voltage Vgnd3 is applied to the second bit line BL5 connected to the target memory tube, and a read ground voltage Vgnd3 is applied to the well region of the memory cell.
[0160] Wherein, the power supply voltage Vpwr is greater than the threshold voltage of the selector S1 in the second storage unit 302 so that the selector S1 can be turned on, the turn-on voltage is greater than the threshold voltage of the first storage tube M1 in the second storage unit 302 so that the first storage tube M1 can be turned on, and the read voltage Vlim is greater than the read ground voltage Vgnd3 so that a voltage difference is generated between the first bit line BL4 and the second bit line BL5, thereby generating a read current.
[0161] In a specific embodiment, the power supply voltage Vpwr is any voltage value that enables the selector S1 to turn on, the turn-on voltage is any voltage value that enables the first storage tube M1 to turn on, the read ground voltage Vgnd3 is 0V, and the voltage difference between the read voltage Vlim and the read ground voltage Vgnd3 is sufficient to generate a read current.
[0162] In a specific embodiment, the power supply voltage Vpwr is 3V, the turn-on voltage is 3V, the grounding voltage Vgnd3 is 0V, and the reading voltage Vlim is 0.5V.
[0163] For example, when the target memory transistor is the second memory transistor M2 in the second memory cell 302 of the first row and fourth column, the other memory transistors are non-target memory transistors. For memory transistors that share memory transistor word lines and word lines with the target cell, such as the second memory transistor M2 in the first memory cell 301, the voltage applied to its first word line WL1 and second selector word line WLS1 is the same as that of the target memory transistor. Since the first memory cell 301 is located to the left of the target memory transistor, the read voltage Vlim is applied to the bit lines on both sides of the memory cell where the second memory transistor M2 is located. There is no voltage difference between the two bit lines, and no read current is generated.
[0164] When the target memory tube is the second memory tube M2 in the second memory cell 302 of the first row and fourth column, for memory tubes that do not share memory tube word lines with the target cell but do share word lines, such as the first memory tube M1 of the first memory cell 301 and the first memory tube M1 of the second memory cell 302, the voltage applied to its first word line WL1 is the same as that of the target memory tube, and the voltage applied to its first memory tube word line WLS0 is the turn-on voltage Vso. For the first memory tube M1 of the second memory cell 302, turning on M1 is a necessary condition for reading the target memory tube, and does not affect the reading of the target memory tube's state. For the first memory tube M1 of the first memory cell 301, the read voltage Vlim is applied to the bit lines on both sides of its memory cell, there is no voltage difference between the side bit lines, and no read current is generated.
[0165] When the target memory tube is the second memory tube M2 in the second memory cell 302 of the first row and fourth column, for other non-selected memory tubes besides the two types mentioned above, such as the first memory tube M1 of the fourth memory cell, the read ground voltage Vgnd3 is applied to the second word line WL2, the select tube S1 is turned off, and no read current is generated.
[0166] In a specific embodiment, the read ground voltage Vgnd3 is 0V, the read ground voltage Vgnd3 is 0V, and the read voltage Vlim is 0.5V.
[0167] Specifically, in the third storage unit 303, the first storage transistor M1 and the target storage transistor are connected to the same storage word line WLS1. That is, the voltage on the storage word line connected to the first storage transistor M1 in the third storage unit 303 is also 0V. However, since the selected transistors S1 in the third storage unit 303 are all in the off state, the current cannot flow through the first storage transistor M1 in the third storage unit 303. Therefore, the storage array of the present invention can select one of the storage transistors connected to the same storage word line for reading during the read operation by applying voltage.
[0168] In other embodiments, when the bit line connected to the target memory tube is located to the left of the target memory cell, such as... Figure 5 The second storage tube M2 in the fourth storage unit 304 in the second row and third column of the table differs from that in Table 3 only in that the voltages on the first and second bit lines are opposite. The voltage types on other voltage terminals are the same, and will not be described in detail here.
[0169] In summary, this invention connects adjacent memory transistors in adjacent rows of memory cells to the same memory word line, enabling adjacent memory transistors in adjacent rows to share a single memory word line. This reduces the number of memory word lines in the memory array, alleviating wiring congestion and effectively reducing the array area, thus facilitating increased integration of the memory array. Furthermore, the write unit in this invention employs hot carrier injection to perform write operations on the target memory transistor, improving memory write speed and storage efficiency.
[0170] Furthermore, by setting the memory tubes of the same memory cell to be connected to different bit lines, but adjacent column memory cells share the same bit line, the present invention reduces the number of metal traces in the column direction of the memory array, effectively reduces the array area, and thus helps to increase the integration of the memory array.
[0171] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.
Claims
1. A storage array, characterized in that, include: Several storage units arranged in an array; The storage unit includes: a selection transistor, a first storage transistor, and a second storage transistor, wherein the selection transistor is connected in series between the first storage transistor and the second storage transistor; In this configuration, the select transistors of the same row of memory cells are connected to the same word line, while the select transistors of different rows of memory cells are connected to different word lines; adjacent memory transistors of adjacent rows of memory cells are connected to the same memory transistor word line; and two memory transistors of the same row of memory cells are connected to different memory transistor word lines.
2. The storage array as described in claim 1, characterized in that, The first storage tube of the nth row of storage units is connected to the first storage tube word line, the second storage tube of the nth row of storage units and the first storage tube of the (n+1)th row of storage units are connected to the second storage tube word line, and the second storage tube of the (n+1)th row of storage units is connected to the third storage tube word line, where n≥1 and n is an integer.
3. The storage array as described in claim 1 or 2, characterized in that, The memory transistors in the same memory cell are connected to different bit lines.
4. The storage array as described in claim 3, characterized in that, Adjacent column storage units share the same bit line.
5. The storage array as described in claim 4, characterized in that, Each first memory tube in an adjacent column memory cell is connected to the same bit line, or each second memory tube in an adjacent column memory cell is connected to the same bit line.
6. The storage array as described in claim 4, characterized in that, The first storage tubes of the k-th column storage unit and the second storage tubes of the (k+1)-th column storage unit are connected to the same bit line, or the second storage tubes of the k-th column storage unit and the first storage tubes of the (k+1)-th column storage unit are connected to the same bit line, where k ≥ 1 and k is an integer.
7. A memory, characterized in that, include: The storage array according to any one of claims 1 to 6.
8. The memory as claimed in claim 7, characterized in that, include: The write unit, connected to the storage array, is adapted to perform write operations on the target storage tube using a hot carrier injection method.
9. The memory as claimed in claim 7, characterized in that, include: The erase unit, connected to the storage array, is adapted to perform erase operations on the row containing the target storage cell and adjacent row storage cells connected to the same storage pipe word line as the target storage cell using FN tunneling.
10. The memory as claimed in claim 7, characterized in that, include: The read unit is adapted to be connected to the storage array and adapted to perform read operations on the target storage tube.
11. A method for writing to a memory according to claim 7, characterized in that, include: When the target memory tube is the second memory tube in the memory cell, the target memory tube, the first memory tube and the select tube in the memory cell are turned on, and the other memory cells are turned off. The memory cell in which the target memory tube is located is then powered to enable writing to the target memory tube. When the target memory tube is the first memory tube in the memory cell, the target memory tube, the second memory tube and the select tube in the memory cell are turned on, and the other memory cells are turned off. The memory cell in which the target memory tube is located is then powered to enable writing to the target memory tube.
12. A method for erasing a memory according to claim 7, characterized in that, include: A first erase voltage is applied to the word lines of the storage pipe shared by the target storage cell and the adjacent row storage cell, and a second erase voltage is applied to the other word lines and bit lines connected to the target storage cell and the adjacent row storage cell. The first erase voltage is greater than the second erase voltage.
13. A method for reading a memory according to claim 7, characterized in that, include: When the target storage tube is the second storage tube in the storage unit, the first storage tube and the selection tube in the storage unit where the target storage tube is located are opened, and the target storage tube and other storage units are closed, so as to realize the reading of the target storage tube; When the target storage tube is the first storage tube in the storage unit, the second storage tube and the selection tube in the storage unit where the target storage tube is located are opened, and the target storage tube and other storage units are closed, so as to realize the reading of the target storage tube.