Memory controller and server

Abstract

The present invention discloses a memory controller and a server, wherein the memory controller is used to access a plurality of channels, wherein each channel includes a plurality of flash memory chips, and the memory controller includes a flash translation layer and a plurality of control modules. The flash translation layer is used to generate a command having a corresponding physical address of one of the plurality of channels, the plurality of control modules are respectively connected to the plurality of channels, and each control module operates independently to receive a corresponding command having a corresponding physical address from the flash translation layer to access the flash memory chip in the corresponding channel.

Description

Technical Field

[0001] The present invention relates to memory control, and more particularly to a control method and a control circuit applied to an all flash array (AFA) server. Background Art

[0002] Flash memory has been widely used in various data storage devices such as solid state drives (SSDs), and a server called an all-flash array server may only include SSDs without a traditional spinning-disk drive. In an all-flash array server, each SSD includes multiple flash memory chips, and each flash memory chip requires a fixed busy time during a read / write operation, that is, the flash memory chip cannot perform another read or write operation during the busy time. Therefore, if the all-flash array server needs to perform a large number of read / write operations on the SSD in a short time, the read / write operation will be delayed due to the influence of the above busy time. In addition, with the update of the fast peripheral component interconnect Express (PCIe) version, the transmission rate demand from the host device is getting higher and higher, and the number of read / write commands from the host device may also increase significantly. Therefore, how to effectively access the SSD is an important issue. Summary of the invention

[0003] Therefore, one of the objectives of the present invention is to disclose a new architecture of a memory controller in an all-flash array server to solve the above-mentioned problems.

[0004] According to one embodiment of the present invention, a memory controller for accessing multiple channels is disclosed. The memory controller includes a flash translation layer and a control module, wherein the flash translation layer is used to generate a command having a corresponding physical address of at least one channel of the multiple channels, the control module is connected to multiple flash memory chips, and includes a central processing unit, multiple command queues, an arbiter, a direct memory access engine, and a codec. The plurality of command queues correspond to the plurality of flash memory chips respectively, and each command queue only stores commands having a physical address of a corresponding flash memory chip. The arbitrator and direct memory access engine are used to execute the commands stored in the plurality of command queues, wherein when the arbitrator and direct memory access engine execute a read command in a specific command queue to read a raw data from a specific flash memory chip of the plurality of flash memory chips, the codec receives and decodes the raw data, and if the codec cannot successfully decode the raw data, the central processing unit transmits a retry command to the specific command queue to enable the arbitrator and direct memory access engine to read a soft data from the specific flash memory chip.

[0005] According to another embodiment of the present invention, a server including a network module, a processor, at least one channel and a memory controller is disclosed. The network module is used to connect to a client device via a network, the processor is used to control the operation of the server, and the at least one channel includes a plurality of flash memory chips. The memory controller is coupled between the processor and the at least one channel, and the memory controller includes a flash translation layer and a control module, wherein the flash translation layer is used to generate a command having a corresponding physical address of the at least one channel, and the control module is connected to the plurality of flash memory chips. The control module includes a central processing unit, a plurality of command queues, an arbitrator, a direct memory access engine and a codec. The plurality of command queues correspond to the plurality of flash memory chips respectively, and each command queue only stores commands having a physical address of a corresponding flash memory chip. The arbitrator and direct memory access engine are used to execute the commands stored in the plurality of command queues, wherein when the arbitrator and direct memory access engine execute a read command in a specific command queue to read a raw data from a specific flash memory chip of the plurality of flash memory chips, the codec receives and decodes the raw data, and if the codec cannot successfully decode the raw data, the central processing unit transmits a retry command to the specific command queue to enable the arbitrator and direct memory access engine to read a soft data from the specific flash memory chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 FIG. 4 is a schematic diagram of a server according to an embodiment of the present invention.

[0007] Figure 2 A schematic diagram of a flash memory chip according to an embodiment of the present invention is shown.

[0008] Figure 3 A schematic diagram of a control module according to an embodiment of the present invention is shown.

[0009] Figure 4 A schematic diagram illustrating the configuration of queues and buffers in a control module among a plurality of control modules according to an embodiment of the present invention is shown.

[0010] Figure 5 is a flow chart of a control method according to an embodiment of the present invention.

[0011] Figure 6 FIG. 4 is a schematic diagram of multiple states (programming states) of a memory cell of a three-level cell block and corresponding read voltages according to an embodiment of the present invention.

[0012] Figure 7 Schematic diagram of read voltages used for the soft decoding method.

[0013]

Explanation of symbols

[0014] 100: Server

[0015] 112: Network module

[0016] 114: Processor

[0017] 116: Dynamic Random Access Memory

[0018] 120: memory controller

[0019] 121,350: Interface circuit

[0020] 122: Flash conversion layer

[0021] 123: Main central processing unit

[0022] 125: Static Random Access Memory

[0023] 126_1~126_N,300: Control module

[0024] 130_1~130_N: Channel

[0025] 131_1~131_A,132_1~132_B,138_1~138_C,200: Flash memory chip

[0026] B_1~B_K: Block

[0027] P1~P256: Page

[0028] 310: Command Processor

[0029] 320: Central Processing Unit

[0030] 330,430: Buffer

[0031] 340:Codec

[0032] 410: First buffer

[0033] 420: Second buffer

[0034] 431_1~431_A: Command Queue

[0035] 440: Arbitrator and direct memory access engine

[0036] 500~518: Steps

[0037] S0~S7: Status

[0038] VR1~VR7,VR11~VR14,VR51~VR54: read voltage DETAILED DESCRIPTION

[0039] Certain terms are used in the following embodiments and the scope of the invention patent application to refer to specific system components. As those skilled in the art will appreciate, manufacturers may use different names to refer to a component. This document does not intend to distinguish between components with different names but the same functions. In the following embodiments and the scope of the invention patent application, the term "including" is used in an open manner and should be interpreted as "including but not limited to..." The term "coupled" is intended to indicate an indirect or direct electrical connection. Therefore, if a first device is coupled to a second device, the connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

[0040] Figure 1 FIG. 1 is a schematic diagram of a server 100 according to an embodiment of the present invention, wherein the server 100 is an all-flash array server. Figure 1As shown, the server 100 includes a network module 112, a processor 114, a dynamic random access memory (DRAM) 116 (for the sake of convenience, labeled as "DRAM"), a memory controller 120, and a plurality of channels 130_1-130_N, where 'N' can be any positive integer greater than or equal to 2. The memory controller 120 includes an interface circuit 121, a flash translation layer (FTL) 122 (for the sake of convenience, labeled as "FTL"), and a plurality of control modules 126_1-126_N, where the flash translation layer 122 includes a main central processing unit (CPU) 123 (for the sake of convenience, labeled as "main CPU") and a static random access memory (SRAM) 125 (for the sake of convenience, labeled as "SRAM"). The multiple channels 130_1-130_N are respectively connected to the multiple control modules 126_1-126_N, and each channel includes multiple flash memory chips. For example, the channel 130_1 includes multiple flash memory chips 131_1-131_A, the channel 130_2 includes multiple flash memory chips 132_1-132_B, and the channel 130_N includes multiple flash memory chips 138_1-138_C. In addition, each of the multiple channels 130_1-130_N can be regarded as a pluggable solid state drive.

[0041] Figure 2 FIG. 2 is a schematic diagram of a flash memory chip 200 according to an embodiment of the present invention, wherein the flash memory chip 200 can be used to implement each of the flash memory chips 131_1 ˜ 131_A, 132_1 ˜ 132_B, and 138_1 ˜ 138_C. Figure 2As shown, the flash memory chip 200 includes a plurality of blocks B_1 to B_K, wherein a block is the smallest erase unit of the flash memory chip 200, and each of the plurality of blocks B_1 to B_K may have a single-level cell (SLC) array, a multiple-level cell (MLC) array, a triple-level cell (TLC) array, or a quad-level cell (QLC) array, and each block includes a plurality of pages such as P1 to P256, wherein a page is the smallest write unit of the flash memory chip 200. In addition, the plurality of blocks B_1 to B_K in the flash memory chip 200 may be divided into a plurality of planes for parallel operation.

[0042] The server 100 is used to connect to at least one client device via the Internet or Ethernet. The network module 112 is used as an interface to receive data from the client device and transmit the data to the client device. The processor 114 is used to control the operation of the server 100. For example, when the processor 114 receives a read command from the client device, the processor 114 refers to a logical address in the read command to transmit a request to the memory controller 120 to request to read the data corresponding to the logical address of the read command, and the processor 114 transmits the data read from at least one channel of the plurality of channels 130_1-130_N to the client device. In addition, when the processor 114 receives a write command and corresponding data from the client device, the data may be temporarily stored in the dynamic random access memory 116, and the processor 114 may perform compression and / or de-duplication operations on the data. The processor 114 then stores the data to at least one channel of the plurality of channels 130_1-130_N through the memory controller 120.

[0043] The memory controller 120 may be implemented by a single chip and may be used to perform operations between the processor 114 of the server 100 and the plurality of channels 130_1 to 130_N. For the components in the memory controller 120, the interface circuit 121 is connected to the processor 114, and the interface circuit 121 may comply with the Non-Volatile Memory Express (NVMe) standard and the fast external component interconnect standard. The flash translation layer 122 is used to perform operations such as the basic mapping scheme, garbage collection, etc. The main CPU 123 may refer to the L2P or P2L table to perform a mapping scheme on the logical address in the read command to obtain the mapping scheme of the plurality of channels 130_1 to 130_N. The physical addresses of 30_1-130_N are used to obtain data from the multiple channels 130_1-130_N. The static random access memory 125 or the dynamic random access memory 116 can also store health-related information for garbage collection, wear leveling mechanism and / or block management, wherein the health-related information can include a read count table recording the number of reads of each block, an erase count table recording the number of erases of each block, a valid page table recording the number of valid pages in each block, and a data retention table recording the write time of each block.

[0044] As described in the background description of the present invention, along with the update of the fast peripheral component interconnect version, the transmission rate requirement from the host device is getting higher and higher, and the number of read / write commands from the host device may also increase significantly. Therefore, the memory controller 120 is designed with a plurality of control modules 126_1~126_N corresponding to the plurality of channels 130_1~130_N, and this internal parallelism enables the memory controller 120 to process a plurality of incoming read / write commands in parallel and achieve a higher bandwidth. Specifically, the main CPU 123 may have an arbiter for transmitting read / write commands and related physical addresses of the plurality of channels 130_1-130_N to the plurality of control modules 126_1-126_N, and each of the plurality of control modules 126_1-126_N operates independently and transmits responses to the main CPU 123. For example, when the main CPU 123 transmits a first read command and a second read command to the control module 126_1 and the control module 126_2 respectively, the control module 126_1 obtains data from the channel 130_1 with reference to the physical address of the first read command and transmits the data to the main CPU 123, and the control module 126_2 obtains data from the channel 130_2 with reference to the physical address of the second read command and transmits the data to the main CPU 123. It should be noted that the physical addresses received by the control modules 126_1 - 126_N indicate a chip number, a block number, and a page number of the channel. That is, the control modules 126_1 - 126_N do not need to perform any address mapping mechanism.

[0045] Figure 3 A schematic diagram of a control module 300 according to an embodiment of the present invention is shown, wherein the control module 300 can be used to implement Figure 1 Each of the multiple control modules 126_1 to 126_N shown in FIG. Figure 3As shown, the control module 300 includes a command processor 310, a central processing unit 320 (for the sake of simplicity, labeled as "CPU"), a buffer 330, a codec 340 (including an encoder and a decoder), and an interface circuit 350. The command processor 310 is used to receive commands from the flash conversion layer 122 and notify the central processing unit 320 to perform corresponding operations. Specifically, if the command processor 310 receives a read command with a corresponding physical address from the flash conversion layer 122, the central processing unit 320 can control the interface circuit 350 to request data stored in the physical address of at least one channel of the plurality of channels 130_1-130_N; and after the interface circuit 350 obtains raw data from at least one channel of the plurality of channels 130_1-130_N, the codec 340 decodes the raw data to generate decoded data, and the central processing unit 320 transmits the decoded data to the flash conversion layer 122 through the command processor 310. If the command processor 310 receives a write command having a corresponding physical address and corresponding data from the flash translation layer 122, the codec 340 encodes the data to generate encoded data, and the central processing unit 320 can control the interface circuit 350 to write the encoded data to the physical address of at least one channel of the multiple channels 130_1~130_N; and after the encoded data is successfully written to at least one channel of the multiple channels 130_1~130_N, the central processing unit 320 or the command processor 310 notifies the flash translation layer 122 that the write command has been completed. If the command processor 310 receives an erase command with a corresponding physical address (e.g., a chip number and a block number) from the flash translation layer 122, the central processing unit 320 can control the interface circuit 350 to notify at least one channel of the multiple channels 130_1~130_N to erase the block with the physical address; and after the block is successfully erased, the central processing unit 320 or the command processor 310 notifies the flash translation layer 122 that the erase command has been completed.

[0046] In one embodiment, the main CPU 123 of the flash translation layer 122 is used to perform event-driven operations, and the CPU 320 in the control module 300 is used to perform timing-driven operations. In detail, because the flash translation layer 122 has many tables about the health of blocks, such as a read count table, an erase count table, a valid page table, and a data retention table, the main CPU 123 can refer to these tables to determine specific blocks that may have quality problems. For example, the main CPU 123 can determine that blocks with a read count higher than a threshold value may have a read barrier problem, the main CPU 123 can determine that blocks with a valid page count lower than a threshold value need to be garbage collected, and the main CPU 123 can determine that blocks with a write time older than a specific time may have data retention problems; then the main CPU 123 can perform garbage collection operations or wear leveling operations on these blocks to improve data quality. In addition, the main CPU 123 can perform garbage collection operation or wear leveling operation by transmitting a read command (garbage collection read command) and a write command (garbage collection write command) to at least one control module of the multiple control modules 126_1~126_N, and the multiple control modules 126_1~126_N execute these read / write commands.

[0047] The control module 300 may periodically scan the blocks in the corresponding channel to determine whether any block has a quality problem, wherein the period may be several minutes or any other appropriate time. Specifically, the control module 300 may read certain pages in a block to determine whether the block has poor quality, wherein the codec 340 may decode the data read from the page to obtain decoding information such as an error bit number or decoding time, and the central processing unit 320 may determine that the block has poor quality by the error bit number being higher than a threshold or the decoding time being longer than a predetermined time. In addition, after the control module 300 determines the health information by periodically scanning the blocks, the central processing unit 320 may actively process these blocks with poor quality, or the central processing unit 320 may transmit the health information to the flash translation layer 122. Specifically, if the control module 300 determines that the three blocks of the corresponding channel have poor quality, the central processing unit 320 can actively move the data of the three blocks to blank blocks respectively without notifying the flash translation layer 122; and after successfully moving the data, the central processing unit 320 creates an address mapping table of data in the old blocks (such as the three blocks with poor quality mentioned above) and the new blocks (such as the blank blocks used to store data from the old blocks), and the address mapping table is transmitted to the flash translation layer 122 to update the P2L table or L2P table stored in the static random access memory 125 or the dynamic random access memory 116; and only when the main central processing unit 123 successfully updates the P2L table or L2P table through the address mapping table generated by the control module 300, the old blocks are allowed to be erased. In another example, if the control module 300 determines that three blocks of the corresponding channel have poor quality, the CPU 320 can directly transmit the health information to the flash translation layer 122 so that the main CPU 123 creates a table to record the blocks with poor quality; and the main CPU 123 can give priority to garbage collection operations on these blocks.

[0048] In view of the above, by designing multiple control modules 126_1~126_N in the memory controller 120 to respectively process the access of multiple channels 130_1~130_N, the memory controller 120 can effectively process a large number of read / write commands. In addition, by configuring the main central processing unit 123 to perform event-driven operations and configuring the multiple control modules 126_1~126_N to perform timing-driven operations, the main central processing unit 123 can become more efficient in execution and simpler in design.

[0049] In addition, each of the plurality of control modules 126_1-126_N may receive many commands from the host (eg, the processor 114 of the server 100) in a short period of time, thereby causing congestion in the internal buffer. Therefore, the present invention further discloses Figure 4 Another embodiment is shown to overcome the command congestion problem. Figure 4 A schematic diagram is shown of a configuration of queues and buffers in a control module of a plurality of control modules 126_1 to 126_N according to an embodiment of the present invention, wherein Figure 3 The control module 126_1 shown in the figure is taken as an example. Figure 4 As shown, the control module 126_1 includes a first buffer 410, a second buffer 420, a buffer 430 including a plurality of command queues 431_1-431_A, and an arbiter and a direct memory access (DMA) engine 440, wherein the arbiter and the direct memory access engine 440 are coupled to the plurality of flash memory chips 131_1-131_A. In this embodiment, the first buffer 410 and the second buffer 420 may be located at Figure 3 In the command processor 310 or buffer 330 shown, a plurality of command queues 431_1 ˜ 431_A and an arbiter and a direct memory access engine 440 may be located in the interface circuit 350 .

[0050] The first buffer 410 and the second buffer 420 are used to receive commands from the flash translation layer 122 and self-generated commands (e.g., read / write commands generated by the central processing unit 320 to perform a timing driving operation). In one embodiment, the first buffer 410 is used to store write commands, and the second buffer 420 is used to store read commands. In another embodiment, the first buffer 410 is used to store commands with a high priority, and the second buffer 420 is used to store commands with a lower priority, wherein the commands with a higher priority may include a read command from the host (e.g., a read command from the processor 114), and the commands with a lower priority may include a write command from the host, a write command generated by the flash translation layer 122 (e.g., a write command related to a garbage collection operation), a read command generated by the flash translation layer 122 (e.g., a read command related to a garbage collection operation) and / or a self-generated command (e.g., a read / write command generated by the central processing unit 320 to perform a timing driving operation).

[0051] The plurality of command queues 431_1 to 431_A respectively correspond to the plurality of planes of the channel 130_1. In this embodiment, it is assumed that each of the plurality of flash memory chips 131_1 to 131_A has only one plane, and thus the plurality of command queues 431_1 to 431_A respectively correspond to the plurality of flash memory chips 131_1 to 131_A. That is, the command queue 430_1 only stores commands having the physical address of the flash memory chip 131-_1, the command queue 430_2 only stores commands having the physical address of the flash memory chip 131-_2, ..., and the command queue 430_A only stores commands having the physical address of the flash memory chip 131-_A. Therefore, the command processor 310 or the central processing unit 320 refers to the physical address of the command in the first buffer 410 and the second buffer 420 to transmit the command to the corresponding command queue. For example, if the first buffer 410 has a write command with the physical address of the flash memory chip 131_2, the command processor 310 or the central processing unit 320 will move the write command to the command queue 131_2; and if the first buffer 420 has a read command with the physical address of the flash memory chip 131_A, the command processor 310 or the central processing unit 320 will move the read command to the command queue 131_A.

[0052] In one embodiment, the command processor 310 or the central processing unit 320 may determine the order in which commands are stored in the command queues according to the configuration of the first buffer 410 and the second buffer 420. For example, if the first buffer 410 is used to store commands with higher priorities and the second buffer 420 is used to store commands with lower priorities, then even if the second buffer 410 has more commands or the commands in the second buffer 420 stay longer than the commands in the first buffer 410, the command processor 310 or the central processing unit 320 may preferentially move the commands in the first buffer 410 to the multiple command queues 431_1 to 431_A.

[0053] The arbiter and direct memory access engine 440 is used to continuously scan the multiple flash memory chips 131_1~131_A to determine the status of the multiple flash memory chips 131_1~131_A, and once the arbiter and direct memory access engine 440 determines that a flash memory chip is not busy and can be accessed, the arbiter and direct memory access engine 440 immediately executes the command in the corresponding command queue. Specifically, each time the flash memory chip receives a command, the flash memory chip requires a busy time to execute the command, wherein the busy time can be a fixed time for a read command (such as 60 microseconds or 80 microseconds), or the busy time can be another fixed time for a write command. Therefore, the arbiter and direct memory access engine 440 periodically scans the plurality of flash memory chips 131_1 to 131_A (e.g., round-robin scan) to determine which flash memory can be accessed, wherein the arbiter and direct memory access engine 440 can detect a pin of each flash memory chip, and the pin has a signal that can indicate whether the flash memory chip is busy. For example, if the arbiter and direct memory access engine 440 detects that the flash memory chip 131_1 is busy, the arbiter and direct memory access engine 440 immediately detects the next flash memory chip 131_2; and if the arbiter and direct memory access engine 440 detects that the flash memory chip 131_2 is not busy, the arbiter and direct memory access engine 440 executes the command in the command queue 431_2 to access the flash memory chip 131_2, wherein if the write command is executed, the arbiter and direct memory access engine 440 can directly write data to the flash memory chip 131_2, and if the read command is executed, the arbiter and direct memory access engine 440 can directly read data from the flash memory chip 131_2; further, if the arbiter and direct memory access engine 440 detects that the next flash memory chip is busy, the processing of the flash memory chip 131_2 is not considered.

[0054] In view of the above, since each of the multiple command queues 431_1~431_A in the control module 123_1 / 300 corresponds to a dedicated flash memory chip or a dedicated plane in a flash memory chip, even if the control module 126_1 / 300 receives many commands in a short time, the arbiter and the direct memory access engine 440 can utilize this internal parallelism to efficiently access the multiple flash memory chips 131_1~131_A.

[0055] During the scanning operation of the arbiter and direct memory access engine 440, the arbiter and direct memory access engine 440 continuously detects the plurality of flash memory chips 131_1-131_A in sequence, that is, each flash memory chip is detected only once in a scanning cycle. In another embodiment, the arbiter and direct memory access engine 440 may perform more detection operations for a specific flash memory chip in a scanning cycle. For example, if the command queue 431_2 has a read command with a higher priority, the arbiter and direct memory access engine 440 may increase the detection rate of the flash memory chip 131_2 (that is, the detection rate of the flash memory chip 131_2 is higher than the detection rate of other flash memory chips), or the arbiter and direct memory access engine 440 may only detect the flash memory chip 131_2 until the read command with a higher priority is executed.

[0056] exist Figure 3 as well as Figure 4 In the control module 126_1 / 130 shown, since the arbiter and direct memory access engine 440 utilize the internal parallelism (ie, the plurality of command queues 431_1-431_A) to access the plurality of flash memory chips 131_1-131_A, each flash memory chip can operate independently without being affected by the failure of other flash memory chips. Figure 5 4 is a flow chart of a control method according to an embodiment of the present invention. In the following description, the command queue 431_1 and the corresponding flash memory chip 131_1 are used as an example. In step 500, the process starts, and the command queue 431_1 stores a read command. In step 502, the arbiter and direct memory access engine 440 detects that the flash memory chip 131_1 is not busy, and the arbiter and direct memory access engine 440 executes the read command in the command queue 431_1 and sets a busy time (e.g., 80 microseconds) for the flash memory chip 131_1. In step 504, the arbiter and direct memory access engine 440 reads a raw data from the flash memory chip 131_1 according to the physical address in the read command. In step 506, the codec 340 receives the raw data from the arbiter and direct memory access engine 440, and the codec 340 decodes the raw data using a hard decoding method. In this embodiment, the hard decoding method may be a BCH (Bose-Chaudhuri-Hocquenghem) decoding method, and the original data is obtained by using a preset read voltage. Specifically, assuming that the block to be read is a three-level cell block (i.e., each memory cell in the block stores three bits), Figure 6FIG. 1 is a schematic diagram of multiple states (programming states) of a memory cell of a three-level cell block and corresponding read voltages according to an embodiment of the present invention. Figure 6 As shown, each memory cell can have 8 states, and each state represents a different combination of three bits (named as the least significant bit (LSB), the center significant bit (CSB), and the most significant bit (MSB)). Figure 6 In the illustrated embodiment, when the memory cell is programmed to have state S0, the least significant bit, the middle significant bit, and the most significant bit stored in the memory cell are (1, 1, 1); when the memory cell is programmed to have state S1, the least significant bit, the middle significant bit, and the most significant bit stored in the memory cell are (1, 1, 0); when the memory cell is programmed to have state S2, the least significant bit, the middle significant bit, and the most significant bit stored in the memory cell are (1, 0, 0); when the memory cell is programmed to have state S3, the least significant bit, the middle significant bit, and the most significant bit stored in the memory cell are (0, 0, 0); 0); when the memory cell is programmed to have state S4, the least significant bit, the middle significant bit, and the most significant bit stored in the memory cell are (0, 1, 0); when the memory cell is programmed to have state S5, the least significant bit, the middle significant bit, and the most significant bit stored in the memory cell are (0, 1, 1); when the memory cell is programmed to have state S6, the least significant bit, the middle significant bit, and the most significant bit stored in the memory cell are (0, 0, 1); and when the memory cell is programmed to have state S7, the least significant bit, the middle significant bit, and the most significant bit stored in the memory cell are (1, 0, 1).

[0057] When the arbiter and direct memory access engine 440 want to read the least significant bit, the arbiter and direct memory access engine 440 can control the flash memory chip 131_1 to apply two read voltages VR3 and VR7 to read the memory cell. If the memory cell is conductive when the read voltage VR7 is applied or the memory cell is non-conductive when the read voltage VR3 is applied, the least significant bit is judged to be "1"; if the memory cell is non-conductive when the read voltage VR7 is applied and conductive when the read voltage VR3 is applied, the least significant bit is judged to be "0". When the arbiter and direct memory access engine 440 want to read the intermediate valid bit, the arbiter and direct memory access engine 440 can control the flash memory chip 131_1 to apply three read voltages VR2, VR4 and VR6 to read the memory cell. If the memory cell is non-conductive when the read voltage VR2 is applied, the intermediate valid bit is determined to be "1"; if the memory cell is non-conductive when the read voltage VR4 is applied, and is conductive when the read voltage VR2 is applied, the intermediate valid bit is determined to be "0"; if the memory cell is non-conductive when the read voltage VR6 is applied, and is conductive when the read voltage VR4 is applied, the intermediate valid bit is determined to be "1"; and, if the memory cell is conductive when the read voltage VR6 is applied, the intermediate valid bit is determined to be "0". When the arbiter and direct memory access engine 440 want to read the most significant bit, the arbiter and direct memory access engine 440 can control the flash memory chip 131_1 to apply two read voltages VR1 and VR5 to read the memory cell. If the memory cell is conductive when the read voltage VR5 is applied, or the memory cell is non-conductive when the read voltage VR1 is applied, then the most significant bit is judged to be "1"; if the memory cell is non-conductive when the read voltage VR5 is applied, and if the memory cell is conductive when the read voltage VR1 is applied, then the most significant bit is judged to be "0".

[0058] exist Figure 6 In the illustrated embodiment, the least significant bits of all memory cells on a single word line constitute a least significant bit data page (logical page), the middle significant bits of all memory cells on a single word line constitute a middle significant bit data page (logical page), and the most significant bits of all memory cells on a single word line constitute a most significant bit data page (logical page), that is, each word line of the three-level cell block has three data pages: the least significant bit data page, the middle significant bit data page, and the most significant bit data page.

[0059] It is worth noting that Figure 6The gray code shown is for illustration only and is not intended to be limiting of the present invention. Any appropriate gray code may be applied to the flash memory chip 131_1 and the read voltages for determining the least significant bit, the middle significant bit, and the most significant bit may vary accordingly.

[0060] The original data obtained in step 504 is generated using only a plurality of read voltages VR1 - VR7 .

[0061] In step 508 , the codec 340 determines whether the original data is successfully decoded. If so, the process proceeds to step 510 ; if not, the process proceeds to step 512 .

[0062] In step 510 , the codec 340 outputs the decoded data to the command processor 310 or the CPU 320 . If the read command comes from the flash translation layer 122 or the host (eg, the processor 114 ), the command processor 310 or the CPU 320 further transmits the decoded data to the flash translation layer 122 .

[0063] In step 512, the central processing unit 320 transmits a retry command to the command queue 431_1, wherein the retry command has the same physical address as the previous read command, and the retry command corresponds to twice the busy time (e.g., 160 microseconds). It is worth noting that the original data obtained in step 504 is still stored in the codec 340.

[0064] In step 514, the arbiter and direct memory access engine 440 detects that the flash memory chip 131_1 is not busy, and the arbiter and direct memory access engine 440 executes the retry command in the command queue 431_1 and sets a twice busy time for the flash memory chip 131_1. The arbiter and direct memory access engine 440 reads a soft data from the flash memory chip 131_1 according to the physical address in the read command.

[0065] In step 516, the codec 340 receives the soft data from the arbiter and the direct memory access engine 440, and the codec 340 uses a soft decoding method to decode the original data using the soft data. In this embodiment, the soft decoding method may be a low-density parity-check code (LDPC) decoding method, and the soft data is decoded by using different Figure 6 The preset read voltages VR1 to VR7 are obtained by referring to Figure 7 , Figure 7Schematic diagram of read voltages used in the soft decoding method, the flash memory chip 131_1 can use multiple read voltages VR11-VR14 around the read voltage VR1 to read each memory cell of the word line to generate multiple first bits (i.e., 4 first bits); and the flash memory chip 131_1 can also use multiple read voltages VR51-VR54 to read each memory cell of the word line to generate multiple second bits (i.e., 4 second bits). In this embodiment, the first bits and the second bits of each memory cell of the word line can be used as soft data.

[0066] In step 518 , the codec 340 outputs the decoded data to the command processor 310 or the CPU 320 . If the read command comes from the flash translation layer 122 or the host, the command processor 310 or the CPU 320 further transmits the decoded data to the flash translation layer 122 .

[0067] It is worth noting that steps 502, 504, 506, 508, 512, 514 and 516 are only executed inside the control module 126_1 without receiving any instructions from the flash translation layer 122. That is, if the codec 340 cannot decode the original data obtained in step 504, the central processing unit 320 in the control module 126_1 can actively generate the retry command to the command queue 131_1 without notifying the flash translation layer 122 to receive the instruction. Therefore, the decoding process is more efficient.

[0068] Furthermore, if the codec 340 fails to decode the original data of the flash memory chip 131_1 in step 504 , the other flash memory chips 131_2 ˜ 131_A still operate normally without being affected by the decoding failure of the flash memory chip 131_1 .

[0069] In summary, in the memory controller of the present invention, by designing multiple control modules corresponding to multiple channels respectively, and by designing multiple command queues corresponding to multiple planes / chips of the channels respectively, the memory controller can effectively process many commands in a short time to overcome the command congestion problem in the prior art.

[0070] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

Claims

1. A memory controller for accessing a plurality of flash memory chips, and comprising: a flash translation layer for generating a command corresponding to a physical address of at least one channel among the plurality of channels; and A control module coupled to the flash conversion layer, wherein the control module is connected to the plurality of flash memory chips, and the control module includes: a central processing unit; A plurality of command queues, wherein the plurality of command queues correspond to a plurality of flash memory chips respectively, and each of the plurality of command queues stores only a command having a physical address of a corresponding flash memory chip; an arbiter and direct memory access engine coupled to the plurality of command queues and configured to execute commands stored in the plurality of command queues; as well as a codec coupled to the arbiter and the direct memory access engine; wherein when the arbiter and direct memory access engine execute a read command in a specific command queue to read a raw data from a specific flash memory chip of the plurality of flash memory chips, the codec receives the raw data and decodes the raw data; and if the codec fails to successfully decode the raw data, the central processing unit sends a retry command to the specific command queue to enable the arbiter and direct memory access engine to read a soft data from the specific flash memory chip; When the arbiter and the direct memory access engine execute the read command in the specific command queue to read the original data from the specific flash memory chip, the arbiter and the direct memory access engine set a first busy time for the read command; And if the codec cannot successfully decode the original data, the central processing unit transmits the retry command to the specific command queue, and when the arbiter and the direct memory access engine execute the retry command in the specific command queue to read the soft data from the specific flash memory chip, the arbiter and the direct memory access engine set a second busy time for the retry command that is different from the first busy time.

2. The memory controller according to claim 1, wherein: The read command and the retry command have the same physical address of the specific flash memory chip, and the multiple read voltages used to execute the read command to read the original data from the specific flash memory chip are different from the multiple read voltages used to execute the retry command to read the soft data from the specific flash memory chip; and after the retry command is executed, the codec uses the soft data to decode the original data to generate a decoded data to the flash translation layer.

3. The memory controller according to claim 1, wherein: If the codec cannot successfully decode the raw data, the central processing unit sends the retry command to the specific command queue to enable the arbiter and the direct memory access engine to read the soft data from the specific flash memory chip without receiving a command from the flash translation layer.

4. The memory controller according to claim 3, wherein: The second busy time is longer than the first busy time.

5. The memory controller according to claim 1, wherein: The arbiter and the direct memory access engine are used to scan the plurality of flash memory chips to determine the status of the plurality of flash memory chips to determine whether to execute the commands stored in the plurality of command queues; And the access of any flash memory chip of the plurality of flash memory chips is independent of the access of other flash memory chips.

6. The memory controller according to claim 1, wherein: If the codec fails to successfully decode the original data, other flash memory chips still operate normally without being affected by the decoding failure of the specific flash memory chip.

7. A server comprising: A network module, used to connect to the client through the network; a processor for controlling the operation of the server; at least one channel including a plurality of flash memory chips; and A memory controller is coupled between the processor and the at least one channel, wherein the memory controller includes: a flash translation layer for generating a command having a corresponding physical address of the at least one channel; and A control module coupled to the flash conversion layer, wherein the control module is connected to the plurality of flash memory chips, and the control module includes: a central processing unit; A plurality of command queues, wherein the plurality of command queues correspond to the plurality of flash memory chips respectively, and each of the plurality of command queues stores only commands having a physical address of a corresponding flash memory chip; an arbiter and direct memory access engine coupled to the plurality of command queues and configured to execute commands stored in the plurality of command queues; as well as a codec coupled to the arbiter and the direct memory access engine; wherein when the arbiter and direct memory access engine execute a read command in a specific command queue to read a raw data from a specific flash memory chip of the plurality of flash memory chips, the codec receives the raw data and decodes the raw data; and if the codec fails to successfully decode the raw data, the central processing unit sends a retry command to the specific command queue to enable the arbiter and direct memory access engine to read a soft data from the specific flash memory chip; When the arbiter and the direct memory access engine execute the read command in the specific command queue to read the original data from the specific flash memory chip, the arbiter and the direct memory access engine set a first busy time for the read command; And if the codec cannot successfully decode the original data, the central processing unit transmits the retry command to the specific command queue, and when the arbiter and the direct memory access engine execute the retry command in the specific command queue to read the soft data from the specific flash memory chip, the arbiter and the direct memory access engine set a second busy time for the retry command that is different from the first busy time.

8. The server according to claim 7, wherein: The read command and the retry command have the same physical address of the specific flash memory chip, and the multiple read voltages used to execute the read command to read the original data from the specific flash memory chip are different from the multiple read voltages used to execute the retry command to read the soft data from the specific flash memory chip; and after the retry command is executed, the codec uses the soft data to decode the original data to generate a decoded data to the flash translation layer.

9. The server according to claim 7, wherein: If the codec cannot successfully decode the raw data, the central processing unit sends the retry command to the specific command queue to enable the arbiter and the direct memory access engine to read the soft data from the specific flash memory chip without receiving a command from the flash translation layer.

10. The server according to claim 7, wherein: The second busy time is longer than the first busy time.

11. The server according to claim 7, wherein: The arbiter and the direct memory access engine are used to scan the plurality of flash memory chips to determine the status of the plurality of flash memory chips to determine whether to execute the commands stored in the plurality of command queues; And the access of any flash memory chip of the plurality of flash memory chips is independent of the access of other flash memory chips.

12. The server according to claim 7, wherein: If the codec fails to successfully decode the original data, other flash memory chips still operate normally without being affected by the decoding failure of the specific flash memory chip.

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