System-on-Chip and Control Method

Abstract

The present invention provides a system single chip and a control method. The system single chip includes a first terminal circuit, a second terminal circuit, and a distribution circuit. The first terminal circuit records a first attribute setting value. The second terminal circuit records a second attribute setting value. When the distribution circuit dispatches an output instruction to the first terminal circuit, the first terminal circuit determines whether the attribute information of the output instruction conforms to the first attribute setting value. When the attribute information of the output instruction conforms to the first attribute setting value, the first terminal circuit executes the output instruction. When the distribution circuit dispatches the output instruction to the second terminal circuit, the second terminal circuit determines whether the attribute information of the output instruction conforms to the second attribute setting value. When the attribute information of the output instruction conforms to the second attribute setting value, the second terminal circuit executes the output instruction.

Description

Technical Field

[0001] The present invention relates to the technical field of system-on-chip, and more particularly to a system-on-chip having a plurality of terminal devices, wherein each terminal device stores a specific attribute setting value. Background Art

[0002] Since the Internet of Things (IOT) can connect many objects to the Internet for the purpose of object identification and intelligent management, the IOT technology has gradually been applied to many fields. Moreover, the IOT technology can be used to save energy consumption and improve people's lives. However, with the booming development of the IOT, security is a very important requirement. Summary of the Invention

[0003] The present invention provides a system-on-chip, including a first terminal circuit, a second terminal circuit, and a distribution circuit. The first terminal circuit records a first attribute setting value. The second terminal circuit records a second attribute setting value. The distribution circuit dispatches an output instruction to the first terminal circuit or the second terminal circuit according to the address information of an output instruction. When the distribution circuit dispatches the output instruction to the first terminal circuit, the first terminal circuit determines whether the attribute information of the output instruction conforms to the first attribute setting value. When the attribute information of the output instruction conforms to the first attribute setting value, the first terminal circuit executes the output instruction. When the distribution circuit dispatches the output instruction to the second terminal circuit, the second terminal circuit determines whether the attribute information of the output instruction conforms to the second attribute setting value. When the attribute information of the output instruction conforms to the second attribute setting value, the second terminal circuit executes the output instruction.

[0004] The present invention further provides a control method applicable to a system-on-chip. The system-on-chip has a first terminal circuit and a second terminal circuit. The control method of the present invention includes storing a first attribute setting value in the first terminal circuit; storing a second attribute setting value in the second terminal circuit; decoding a first output instruction for dispatching the first output instruction to the first terminal circuit or the second terminal circuit. When the first output instruction is dispatched to the first terminal circuit, the first terminal circuit determines whether the attribute information of the first output instruction conforms to the first attribute setting value. When the attribute information of the first output instruction conforms to the first attribute setting value, the first terminal circuit executes the first output instruction. When the first distribution circuit dispatches the first output instruction to the second terminal circuit, the second terminal circuit determines whether the attribute information of the first output instruction conforms to the second attribute setting value. When the attribute information of the first output instruction conforms to the second attribute setting value, the second terminal circuit executes the first output instruction.

[0005] The control method described in the present invention can be implemented by the system single chip of the present invention, which is hardware or firmware capable of executing specific functions, or can be included in a recording medium in the form of source code and implemented in combination with specific hardware. When the source code is loaded and executed by an electronic device, a processor, a computer, or a machine, the electronic device, the processor, the computer, or the machine is the system single chip for implementing the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 It is a schematic diagram of the system single chip of the present invention.

[0007] Figure 2 It is another schematic diagram of the system single chip of the present invention.

[0008] Figure 3 It is another schematic diagram of the system single chip of the present invention.

[0009] Figure 4 It is a schematic flowchart of the control method of the present invention.

[0010] SYMBOLS USED IN THE DRAWINGS:

[0011] 100, 200, 300: System single chip

[0012] 110, 210, 310: Main control layer

[0013] 120, 220, 320: Device layer

[0014] 130, 230, 330: Peripheral layer

[0015] 111, 211, 212, 311~313: Main control circuit

[0016] 121 222, 223, 322, 323: Distribution circuit

[0017] 131, 132, 231~235, 331~335: Terminal circuit

[0018] 133, 134: Control circuit

[0019] 135, 136: Peripheral circuit

[0020] 221, 321: Routing circuit

[0021] 324, 325: High-order control circuit

[0022] AS 131 ,AS 132 ,AS 231 ~AS 235 ,AS 324 ,AS 325: Attribute setting value

[0023] SO CM1 ~SO CM4 : Output instruction

[0024] S CM1 ~S CM3 : Instruction

[0025] S411~S415: Steps Detailed implementation manner

[0026] To make the objectives, features, and beneficial effects of the present invention more obvious and understandable, specific embodiments are given below and detailed descriptions are made in conjunction with the accompanying drawings. The specification of the present invention provides different embodiments to illustrate the technical features of different implementation manners of the present invention. Among them, the configuration of each component in the embodiments is only for illustration and is not used to limit the present invention. In addition, the reference numerals in the drawings of the embodiments are partially repeated for the purpose of simplifying the description and do not imply the relevance between different embodiments.

[0027] Figure 1 Is a schematic diagram of the system single chip of the present invention. As shown in the figure, the system single chip (system on chip; SoC) 100 includes a master layer 110, a device layer 120, and a peripheral layer 130. In this embodiment, the master layer 110 includes a master circuit 111. The master circuit 111 is used to generate an instruction S CM1 . The present invention does not limit the type of the master circuit 111. Any circuit with data processing capabilities can be used as the master circuit 111. In an alternative embodiment, the master circuit 111 is a processor or a memory transfer controller, such as a direct memory access controller. In another alternative embodiment, the master circuit 111 is a secure device for performing highly secure operations, such as mobile payment. In some embodiments, the master circuit 111 is a data processing unit, such as an encryption / decryption circuit and a convolutional neural network accelerator. In other embodiments, the master layer has more master circuits.

[0028] In this embodiment, the device layer 120 includes a distribution circuit 121. In an alternative embodiment, the distribution circuit 121 has a plurality of decoding devices. In other embodiments, the distribution circuit 121 further includes a busmaster slave interface or a bus bridge for peripheral devices. The distribution circuit 121 decodes the instruction S CM1 , to obtain a decoding result (such as address information). In this example, the distribution circuit 121 provides the instruction S CM1 to the peripheral layer 130 according to the address information of the instruction S CM1 . The present invention does not limit the architecture of the distribution circuit 121. In an alternative embodiment, the distribution circuit 121 is a bridge between a high-frequency circuit and a low-frequency circuit, such as a peripheral bridge. In this example, the operating frequency of the components in the main control layer 110 may be higher than 100 MHz, even greater than 1 GHz, while the operating frequency of the components in the peripheral layer 130 may be below 100 MHz, even kHz.

[0029] In this embodiment, the peripheral layer 130 includes terminal circuits 131 and 132. The terminal circuit 131 records an attribute setting AS 131 . In an alternative embodiment, the terminal circuit 131 is an end device. As shown in the figure, the terminal circuit 131 includes a control circuit 133 and a peripheral circuit 135. In this example, the control circuit 133 determines whether the main control circuit 111 that sends the instruction S CM1 has the right to access the peripheral circuit 135.

[0030] The present invention does not limit how the control circuit 133 determines whether the main control circuit 111 that sends the instruction S CM1 has the right to access the peripheral circuit 135. In an alternative embodiment, when the distribution circuit 121 outputs the instruction S CM1 to the terminal circuit 131, the control circuit 133 determines whether the attribute information of the instruction S CM1 conforms to the attribute setting value AS 131 . When the attribute information of the instruction S CM1 conforms to the attribute setting value AS 131 , it indicates that the main control circuit 111 has the right to access the peripheral circuit 135. Therefore, the control circuit 133 enables the peripheral circuit 135, so that the peripheral circuit 135 executes the instruction S CM1 .

[0031] However, when the attribute information of the instruction S CM1 does not conform to the attribute setting value AS 131When it indicates that the main control circuit 111 has no right to access the peripheral circuit 135. Therefore, the control circuit 133 does not enable the peripheral circuit 135. At this time, the peripheral circuit 135 does not execute the instruction S CM1 . In an alternative embodiment, when the instruction S CM1 's attribute information does not conform to the attribute setting value AS 131 , it indicates that the instruction S CM1 is not a legal instruction and may be an instruction issued by a malware attempting to tamper with the data of the peripheral circuit 135. Therefore, the control circuit 133 may issue an interrupt signal to notify other components of the system-on-chip 100 that an illegal access is currently occurring. In some embodiments, the control circuit 133 may execute relevant system security settings, such as generating an error response and providing it to the main control circuit 111 through the distribution circuit 121. Exemplarily, if the instruction S CM1 is a read instruction, the control circuit 133 may return a specific data (multiple 0s, multiple 1s, or scrambled data) to the main control circuit 111. If the instruction S CM1 is a write instruction, the control circuit 133 may ignore the write data provided by the main control circuit 111.

[0032] The present invention does not limit the architecture of the control circuit 133. In an alternative embodiment, the control circuit 133 includes a resource domain access controller. In this example, the resource domain access controller has decoding and comparison functions. Exemplarily, the resource domain access controller decodes the instruction S CM1 to obtain the attribute information of the instruction S CM1 . Then, the resource domain access controller determines whether the attribute information of the instruction S CM1 conforms to the attribute setting value AS 131 and decides whether to access the peripheral circuit 135 according to the judgment result.

[0033] The present invention does not limit the architecture of the peripheral circuit 135. Any circuit that can execute instructions can be used as the peripheral circuit 135. Exemplarily, assume that the peripheral circuit 135 is an encryption / decryption circuit. In this example, the peripheral circuit 135 performs an encryption / decryption operation according to the instruction S CM1 . In other embodiments, when the peripheral circuit 135 is a communication circuit, the peripheral circuit 135 performs a communication operation according to the instruction S CM1 , such as outputting the instruction S CM1 to components outside the system-on-chip 100 or receiving signals or instructions from components outside the system-on-chip 100.

[0034] The terminal circuit 132 records another attribute setting AS132 。In an alternative embodiment, the terminal circuit 132 includes a control circuit 134 and a peripheral circuit 136. The control circuit 134 is configured to determine whether the main control circuit 111 has the right to access the peripheral circuit 136. When the main control circuit 111 has the right to access the peripheral circuit 136, the control circuit 134 enables the peripheral circuit 136. Accordingly, the peripheral circuit 136 operates according to the instruction S CM1 However, when the main control circuit 111 does not have the right to access the peripheral circuit 136, the control circuit 134 does not enable the peripheral circuit 136. At this time, the peripheral circuit 136 does not operate according to the instruction S CM1 Since the characteristics of the control circuit 134 and the peripheral circuit 136 are similar to those of the control circuit 133 and the peripheral circuit 135, they will not be described in detail herein.

[0035] In this embodiment, each peripheral circuit operates according to the judgment result of the corresponding control circuit. Exemplarily, when the control circuit 133 determines that the attribute information of the instruction S CM1 matches the attribute setting value AS 131 it indicates that the main control circuit 111 has the right to access the peripheral circuit 135. Accordingly, the control circuit 133 enables the peripheral circuit 135. At this time, only the peripheral circuit 135 operates according to the instruction S CM1 However, if the control circuit 134 determines that the attribute information of the instruction S CM1 matches the attribute setting value AS 132 it indicates that the main control circuit 111 also has the right to access the peripheral circuit 136. In this example, the control circuit 134 enables the peripheral circuit 136.

[0036] Figure 2 FIG. 22 is another schematic diagram of the system-on-chip of the present invention. As shown in the figure, the system-on-chip 200 includes a main control layer 210, a device layer 220, and a peripheral layer 230. In this embodiment, the main control layer 210 includes a main control circuit 211 and a main control circuit 212. The main control circuit 211 and the main control circuit 212 respectively generate instructions S CM1 and S CM2。The present invention does not limit the architectures of the main control circuits 211 and 212. In some embodiments, the main control circuit 211 and the main control circuit 212 have the same nature. Exemplarily, both the main control circuit 211 and the main control circuit 212 are security devices, non-secure devices, privilege devices, or non-privilege devices. In other embodiments, the main control circuit 211 and the main control circuit 212 have different natures. Exemplarily, the main control circuit 211 is one of a security device, a non-secure device, a privilege device, and a non-privilege device. In this example, the main control circuit 212 is another one of a security device, a non-secure device, a privilege device, and a non-privilege device. In an alternative embodiment, the main control circuit 211 is a security device, and the main control circuit 212 is a privilege device. In another alternative embodiment, the main control circuit 211 is a security device, and the main control circuit 212 is a non-privilege device. In some embodiments, the main control circuit 211 is a non-secure device, and the main control circuit 212 is a privilege device, or the main control circuit 211 is a non-secure device, and the main control circuit 212 is a non-privilege device. Since the operations of the main control circuits 211 and 212 are similar to those of the main control circuit 111 of Figure 1 they will not be elaborated herein. Additionally, the present invention does not limit the number of main control circuits. In some embodiments, the main control layer 210 has more or fewer main control circuits.

[0037] In this embodiment, the device layer 220 includes a routing circuit 221, and distribution circuits 222 and 223. The routing circuit 221 generates at least one of output instructions SO CM1 and SO CM2 according to the address information of external instructions (such as S CM1 and SO CM2 ). Exemplarily, when the routing circuit 221 receives the instruction S CM1 , if the address information of the instruction S CM1 points to the terminal circuit 231 or the terminal circuit 232, the routing circuit 221 takes the instruction S CM1 as the output instruction SO CM1 and provides it to the distribution circuit 222. However, if the address information of the instruction S CM1 points to any one of the terminal circuits 233 to 235, the routing circuit 221 takes the instruction S CM1 as the output instruction SO CM2 and provides it to the distribution circuit 223.

[0038] Similarly, when the routing circuit 221 receives the instruction S CM2When the instruction S CM2 has an address information that points to the terminal circuit 231 or 232, the routing circuit 221 uses the instruction S CM2 as the output instruction SO CM1 and provides it to the distribution circuit 222. However, if the instruction S CM2 has an address information that points to any one of the terminal circuits 233 to 235, the routing circuit 221 uses the instruction S CM2 as the output instruction SO CM2 and provides it to the distribution circuit 223.

[0039] In other embodiments, when the address information of the instructions S CM1 and S CM2 points to the same terminal circuit, the routing circuit 221 generates the output instruction SO CM1 or SO CM2 according to a priority order. Exemplarily, assume that the priority of the main control circuit 211 is higher than that of the main control circuit 212. In this example, when the routing circuit 221 receives the instructions S CM1 and S CM2 at the same time, if the address information of the instructions S CM1 and S CM2 both point to the terminal circuit 231, the routing circuit 221 first uses the instruction S CM1 as the output instruction SO CM1 and provides it to the distribution circuit 222, and then uses the instruction S CM2 as the output instruction SO CM1 and provides it to the distribution circuit 222. In an alternative embodiment, the priority order is pre-stored in the routing circuit 221.

[0040] The present invention does not limit the architecture of the routing circuit 221. In an alternative embodiment, the routing circuit 221 has a bus matrix architecture. In another alternative embodiment, the routing circuit 221 includes a router.

[0041] The distribution circuit 222 and the distribution circuit 223 transmit the external instructions to the corresponding terminal circuits according to the address information of the external instructions (such as SO CM1 and SO CM2 ). Since the operations of the distribution circuit 222 and the distribution circuit 223 are the same as Figure 1The operation of the distribution circuit 121 is similar, so it will not be elaborated here. In this embodiment, the distribution circuit 222 is connected to the terminal circuits 231 and 232, and the distribution circuit 223 is connected to the terminal circuits 233 - 235, but this is not intended to limit the present invention. In other embodiments, both the distribution circuit 222 and the distribution circuit 223 are coupled to the same number of terminal circuits. In addition, the present invention does not limit the number of distribution circuits. In other embodiments, the device layer 220 has more distribution circuits for dispatching instructions to more terminal circuits.

[0042] The peripheral layer 230 includes terminal circuits 231 - 235, but this is not intended to limit the present invention. In other embodiments, the peripheral layer 230 has other numbers of terminal circuits. The present invention does not limit the architectures of the terminal circuits 231 - 235. In an alternative embodiment, one of the terminal circuits 231 - 235 has the same nature as another one of the terminal circuits 231 - 235. Exemplarily, the terminal circuits 231 and 233 are both communication circuits. Since the characteristics of the terminal circuits 231 - 235 are similar to Figure 1 those of the terminal circuit 131, they will not be elaborated here.

[0043] In this embodiment, the terminal circuits 231 - 235 respectively record the attribute setting values AS 231 ~AS 235 . Each terminal circuit determines whether to execute an external instruction according to the attribute information of an external instruction (such as SO CM1 or SO CM2 ). Taking the terminal circuit 233 as an example, when the attribute information of the output instruction SO CM2 is the same as the attribute setting value AS 233 , the terminal circuit 233 executes the output instruction SO CM2 . However, when the attribute information of the output instruction SO CM2 is different from the attribute setting value AS 233 , the terminal circuit 233 may perform relevant security operations, such as ignoring the output instruction SO CM2 , or sending an interrupt signal to inform other components of the system single chip 200 that an illegal access has occurred.

[0044] In an alternative embodiment, the terminal circuits 231 - 235 each have a register for storing the attribute setting values AS 231 ~AS 235 . In this example, when the attribute setting values AS 231 ~AS 235 have the same data length, the complexity of hardware or software development can be reduced. Furthermore, since the attribute setting values AS 231 ~AS 235They are recorded dispersedly (distribute) in different terminal circuits, so the architecture of the system-on-chip 200 can be simplified and the debugging time can be reduced.

[0045] Figure 3 This is another schematic diagram of the system-on-chip of the present invention. Figure 3 Similar Figure 2 , the difference is that Figure 3 The main control layer 310 of also includes a main control circuit 313. The main control circuit 313 is used to generate an instruction S CM3 . Since the characteristics of the main control circuits 311-313 are the same as those of Figure 1 the main control circuit 111 of and Figure 2 the main control circuits 211 and 212 of are all similar, they will not be elaborated here. In an alternative embodiment, the main control circuits 311 and 312 are both safety devices, while the main control circuit 313 is a non-safety device. In other embodiments, the main control circuit 313 is a direct memory access (DMA) controller.

[0046] In this embodiment, the device layer 320 includes a routing circuit 321, a distribution circuit 322, a distribution circuit 323, and high-order control circuits 324 and 325. Since the characteristics of the routing circuit 321, the distribution circuits 322 and 323 are the same as those of Figure 2 the routing circuit 221, the distribution circuits 222 and 223 of are similar, they will not be elaborated here.

[0047] The high-order control circuit 324 records a device attribute setting value AS 324 . The high-order control circuit 325 records a device attribute setting value AS 325 . In an alternative embodiment, the high-order control circuits 324 and 325 are high-order devices. In this embodiment, the high-order control circuits 324 and 325 are directly connected to the routing circuit 321. Therefore, the routing circuit 321 directly provides output instructions SO CM3 and SO CM4 to the high-order control circuits 324 and 325. In this example, the high-order control circuits 324 and 325 are also terminal circuits, but the operating frequencies of the high-order control circuits 324 and 325 are higher than those of the terminal circuits 331-335. Exemplarily, the operating frequencies of the high-order control circuits 324 and 325 may be higher than 100 MHz, or higher than 1 GHz.

[0048] Since the operations of the high-order control circuit 324 and the high-order control circuit 325 are similar, the operation of the high-order control circuit 324 will be described below. When the routing circuit 321 provides an output instruction SO CM3 the high-order control circuit 324 determines whether the attribute information of the output instruction SO CM3 matches the device attribute setting value AS 324 . When the attribute information of the output instruction SO CM3 matches the device attribute setting value AS 324 the high-order control circuit 324 executes the output instruction SO CM3 . The present invention does not limit the type of the output instruction SO CM3 . When the output instruction SO CM3 is a write instruction, the high-order control circuit 324 performs a write operation. When the output instruction SO CM3 is a read instruction, the high-order control circuit 324 performs a read operation.

[0049] However, when the attribute information of the output instruction SO CM3 does not match the device attribute setting value AS 324 it indicates that the output instruction SO CM3 is an illegal instruction. Therefore, the high-order control circuit 324 does not execute the output instruction SO CM3 . In another alternative embodiment, the high-order control circuit 324 issues an interrupt signal for notifying another component (not shown) of the system single chip 300. The present invention does not limit the number of high-order control circuits. In other embodiments, the device layer 320 has more or fewer high-order control circuits. In this example, each high-order control circuit stores a device attribute setting value.

[0050] The present invention does not limit the architecture of the high-order control circuit 324. In an alternative embodiment, the high-order control circuit 324 has a resource domain access controller (not shown) and a device circuit (not shown). The resource domain access controller is used to decode the output instruction SO CM3 and determine whether the attribute information of the output instruction SO CM3 matches the device attribute setting value AS 324 . When the attribute information of the output instruction SO CM3 matches the device attribute setting value AS 324 the device circuit executes the operation corresponding to the output instruction SO CM3The operation. In an alternative embodiment, the high-order control circuit 324 is an encryption / decryption circuit for performing encryption / decryption operations. In other embodiments, the device circuit of the high-order control circuit 324 is a gigabit Ethernet or a LAN slave device.

[0051] In other embodiments, the architecture of the high-order control circuit 324 may be the same as or different from that of the high-order control circuit 325. Exemplarily, the high-order control circuit 324 may be an encryption / decryption circuit, while the high-order control circuit 325 is a bus bridge. Additionally, the peripheral layer 330 has terminal circuits 331-335. Since the characteristics of the terminal circuits 331-335 are similar to those of Figure 1 the terminal circuit 131, they will not be elaborated here.

[0052] Figure 4 FIG. is a schematic flow chart of the control method of the present invention. The control method of the present invention is applicable to a system-on-chip. The system-on-chip has a plurality of terminal circuits. First, store a plurality of attribute setting values in the terminal circuits (step S411). The present invention does not limit the types of terminal circuits. In an alternative embodiment, at least one of the terminal circuits is located in the device layer, and another one of the terminal circuits is located in the peripheral layer. In this embodiment, each terminal circuit records a single attribute setting value.

[0053] Decode an output instruction for dispatching the terminal circuit corresponding to the output instruction (step S412). In an alternative embodiment, the output instruction is provided by a routing circuit. In this example, the routing circuit generates the output instruction according to the address information of an input instruction. In this example, the input instruction is provided by a main control device.

[0054] Taking Figure 2 the system-on-chip 200 as an example, when the instruction S CM1 issued by the main control device 211 points to the terminal circuit 231, the routing circuit 221 uses the instruction S CM1 as the output instruction SO CM1 and provides it to the distribution circuit 222. At this time, the distribution circuit 222 decodes the output instruction SO CM1 to know that the instruction S CM1 points to the terminal circuit 231. Therefore, the distribution circuit 222 dispatches the output instruction SO CM1 to the terminal circuit 231.

[0055] Next, it is determined whether the attribute information of the output instruction matches the attribute setting value of the corresponding terminal circuit (step S413). When the attribute information of the output instruction matches the attribute setting value of the corresponding terminal circuit, the terminal circuit executes the output instruction (step S414). However, when the attribute information of the output instruction does not match the attribute setting value of the corresponding terminal circuit, the terminal circuit does not execute the output instruction (step S415). In an alternative embodiment, when the attribute information of the output instruction does not match the attribute setting value of the corresponding terminal circuit, the terminal circuit performs a security operation.

[0056] Take Figure 2 as an example. Suppose the routing circuit 221 takes the instruction S CM1 as the output instruction SO CM1 . In this example, when the terminal circuit 231 receives the output instruction SO CM1 , the terminal circuit 231 determines whether the attribute information of the output instruction SO CM1 matches the attribute setting value AS 231 . When the attribute information of the output instruction SO CM1 matches the attribute setting value AS 231 , it indicates that the main control circuit 211 has the right to access the terminal circuit 231. Therefore, the terminal circuit 231 executes the output instruction SO CM1 . Similarly, when the distribution circuit 222 dispatches the output instruction SO CM1 to the terminal circuit 232, the terminal circuit 232 determines whether the attribute information of the output instruction SO CM1 matches the attribute setting value AS 232 . When the attribute information of the output instruction SO CM1 matches the attribute setting value AS 232 , the terminal circuit 232 executes the output instruction SO CM1 .

[0057] However, when the attribute information of the output instruction SO CM1 does not match the attribute setting value AS 231 , it indicates that the main control circuit 211 has no right to access the terminal circuit 231. Therefore, the terminal circuit 231 does not execute the output instruction SO CM1 . In an alternative embodiment, the terminal circuit 231 issues an interrupt or generates an error report. In other embodiments, if the output instruction SO CM1 is a read instruction, the terminal circuit 231 may return a specific data (such as all 0s, 1s, or scrambled data) to the main control circuit 211. If the output instruction SO CM1 is a write instruction, the terminal circuit 231 ignores the write data provided by the main control circuit 211.

[0058] In other embodiments, step S411 stores the attribute setting value (or device attribute setting value) in a high-level control circuit. In this example, the high-level control circuit is located at the device layer, and the operating frequency of the high-level control circuit is higher than that of the above-mentioned terminal circuits (such as 231-235). Exemplarily, the operating frequency of the high-level control circuit may be greater than 100 MHz, while the operating frequency of the terminal circuit is less than 100 MHz.

[0059] When the high-level control circuit receives an output instruction, the high-level control circuit determines whether the attribute information of the output instruction conforms to the device attribute setting value stored in itself. When the attribute information of the output instruction conforms to the device attribute setting value, the high-level control circuit executes the output instruction. However, when the attribute information of the output instruction does not conform to the device attribute setting value, the high-level control circuit does not execute the output instruction. In an alternative embodiment, when the attribute information of the output instruction does not conform to the device attribute setting value, the high-level control circuit performs a security operation.

[0060] Since the attribute setting values are stored dispersedly in each terminal circuit (including the high-level control circuit), the circuit complexity can be simplified and reduced, and the debugging time of the tester can be reduced. Furthermore, only when the attribute information of the external instruction conforms to the attribute setting value stored in the corresponding terminal circuit, the corresponding terminal circuit will operate, so illegal access to the terminal circuit can be avoided, thus improving the security of the system single chip.

[0061] The control method of the present invention, or a specific type or part thereof, may exist in the form of source code. The source code can be stored in a physical medium, such as a floppy disk, optical disc, hard disk, or any other machine-readable (such as computer-readable) storage medium, or a computer program product not limited to an external form. Among them, when the source code is loaded and executed by a machine, such as a computer, this machine can be the system single chip for the present invention. The source code can also be transmitted through some transmission media, such as wires or cables, optical fibers, or any transmission type. Among them, when the source code is received, loaded, and executed by a machine, such as a computer, this machine can be the system single chip for the present invention. When running on a general-purpose processing unit, the source code combined with the processing unit provides a unique device whose operation is similar to that of an application-specific logic circuit.

[0062] Unless otherwise defined, all terms (including technical and scientific terms) contained in the present invention are understood by those of ordinary skill in the technical field to which the present invention belongs. In addition, unless explicitly stated, the definitions of terms recorded in a general dictionary should be interpreted as being consistent with their meanings in the articles of the relevant technical field, and should not be interpreted as an ideal state or an overly formal voice.

[0063] Although the above preferred embodiments of the present invention have been disclosed, these embodiments are not intended to limit the present invention. Any person of ordinary skill in the art can make some changes and improvements without departing from the spirit and scope of the present invention. For example, the systems, devices or methods described in the embodiments of the present invention can be implemented by physical embodiments of hardware, software or a combination of hardware and software. Therefore, the protection scope of the present invention shall be subject to the scope recorded in the claims.

Claims

1. A system-on-chip, characterized in that, Including: A first terminal circuit for recording a first attribute setting value; A second terminal circuit for recording a second attribute setting value; A first distribution circuit for dispatching the first output instruction to the first terminal circuit or the second terminal circuit according to the address information of a first output instruction; A high-order control circuit for recording a device attribute setting value; A first main control circuit for generating a first instruction; A routing circuit for providing the first instruction as the first output instruction to the first distribution circuit according to the address information of the first instruction; A third terminal circuit for recording a third attribute setting value; A fourth terminal circuit for recording a fourth attribute setting value; A second distribution circuit for dispatching the second output instruction to the third terminal circuit or the fourth terminal circuit according to the address information of a second output instruction, wherein, when the first distribution circuit dispatches the first output instruction to the first terminal circuit, the first terminal circuit determines whether the attribute information of the first output instruction conforms to the first attribute setting value, and when the attribute information of the first output instruction conforms to the first attribute setting value, the first terminal circuit executes the first output instruction, wherein, when the first distribution circuit dispatches the first output instruction to the second terminal circuit, the second terminal circuit determines whether the attribute information of the first output instruction conforms to the second attribute setting value, and when the attribute information of the first output instruction conforms to the second attribute setting value, the second terminal circuit executes the first output instruction, wherein, when the second distribution circuit dispatches the second output instruction to the third terminal circuit, the third terminal circuit determines whether the attribute information of the second output instruction conforms to the third attribute setting value, and when the attribute information of the second output instruction conforms to the third attribute setting value, the third terminal circuit executes the second output instruction, wherein, when the second distribution circuit dispatches the second output instruction to the fourth terminal circuit, the fourth terminal circuit determines whether the attribute information of the second output instruction conforms to the fourth attribute setting value, and when the attribute information of the second output instruction conforms to the fourth attribute setting value, the fourth terminal circuit executes the second output instruction, wherein, the high-order control circuit determines whether the attribute information of a third output instruction conforms to the device attribute setting value, and when the attribute information of the third output instruction conforms to the device attribute setting value, the high-order control circuit executes the third output instruction, and the routing circuit provides the first instruction as the third output instruction to the high-order control circuit according to the address information of the first instruction, wherein, the high-order control circuit is directly coupled to the routing circuit, and the operating frequency of the high-order control circuit is greater than the operating frequencies of the first terminal circuit and the second terminal circuit.

2. The system single chip according to claim 1, wherein Including: A second main control circuit for generating a second instruction, The routing circuit provides the second instruction as the second output instruction to the second distribution circuit according to the address information of the second instruction, and the routing circuit has a bus matrix architecture.

3. The system single chip according to claim 1, wherein, Including: A direct memory access controller for generating a third instruction, wherein the routing circuit provides the third instruction as the third output instruction to the high-order control circuit according to the address information of the third instruction.

4. The system single chip according to claim 1, wherein The first distribution circuit is a peripheral bridge. When the first distribution circuit dispatches the first output instruction to the first terminal circuit and the attribute information of the first output instruction does not conform to the first attribute setting value, the first terminal circuit ignores the first output instruction.

5. The system single chip according to claim 1, wherein When the first distribution circuit dispatches the first output instruction to the first terminal circuit and the attribute information of the first output instruction does not conform to the first attribute setting value, the first terminal circuit issues an interrupt signal.

6. A control method, applicable to a system-on-chip, characterized in that, The system-on-chip has a first terminal circuit, a second terminal circuit, a first distribution circuit, a third terminal circuit, a fourth terminal circuit, a second distribution circuit, a main control circuit, and a high-order control circuit. The main control circuit generates a first instruction. The control method includes: Storing a first attribute setting value in the first terminal circuit; Storing a second attribute setting value in the second terminal circuit; Storing a third attribute setting value in the third terminal circuit; Storing a fourth attribute setting value in the fourth terminal circuit; Storing a device attribute setting value in the high-order control circuit; Decoding a first output instruction for dispatching the first output instruction to the first terminal circuit or the second terminal circuit; Decoding a second output instruction for dispatching the second output instruction to the third terminal circuit or the fourth terminal circuit; Providing a third output instruction to the high-order control circuit, wherein when the first output instruction is dispatched to the first terminal circuit, the first terminal circuit determines whether the attribute information of the first output instruction conforms to the first attribute setting value. When the attribute information of the first output instruction conforms to the first attribute setting value, the first terminal circuit executes the first output instruction. wherein when the first distribution circuit dispatches the first output instruction to the second terminal circuit, the second terminal circuit determines whether the attribute information of the first output instruction conforms to the second attribute setting value. When the attribute information of the first output instruction conforms to the second attribute setting value, the second terminal circuit executes the first output instruction. wherein when the second output instruction is dispatched to the third terminal circuit, the third terminal circuit determines whether the attribute information of the second output instruction conforms to the third attribute setting value. When the attribute information of the second output instruction conforms to the third attribute setting value, the third terminal circuit executes the second output instruction. Wherein, when the second distribution circuit distributes the second output instruction to the fourth terminal circuit, the fourth terminal circuit determines whether the attribute information of the second output instruction conforms to the fourth attribute setting value. When the attribute information of the second output instruction conforms to the fourth attribute setting value, the fourth terminal circuit executes the second output instruction. Wherein, the high-order control circuit determines whether the attribute information of the third output instruction conforms to the device attribute setting value. When the attribute information of the third output instruction conforms to the device attribute setting value, the high-order control circuit executes the third output instruction. The routing circuit provides the first instruction as the third output instruction to the high-order control circuit according to the address information of the first instruction. Wherein, the high-order control circuit is directly coupled to the routing circuit, and the operating frequency of the high-order control circuit is greater than the operating frequencies of the first terminal circuit and the second terminal circuit.

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