A method, apparatus, device, and medium for determining the maximum power consumption of a chip

Abstract

The present invention relates to the field of integrated circuit technology, and particularly to a method, apparatus, device and medium for determining the maximum power consumption of a chip. The method includes: building a formal verification environment with a formal verification tool; compiling the RTL-level design code of a target chip in the formal verification environment to generate a gate-level model; combining each logic gate in the gate-level model to generate a number of logic gate combinations; generating assertions corresponding to each logic gate combination through the formal verification tool, and screening out the logic gate combination with the most simultaneously flipped logic gates from all the logic gate combinations as the target logic gate combination based on the assertions, where the assertions are used to prove whether all the logic gates in the logic gate combination can be flipped simultaneously; generating a waveform for the target logic gate combination through the formal verification tool, and determining the maximum power consumption of the target chip based on the waveform of the target logic gate combination. The solution of the present invention greatly improves the generation efficiency of waveform files and saves a large amount of manpower and material resources.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular, to a method, apparatus, device, and medium for determining the maximum power consumption of a chip. Background Art

[0002] The success of a System on Chip (SoC) chip design is measured by many criteria. Currently, the most common method in the industry is to look at the three parameters of power consumption, performance, and area of the chip. Therefore, the goal pursued in chip design is how to achieve lower power consumption and higher performance with as small an area as possible. However, under market pressure, the chip design team does not have sufficient time to achieve this, so the chip design goal has changed to a balance of area, power consumption, and performance. Therefore, in chip design, it is necessary to measure the power consumption of the chip before tape-out to ensure that the power consumption of the final taped-out chip meets the design requirements. The power consumption of an SoC chip can be divided into static power consumption and dynamic power consumption. The static power consumption mainly comes from the leakage current of transistors, which is determined by the process and is usually not within the scope of consideration in chip design. Therefore, it is mainly to determine the dynamic power consumption of the SoC chip. The dynamic power consumption of the chip mainly comes from the switching power consumption of charging and discharging the load capacitance when the logic gates switch and the short-circuit power consumption caused by the short-circuit current when the circuit is short-circuited. Therefore, the measurement of the chip's dynamic power consumption can be achieved by checking the switching of the logic gates. That is, if more logic gates switch simultaneously within a certain period of time, then the dynamic power consumption is greater.

[0003] Please refer to Figure 1 as shown Figure 1 which shows the flowchart of the traditional measurement of dynamic power consumption. Specifically, after the chip completes the backend implementation, the verification engineer provides a simulation waveform representing the chip's activities. Using a backend tool such as PTPX (PrimeTime Power Extension, a power consumption simulation tool), the waveform file is read to count the switching rate of the logic gates. Through the switching rate data, the dynamic power consumption of the chip during this period can be calculated. However, in order to make the measurement result of the maximum power consumption more accurate, the waveform provided by the verification engineer needs to enable as many gates as possible to switch simultaneously. The most difficult part is that the verification engineer often can only be based on the functional definition test cases and cannot be accurate to the logic gate level. Therefore, in order to achieve the goal of triggering the switching of as many logic gates as possible, the verification engineer needs to provide a large number of simulation waveforms and continuously repeat the measurement of the dynamic power consumption value to find the possible maximum power consumption of the chip, which not only requires a large amount of manpower but also has low efficiency. Therefore, it is urgent to improve the current mainstream measurement of dynamic power consumption in the industry. Summary of the Invention

[0004] In view of this, it is necessary to provide a method, apparatus, device, and medium for determining the maximum power consumption of a chip for the above technical problems.

[0005] According to a first aspect of the present invention, there is provided a method for determining the maximum power consumption of a chip, the method comprising:

[0006] Construct a formal verification environment with a formal verification tool;

[0007] Compile the RTL-level design code of the target chip in the formal verification environment to generate a gate-level model;

[0008] Combine each logic gate in the gate-level model to generate a number of logic gate combinations;

[0009] Generate assertions corresponding to each logic gate combination through the formal verification tool, and screen out the logic gate combination with the most simultaneously flipped logic gates from all logic gate combinations as the target logic gate combination based on the assertions, wherein the assertions are used to prove whether all the logic gates in the logic gate combination can be flipped simultaneously;

[0010] Generate a waveform for the target logic gate combination through the formal verification tool, and determine the maximum power consumption of the target chip based on the waveform of the target logic gate combination.

[0011] In some embodiments, the step of constructing a formal verification environment with a formal verification tool includes:

[0012] Generate a formal verification environment supporting property based on a predefined design file, clock signal, reset signal and polarity.

[0013] In some embodiments, the step of combining each logic gate in the gate-level model to generate a number of logic gate combinations includes:

[0014] Export all the logic gates in the gate-level model through the formal verification tool to generate a logic gate list;

[0015] Read the logic gates in the logic gate list and remove duplicate logic gates;

[0016] Combine all the logic gates with duplicates removed in every possible combination manner by gate to generate a number of logic gate combinations.

[0017] In some embodiments, the step of generating assertions corresponding to each logic gate combination through the formal verification tool, and screening out the logic gate combination with the most simultaneously flipped logic gates from all logic gate combinations as the target logic gate combination includes:

[0018] Count the number of logic gates included in each logic gate combination;

[0019] Each time, without replacement, select the combination of logic gates with the largest number of current logic gates from all combinations of logic gates;

[0020] Use the formal verification tool to generate an assertion for the combination of logic gates with the largest number of current logic gates selected;

[0021] In response to the assertion proving that all logic gates in the combination of logic gates with the largest number of current logic gates cannot flip simultaneously, return to execute the step of each time, without replacement, selecting the combination of logic gates with the largest number of current logic gates from all combinations of logic gates;

[0022] In response to the assertion proving that all logic gates in the combination of logic gates with the largest number of current logic gates can flip simultaneously, use the combination of logic gates with the largest number of current logic gates selected as the target logic gate combination.

[0023] In some embodiments, before executing the step of using the combination of logic gates with the largest number of current logic gates selected as the target logic gate combination, the method further includes:

[0024] Perform a legality verification on the combination of logic gates with the largest number of current logic gates selected to determine whether the combination of logic gates with the largest number of current logic gates selected is legal;

[0025] In response to the combination of logic gates with the largest number of current logic gates selected being illegal, return to execute the step of each time, without replacement, selecting the combination of logic gates with the largest number of current logic gates from all combinations of logic gates;

[0026] In response to the combination of logic gates with the largest number of current logic gates selected being legal, execute the step of using the combination of logic gates with the largest number of current logic gates selected as the target logic gate combination.

[0027] In some embodiments, the step of performing a legality verification on the combination of logic gates with the largest number of current logic gates selected to determine whether the combination of logic gates with the largest number of current logic gates selected is legal includes:

[0028] Compare each logic gate in the combination of logic gates with the largest number of current logic gates selected with a preset list of illegal logic gate combinations, where the preset list of illegal logic gate combinations includes several combinations of illegal logic gates;

[0029] In response to there being at least one identical logic gate combination between the combination of logic gates with the largest number of current logic gates selected and the preset list of illegal logic gate combinations, determine that the combination of logic gates with the largest number of current logic gates selected is illegal;

[0030] Otherwise, determine that the logic gate combination with the largest number of currently selected logic gates is legal.

[0031] In some embodiments, the step of generating a waveform for the target logic gate combination by the formal verification tool and determining the maximum power consumption of the target chip based on the waveform of the target logic gate combination includes:

[0032] In response to there being multiple groups of the target logic gate combinations, use the formal verification tool to generate waveforms for each group of target logic gate combinations respectively;

[0033] Determine the power consumption value of each group of target logic gate combinations based on the waveforms, and use the maximum power consumption value as the maximum power consumption of the target chip.

[0034] According to a second aspect of the present invention, there is provided a device for determining the maximum power consumption of a chip, the device including:

[0035] A building module, configured to build a formal verification environment with a formal verification tool;

[0036] A compilation module, configured to compile the RTL-level design code of the target chip in the formal verification environment to generate a gate-level model;

[0037] A combination module, configured to combine each logic gate in the gate-level model to generate several logic gate combinations;

[0038] A screening module, configured to generate assertions corresponding to each logic gate combination through the formal verification tool, and screen out the logic gate combination with the largest number of simultaneously flipped logic gates as the target logic gate combination from all the logic gate combinations, wherein the assertion is used to prove whether all the logic gates in the logic gate combination can be flipped simultaneously;

[0039] A determination module, configured to generate a waveform for the target logic gate combination through the formal verification tool, and determine the maximum power consumption of the target chip based on the waveform of the target logic gate combination.

[0040] According to a third aspect of the present invention, there is also provided a computer device, which includes:

[0041] At least one processor; and

[0042] A memory, the memory stores a computer program that can run on the processor, and when the processor executes the program, it executes the aforementioned method for determining the maximum power consumption of the chip.

[0043] According to a fourth aspect of the present invention, there is also provided a computer-readable storage medium, the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, it executes the aforementioned method for determining the maximum power consumption of the chip.

[0044] In the above method for determining the maximum power consumption of a chip, by utilizing the exhaustive feature of the formal verification tool, the maximum number of flip-flops in theory can be found. Formal verification is used to generate waveform stimuli, replacing the extremely time-consuming gate-level simulation, greatly improving the generation efficiency of waveform files. It is not necessary to wait until the backend design is completed. Chip design engineers can obtain feedback in a timely manner and have sufficient time to modify the design code, saving a great deal of manpower and material resources for chip design.

[0045] In addition, the present invention also provides a device for determining the maximum power consumption of a chip, a computer device, and a computer-readable storage medium, which can also achieve the above technical effects and will not be elaborated here. Description of the Drawings

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following-described drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other embodiments can also be obtained based on these drawings.

[0047] Figure 1 It is a flowchart of the traditional method for measuring dynamic power consumption;

[0048] Figure 2 It is a flowchart of a method for determining the maximum power consumption of a chip provided by an embodiment of the present invention;

[0049] Figure 3 It is a flowchart of another method for determining the maximum power consumption of a chip provided by another embodiment of the present invention;

[0050] Figure 4 It is a schematic structural diagram of a device for determining the maximum power consumption of a chip provided by another embodiment of the present invention;

[0051] Figure 5 It is the internal structure diagram of a computer device in another embodiment of the present invention. Detailed Embodiments

[0052] To make the objectives, technical solutions, and advantages of the present invention more clearly understood, the following further elaborates on the embodiments of the present invention in detail with reference to specific embodiments and the accompanying drawings.

[0053] It should be noted that all the expressions using "first" and "second" in the embodiments of the present invention are used to distinguish two entities or parameters with the same name but different identities. It can be seen that "first" and "second" are only for the convenience of expression and should not be construed as limitations on the embodiments of the present invention. This will not be further explained in the subsequent embodiments.

[0054] In one embodiment, please refer to Figure 2 As shown, the present invention provides a method for determining the maximum power consumption of a chip. Specifically, the method includes the following steps:

[0055] Step 101, build a formal verification environment with a formal verification tool;

[0056] Step 102, compile the RTL-level design code of the target chip in the formal verification environment to generate a gate-level model;

[0057] Step 103, combine each logic gate in the gate-level model to generate several logic gate combinations;

[0058] Step 104, generate assertions corresponding to each logic gate combination through the formal verification tool, and filter out the logic gate combination with the most simultaneously flipped logic gates from all logic gate combinations as the target logic gate combination based on the assertions, where the assertions are used to prove whether all the logic gates in the logic gate combination can be flipped simultaneously;

[0059] Step 105, generate a waveform for the target logic gate combination through the formal verification tool, and determine the maximum power consumption of the target chip based on the waveform of the target logic gate combination.

[0060] For the above method for determining the maximum power consumption of a chip, by utilizing the exhaustive feature of the formal verification tool, the theoretically maximum number of flipped gates can be found. Using formal verification to generate waveform stimuli replaces the extremely time-consuming gate-level simulation, greatly improving the generation efficiency of waveform files. It does not need to wait until the backend design is completed. Chip design engineers can obtain feedback in a timely manner and have sufficient time to change the design code, saving a large amount of manpower and material resources for chip design.

[0061] In some embodiments, the foregoing step 101 of building a formal verification environment with a formal verification tool specifically includes:

[0062] Generate a formal verification environment that supports properties based on predefined design files, clock signals, reset signals, and polarities.

[0063] In some embodiments, the foregoing step 103 of combining each logic gate in the gate-level model to generate several logic gate combinations specifically includes:

[0064] Export all the logic gates in the gate-level model through the formal verification tool to generate a logic gate list;

[0065] Read the logic gates in the logic gate list and eliminate duplicate logic gates;

[0066] For each combination method of traversing every possibility with the gates, combine all the logic gates from which duplicates have been removed to generate several combinations of logic gates.

[0067] In some embodiments, in the aforementioned step 104, generating an assertion corresponding to each combination of logic gates through the formal verification tool, and screening out the combination of logic gates with the most simultaneously flipped logic gates from all combinations of logic gates as the target combination of logic gates specifically includes:

[0068] Count the number of logic gates included in each combination of logic gates;

[0069] Each time, select without replacement from all combinations of logic gates the combination of logic gates with the largest number of current logic gates;

[0070] Use the formal verification tool to generate an assertion for the combination of logic gates with the largest number of current logic gates selected;

[0071] In response to the assertion proving that all the logic gates in the combination of logic gates with the largest number of current logic gates cannot be flipped simultaneously, return to execute the step of selecting without replacement from all combinations of logic gates the combination of logic gates with the largest number of current logic gates;

[0072] In response to the assertion proving that all the logic gates in the combination of logic gates with the largest number of current logic gates can be flipped simultaneously, use the combination of logic gates with the largest number of current logic gates selected as the target combination of logic gates.

[0073] In some embodiments, before executing the step of using the combination of logic gates with the largest number of current logic gates selected as the target combination of logic gates, the method further includes:

[0074] Perform a legality verification on the combination of logic gates with the largest number of current logic gates selected to determine whether the combination of logic gates with the largest number of current logic gates selected is legal;

[0075] In response to the combination of logic gates with the largest number of current logic gates selected being illegal, return to execute the step of selecting without replacement from all combinations of logic gates the combination of logic gates with the largest number of current logic gates;

[0076] In response to the combination of logic gates with the largest number of current logic gates selected being legal, execute the step of using the combination of logic gates with the largest number of current logic gates selected as the target combination of logic gates.

[0077] In some embodiments, the step of performing a legality verification on the combination of logic gates with the largest number of current logic gates selected to determine whether the combination of logic gates with the largest number of current logic gates selected is legal specifically includes:

[0078] Compare each logic gate in the logic gate combination with the largest number of currently selected logic gates with a preset list of illegal logic gate combinations, where the preset list of illegal logic gate combinations includes several combinations of illegal logic gates;

[0079] In response to there being at least one identical logic gate combination between the logic gate combination with the largest number of currently selected logic gates and the preset list of illegal logic gate combinations, determine that the logic gate combination with the largest number of currently selected logic gates is illegal;

[0080] Otherwise, determine that the logic gate combination with the largest number of currently selected logic gates is legal.

[0081] In some embodiments, for the foregoing step 105, the specific steps of generating a waveform for the target logic gate combination by the formal verification tool and determining the maximum power consumption of the target chip based on the waveform of the target logic gate combination include:

[0082] In response to there being multiple groups of the target logic gate combination, use the formal verification tool to generate waveforms for each group of target logic gate combinations respectively;

[0083] Determine the power consumption value of each group of target logic gate combinations based on the waveform, and use the maximum power consumption value as the maximum power consumption of the target chip.

[0084] In another embodiment, for the convenience of understanding the solution of the present invention, the following takes VC formal of Synopsys as an example to determine the maximum power consumption of a certain SoC chip by using the method of the present invention as an application scenario. Please refer to Figure 3 The present embodiment provides another method for determining the maximum power consumption of a chip. The specific implementation manner is as follows:

[0085] Step 1. Building a property-based formal verification environment is the most basic working mode supported by all formal verification tools and does not require special support work. Users only need to specify the design file, define the clock and reset signals, and then they can generate a formal verification environment that supports properties. The partial code of the formal verification environment built in the specific implementation process is as follows:

[0086] set design top_tb

[0087] set vcs“

[0088] +lint=TFIPC-L\

[0089] ${DESIGN_DIR} / *.sv

[0090] ”

[0091] …

[0092] read_file – sva top$design – format sverilog – vcs “$vcs” # Compile the design code

[0093] create_clock clk – period 100 # Specify the clock and frequency

[0094] create_reset rstn – low # Specify the reset signal and polarity

[0095] …

[0096] Step 2: After being compiled and executed by the formal verification tool, the RTL-level design code is converted into a gate-level model. All the logic gates in the circuit can be easily exported through the formal verification tool. Commonly used digital circuit logic gates are divided into two categories: registers and combinational logic. For example, the list containing the path information of logic gates generated by Synopsys's VC formal is as follows:

[0097] Registers: 142

[0098] Dut.genblk2[0].inst_sync2_rstn.first_stage_sync_r

[0099] Dut.genblk2[0].inst_sync2_rstn.second_stage_sync_r

[0100] Dut.genblk2[1].inst_sync2_rstn.first_stage_sync_r

[0101] Dut.genblk2[1].inst_sync2_rstn.second_stage_sync_r

[0102] …

[0103] Comb. Logics: 500

[0104] Dut.genblk2[0].inst_sync2_rstn.dout

[0105] Dut.genblk2[0].inst_sync2_rstn.second_stage_sync_r

[0106] Step 3, use a formal verification tool to complete the following tasks: Read the register logic gates in the logic gate list, eliminate the possibly duplicate logic gates, combine the logic gates in the list, traverse each possible combination, generate system verilog assertions to prove that the logic gates can toggle simultaneously. Examples of the generated system Verilog assertions are as follows:

[0107] ivt_logic_reg_all_toggle_ast: assertproperty(p_ivt_sig_toggle_together(combined_regs_bits))

[0108] else $display(“ERROR”, “all reg bits could not toggle at the sametime!”)

[0109] …

[0110] ivt_logic_reg123_toggle_ast: assertproperty(p_ivt_sig_toggle_together(combined_reg123_bits))

[0111] else $display(“ERROR”, “reg 1 / 2 / 3could not toggle at the same time!”)

[0112] ivt_logic_reg13_toggle_ast: assertproperty(p_ivt_sig_toggle_together(combined_reg13_bits))

[0113] else $display(“ERROR”, “reg 1 / 3could not toggle at the same time!”)

[0114] ivt_logic_reg23_toggle_ast: assertproperty(p_ivt_sig_toggle_together(combined_reg23_bits))

[0115] else $display(“ERROR”, “reg 2 / 3could not toggle at the same time!”)

[0116] ivt_logic_reg12_toggle_ast: assert property(p_ivt_sig_toggle_together(combined_reg12_bits))

[0117] else $display("ERROR", "reg 1 / 2 could not toggle at the same time!")

[0118] Step 4: Run the formal verification tool to prove the automatically generated combinations. Select the assertion with the highest combination level and use the built-in function of the formal verification tool to generate waveforms, which is the scenario with the most flips at a certain moment.

[0119] To better understand the content of Step 3 and Step 4, let's assume that all the logic gates in the derived circuit are 10, and each logic gate is a non-repeated one. Then, combine all 10 logics together as a logic gate combination in a combinatorial way, and then take out 9 of them as a new combination to get nine logic gate combinations, and so on, until several logic gate combinations are obtained by pairwise combination. Subsequently, start the verification from the combination with the largest number of logic gates. For example, assume that the assertion of the logic gate combination containing ten logic gates determines that they cannot flip simultaneously, then verify the combination containing nine logic gates in turn. To save time and improve efficiency, if it is found that a certain combination containing at most 7 logic gates can flip simultaneously, there is no need to analyze the remaining combinations with fewer than 7 logic gates.

[0120] Step: In the specific implementation process, considering that the scenarios automatically found by the formal verification tool may be illegal, such as there is no such usage or the function is not supported. In this case, constraints are needed to eliminate the illegal scenarios and run the entire process again until the first legal scenario is found.

[0121] The method for determining the maximum power consumption of the chip in this embodiment has at least the following beneficial technical effects:

[0122] (1) Utilizing the exhaustive feature of the formal verification tool, the theoretically maximum number of flip gates can be found, which cannot be achieved through simulation because it is impossible to accurately apply the excitation to individual logic gates in simulation.

[0123] (2) Using formal verification to generate waveform excitation replaces the extremely time-consuming gate-level simulation, greatly improving the generation efficiency of waveform files.

[0124] (3) The dynamic power consumption of the chip can be estimated in advance on the RTL code, without waiting until the backend design is completed. Chip design engineers can get timely feedback and have ample time to change the design code, which undoubtedly saves a great deal of manpower and material resources for chip design.

[0125] In some embodiments, as shown in Figure 4 FIG. 5, the present invention further provides a device 200 for determining the maximum power consumption of a chip, and the device includes:

[0126] A building module 201 configured to build a formal verification environment with a formal verification tool;

[0127] A compiling module 202 configured to compile the RTL-level design code of the target chip in the formal verification environment to generate a gate-level model;

[0128] A combining module 203 configured to combine each logic gate in the gate-level model to generate a plurality of logic gate combinations;

[0129] A screening module 204 configured to generate assertions corresponding to each logic gate combination through the formal verification tool, and based on the assertions, screen out the logic gate combination with the most simultaneously flipped logic gates from all logic gate combinations as the target logic gate combination, wherein the assertions are used to prove whether all logic gates in the logic gate combination can be flipped simultaneously;

[0130] A determining module 205 configured to generate a waveform for the target logic gate combination through the formal verification tool, and determine the maximum power consumption of the target chip based on the waveform of the target logic gate combination.

[0131] The above device for determining the maximum power consumption of a chip, by utilizing the exhaustive feature of the formal verification tool, can find the theoretically maximum number of flipped gates, uses formal verification to generate waveform stimuli, replaces the extremely time-consuming gate-level simulation, greatly improves the generation efficiency of waveform files, without waiting until the backend design is completed. Chip design engineers can get timely feedback and have ample time to change the design code, saving a great deal of manpower and material resources for chip design.

[0132] It should be noted that the specific limitations on the device for determining the maximum power consumption of a chip can refer to the limitations on the method for determining the maximum power consumption of a chip in the above text, and will not be elaborated here. Each module in the above device for determining the maximum power consumption of a chip can be implemented in whole or in part through software, hardware, and their combination. The above modules can be embedded in the processor of the computer device in hardware form or be independent of it, or can be stored in the memory of the computer device in software form, so as to facilitate the processor to call and execute the operations corresponding to the above modules.

[0133] According to another aspect of the present invention, there is provided a computer device, which may be a server. For the internal structure diagram, please refer to Figure 5 as shown. The computer device includes a processor, a memory, a network interface, and a database connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, the above-mentioned method for determining the maximum power consumption of the chip is implemented. Specifically, the method includes the following steps:

[0134] Build a formal verification environment with a formal verification tool;

[0135] Compile the RTL-level design code of the target chip in the formal verification environment to generate a gate-level model;

[0136] Combine the logic gates in the gate-level model to generate a number of logic gate combinations;

[0137] Generate assertions corresponding to each logic gate combination through the formal verification tool, and screen out the logic gate combination with the most simultaneously flipped logic gates from all logic gate combinations as the target logic gate combination based on the assertions, where the assertions are used to prove whether all the logic gates in the logic gate combination can be flipped simultaneously;

[0138] Generate a waveform for the target logic gate combination through the formal verification tool, and determine the maximum power consumption of the target chip based on the waveform of the target logic gate combination.

[0139] According to still another aspect of the present invention, there is provided a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the above-mentioned method for determining the maximum power consumption of the chip is implemented. Specifically, it includes performing the following steps:

[0140] Build a formal verification environment with a formal verification tool;

[0141] Compile the RTL-level design code of the target chip in the formal verification environment to generate a gate-level model;

[0142] Combine the logic gates in the gate-level model to generate a number of logic gate combinations;

[0143] Generate assertions corresponding to each logic gate combination through the formal verification tool, and screen out the logic gate combination with the most simultaneously flipped logic gates from all logic gate combinations as the target logic gate combination based on the assertions, where the assertions are used to prove whether all logic gates in the logic gate combination can be flipped simultaneously;

[0144] Generate a waveform for the target logic gate combination through the formal verification tool, and determine the maximum power consumption of the target chip based on the waveform of the target logic gate combination.

[0145] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database, or other medium used in the various embodiments provided in the present application can include non-volatile and / or volatile memories. Non-volatile memories can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memories can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0146] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0147] The above-described embodiments merely represent several implementation manners of the present application. Their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method for determining the maximum power consumption of a chip, characterized in that, The method includes: Building a formal verification environment with a formal verification tool; Compiling the RTL-level design code of the target chip in the formal verification environment to generate a gate-level model; Combining each logic gate in the gate-level model to generate several logic gate combinations; Generating assertions corresponding to each logic gate combination through the formal verification tool, and screening out the logic gate combination with the most simultaneously flipped logic gates from all logic gate combinations as the target logic gate combination based on the assertions, where the assertions are used to prove whether all the logic gates in the logic gate combination can be flipped simultaneously; Generating a waveform for the target logic gate combination through the formal verification tool, and determining the maximum power consumption of the target chip based on the waveform of the target logic gate combination.

2. The method according to claim 1, wherein The step of building a formal verification environment with a formal verification tool includes: Generating a formal verification environment that supports properties based on a predefined design file, clock signal, reset signal, and polarity.

3. The method according to claim 1, wherein The step of combining each logic gate in the gate-level model to generate several logic gate combinations includes: Exporting all the logic gates in the gate-level model through the formal verification tool to generate a logic gate list; Reading the logic gates in the logic gate list and removing duplicate logic gates; Combining all the logic gates with duplicates removed in every possible combination way by traversing the gates to generate several logic gate combinations.

4. The method according to claim 1, wherein The step of generating assertions corresponding to each logic gate combination through the formal verification tool, and screening out the logic gate combination with the most simultaneously flipped logic gates from all logic gate combinations as the target logic gate combination includes: Counting the number of logic gates included in each logic gate combination; Each time, selecting the logic gate combination with the largest number of current logic gates from all logic gate combinations without replacement; Using the formal verification tool to generate an assertion for the selected logic gate combination with the largest number of current logic gates; In response to the assertion proving that all the logic gates in the selected logic gate combination with the largest number of current logic gates cannot be flipped simultaneously, returning to execute the step of selecting the logic gate combination with the largest number of current logic gates from all logic gate combinations without replacement; In response to the assertion proving that all the logic gates in the selected logic gate combination with the largest number of current logic gates can be flipped simultaneously, taking the selected logic gate combination with the largest number of current logic gates as the target logic gate combination.

5. The method according to claim 4, characterized in that Before executing the step of taking the selected logic gate combination with the largest number of current logic gates as the target logic gate combination, the method further includes: Performing a legality verification on the selected logic gate combination with the largest number of current logic gates to determine whether the selected logic gate combination with the largest number of current logic gates is legal; In response to the selected logic gate combination with the largest number of current logic gates being illegal, returning to execute the step of selecting the logic gate combination with the largest number of current logic gates from all logic gate combinations without replacement; If the combination of logic gates with the largest number of currently selected logic gates is legal, then perform the step of taking the combination of logic gates with the largest number of currently selected logic gates as the target logic gate combination.

6. The method according to claim 5, wherein The step of verifying the legality of the combination of logic gates with the largest number of currently selected logic gates to determine whether the combination of logic gates with the largest number of currently selected logic gates is legal includes: Compare each logic gate in the combination of logic gates with the largest number of currently selected logic gates with a preset list of illegal logic gate combinations, where the preset list of illegal logic gate combinations includes several combinations of illegal logic gates; If there is at least one identical logic gate combination between the combination of logic gates with the largest number of currently selected logic gates and the preset list of illegal logic gate combinations, then determine that the combination of logic gates with the largest number of currently selected logic gates is illegal; Otherwise, determine that the combination of logic gates with the largest number of currently selected logic gates is legal.

7. The method according to claim 1, characterized in that, The step of generating a waveform for the target logic gate combination by the formal verification tool and determining the maximum power consumption of the target chip based on the waveform of the target logic gate combination includes: If there are multiple groups of the target logic gate combination, use the formal verification tool to generate waveforms for each group of target logic gate combinations respectively; Determine the power consumption value of each group of target logic gate combinations based on the waveforms, and take the maximum power consumption value as the maximum power consumption of the target chip.

8. A device for determining the maximum power consumption of a chip, characterized in that, The device includes: A building module configured to build a formal verification environment with a formal verification tool; A compilation module configured to compile the RTL-level design code of the target chip in the formal verification environment to generate a gate-level model; A combination module configured to combine each logic gate in the gate-level model to generate several logic gate combinations; A screening module configured to generate assertions corresponding to each logic gate combination by the formal verification tool, and screen out the combination of logic gates with the largest number of simultaneously flipped logic gates as the target logic gate combination from all logic gate combinations based on the assertions, where the assertions are used to prove whether all logic gates in the logic gate combination can be flipped simultaneously; A determination module configured to generate a waveform for the target logic gate combination by the formal verification tool and determine the maximum power consumption of the target chip based on the waveform of the target logic gate combination.

9. A computer device, characterized in that, Includes: At least one processor; And A memory storing a computer program that can run in the processor, and when the processor executes the program, it executes the method according to any one of claims 1-7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it executes the method according to any one of claims 1-7.

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