Waveform generation device, waveform generation method, and charged particle beam irradiation device

Abstract

A waveform generating device, waveform generating method, and charged particle beam irradiation device capable of canceling voltage spikes generated in the output of an amplifier. The waveform generating device comprises: a first DA converter that performs digital-to-analog conversion on input data and outputs the result; a control unit that outputs a first signal having a command value based on the input data and a second signal having a command value such that the difference from the command value of the first signal is constant; a second DA converter that performs digital-to-analog conversion on the first signal and outputs the result; a third DA converter that performs digital-to-analog conversion on the second signal and outputs the result; and a synthesizer that synthesizes the outputs of the first, second, and third DA converters. When the value of a predetermined first high-order bit of the input data is inverted, the control unit changes the command value of the first signal so that the value of the first high-order bit or a second high-order bit different from the first high-order bit is inverted.

Description

[0001] Related applications

[0002] This application claims the benefit of priority based on Japanese Patent Application No. 2021-016707 (filing date: February 4, 2021), and the present application incorporates all the contents of the basic application by reference. Technical Field

[0003] The present invention relates to a waveform generating device, a waveform generating method, and a charged particle beam irradiation device. Background Art

[0004] With the high integration of LSI, the circuit line width and metal wiring spacing of semiconductor devices are becoming smaller and smaller year by year. In order to form the circuit pattern of such a semiconductor device, the following method is adopted, namely, using a reduced projection exposure device, using a laser such as ArF to reduce and transfer the high-precision original pattern formed on quartz to a wafer (photolithography). In recent years, in order to form finer patterns, EUV lithography using extreme ultraviolet rays has begun to be used. In EUV lithography, a mask with a multilayer structure composed of multiple materials is used. In any mask, the so-called electron beam lithography technology is used in the production of high-precision original patterns, that is, the resist on the mask blank is selectively exposed by an electron beam drawing device to form a pattern.

[0005] In electron beam lithography, a substrate to be lithography is placed on a stage, and lithography is performed while the stage moves. Tracking control is performed to ensure that the beam irradiation position follows the stage's movement, preventing it from shifting. The tracking amplifier, which outputs the deflection voltage for tracking control, operates continuously, sometimes generating voltage spikes (instantaneous, sudden voltage fluctuations) in the output. These voltage spikes can cause the beam irradiation position to shift, degrading lithography accuracy. Summary of the Invention

[0006] The present invention provides a waveform generating device, a waveform generating method, and a charged particle beam irradiation device capable of canceling a spike pulse generated in the output of an amplifier.

[0007] A waveform generating device according to one embodiment of the present invention comprises: a first DA converter that performs digital-to-analog conversion on input data and outputs the result; a control unit that outputs a first signal and a second signal, the first signal having an instruction value based on the input data and the second signal having an instruction value such that the difference between the first signal and the instruction value is constant; a second DA converter that performs digital-to-analog conversion on the first signal and outputs the result; a third DA converter that performs digital-to-analog conversion on the second signal and outputs the result; and a synthesizer that synthesizes the outputs of the first DA converter, the second DA converter, and the third DA converter, wherein, when the value of a predetermined first high-order bit of the input data is inverted, the control unit changes the instruction value of the first signal so as to invert the value of the first high-order bit or a second high-order bit different from the first high-order bit. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a configuration diagram of a waveform generating device according to an embodiment of the present invention.

[0009] Figure 2 (a) is a graph showing the output of the DA converter including a voltage spike pulse. Figure 2 (b) is a graph showing the output of the DA converter used for displacement cancellation. Figure 2 (c) is a graph showing a voltage spike pulse waveform.

[0010] Figure 3 (a) is a graph showing the output of the DA converter including a voltage spike pulse. Figure 3 (b) is a graph showing the waveform of the voltage spike pulse used for cancellation. Figure 3 (c) is a graph showing the voltage change after the voltage spike pulse is offset.

[0011] Figure 4 It is a diagram showing the configuration of a waveform generating device according to a modified example.

[0012] Figure 5 (a) is a graph showing the output of the DA converter including a voltage spike pulse. Figure 5 (b) is a graph showing the output of the DA converter used for displacement cancellation. Figure 5 (c) is a graph showing a voltage spike pulse waveform.

[0013] Figure 6 (a) is a graph showing the output of the DA converter including a voltage spike pulse. Figure 6 (b) is a graph showing the waveform of the voltage spike pulse used for cancellation. Figure 6 (c) is a graph showing the voltage change after the voltage spike pulse is offset.

[0014] Figure 7 This is a diagram showing the configuration of a drawing device according to an embodiment of the present invention.

[0015] Figure 8 It is a diagram explaining each area.

[0016] Figure 9 This is a schematic diagram of the tracking amplifier.

[0017] Figure 10 (a) is a diagram showing an example of an output waveform of a DA converter.

[0018] Figure 10 (b) is a diagram showing an example of a voltage spike waveform for cancellation.

[0019] Figure 10 (c) is a diagram showing an example of a waveform after synthesizing the offset voltage spike waveform.

[0020] Figure 10 (d) is a diagram showing an example of a voltage spike waveform for cancellation.

[0021] Figure 10 (e) is a diagram showing an example of a waveform after synthesizing the offset voltage spike waveform.

[0022] Figure 11 This is a diagram showing the configuration of a waveform generating device according to another embodiment.

[0023] Figure 12 This is a diagram showing the configuration of a waveform generating device according to another embodiment.

[0024] Description of Reference Numerals

[0025] 60 Control Department

[0026] 62 DA converter

[0027] 64 Synthesizer

[0028] 70 Offset voltage spike pulse generation unit

[0029] 71~76 DA converter

[0030] 77-79 Synthesizer

[0031] 100 Drawing Device

[0032] 101 substrate

[0033] 120 Deflection control circuit

[0034] 132, 134 DAC amplifiers

[0035] 136 DAC amplifier (tracking amplifier)

[0036] 138 Adder

[0037] 200 electron beam

[0038] 208 Main Deflector

[0039] 209 Auxiliary deflector DETAILED DESCRIPTION

[0040] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

[0041] Figure 1 FIG. 5 shows the configuration of a waveform generating device according to an embodiment of the present invention. Figure 1 As shown, the waveform generating device includes a control unit 60 , a DA converter 62 (first DA converter), a synthesizer 64 , and a canceling voltage spike pulse generating unit 70 .

[0042] The DA converter 62 receives input data, which includes a command value, via the control unit 60 and converts it into an analog signal. The DA converter 62 generates an output proportional to the received command value. In binary notation of the command value, the bit with the greatest weight on the output is called the most significant bit, and the bit with the least significant weight on the output is called the least significant bit. This command value changes continuously.

[0043] When a change in the command value is accompanied by an inversion of a high-order bit, a large voltage spike is generated in the output of DA converter 62. For example, when a command value represented in binary 8 bits (offset binary) changes from "00111111" (hereinafter, binary numbers are enclosed in parentheses) to "01000000," or from "01000000" to "00111111," the second high-order bit is inverted. In this case, a large voltage spike is generated in the output of DA converter 62. Generally speaking, voltage spikes tend to be somewhat larger for higher-order bits.

[0044] The control unit 60 monitors input data and, when a change in the command value is accompanied by an inversion of a high-order bit, instructs the cancellation voltage spike generator 70 to generate a cancellation voltage spike waveform. The canceling voltage spike waveform generated by the cancellation voltage spike generator 70 is subtracted from the output of the DA converter 62, which contains a voltage spike, by the synthesizer 64, thereby canceling the voltage spike that appears in the output of the DA converter 62.

[0045] Furthermore, when the command value changes from "00000001" to "00000010" without inversion of the upper bit (when only the lower bit is inverted), (almost) no voltage spike is generated in the output of the DA converter 62, and therefore, there is no need to generate a voltage spike for cancellation.

[0046] The cancellation voltage spike generator 70 includes DA converters 71 and 74 connected in parallel, and a synthesizer 77. Here, the explanation is made assuming that a large voltage spike is generated in the output of the DA converter 62 when the upper first bit of the command value is inverted.

[0047] A first signal having an 8-bit command value with the most significant bit inverted, which generates a large voltage spike at the output of DA converter 71 (second DA converter), is output from control unit 60 and input to DA converter 71. For example, the command value with the most significant bit inverted, such as from "01111111" to "10000000" (or vice versa), is input to DA converter 71.

[0048] One of these two command values is input to DA converter 71 based on the input to DA converter 62. Specifically, when the input to DA converter 62 is "01111111" or less ("00000000" to "01111111"), the input to DA converter 71 is "01111111." When the input to DA converter 62 is "10000000" or greater ("10000000" to "11111111"), the input to DA converter 71 is "10000000."

[0049] For example, when the input of DA converter 62 changes continuously as follows: "01111110" → "01111111" → "10000000" → "10000001", the input of DA converter 71 changes as follows: "01111111" → "01111111" → "10000000" → "100000001".

[0050] When the input of DA converter 71 (and DA converter 62 ) changes from “01111111” to “10000000”, the output of DA converter 71 includes a voltage spike pulse accompanying the inversion of the upper first bit.

[0051] A second signal is output from the control unit 60 so that no (large) voltage spike pulse is generated in the output of the DA converter 74 (third DA converter), that is, no inversion of the most significant bit is accompanied, and the second signal has an 8-bit instruction value with the same displacement as the first signal input to the DA converter 71, and is input to the DA converter 74.

[0052] For example, an 8-bit command value that differs by one least significant bit ("00000001") from the input of DA converter 71, such as from "10000000" to "10000001", is input to DA converter 74. Difference by one least significant bit means addition of "00000001" (or subtraction of "00000001"). Therefore, when the input of DA converter 71 is "01111111", the input of DA converter 74 is "10000000", and when the input of DA converter 71 is "10000000", the input of DA converter 74 is "10000001" (when "00000001" is subtracted, when the input of DA converter 71 is "01111111", the input of DA converter 74 is "01111110", and when the input of DA converter 71 is "10000000", the input of DA converter 74 is "01111111").

[0053] Figure 2 (a) shows an example of the output of the DA converter 71 . Figure 2 (b) shows an example of the output of DA converter 74. When the input of DA converter 71 changes from "01111111" to "10000000", a voltage spike is generated due to the inversion of the most significant bit. Since the input change of DA converter 74 does not include the inversion of the most significant bit, no voltage spike is generated in the output.

[0054] If the output of DA converter 74 is subtracted from the output of DA converter 71 by synthesizer 77 ( Figure 2 (a)- Figure 2 (b)), then Figure 2 As shown in (c), the voltage spike waveform associated with the inversion of the most significant bit can be extracted. Furthermore, although a deviation of one least significant bit ("00000001") remains as the difference between the outputs of DA converter 71 and DA converter 74, this is extremely small relative to the voltage spike waveform and can be ignored (allowed). The voltage spike waveform thus extracted is used to cancel the voltage spike generated in the output of DA converter 62 when the input of DA converter 62 changes from "01111111" to "10000000."

[0055] The control unit 60 generates a canceling voltage spike waveform using the DA converters 71 and 74 and the synthesizer (subtractor) 77 in accordance with the timing of inversion of the most significant bit of the command value input to the DA converter 62 .

[0056] Figure 3(a) shows an example of the output of the DA converter 62. In this example, the input of the DA converter 62 increases monotonically with the passage of time. In the synthesizer 64, the output of the DA converter 62 is subtracted by Figure 3 The voltage spike waveform for cancellation shown in (b) ( Figure 3 (a)- Figure 3 (b) of the subtraction), so that Figure 3 (c) shows the offset voltage spike pulse.

[0057] The order of subtracting the output of DA converter 71 and adding the output of DA converter 74 to the output of DA converter 62 is not limited. For example, the output of DA converter 74 may be added after the output of DA converter 62 and the output of DA converter 71 are subtracted. Alternatively, the output of DA converter 71 may be subtracted after the output of DA converter 62 and the output of DA converter 74 are added.

[0058] Furthermore, the method for synthesizing the outputs of DA converter 71 and DA converter 74 with respect to the output of DA converter 62 (addition / subtraction) is not particularly limited, as long as the voltage spikes included in the output of DA converter 62 are reduced. For example, the inputs of DA converter 71 and DA converter 74 may be set so that a desired signal is obtained by adding the outputs of DA converter 71 and DA converter 74 to the output of DA converter 62.

[0059] Figure 1 The synthesizer 64 and the synthesizer 77 in the offset voltage spike pulse generating unit 70 may also be functionally integrated into one. Figure 1 The synthesizer 64 and the synthesizer 77 in the canceling voltage spike pulse generating section 70 form a synthesizer composed of a single analog circuit.

[0060] Figure 4 The waveform generating device is configured to cancel the voltage spike pulse generated in the output of the DA converter 62 when the upper first bit of the command value of the input data is inverted and the upper second bit of the command value is inverted. Figure 1 The waveform generator shown has DA converters 72, 73, 75, and 76 added to the offset voltage spike generator 70 in parallel with DA converters 71 and 74, and further has synthesizers 78 and 79. The operations of DA converters 71 and 74 are the same as those described above, so their description is omitted.

[0061] The synthesizer 78 adds the outputs of the DA converters 71 to 73 (the second DA converter group). The synthesizer 79 adds the outputs of the DA converters 74 to 76 (the third DA converter group). The synthesizer 77 subtracts the output of the synthesizer 79 from the output of the synthesizer 78.

[0062] Assuming that the voltage spike generated when the second-most significant bit of the input data command value is inverted varies in magnitude depending on the value of the first-most significant bit (most significant bit), the voltage spike generated when the second-most significant bit is inverted is handled differently depending on the value of the most significant bit.

[0063] The designer can determine the maximum number of bits in the command value that will generate a large voltage spike in the output of DA converter 62 when inversion occurs, for example, "maximum three bits," "maximum four bits," etc., based on accuracy and other factors. Alternatively, the maximum number of bits in the command value may be set to, for example, the bit sequence higher than half the value. Furthermore, for example, all bits higher than half the value need not be used. Although the effect will be less pronounced, a voltage spike waveform may be generated to offset the voltage spike generated when inversion occurs for a portion of the bits higher than half the value, for example, only the most significant bit or only the second most significant bit.

[0064] The DA converter 72 receives an 8-bit command value, in which the most significant bit is 0 and the second most significant bit is inverted, such as changing from “00111111” to “01000000” (or vice versa).

[0065] Depending on the input to DA converter 62, one of these two command values is input to DA converter 72. Specifically, when the input to DA converter 62 is "00111111" or less ("00000000" to "00111111"), the input to DA converter 72 becomes "00111111." When the input to DA converter 62 is "01000000" or greater ("01000000" to "11111111"), the input to DA converter 72 becomes "01000000." When the input to DA converter 72 (and DA converter 62) changes from "00111111" to "01000000," the output of DA converter 72 includes a voltage spike associated with the inversion of the second most significant bit.

[0066] The DA converter 73 receives an 8-bit command value, in which the most significant bit is 1 and the second most significant bit is inverted, such as changing from “10111111” to “11000000” (or vice versa).

[0067] Depending on the input to DA converter 62, one of these two command values is input to DA converter 73. Specifically, when the input to DA converter 62 is "10111111" or less ("00000000" to "10111111"), the input to DA converter 73 becomes "10111111." When the input to DA converter 62 is "11000000" or greater ("11000000" to "11111111"), the input to DA converter 71 becomes "11000000." When the input to DA converter 73 (and DA converter 62) changes from "10111111" to "11000000," the output of DA converter 73 includes a voltage spike associated with the inversion of the second most significant bit.

[0068] DA converter 75 receives a command value that changes from "01000000" to "01000001," which differs from the input of DA converter 72 by only one least significant bit ("00000001"). Subtracting the output of DA converter 75 from the output of DA converter 72 yields a voltage spike waveform with the inversion of the second most significant bit when the most significant bit is 0. This voltage spike waveform is used to offset the voltage spike generated in the output of DA converter 62 when the input of DA converter 62 changes from "00111111" to "01000000."

[0069] When "00000001" is added, DA converter 76 receives a command value that changes from "11000000" to "11000001" (when "00000001" is subtracted, DA converter 76 receives a command value that differs from the input of DA converter 73 by only one least significant bit ("00000001"), such that the value changes from "11000000" to "11000001" (and from "10111110" to "10111111"). Subtracting the output of DA converter 76 from the output of DA converter 73 yields a voltage spike waveform with the inversion of the second most significant bit when the most significant bit is 1. This voltage spike waveform is used to offset the voltage spike generated in the output of DA converter 62 when the input of DA converter 62 changes from "10111111" to "11000000."

[0070] Control unit 60 changes the inputs to DA converters 72 and 75 in time with the timing when the most significant bit of the command value input to DA converter 62 is 0 and the second most significant bit is inverted, and synthesizer 77 outputs a canceling voltage spike waveform.

[0071] Control unit 60 changes the inputs to DA converters 73 and 76 in time with the timing when the most significant bit of the command value input to DA converter 62 is 1 and the second most significant bit is inverted, and synthesizer 77 outputs a canceling voltage spike waveform.

[0072] Figure 5 (a) shows an example of the outputs of the DA converters 71 to 73 . Figure 5 (b) shows an example of the output of the DA converters 74 to 76 . Figure 5 (c) is a diagram showing an example of a voltage spike pulse waveform for cancellation generated using the outputs of DA converters 71 to 76, which can be obtained by performing the operation (synthesis) of +(output of DA converter 71) +(output of DA converter 72) +(output of DA converter 73) -(output of DA converter 74) -(output of DA converter 75) -(output of DA converter 76) using synthesizers 77 to 79.

[0073] Figure 6 (a) shows an example of the output of the DA converter 62. In this example, the input of the DA converter 62 increases monotonically with the passage of time. The synthesizer 64 subtracts the output of the DA converter 62 from the output of the DA converter 62. Figure 6 The voltage spike waveform for cancellation shown in (b) ( Figure 6 (a)- Figure 6 (b) of the subtraction operation), so that Figure 6 The voltage spike pulse is offset as shown in (c).

[0074] In the above embodiment, the configuration in which the cancel voltage spike pulse generator 70 includes three DA converters 71 to 73 and three DA converters 74 to 76 for offsetting the shift is described as a total of six DA converters in order to offset the voltage spike pulse generated by the inversion of the upper first and second bits. However, in order to offset the voltage spike pulse generated by the inversion of the upper n-th bit (n is an integer greater than or equal to 1), the cancel voltage spike pulse generator 70 includes (2 n -1) × 2 DA converters.

[0075] In the above embodiment, when the voltage spike waveform is generated by the cancellation voltage spike generator 70, a deviation of one least significant bit ("00000001") remains. However, by balancing the operations of the DA converters 74 to 76, the deviation can ultimately be reduced to zero. For example, the inputs of the DA converters 71 to 76 can be set as follows based on changes in the input of the DA converter 62.

[0076] DA converter 62 "01111111" → "10000000"

[0077] DA converter 71 "01111111" → "10000000"

[0078] DA converter 74 "01111101" → "01111110"

[0079] DA converter 62 "00111111" → "01000000"

[0080] DA converter 72 "00111111" → "01000000"

[0081] DA converter 75 "01000000" → "01000001"

[0082] DA converter 62 "10111111" → "11000000"

[0083] DA converter 73 "10111111" → "11000000"

[0084] DA converter 76 "11000000" → "11000001"

[0085] The input to DA converter 75 is one least significant bit greater than the input to DA converter 72, and the input to DA converter 76 is one least significant bit greater than the input to DA converter 73. On the other hand, the input to DA converter 74 is two least significant bits smaller than the input to DA converter 71. This ultimately reduces the deviation to zero.

[0086] In the above embodiment, an example in which the input value of the DA converter 62 increases has been described, but the same processing can be applied also when the input value decreases.

[0087] In the above embodiment, a configuration is described in which a signal obtained by adding the outputs of DA converters 71 to 73 is subtracted from a signal obtained by adding the outputs of DA converters 74 to 76 to generate a canceling voltage spike waveform, and then the canceling voltage spike waveform is subtracted from the output of DA converter 62. However, the order of signal synthesis is not limited to this. For example, a signal obtained by adding the outputs of DA converters 71 to 73 may be subtracted from the output of DA converter 62, and then the signal obtained by adding the outputs of DA converters 74 to 76 may be added. Alternatively, a signal obtained by adding the outputs of DA converters 74 to 76 may be added to the output of DA converter 62, and then the signal obtained by adding the outputs of DA converters 71 to 73 may be subtracted.

[0088] Next, a charged particle beam irradiation device employing this waveform generation device will be described. In the embodiments, an electron beam is described as an example of a charged particle beam. However, the charged particle beam is not limited to an electron beam and may also be an ion beam, etc. Furthermore, in the embodiments, a drawing device is described as an example of an irradiation device, but an inspection device, etc., may also be used.

[0089] Figure 7 This is a conceptual diagram showing the structure of a drawing device according to an embodiment of the present invention. Figure 7 In FIG, the rendering device 100 includes a rendering unit 150 and a control unit 160. The rendering device 100 is an example of a formattable rendering device.

[0090] The drawing unit 150 includes an electron lens column (electron beam column) 102 and a drawing chamber 103. Within the electron lens column 102 are located an electron gun 201, an illumination lens 202, a blanking deflector 212, a first aperture-forming substrate 203, a projection lens 204, a deflector 205, a second aperture-forming substrate 206, an objective lens 207, a main deflector 208, and a sub-deflector 209. Within the drawing chamber 103 is located an XY stage 105. A substrate 101, such as a resist-coated mask to be drawn, is placed on the XY stage 105. The substrate 101 may be an exposure mask used in semiconductor device manufacturing or a resist-coated mask blank that has not yet been drawn.

[0091] The control unit 160 includes a control computer 110, a memory 111, a deflection control circuit 120, a control circuit 122, DAC (digital-to-analog converter) amplifiers 132, 134, and 136, an adder 138, and storage devices 140 and 142, such as magnetic disks. The DAC amplifiers 132, 134, and 136 are connected to the deflection control circuit 120. The adder 138 is connected to the outputs of the DAC amplifiers 134 and 136.

[0092] The DAC amplifier 132 is connected to the auxiliary deflector 209. The output of the DAC amplifier 134 is connected to the adder 138. The output of the DAC amplifier 136 is connected to the adder 138. The output of the adder 138 is connected to the main deflector 208.

[0093] The deflection control circuit 120 outputs corresponding digital control signals to the DAC amplifiers 132, 134, and 136. Each DAC amplifier then converts the digital signals into analog signals, amplifies them, and outputs them as deflection voltages. The sum of the outputs from the DAC amplifiers 134 and 136 is applied to the main deflection unit 208 as the deflection voltage for main deflection. The output from the DAC amplifier 132 is applied to the sub-deflection unit 209 as the deflection voltage for sub-deflection. These deflection voltages are used to deflect the electron beam. The control circuit 122 controls the operation of the drawing unit 150 under the control of the drawing control unit 52 within the control computer 110.

[0094] The control computer 110 includes a data processing unit 50 and a rendering control unit 52. Each of these "units" includes a processing circuit. The processing circuit may include, for example, an electronic circuit, a computer, a processor, a circuit board, a quantum circuit, or a semiconductor device. Each "unit" may use a common processing circuit (the same processing circuit) or different processing circuits (separate processing circuits). Information input and output to and from the data processing unit 50 and the rendering control unit 52, as well as information being calculated, is always stored in the memory 111.

[0095] Data for the chip pattern to be drawn (chip data) is input from outside the drawing device 100 and stored in the storage device 140. The chip data defines a graphic code indicating the type of graphic pattern to be drawn, as well as layout coordinates, dimensions, and other information. Furthermore, this data may also define exposure information. Alternatively, the exposure information may be input as separate data.

[0096] Figure 8 This is a conceptual diagram used to illustrate each area. Figure 8 In the drawing area 10 of the substrate 101, the deflectable width of the main deflector 208 is virtually divided into a plurality of stripe areas 20 in a rectangular shape, for example, in the y direction. The main deflector 208 deflects along the x and y directions within the main deflection area 22 surrounded by the deflectable width of the main deflector 208. By virtually dividing each stripe area 20 into a grid shape according to the deflectable size of the auxiliary deflector 209, a plurality of subfields (SF) 30 (small areas) are generated. Figure 8 In the example of FIG. 3 , emission patterns 42 , 44 , and 46 are drawn at an emission position of a certain SF 30 .

[0097] A digital signal for blanking control is output from the deflection control circuit 120 to a DAC amplifier (not shown) for blanking control. The DAC amplifier converts the digital signal into an analog signal, amplifies it, and applies it as a deflection voltage to the blanking deflector 212. The blanking deflector 212 deflects the electron beam 200 and switches the beam on and off.

[0098] The deflection control circuit 120 outputs a digital signal for shaping deflection control to a DAC amplifier (not shown) for shaping deflection control. The DAC amplifier converts the digital signal into an analog signal, amplifies it, and applies it as a deflection voltage to the deflector 205. The deflector 205 deflects the electron beam 200, thereby controlling the position at which the electron beam 200, after passing through the first shaping aperture substrate 203, passes through the opening of the second shaping aperture substrate 206, thereby shaping each emitted beam.

[0099] The deflection control circuit 120 outputs a digital signal (main deflection data) for main deflection control to a DAC amplifier 134 (first amplifier). The DAC amplifier 134 converts the digital signal into an analog signal, amplifies it, and applies it as a deflection voltage (first deflection voltage) to the main deflector 208. The main deflector 208 deflects each transmitted beam to a reference position within a predetermined subfield (SF) 30 virtually divided into a grid.

[0100] At the same time, the deflection control circuit 120 outputs a digital signal for tracking control (tracking data) to the DAC amplifier 136 (second amplifier). The DAC amplifier 136 converts the digital signal into an analog signal, amplifies it, and applies it as a deflection voltage (second deflection voltage) to the main deflector 208. Furthermore, the main deflector 208 receives a deflection voltage obtained by adding the deflection voltage for main deflection control and the deflection voltage for tracking control by the adder 138.

[0101] The deflection control circuit 120 outputs a digital signal for sub-deflection control to the DAC amplifier 132. The DAC amplifier 132 converts the digital signal into an analog signal, amplifies it, and applies it as a deflection voltage to the sub-deflector 209. The sub-deflector 209 deflects each transmitted beam toward each transmission position within a predetermined subfield (SF) virtually divided into a grid.

[0102] In the drawing apparatus 100, a multi-stage deflector is used to gradually perform drawing processing for each stripe region 20. Here, as an example, a two-stage deflector, namely a main deflector 208 and a sub-deflector 209, is used.

[0103] For example, the XY worktable 105 continuously moves in the -x direction while gradually depicting the first stripe area 20 in the x direction. In the case where multiple depictions are not performed but each stripe area 20 is depicted once, the operation is performed, for example, as follows. After the depiction of the first stripe area 20 is completed, the second stripe area 20 is gradually depicted in the same or opposite direction. Thereafter, the third and subsequent stripe areas 20 are also gradually depicted. When depicting each stripe area 20, the main deflector 208 deflects the electron beam 200 to the reference position (for example, the center) of the SF30 in sequence in a manner following the movement of the XY worktable 105. In addition, the sub-deflector 209 deflects the electron beam 200 from the reference position of each SF30 to each emission position of the beam irradiated into the SF30. In this way, the main deflector 208 and the sub-deflector 209 have deflection areas of different sizes. SF30 becomes the smallest deflection area among the deflection areas of the multi-stage deflector.

[0104] The electron beam 200 emitted from the electron gun 201 (emission unit) passes through the blanking deflector 212. The blanking deflector 212, controlled by a deflection signal from a blanking DAC amplifier, illuminates the entire rectangular opening of the first shaping aperture substrate 203 when the beam is on. In the beam-off state, the beam is deflected so that the entire beam is blocked by the first shaping aperture substrate 203. From the beam-off state to the beam-on state and then back to the beam-off state, the electron beam 200 that passes through the first shaping aperture substrate 203 constitutes a single electron beam emission. The blanking deflector 212 controls the direction of the passing electron beam 200, alternating between the beam-on and beam-off states. For example, no voltage is applied in the beam-on state, and voltage is applied to the blanking deflector 212 when the beam is off. The irradiation amount of the electron beam 200 irradiated to the substrate 101 per shot is adjusted within the irradiation time of each shot.

[0105] The electron beam 200, controlled to be beam-on (ON), illuminates the entire first aperture-forming substrate 203, which has a rectangular opening, using an illumination lens 202. The electron beam 200 is shaped into a rectangular shape by the first aperture-forming substrate 203. Having passed through the first aperture image of the first aperture-forming substrate 203, the electron beam 200 is projected onto the second aperture-forming substrate 206 using a projection lens 204. The first aperture image on the second aperture-forming substrate 206 is deflected and controlled by a deflector 205, enabling the beam shape and size to be varied (variable shaping). Variable shaping is performed with each emission, for example, to achieve a different beam shape and size with each emission. The electron beam 200, having passed through the second aperture image of the second aperture-forming substrate 206, is then focused by an objective lens 207, deflected by a main deflector 208 and a sub-deflector 209, and irradiated onto a desired position on the substrate 101, which is positioned on the continuously moving XY stage 105.

[0106] exist Figure 7 Figure 2 shows a case where multi-stage deflection, using both main and auxiliary stages, is used for position deflection. In this case, the emitted electron beam 200 is deflected to the reference position of the SF 30 using the main deflector 208 while following the movement of the stage, and the emitted beam is deflected to various irradiation positions within the SF using the auxiliary deflector 209. By repeating this operation, the emission patterns of the individual emissions are connected, creating a desired pattern.

[0107] Figure 9 This is a diagram showing the configuration of a DAC amplifier 136 (hereinafter also referred to as tracking amplifier 136) that outputs a deflection voltage for tracking control. Figure 4 A waveform generating device with the same structure.

[0108] The DA converter 62 receives tracking data as a command value from the deflection control circuit 120 via the control unit 60 and converts the data into an analog signal. The command value continuously changes according to the movement of the XY stage 105.

[0109] The control unit 60 monitors the trace data and, when a change in the command value is accompanied by an inversion of the upper bits (in this example, the first and second upper bits), instructs the cancelling voltage spike generator 70 to generate a cancelling voltage spike waveform. A synthesizer (subtractor) 64 subtracts the cancelling voltage spike generated by the cancelling voltage spike generator 70 from the output of the DA converter 62, which contains the voltage spike, thereby cancelling the voltage spike that appears in the output of the DA converter 62.

[0110] Since the voltage spike pulse of the output of the tracking amplifier 136 is suppressed, the beam deflection amount by the main deflector 208 is stabilized, and the imaging accuracy can be improved.

[0111] exist Figure 7 , the components necessary to explain the embodiment are described. The rendering apparatus 100 may also include other commonly required components. For example, although a multi-stage deflector with two main and auxiliary stages, namely, the main deflector 208 and the auxiliary deflector 209, is used for position deflection, a multi-stage deflector with three or more stages may also be used for position deflection.

[0112] The main deflector 208 and the auxiliary deflector 209 are configured, for example, with octapole electrodes surrounding the electron beam's passage area, and a DAC amplifier is provided for each electrode. The shape-shifting deflector 205 can be configured, for example, with quaternary electrodes, and naturally, a DAC amplifier (not shown) is provided for each electrode. Similarly, the blanking deflector 212 can be configured, for example, with bipolar electrodes, and naturally, a DAC amplifier (not shown) is provided for at least one of the two electrodes.

[0113] Furthermore, the rendering device 100 may be connected to an input device such as a mouse and a keyboard, a monitor device, an external interface circuit, and the like.

[0114] Alternatively, the deflection control circuit 120 may have Figure 4 The waveform generating device of the same structure converts a digital signal for shaping deflection control, main deflection control, or sub-deflection control into an analog signal, and applies it to the deflector 205 , the main deflector 208 , or the sub-deflector 209 as a deflection voltage.

[0115] In the above embodiment, an example was described in which, when the value of a predetermined upper-order bit of the input data to the first DA converter is inverted, the command value of the input signal to the second DA converter is changed so that the value of the same bit is inverted, and the output of the second DA converter is combined with the output of the third DA converter to generate a canceling voltage spike waveform. For example, when the value of the most significant bit of the input data to the first DA converter is inverted, the value of the most significant bit of the command value of the input signal to the second DA converter is also inverted.

[0116] However, the bits whose values are inverted in the input data of the first DA converter and the bits whose values are inverted in the input signal of the second DA converter may be different. This is explained below using a specific example. For ease of explanation, the input data of the first and second DA converters are represented as 4-bit binary numbers.

[0117] For example, if the input to the first DA converter changes continuously from "0010" to "0011" to "0100" to "0101," the input to the second DA converter will change from "0111" to "0111" to "1000" to "1000." In other words, when the second most significant bit of the input to the first DA converter is inverted, the most significant bit of the input to the second DA converter is also inverted.

[0118] The input of the third DA converter differs from the input of the second DA converter by one least significant bit ("0001"). When the input of the second DA converter is "0111", the input of the third DA converter is "1000". When the input of the second DA converter is "1000", the input of the third DA converter is "1001".

[0119] The output of the second DA converter is combined with the output of the third DA converter to generate a canceling voltage spike waveform. This canceling voltage spike waveform is combined with the output of the first DA converter to reduce voltage spikes in the output of the first DA converter.

[0120] Because the number of inverted bits differs between the inputs of the first and second DA converters, the magnitude of the voltage spike pulse included in the output of the first and second DA converters differs. Depending on the relationship between the magnitudes of the voltage spike pulses included in the output of the first and second DA converters, even when combining the canceling voltage spike waveforms, the voltage spike pulse included in the output of the first DA converter may not be sufficiently reduced.

[0121] Figure 10 (a) shows an example of the output of the first DA converter, Figure 10 (b) shows an example of a voltage spike waveform for cancellation. For example, when the input of the first DA converter changes continuously as "0010" → "0011" → "0100" → "0101", Figure 10 As shown in (a), a voltage spike pulse of 20mV is generated. If the input of the second DA converter is changed as "0111" → "0111" → "1000" → "1000", then Figure 10 As shown in (b), a 40mV offset voltage spike waveform is generated. If these are directly subtracted and synthesized, the result is as follows Figure 10 As shown in (c), a -20mV voltage spike pulse remains.

[0122] In order to effectively reduce the voltage spike included in the output of the first DA converter, it is preferable to amplify the output of the second DA converter (the canceling voltage spike waveform obtained by combining the output of the second DA converter and the output of the third DA converter).

[0123] For example, in the above example, the output of the second DA converter and the output of the third DA converter are each amplified by 0.5 times. Alternatively, the signal obtained by combining the output of the second DA converter and the output of the third DA converter is also amplified by 0.5 times. Figure 10 As shown in (d), a 20mV offset voltage spike waveform is generated. Figure 10 The output of the first DA converter shown in (a) is Figure 10 The offset voltage spike pulse waveform shown in (d) can be synthesized as Figure 10 (e) shows that the voltage spike pulse is effectively cancelled.

[0124] In the above embodiment, if Figure 1 、 Figure 4 As shown in FIG, a configuration in which a plurality of synthesizers are used to cancel the voltage spike pulse contained in the output of the first DA converter is described, but the number of synthesizers may also be one. Figure 11 As shown, a DA converter 80 serving as a first DA converter, DA converters 81 to 83 serving as a second DA converter group, and DA converters 88 and 89 serving as a third DA converter group are provided. Outputs of the DA converters are added and combined by a combiner 90 .

[0125] There are three situations in which a large voltage spike is generated in the output of DA converter 80: when the most significant bit of the input data is inverted, when the most significant bit of the input data is "1" and the second most significant bit is inverted, and when the most significant bit of the input data is "0" and the second most significant bit is inverted. The magnitude of the voltage spike varies in each case. Furthermore, the magnitude (absolute value) of the voltage spike differs when bit inversion occurs as the input data to DA converter 80 increases versus when bit inversion occurs as the input data decreases.

[0126] For example, the magnitude of the voltage spike pulse generated in the output of the DA converter 80 is as shown in Table 1 below.

[0127]

Table 1

[0128]

[0129] Assuming that DA converters 81 to 83 also generate the same voltage spike pulse as DA converter 80, different amplification factors are set for DA converters 81 to 83, and the output of one of DA converters 81 to 83 is synthesized based on the inverted bit in the input data of DA converter 80. This can effectively reduce the voltage spike pulse generated in the output of DA converter 80.

[0130] When the most significant bit of the input data to DA converter 80 is 0 and the second most significant bit is inverted, control unit 60 outputs a signal to DA converter 81 with the most significant bit set to 1 and the second most significant bit inverted, and with increases and decreases that are opposite to the input data to DA converter 80. Furthermore, the output of DA converter 81 is multiplied by 0.67. This allows for the production of voltage spikes that cancel out voltage spikes in the output of DA converter 80.

[0131] For example, when the input data to DA converter 80 increases from "0011" to "0100," the magnitude of the voltage spike in the output of DA converter 80 becomes 20 mV. At this time, the input to DA converter 81 decreases from "1100" to "1011," and the magnitude of the voltage spike in the output, which has been multiplied by 0.67, becomes -20 mV (= -30 × 0.67), canceling out the voltage spike in the output of DA converter 80.

[0132] When the input data to DA converter 80 decreases from "0100" to "0011," the magnitude of the voltage spike in the output of DA converter 80 becomes -10 mV. At this time, the input to DA converter 81 increases from "1011" to "1100," and the magnitude of the voltage spike in the output, which has been multiplied by 0.67, becomes 10 mV (=15 × 0.67), canceling out the voltage spike in the output of DA converter 80.

[0133] When the most significant bit of the input data of DA converter 80 is inverted, control unit 60 outputs a signal to DA converter 82 with the most significant bit inverted and with increases and decreases opposite to the input data of DA converter 80. The amplification factor of the output of DA converter 82 is 1.

[0134] For example, when the input data to DA converter 80 increases from "0111" to "1000," the magnitude of the voltage spike in the output of DA converter 80 becomes 50 mV. At this time, the input to DA converter 82 decreases from "1000" to "0111," and the magnitude of the voltage spike in the output becomes -50 mV, canceling out the voltage spike in the output of DA converter 80.

[0135] When the input data to DA converter 80 decreases from "1000" to "0111," the magnitude of the voltage spike in the output of DA converter 80 becomes -50 mV. At this time, the input to DA converter 82 increases from "0111" to "1000," and the magnitude of the voltage spike in the output becomes 50 mV, canceling out the voltage spike in the output of DA converter 80.

[0136] When the most significant bit of the input data to DA converter 80 is 1 and the second most significant bit is inverted, control unit 60 outputs a signal to DA converter 83 with the most significant bit being 0 and the second most significant bit inverted, and with the increase and decrease being opposite to the input data to DA converter 80. Furthermore, the output of DA converter 83 is multiplied by 1.5. This allows for the production of voltage spikes that cancel out voltage spikes contained in the output of DA converter 80.

[0137] For example, if the input data to DA converter 80 decreases from "1100" to "1011," the magnitude of the voltage spike in the output of DA converter 80 becomes -30 mV. At this time, the input to DA converter 81 increases from "0011" to "0100," and the magnitude of the voltage spike in the output, which has been multiplied by 1.5, becomes 30 mV (= 20 × 1.5), canceling out the voltage spike in the output of DA converter 80.

[0138] When the input data to DA converter 80 increases from "1011" to "1100," the magnitude of the voltage spike in the output of DA converter 80 becomes 15 mV. At this time, the input to DA converter 81 decreases from "0100" to "0011," and the magnitude of the voltage spike in the output, which has been multiplied by 1.5, becomes -15 mV (= -10 × 1.5), canceling out the voltage spike in the output of DA converter 80.

[0139] In addition, one of the DA converters 88 and 89 is used to cancel the output displacement of the DA converters 81 to 83 , and the other is used to cancel the offset.

[0140] In this way, by using synthesizer 90 to add and synthesize the output of DA converter 80, the output of one of DA converters 81 to 83 selected based on the inverted bit of the input data of the first DA converter 80, and the outputs of DA converters 88 and 89, it is possible to reduce voltage spikes included in the output of DA converter 80.

[0141] Figure 11 The structure for canceling the voltage spike pulse in the inversion of the upper 1st to 2nd bits is shown, but in order to cancel the voltage spike pulse in the inversion of the upper 1st to 3rd bits, as shown in FIG. Figure 12 As shown, the configuration is such that DA converters 84 to 87 are added to the second DA converter group. The amplification factors of the outputs of DA converters 84 to 87 are appropriately set according to the magnitude of the voltage spike during inversion of the upper third bit.

[0142] In addition, the present invention is not limited to the above-mentioned embodiments as they are. During the implementation stage, the constituent elements can be deformed and concretized without departing from the scope of the present invention. In addition, various inventions can be formed by appropriately combining the multiple constituent elements disclosed in the above-mentioned embodiments. For example, some constituent elements can be deleted from all the constituent elements shown in the embodiments. Moreover, constituent elements of different embodiments can also be appropriately combined.

Claims

1. A waveform generating device, characterized in that: have: The first DA converter performs digital-to-analog conversion on the input data and outputs the result; a control unit configured to output a first signal having a command value based on the input data and a second signal having a command value such that a difference between the first signal and the command value becomes constant; a second DA converter, performing digital-to-analog conversion on the first signal and outputting the result; a third DA converter, performing digital-to-analog conversion on the second signal and outputting the result; as well as a synthesizer that synthesizes the output of the first DA converter, the output of the second DA converter, and the output of the third DA converter, When the value of a predetermined first upper bit of the input data is inverted, the control unit changes the command value of the first signal so as to invert the value of the first upper bit or a second upper bit different from the first upper bit.

2. The waveform generating device according to claim 1, wherein: The synthesizer includes a first subtractor and a second subtractor. The first subtractor subtracts the output of the third DA converter from the output of the second DA converter. The second subtractor subtracts the output of the first subtractor from the output of the first DA converter.

3. The waveform generating device according to claim 1, wherein: The instruction value of the first signal and the instruction value of the second signal differ by one least significant bit.

4. The waveform generating device according to claim 1, wherein: having a plurality of said second DA converters, The command values of the first signal input to the second DA converters have different inverted bits, or have the same inverted bits but different values of bits higher than the inverted bits.

5. The waveform generating device according to claim 4, characterized in that: The plurality of second DA converters amplify and output signals at different amplification factors.

6. A waveform generation method, characterized in that: It has the following processes: The process of using a first DA converter to perform digital-to-analog conversion on input data and output a voltage; a step of inputting a first signal to a second DA converter, performing digital-to-analog conversion, and outputting the converted signal, wherein the first signal has a command value based on the input data; as well as a step of inputting a second signal to a third DA converter, performing digital-to-analog conversion, and outputting the signal, wherein the second signal has a command value at which a difference from a command value of the first signal becomes constant; When the value of a predetermined first upper bit of the input data is inverted, the command value of the first signal is changed so as to invert the value of the first upper bit or a second upper bit different from the first upper bit. The output of the first DA converter, the output of the second DA converter, and the output of the third DA converter are synthesized to obtain a signal in which a voltage spike included in the output of the first DA converter is reduced.

7. The waveform generation method according to claim 6, characterized in that: subtracting the output of the third DA converter from the output of the second DA converter using a first subtractor, The output of the first subtractor is subtracted from the output of the first DA converter using a second subtractor to obtain a signal in which the voltage spike is reduced.

8. The waveform generation method according to claim 6, characterized in that: The instruction value of the first signal and the instruction value of the second signal differ by one least significant bit.

9. The waveform generation method according to claim 6, characterized in that: A first signal having a command value in which inverted bits are different or inverted bits are the same but values of bits higher than the inverted bits are different is input to each of the plurality of second DA converters, subjected to digital-to-analog conversion, and output.

10. The waveform generation method according to claim 9, characterized in that: The plurality of second DA converters amplify and output signals at different amplification factors.

11. A charged particle beam irradiation device, characterized in that: have: a releasing portion for releasing a charged particle beam; A workbench for placing substrates; a deflection control circuit comprising the waveform generating device according to claim 1 and outputting deflection data for deflecting the charged particle beam; a deflector for deflecting the charged particle beam according to the deflection data from the deflection control circuit; and The drawing unit draws a pattern on the substrate using the charged particle beam while moving a deflection position of the charged particle beam on the substrate.

12. The charged particle beam irradiation device according to claim 11, wherein The synthesizer includes a first subtractor and a second subtractor. The first subtractor subtracts the output of the third DA converter from the output of the second DA converter. The second subtractor subtracts the output of the first subtractor from the output of the first DA converter.

13. The charged particle beam irradiation device according to claim 11, wherein The instruction value of the first signal and the instruction value of the second signal differ by one least significant bit.

14. The charged particle beam irradiation device according to claim 11, wherein having a plurality of said second DA converters, The command values of the first signal input to the second DA converters have different inverted bits, or have the same inverted bits but different values of bits higher than the inverted bits.

15. The charged particle beam irradiation device according to claim 14, characterized in that The plurality of second DA converters amplify and output signals at different amplification factors.

16. A charged particle beam irradiation device, characterized in that: have: a releasing portion for releasing a charged particle beam; A workbench for placing substrates; a drawing unit including a deflector for deflecting the charged particle beam, and drawing a pattern on the substrate using the charged particle beam while moving the stage and moving a deflection position of the charged particle beam on the substrate to follow the movement of the stage; as well as a deflection control circuit that outputs deflection data for deflecting the charged particle beam to the deflector, The drawing unit moves the deflection position of the charged particle beam on the substrate so as to follow the movement of the stage using a tracking amplifier, and the tracking amplifier includes the waveform generating device according to claim 1 .

17. The charged particle beam irradiation device according to claim 16, wherein The synthesizer includes a first subtractor and a second subtractor. The first subtractor subtracts the output of the third DA converter from the output of the second DA converter. The second subtractor subtracts the output of the first subtractor from the output of the first DA converter.

18. The charged particle beam irradiation device according to claim 16, wherein The instruction value of the first signal and the instruction value of the second signal differ by one least significant bit.

19. The charged particle beam irradiation device according to claim 16, wherein having a plurality of said second DA converters, The command values of the first signal input to the second DA converters have different inverted bits, or have the same inverted bits but different values of bits higher than the inverted bits.

20. The charged particle beam irradiation device according to claim 19, wherein The plurality of second DA converters amplify and output signals at different amplification factors.

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