Method for wafer bonding and wafer bonding structure

Abstract

The present application provides a method for wafer bonding and a wafer bonding structure. The method for wafer bonding includes: providing a bonded bare wafer, the bonded bare wafer including a first surface; forming an initial layer on the first surface; forming a first groove in the initial layer and the bonded bare wafer as an initial mark, and the first groove does not penetrate the bonded bare wafer; forming a first oxide layer on the surface of the initial layer and in the first groove, and the top surface of the first oxide layer above the surface of the initial layer and in the first groove is coplanar; forming a bonding mark material layer on the surface of the first oxide layer; referring to the initial mark, etching the bonding mark material layer by a lithography process to form a first bonding mark, and the first bonding mark covers a part of the surface of the first oxide layer. The technical solution of the present application can improve the quality of wafer stacking and bonding and increase the yield.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, and particularly to a method for wafer bonding and a wafer bonding structure. Background Art

[0002] Three-dimensional integration technology (3DIC) is currently recognized as the preferred solution for continuously achieving miniaturization, high density, and multi-functionality beyond Moore's Law. Compared with traditional planar two-dimensional packaging technology, 3DIC technology vertically stacks and packages two or more layers of chips together, with advantages such as small volume, light weight, high integration, small signal delay, and low power consumption. At the same time, the three-dimensional stacked packaging technology can integrate different chips, including logic chips, memory chips, radio frequency chips, etc. into a system, greatly improving the system integration and opening up a broader development direction for semiconductor technology.

[0003] However, how to better improve the quality of wafer stacking and bonding and increase the yield rate remains an urgent problem to be solved. Summary of the Invention

[0004] The technical problem to be solved by this application is to improve the quality of wafer stacking and bonding and increase the yield rate.

[0005] To solve the above technical problem, this application provides a method for wafer bonding, including: providing a bonded bare wafer, the bonded bare wafer including a first surface; forming an initial layer on the first surface; forming a first groove in the initial layer and the bonded bare wafer as an initial mark, and the first groove does not penetrate the bonded bare wafer; forming a first oxide layer on the surface of the initial layer and in the first groove, and the top surface of the first oxide layer above the surface of the initial layer and in the first groove is coplanar; forming a bonding mark material layer on the surface of the first oxide layer; referring to the initial mark, etching the bonding mark material layer by a lithography process to form a first bonding mark, and the first bonding mark covers a part of the surface of the first oxide layer.

[0006] In an embodiment of this application, the process of etching the bonding mark material layer by a lithography process referring to the initial mark includes: forming a first photoresist on the surface of the bonding mark material layer; forming a first photomask above the first photoresist, the first photomask including a first bonding mark pattern and a first calibration mark, and the first calibration mark is aligned with the initial mark; using the first photomask as a mask, exposing and developing to form the first bonding mark.

[0007] In an embodiment of the present application, the method for wafer bonding further includes: providing a carrier wafer; sequentially forming a second oxide layer and a first nitride layer on the surfaces of the first oxide layer and the first bonding mark, and the bonded bare wafer further includes a second surface opposite to the first surface; bonding the carrier wafer to the surface of the first nitride layer; thinning the bonded bare wafer on one side of the second surface, and sequentially forming a third oxide layer and a second photoresist on the second surface; forming a second photomask above the second photoresist, the second photomask including a second bonding mark pattern and a second calibration mark, wherein the second calibration mark is aligned with the initial mark; exposing and developing to form a second groove in the third oxide layer, and the second groove serves as the second bonding mark.

[0008] In an embodiment of the present application, the carrier wafer includes: a carrier bare wafer; a fourth oxide layer located on the surface of the carrier bare wafer; a second nitride layer located on the surface of the fourth oxide layer; a fifth oxide layer located on the surface of the second nitride layer, serving as the bonding layer of the carrier wafer; a third groove located in the fifth oxide layer and the second nitride layer and not penetrating the second nitride layer.

[0009] In an embodiment of the present application, the thickness of the fourth oxide layer is 1.8 μm - 2.2 μm, the thickness of the second nitride layer is 280 nm - 320 nm, the thickness of the fifth oxide layer is 200 nm - 220 nm, the depth of the third groove is 280 nm - 300 nm, and the depth of the second groove is 430 nm - 470 nm.

[0010] In an embodiment of the present application, the method for wafer bonding further includes: providing a bottom wafer, the bottom wafer including a third bonding mark; aligning the second bonding mark and the third bonding mark, and bonding the bottom wafer to the surface of the third oxide layer; removing the carrier bare wafer and the fourth oxide layer to expose the second nitride layer as the bonding layer for subsequent bonding processes.

[0011] In an embodiment of the present application, the bottom wafer further includes: a bottom bare wafer; a sixth oxide layer located on the surface of the bottom bare wafer, and the third bonding mark is formed in the sixth oxide layer; a third nitride layer located on the surface of the sixth oxide layer and bonded to the third oxide layer.

[0012] In an embodiment of the present application, the materials of the first bonding mark and the third bonding mark include at least one of aluminum, copper, and tungsten.

[0013] In the embodiments of the present application, the materials of the initial layer, the first oxide layer, the second oxide layer, the third oxide layer, the fourth oxide layer, the fifth oxide layer, and the sixth oxide layer include silicon oxide, and the materials of the first nitride layer, the second nitride layer, and the third nitride layer include silicon nitride.

[0014] The technical solution of the present application further provides a wafer bonding structure, including: a bonded bare wafer including a first surface; an initial layer located on the first surface of the bonded bare wafer; a first groove, serving as an initial mark, located in the bonded bare wafer and the initial layer, and the first groove does not penetrate the bonded bare wafer; a first oxide layer located on the surface of the initial layer and in the first groove, and the top surfaces of the first oxide layer above the surface of the initial layer and in the first groove are coplanar; a first bonding mark located on the surface of a part of the first oxide layer.

[0015] In the embodiments of the present application, the first bonding mark does not cover the first groove.

[0016] In the embodiments of the present application, the depth of the first groove is 250 nm - 300 nm, and the thickness of the first bonding mark is 630 nm - 670 nm.

[0017] In the embodiments of the present application, the wafer bonding structure further includes: a second oxide layer located on the surfaces of the first oxide layer and the first bonding mark; a first nitride layer located on the surface of the second oxide layer; a fifth oxide layer located on the surface of the first nitride layer; a second nitride layer located on the surface of the fifth oxide layer, serving as the bonding layer of the wafer bonding structure; a third groove located in the fifth oxide layer and the second nitride layer, and not penetrating the second nitride layer.

[0018] In the embodiments of the present application, the bonded bare wafer further includes a second surface opposite to the first surface, and the wafer bonding structure further includes a third oxide layer located on the second surface, and a second groove is provided in the third oxide layer, and the second groove serves as a second bonding mark.

[0019] In the embodiments of the present application, the depth of the second groove is 430 nm - 470 nm, and the depth of the third groove is 280 nm - 300 nm.

[0020] In the embodiments of the present application, the wafer bonding structure further includes: a bottom bare wafer; a sixth oxide layer located on the surface of the bottom bare wafer, and a third bonding mark is provided in the sixth oxide layer, and the third bonding mark is aligned with the second bonding mark; a third nitride layer located on the surface of the sixth oxide layer, and bonded to the third oxide layer.

[0021] In the embodiments of the present application, the edges of the bonded bare wafer, the initial layer, the first oxide layer, the second oxide layer, the first nitride layer, the fifth oxide layer, the second nitride layer, and the third oxide layer have recessed portions after trimming.

[0022] In the embodiments of the present application, the materials of the first bonding mark and the third bonding mark include at least one of aluminum, copper, and tungsten.

[0023] In the embodiments of the present application, the materials of the initial layer, the first oxide layer, the second oxide layer, the third oxide layer, the fifth oxide layer, and the sixth oxide layer include silicon oxide, and the materials of the first nitride layer, the second nitride layer, and the third nitride layer include silicon nitride.

[0024] Compared with the prior art, the wafer bonding method and the wafer bonding structure of the technical solution of the present application have the following beneficial effects:

[0025] The wafer bonding method of the technical solution of the present application includes the step of making an initial mark. By forming an initial layer on the surface of the bonded bare wafer and forming a first groove in the initial layer and the bonded bare wafer, the first groove serves as an initial mark, which can not only be used as a calibration reference when making the front bonding mark, but also be used as a calibration reference when making the back bonding mark. At the same time, it shortens the calibration distance when making the back bonding mark, improves the recognition ability of the machine and the calibration accuracy of the bonding mark. The wafer bonding structure made by the wafer bonding method of the technical solution of the present application has a high bonding alignment accuracy, greatly improves the yield of the bonded product, and the manufacturing process is simple.

[0026] In the wafer bonding method of the technical solution of the present application, the carrier wafer used takes the second groove as the bonding mark. Compared with the metal bonding mark, it avoids the problems that the bonding mark cannot be removed or the surface topography is poor after removal, and at the same time reduces the manufacturing cost. Description of the Drawings

[0027] The following drawings detail the exemplary embodiments disclosed in the present application. Wherein the same reference numerals represent similar structures in several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of the present application. Embodiments in other ways may also achieve the inventive intent of the present application. It should be understood that the drawings are not drawn to scale. Among them:

[0028] Figures 1 to 4 It is a schematic structural diagram of each step of a wafer bonding method;

[0029] Figures 5 to 20 It is a schematic structural diagram of each step of the wafer bonding method of the embodiment of the present application. Detailed Implementation Modes

[0030] The following description provides specific application scenarios and requirements of the present application, aiming to enable those skilled in the art to manufacture and use the content of the present application. For those skilled in the art, various partial modifications to the disclosed embodiments are obvious, and the general principles defined here can be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the illustrated embodiments, but has the broadest scope consistent with the claims.

[0031] Currently, both the front and back sides of the stacked wafer in the multi-layer wafer stacking and bonding process need to be bonded, so bonding marks need to be fabricated on the front and back sides of the stacked wafer.

[0032] Reference Figures 1 to 3 , when fabricating the bonding marks on the front and back sides of the stacked wafer 10, first, a transition layer 20 and a metal layer 31 are sequentially deposited on the front side, then the metal layer 31 is etched to form a metal bonding mark 32, and then other film layers 40 are deposited on the surfaces of the transition layer 20 and the metal bonding mark 32 to complete the fabrication of the front bonding mark.

[0033] Reference Figure 4 , when fabricating the bonding mark on the back side of the stacked wafer 10, first, the stacked wafer 10 can be flipped so that the back side faces up, then the stacked wafer 10 is thinned, and other film layers 50 are deposited on the back side of the stacked wafer 10, and then the other film layers 50 are etched by a photolithography process to form the bonding mark on the back side.

[0034] However, it should be noted that when fabricating the bonding mark on the back side of the stacked wafer 10, the photomask 60 needs to be calibrated, and the calibration mark 61 on the photomask 60 needs to be aligned with the metal bonding mark 32 on the front side during calibration. Therefore, during exposure, it must be able to penetrate the thinned stacked wafer 10 and the film layers deposited on the front and back sides to reach the metal bonding mark 32. However, due to the relatively long penetration distance L, about 65 μm, it poses high requirements on the machine tool, resulting in poor alignment accuracy, affecting the alignment accuracy of subsequent bonding, and at the same time limiting the deposition thickness of the front film layer.

[0035] In view of this, the technical solution of the present application provides a wafer bonding method and a wafer bonding structure, by forming an initial layer on the surface of the bonding bare wafer and forming initial marks in the initial layer and the bonding bare wafer, the initial marks can provide a calibration reference for the fabrication of the front bonding mark and the back bonding mark, and at the same time can shorten the calibration distance when fabricating the back bonding mark, improve the recognition ability of the machine tool, and further improve the calibration accuracy of the bonding mark.

[0036] The method of wafer bonding for the technical solution of the present application will be described in detail below through specific embodiments and drawings.

[0037] An embodiment of the present application provides a method of wafer bonding, including:

[0038] Step S1: Provide a bonded bare wafer, the bonded bare wafer including a first surface;

[0039] Step S2: Form an initial layer on the first surface;

[0040] Step S3: Form a first groove in the initial layer and the bonded bare wafer as an initial mark;

[0041] Step S4: Form a first oxide layer on the surface of the initial layer and in the first groove, and the top surface of the first oxide layer above the surface of the initial layer and the first groove is coplanar;

[0042] Step S5: Form a bonding mark material layer on the surface of the first oxide layer;

[0043] Step S6: Referring to the initial mark, etch the bonding mark material layer by a lithography process to form a first bonding mark, the first bonding mark covering a part of the surface of the first oxide layer.

[0044] The bonded bare wafer has a first surface and a second surface. In the embodiment of the present application, the first surface serves as the front side of the bonded bare wafer, and the second surface serves as the back side of the bonded bare wafer.

[0045] Refer to Figure 5 , provide a bonded bare wafer 100, the bonded bare wafer 100 may be a silicon wafer to meet process compatibility, the bonded bare wafer 100 including a first surface. An initial layer 200 is formed on the first surface, the initial layer 200 being used to make an initial mark, and at the same time the initial layer 200 can serve as both a transition layer during lithography and a hard mask layer during lithography. The material of the initial layer 200 may include silicon oxide, or other materials suitable for deposition on the surface of the bonded bare wafer 100. The initial layer 200 may be formed by a thermal oxidation process in a furnace tube, or by a deposition process such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc. The thickness of the initial layer 200 may be between 5 nm and 15 nm.

[0046] Refer to Figure 6, a first groove 300 is formed in the initial layer 200 and the bonded bare wafer 100, and the first groove 300 does not penetrate through the bonded bare wafer 100, preventing the film layer material from contaminating the other side of the bonded bare wafer 100 through the first groove 300 when other film layers are formed on one side of the bonded bare wafer 100 subsequently. The process of forming the first groove 300 can be any conventional etching process, such as a wet etching process, a dry etching process, etc. The first groove 300 serves as an initial mark (zero mark). The depth of the first groove 300 affects the calibration distance when forming the bonding mark on the subsequent second surface (i.e., the back surface). If the first groove 300 is deeper, the calibration distance is smaller, but the first groove 300 should not be too deep. When it is too deep, a thicker photoresist is required for blocking and a longer etching time, increasing the cost and difficulty of the process. In the embodiment of the present application, the depth of the first groove 300 is 250 nm - 300 nm.

[0047] Reference Figure 7 , a first oxide layer 400 is formed on the surface of the initial layer 200 and in the first groove 300. The process of forming the first oxide layer 400 may include: depositing a first oxide layer material by using a process capable of depositing a film layer, such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc.; then planarizing the first oxide layer material to a target thickness through a polishing process such as physical mechanical polishing, chemical mechanical polishing, etc., and finally, the top surface of the first oxide layer 400 above the surface of the initial layer 200 and in the first groove 300 is coplanar or substantially coplanar. The material of the first oxide layer 400 may include silicon oxide. For example, the material of the first oxide layer 400 includes TEOS. The thickness of the first oxide layer 400 affects the curvature of the bonded wafer. The greater the thickness of the first oxide layer 400, the greater the curvature of the bonded wafer. During the bonding process, it is more difficult for the machine to grasp and fragmentation is likely to occur, which is not conducive to the production of bonding marks. The thickness of the first oxide layer 400 should not be too small either, otherwise it cannot ensure filling the first groove 300. In the embodiment of the present application, the thickness of the first oxide layer 400 on the surface of the initial layer 200 can be 1.8 μm - 2.2 μm.

[0048] Reference Figure 8, a bonding mark material layer 510 is formed on the surface of the first oxide layer 400. The bonding mark material layer 510 is used to fabricate a first bonding mark. The process for forming the bonding mark material layer 510 can be physical vapor deposition, chemical vapor deposition, atomic layer deposition, or other processes capable of depositing a film layer. The thickness of the bonding mark material layer 510 determines the thickness of the formed first bonding mark, thus directly affecting the bonding quality. If the thickness of the bonding mark material layer 510 is too small, the thickness of the formed first bonding mark will be too small, making it difficult to identify during bonding, resulting in a decrease in the alignment accuracy during bonding. At the same time, the thickness of the bonding mark material layer 510 should not be too large either, as the improvement in the machine's recognition ability is not obvious, but instead increases the manufacturing cost. In the embodiment of the present application, the thickness of the bonding mark material layer 510 is 630 nm - 670 nm. The bonding mark material 510 can include various metals. In some embodiments, the bonding mark material 510 includes at least one of copper, aluminum, and tungsten.

[0049] Next, referring to the initial mark, the bonding mark material layer is etched using a photolithography process to form a first bonding mark.

[0050] Referring to Figure 8 and Figure 9 , a first photoresist (not shown) is formed on the surface of the bonding mark material layer 510; a first photomask 610 is formed above the first photoresist. The first photomask 610 includes a first bonding mark pattern 611 and a first calibration mark 612. Among them, the first bonding mark pattern 611 determines the pattern of the formed first bonding mark, and the first calibration mark 612 is used to calibrate the position of the first photomask 610, and the first calibration mark 612 is aligned with the initial mark 300. The first bonding mark pattern 611 and the first calibration mark 612 are distributed at different positions on the first photomask 610 to ensure that the formed first bonding mark 520 does not cover the initial mark 300. Due to the presence of the initial mark 300, the position of the first photomask 610 can be accurately calibrated, thereby improving the manufacturing accuracy of the first bonding mark and further improving the accuracy during wafer bonding. Then, using the first photomask 610 as a mask, the first bonding mark 520 is formed by exposure and development, and the first bonding mark 520 covers a part of the surface of the first oxide layer 400.

[0051] Referring to Figure 10, the method for wafer bonding according to the embodiments of the present application may further include: sequentially forming a second oxide layer 700 and a first nitride layer 800 on the surfaces of the first oxide layer 400 and the first bonding mark 520. The thickness of the second oxide layer 700 on the surface of the first bonding mark 520 may be 1.2 μm - 2 μm, and the thickness of the first nitride layer 800 may be 45 nm - 55 nm. The material of the second oxide layer 700 may include silicon oxide, and the material of the first nitride layer 800 may include silicon nitride. The process for forming the second oxide layer 700 and the first nitride layer 800 may be physical vapor deposition, chemical vapor deposition, atomic layer deposition, etc. Thus, the bonded wafer B is formed.

[0052] Reference Figure 11 , in some embodiments, the bonded wafer B may also be trimmed to remove part of the first nitride layer 800, the second oxide layer 700, the first oxide layer 400, the initial layer 200, and part of the bonded bare wafer 100 to form a recess O. Trimming the bonded wafer B can remove the defects caused during the formation of the first bonding mark 520 and can also eliminate stress.

[0053] Reference Figure 12 , the embodiments of the present application also provide a carrier wafer A, including: a carrier bare wafer 1000; a fourth oxide layer 2000 located on the surface of the carrier bare wafer 1000; a second nitride layer 3000 located on the surface of the fourth oxide layer 2000; a fifth oxide layer 4000 located on the surface of the second nitride layer 3000, which is the bonding layer of the carrier wafer A; and a third groove 5000 located in the fifth oxide layer 4000 and the second nitride layer 3000 and not penetrating through the second nitride layer 3000. Wherein, the materials of the fourth oxide layer 2000 and the fifth oxide layer 4000 may include silicon oxide, such as TEOS, and the material of the second nitride layer 3000 may include silicon nitride.

[0054] The embodiments of the present application form a three-layer structure of oxide layer / nitride layer / oxide layer on the surface of the carrier bare wafer 1000. When the incident light source of the machine table irradiates the second nitride layer 3000, the fourth oxide layer 2000, and the fifth oxide layer 4000, the obtained reflected light has different intensities, forming a large color difference. Therefore, the machine table can clearly display the pattern of the bonding mark. At the same time, since the fourth oxide layer 2000, the fifth oxide layer 4000, and the second nitride layer 3000 have opposite stresses, the second nitride layer 3000 can play a role in controlling the curvature of the carrier wafer A.

[0055] The third groove 5000 serves as a bonding mark for the carrier wafer A. Compared with the metal marks in the prior art, it can avoid the problems that the bonding marks cannot be completely removed or the surface topography after removal varies greatly. Moreover, the metal deposition process is omitted, significantly reducing the manufacturing cost.

[0056] In the embodiment of the present application, the thickness of the fourth oxide layer 2000 is controlled to be 1.8 μm - 2.2 μm, the thickness of the second nitride layer 3000 is 280 nm - 320 nm, the thickness of the fifth oxide layer 4000 is 200 nm - 220 nm, and the depth of the third groove 5000 is 280 nm - 300 nm, so as to balance the requirements for the clarity of the bonding mark, the curvature of the carrier wafer, and the overall manufacturing process.

[0057] Reference Figure 13 and Figure 14 According to [references], the method for wafer bonding in the embodiment of the present application further includes: bonding the carrier wafer A to the surface of the first nitride layer 800 of the bonding wafer B. After bonding, the carrier wafer A is on top and the bonding wafer B is at the bottom. Therefore, before fabricating the bonding mark (i.e., the second bonding mark) on the back surface of the bonding wafer B, a wafer flipping operation is required to make the carrier wafer A at the bottom and the bonding wafer B on top. Then, the bonded bare wafer 100 is thinned to a target thickness on one side of the second surface, and the target thickness is determined according to the actual situation.

[0058] Reference Figure 15 According to [references], a third oxide layer 900 and a second photoresist (not shown) are sequentially formed on the second surface. The material of the third oxide layer 900 may include silicon oxide. A second photomask 620 is formed above the second photoresist. The second photomask 620 includes a second bonding mark pattern 622 and a second calibration mark 621. The second bonding mark pattern 622 and the second calibration mark 621 are distributed at different positions on the second photomask 620. Among them, the second bonding mark pattern 622 determines the pattern of the formed second bonding mark, and the second calibration mark 621 is used for position calibration when placing the second photomask 620. The second calibration mark 621 is aligned with the initial mark 300. Since the distance L1 from the initial mark 300 to the second photomask 620 is relatively small, being 50 μm - 55 μm, which is much smaller than the penetration distance L in the prior art, the calibration distance is shortened, improving the calibration accuracy of the bonding mark.

[0059] Reference Figure 16, perform exposure and development to form a second groove 910 in the third oxide layer 900, and the second groove 910 serves as a second bonding mark. The depth of the second groove 910 affects the bonding quality in the next step. The deeper the second groove 910 is, the easier it is to be recognized during bonding. However, the depth of the second groove 910 should not be too large because when the depth of the second groove 910 reaches a certain level, the recognition ability of the machine platform no longer has a significant improvement, but the manufacturing cost is increased. In the embodiment of the present application, the depth of the second groove 910 is 430nm - 470nm.

[0060] Reference Figure 17 , after forming the second bonding mark, the carrier wafer A can also be trimmed so that the widths of the fifth oxide layer 4000, the second nitride layer 3000, the fourth oxide layer 2000, and a part of the carrier bare wafer 1000 are equal to those of the trimmed bonding wafer B.

[0061] Reference Figure 18 , the embodiment of the present application further provides a bottom wafer C, and the bottom wafer C includes a bottom bare wafer 10; a sixth oxide layer 20 located on the surface of the bottom bare wafer 10, a third bonding mark 30 is formed in the sixth oxide layer 20, the material of the sixth oxide layer 20 may include silicon oxide, and the material of the third bonding mark 30 may include at least one of aluminum, copper, and tungsten; a third nitride layer 40 located on the surface of the sixth oxide layer 20 and used for bonding with the third oxide layer 900, and the material of the third nitride layer 40 may include silicon nitride.

[0062] Reference Figure 19 and Figure 20 , the wafer bonding method of the embodiment of the present application further includes: aligning the second bonding mark 910 and the third bonding mark 30, and bonding the bottom wafer C on the surface of the third oxide layer 900. After bonding, the bottom wafer C is at the bottom, and the bonding wafer B and the carrier wafer A are on the top. Then, the carrier bare wafer 1000 and the fourth oxide layer 2000 are removed to expose the second nitride layer 3000 as the bonding layer for the subsequent bonding process. The method for removing the carrier bare wafer 1000 and the fourth oxide layer 2000 may include mechanical grinding and wet etching processes.

[0063] Reference Figure 9, embodiments of the present application also provide a wafer bonding structure, including: a bonded bare wafer 100, including a first surface; an initial layer 200, located on the first surface of the bonded bare wafer 100; a first groove 300, serving as an initial mark, located in the bonded bare wafer 100 and the initial layer 200, and the first groove 300 does not penetrate through the bonded bare wafer 100; a first oxide layer 400, located on the surface of the initial layer 200 and in the first groove 300, and the top surface of the first oxide layer 400 above the surface of the initial layer 200 and the first groove 300 is coplanar; a first bonding mark 520, located on the surface of a part of the first oxide layer 400, and the first bonding mark 520 does not cover the first groove 300. Wherein the materials of the initial layer 200 and the first oxide layer 400 may include silicon oxide, and the material of the first bonding mark 520 includes at least one of aluminum, copper, and tungsten. The depth of the first groove 300 is 250 nm - 300 nm, and the thickness of the first bonding mark 520 is 630 nm - 670 nm.

[0064] Reference Figure 20 , in some embodiments, the wafer bonding structure may further include: a second oxide layer 700, located on the surfaces of the first oxide layer 400 and the first bonding mark 520; a first nitride layer 800, located on the surface of the second oxide layer 700; a fifth oxide layer 4000, located on the surface of the first nitride layer 800; a second nitride layer 3000, located on the surface of the fifth oxide layer 4000, serving as a bonding layer of the wafer bonding structure; a third groove 5000, located in the fifth oxide layer 4000 and the second nitride layer 3000, and does not penetrate through the second nitride layer 3000, and the depth of the third groove may be 280 nm - 300 nm. The materials of the second oxide layer 700 and the fifth oxide layer 4000 may include silicon oxide, and the materials of the first nitride layer 800 and the second nitride layer 3000 may include silicon nitride.

[0065] In some embodiments, the bonded bare wafer further includes a second surface opposite to the first surface, and the wafer bonding structure further includes a third oxide layer 900 located on the second surface. The material of the third oxide layer 900 may include silicon oxide, and the third oxide layer 900 has a second groove 910, and the depth of the second groove may be 430 nm - 470 nm, and the second groove 910 serves as a second bonding mark.

[0066] Continue to refer to Figure 20, the wafer bonding structure may further include: a bottom bare wafer 10; a sixth oxide layer 20 located on the surface of the bottom bare wafer 10, the sixth oxide layer 20 having a third bonding mark 30, the material of the sixth oxide layer 20 may include silicon oxide, and the material of the third bonding mark includes at least one of aluminum, copper, and tungsten, and the third bonding mark 30 is aligned with the second bonding mark 910; a third nitride layer 40 located on the surface of the sixth oxide layer 20 and bonded to the third oxide layer 900, and the material of the third nitride layer 40 may include silicon nitride.

[0067] Edges of the bonded bare wafer 100, the initial layer 200, the first oxide layer 400, the second oxide layer 700, the first nitride layer 800, the fifth oxide layer 4000, the second nitride layer 3000, and the third oxide layer 900 have trimmed recesses.

[0068] In summary, after reading the content of this application, those skilled in the art can understand that the foregoing application content may be presented only by way of example and may not be restrictive. Although not explicitly stated here, those skilled in the art can understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0069] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may also be intermediate elements.

[0070] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or there may also be intermediate elements. In contrast, the term "directly" means without intermediate elements. It should also be understood that the terms "comprise", "comprising", "include", or "including", when used in this application document, indicate the presence of the recited features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their groups.

[0071] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be referred to as a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or the same reference designators represent the same elements throughout the specification.

[0072] In addition, the present application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the shapes shown due to, for example, manufacturing techniques and / or tolerances are foreseeable. Thus, the exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but should include deviations in the shapes caused by, for example, manufacturing. For example, an etched region shown as rectangular will typically have rounded or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shape of the regions of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for wafer bonding, characterized in that, Comprising: Providing a bonded bare wafer, the bonded bare wafer including a first surface; Forming an initial layer on the first surface; Forming a first groove in the initial layer and the bonded bare wafer as an initial mark, and the first groove does not penetrate the bonded bare wafer; Forming a first oxide layer on the surface of the initial layer and in the first groove, and the top surface of the first oxide layer above the surface of the initial layer and the first groove is coplanar; Forming a bonding mark material layer on the surface of the first oxide layer; Referring to the initial mark, etching the bonding mark material layer by a photolithography process to form a first bonding mark, the first bonding mark covering a part of the surface of the first oxide layer; Providing a carrier wafer, the carrier wafer including: a carrier bare wafer; a fourth oxide layer located on the surface of the carrier bare wafer; a second nitride layer located on the surface of the fourth oxide layer; a fifth oxide layer located on the surface of the second nitride layer, being the bonding layer of the carrier wafer; a third groove located in the fifth oxide layer and the second nitride layer and not penetrating the second nitride layer; Sequentially forming a second oxide layer and a first nitride layer on the surface of the first oxide layer and the first bonding mark, the bonded bare wafer further including a second surface opposite to the first surface; Bonding the carrier wafer to the surface of the first nitride layer; Thinning the bonded bare wafer on one side of the second surface and sequentially forming a third oxide layer and a second photoresist on the second surface; Forming a second photomask above the second photoresist, the second photomask including a second bonding mark pattern and a second calibration mark, wherein the second calibration mark is aligned with the initial mark; Exposing and developing to form a second groove in the third oxide layer, the second groove serving as a second bonding mark.

2. The method for wafer bonding according to claim 1, characterized in that, The process of etching the bonding mark material layer by a photolithography process with reference to the initial mark includes: Forming a first photoresist on the surface of the bonding mark material layer; Forming a first photomask above the first photoresist, the first photomask including a first bonding mark pattern and a first calibration mark, and the first calibration mark is aligned with the initial mark; Using the first photomask as a mask, exposing and developing to form the first bonding mark.

3. The method for wafer bonding according to claim 1, wherein The thickness of the fourth oxide layer is 1.8 μm - 2.2 μm, the thickness of the second nitride layer is 280 nm - 320 nm, the thickness of the fifth oxide layer is 200 nm - 220 nm, the depth of the third groove is 280 nm - 300 nm, and the depth of the second groove is 430 nm - 470 nm.

4. The method for wafer bonding according to claim 1, characterized in that, Further comprising: Providing a bottom wafer, the bottom wafer including a third bonding mark; Aligning the second bonding mark and the third bonding mark, and bonding the bottom wafer to the surface of the third oxide layer; Removing the carrier bare wafer and the fourth oxide layer to expose the second nitride layer as the bonding layer for subsequent bonding processes.

5. The method for wafer bonding according to claim 4, wherein The bottom wafer further includes: A bottom bare wafer; A sixth oxide layer located on the surface of the bottom bare wafer, and the third bonding mark is formed in the sixth oxide layer; The third nitride layer is located on the surface of the sixth oxide layer and is bonded to the third oxide layer.

6. The method for wafer bonding according to claim 5, characterized in that, The materials of the first bonding mark and the third bonding mark include at least one of aluminum, copper, and tungsten.

7. The method for wafer bonding according to claim 5, wherein, The materials of the initial layer, the first oxide layer, the second oxide layer, the third oxide layer, the fourth oxide layer, the fifth oxide layer, and the sixth oxide layer include silicon oxide, and the materials of the first nitride layer, the second nitride layer, and the third nitride layer include silicon nitride.

8. A wafer bonding structure, characterized in that, Comprising: A bonded bare wafer including a first surface; An initial layer located on the first surface of the bonded bare wafer; A first groove, serving as an initial mark, is located in the bonded bare wafer and the initial layer, and the first groove does not penetrate the bonded bare wafer; A first oxide layer is located on the surface of the initial layer and in the first groove, and the top surfaces of the first oxide layer above the surface of the initial layer and in the first groove are coplanar; A first bonding mark is located on the surface of a part of the first oxide layer; A second oxide layer is located on the surfaces of the first oxide layer and the first bonding mark; A first nitride layer is located on the surface of the second oxide layer; A fifth oxide layer is located on the surface of the first nitride layer; A second nitride layer is located on the surface of the fifth oxide layer and serves as a bonding layer of the wafer bonding structure; A third groove is located in the fifth oxide layer and the second nitride layer and does not penetrate the second nitride layer.

9. The wafer bonding structure according to claim 8, wherein, The first bonding mark does not cover the first groove.

10. The wafer bonding structure according to claim 8, wherein, The depth of the first groove is 250 nm - 300 nm, and the thickness of the first bonding mark is 630 nm - 670 nm.

11. The wafer bonding structure according to claim 8, wherein, The bonded bare wafer further includes a second surface opposite to the first surface, the wafer bonding structure further includes a third oxide layer located on the second surface, and a second groove is provided in the third oxide layer, and the second groove serves as a second bonding mark.

12. The wafer bonding structure according to claim 11, wherein, The depth of the second groove is 430 nm - 470 nm, and the depth of the third groove is 280 nm - 300 nm.

13. The wafer bonding structure according to claim 11, wherein, Further comprising: A bottom bare wafer; A sixth oxide layer is located on the surface of the bottom bare wafer, and a third bonding mark is provided in the sixth oxide layer, and the third bonding mark is aligned with the second bonding mark; The third nitride layer is located on the surface of the sixth oxide layer and is bonded to the third oxide layer.

14. The wafer bonding structure according to claim 13, wherein The edges of the bonded bare wafer, the initial layer, the first oxide layer, the second oxide layer, the first nitride layer, the fifth oxide layer, the second nitride layer, and the third oxide layer have trimmed recesses.

15. The wafer bonding structure according to claim 13, wherein The materials of the first bonding mark and the third bonding mark include at least one of aluminum, copper, and tungsten.

16. The wafer bonding structure according to claim 13, wherein The materials of the initial layer, the first oxide layer, the second oxide layer, the third oxide layer, the fifth oxide layer, and the sixth oxide layer include silicon oxide, and the materials of the first nitride layer, the second nitride layer, and the third nitride layer include silicon nitride.

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