Method and apparatus for synchronizing two systems

Abstract

An apparatus (20) and method for synchronizing a triggered system (system B) to a triggering system (system A) by tracking the timing of rising and falling edges of a clock signal (CLK_IN) at the triggered system and using the tracked timing values ​​(from within a recorder 27 of a counter 22) to perform a phase shift adjustment (25: setting) on ​​a time base (CLK_IN at the output of 28) at the triggered system.

Description

Background Art

[0001] In many applications, there are interactive systems that run on independent time bases (e.g., system clocks) that control the timing of their operations (e.g., start, stop, wait, etc.). In such applications, a common time base for these systems controls the independent time bases to ensure that their operations are synchronized with each other. Examples of such applications are touch and stylus sensing chips that together control large or foldable touch screens, or networked devices that communicate with each other. Summary of the Invention

[0002] This Summary is provided to introduce a selection of concepts in a simplified form that are further described in the Detailed Description below. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. The claimed subject matter is also not limited to implementations that solve any or all of the disadvantages noted herein.

[0003] In some embodiments, the present disclosure relates to an apparatus for synchronizing a counter to an input trigger signal, the apparatus comprising a data acquisition module (recorder circuit) for sampling and recording a value of the counter in response to detecting a rising edge and / or a falling edge of the input trigger signal, wherein the sampling is performed at a rising edge and a falling edge of a common clock signal provided to the counter and the data acquisition module; and a control circuit for reading the recorded value and calculating at least one of an offset and a configurable delay of the counter based on the recorded value and a predetermined collected value.

[0004] According to another aspect, a method of synchronizing a counter to an input trigger signal is provided, the method comprising sampling and recording a value of the counter in response to detecting a rising edge and / or a falling edge of the input trigger signal, wherein the sampling is performed at a rising edge and a falling edge of a common clock signal provided to the counter; and calculating at least one of an offset and a configurable delay of the counter based on the recorded value and a predetermined collected value.

[0005] Unless otherwise defined, all technical and / or scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. Although methods, components, and signals similar or equivalent to those described herein can be used to practice or test embodiments of the present disclosure, example methods and / or components and / or signals are described below. In addition, the components, signals, methods, and examples are illustrative only and are not intended to be necessarily limiting. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] To assist in understanding the present disclosure and to show how these embodiments may be practiced, reference is made to the accompanying drawings, by way of example only, in which:

[0007] Figure 1 is a schematic block diagram of an example of two interactive systems operating on the basis of a common clock signal,

[0008] Figure 2 is a schematic block diagram of an example of a conventional method for synchronizing two interactive systems operating on the basis of a common clock signal,

[0009] Figure 3 is a schematic diagram explaining the uncertain nature of synchronization of two systems operating on the basis of a common clock signal using examples of waveforms of a trigger signal and a related clock signal.

[0010] Figure 4 is a schematic block diagram of an example system with enhanced synchronization for improved accuracy,

[0011] Figure 5 This diagram uses the waveform of a common clock signal and four regions to explain the uncertain nature of synchronization.

[0012] Figure 6 is a schematic flow chart of an example of an enhanced synchronization procedure with improved accuracy,

[0013] Figure 7 is a first part of a schematic flow chart of an example of a procedure for determining a counter offset and a configurable delay,

[0014] Figure 8 is a second part of a schematic flow chart of an example of a procedure for determining a counter offset and a configurable delay,

[0015] Figure 9 is a diagram of an example of a histogram of the resulting inaccuracy between two systems after synchronization with longer hold and setup times, and

[0016] Figure 10 is a diagram of an example of a histogram of the resulting inaccuracy between two systems after synchronization with shorter hold and setup times. DETAILED DESCRIPTION

[0017] The present disclosure relates to improved synchronization of the time bases of two or more systems with each other with a higher accuracy of less than one clock cycle. In various examples, the accuracy can range from one quarter to one eighth of a clock cycle of the time base. Conventional synchronization methods can synchronize two systems with a maximum accuracy of one clock cycle of the time base.

[0018] Figure 11 is a schematic block diagram of an example of two interactive systems A10 and B20 operating on a common clock signal CLK_IN (clock input) generated by a common clock source (e.g., a clock generator) 30. The two systems A10 and B20 can be implemented as electronic circuits that are implemented on different parts of an integrated circuit or in different integrated circuits. In an example, the common clock signal CLK_IN can be used as a common time base for the two systems A10 and B20 to control their independent time bases to ensure that their operations are synchronized with each other. Examples of such systems can be touch and touch sensing chips that together control a large or foldable touch screen, or networked devices that communicate with each other, or any other type of collaborative or interactive system that needs to be synchronized for proper operation.

[0019] Note that for simplicity, Figure 1 and subsequently Figure 2 and Figure 4 Only those system components useful for explaining the specific example operations of the example embodiments are shown. In addition, unless otherwise specified, components or signals with the same reference numerals have the same or similar functions and / or structures and may be described only once in this disclosure.

[0020] In an example, the common clock signal may be in the form of a square wave with a 50% duty cycle and a fixed constant frequency. The circuits of the two systems A10 and B20 synchronized using the clock signal CLK_IN may become active at the rising edge, the falling edge, or, in the case of double data rate (DDR), at both the rising and falling edges of the clock cycle.

[0021] In an example, the common clock signal CLK_IN or a clock signal CLK_IN derived from the common clock can be gated, i.e., combined with a control signal (not shown) that enables or disables the clock signal CLK_IN, e.g., for a portion of the circuitry of each system. The time base of the common clock source 30 can constantly run at a relatively slow speed compared to the faster internal clock rate ("fast clock") available in each of the systems 10, 20.

[0022] In addition, each of systems 10 and 20 may include a phase-locked loop (PLL) circuit 14 or 24 that generates a higher frequency based on a common clock signal CLK_IN for internal operations that require a higher clock rate (e.g., a fast clock), such as an internal central processing unit (CPU, not shown). PLL circuits 14 and 24 may be control circuits that generate a fast clock with a phase related to the phase of the input clock signal CLK_IN. Several different types of circuits can be used to implement PLL circuits 14 and 24. In one example, a simple option may be an electronic circuit consisting of a variable frequency oscillator and a phase detector in a feedback loop. The oscillator generates a periodic signal, and the phase detector compares the phase of this signal with the phase of the input periodic signal, adjusting the oscillator to maintain phase matching. Keeping the input and output phases locked also means keeping the input and output frequencies the same. Therefore, in addition to synchronizing the fast clock and the common clock signal CLK_IN, PLL circuits 14 and 24 can track the input frequency of the common clock signal CLK_IN, or they can generate frequencies that are multiples of this input frequency.

[0023] In an example, the PLL circuits 14, 24 can be frequently turned off / on to save power, so that the fast clock can be temporarily turned off for power saving considerations. Thus, power can be saved by effectively turning off parts of the digital circuits of the systems 10 and 20 when not in use.

[0024] In an example, the common clock source 30 may include an electronic oscillator (circuit) that generates a common clock signal CLK_IN, which may range from a simple symmetrical square wave to a more complex arrangement. The basic parts of the clock source 30 may be a resonant circuit and an amplifier. The resonant circuit may be a quartz piezoelectric oscillator, but a simpler resonant circuit or even a resistor and capacitor (RC) circuit may also be used. The amplifier circuit may be used to invert the signal from the oscillator and feed a portion back into the oscillator to maintain oscillation. In an example, the common clock source 30 may have an additional part for modifying the base clock signal. As an example, the common clock source 30 may include logic for converting a 50% duty cycle (typical for the original oscillator) into a different duty cycle.

[0025] In an example, other optional portions of the common clock source 30 may include a hardware and / or software implemented frequency divider or clock multiplier portion. Additionally, a programmable clock generator may allow the numbers used in the frequency divider or multiplier to be changed, thereby allowing any of a variety of output frequencies to be selected without modifying the hardware.

[0026] Figure 1The two systems 10, 20 share a common clock source 30, for example by having one of the two systems 10, 20 (e.g., system A 10) drive the CLK_IN input of the other system (e.g., system B 20), or by having the common clock source 30 drive the two systems 10, 20, as shown in FIG. Figure 1 However, due to propagation delays in the entire clock path within and / or between systems 10, 20 and / or from the common clock source 30 to each system in the systems 10, 20, there is an unknown phase shift between the two CLK_IN domains (i.e., they are frequency aligned but not phase aligned). Figure 1 As indicated in , the unknown phase shift may be caused by respective unknown delays A and B between the common clock source 30 and the respective CLK_IN inputs of the two systems 10 , 20 .

[0027] Furthermore, in the example, in each of the two systems 10, 20, a respective counter 12, 22 is provided that accumulates the number of clock events of the respective clock signal CLK_IN to provide a time signal (e.g., a timestamp) as a time base that must be calibrated very accurately. Throughout this disclosure, the time base of each of the two systems 10, 20 will therefore be referred to as a "counter" 12, 22.

[0028] In an example, the counters 12 and 22 may store the number of times a particular event has occurred (i.e., a clock cycle or edge of the input clock signal CLK_IN). The counter may be implemented as a sequential digital logic circuit having an input line for the clock signal CLK_IN and a plurality of output lines. The value on the output line may represent a number in a binary or binary coded digital (BCD) numbering system. Each pulse or pulse edge applied to the clock input increments or decrements the number in the counter. More specifically, in an example, the circuitry of the counters 12 and 22 may be composed of a plurality of cascade-connected flip-flops. In an example, the counters 12 and 22 may be manufactured as separate integrated circuits or may be incorporated as part of a larger integrated circuit. In other examples, the counters 12 and 22 may be implemented by corresponding processor circuits that are controlled via a software program that implements the counter functionality.

[0029] In an example, the counters 12, 22 may include some form of amplifier, filtering and shaping circuitry at the input.Digital signal processing (DSP) techniques, sensitivity control and hysteresis are other techniques that may be applied to improve the performance of the counters 12, 22.

[0030] like Figure 1As shown, the internal clock signal CLK_IN of each of the two systems 10 and 20 is provided to the corresponding counter 12 and 22, so that the corresponding counter 12 and 22 of each system operates based on the CLK_IN domain. However, in the example, each of the two systems 10 and 20 can be powered on independently, and their startup times can be different, so that each of the corresponding counters 12 and 22 can start counting at different times.

[0031] Furthermore, the interaction between the two systems 10, 20 may be based on exchanging input / output (IO) signals 100 and / or communication signals 110 via corresponding connection channels or lines. In an example, such communication signals 110 may be based on Bluetooth, Wi-Fi, near field communication (NFC), etc., wherein the corresponding communication unit (not shown) may include a transceiver for transmitting or receiving communication commands, pairing requests, etc. from the communication unit of the corresponding other system. Additionally or alternatively, the communication between the two systems 10, 20 may be based on wired transmission, such as a universal serial bus (USB) or Ethernet connection or other wired connection system.

[0032] The systems 10, 20 may further include a power source (not shown), which may include batteries for powering the various components of the systems 10, 20. The batteries may be rechargeable, replaceable, disposable, or the like.

[0033] Figure 2 1 is a schematic block diagram of an example of a method for synchronizing two interactive systems A 10 and B 20 operating on a common clock signal CLK_IN. According to the method, one of the two systems 10, 20 (e.g., system A 10, i.e., the triggering system) sends a "trigger" signal T to the other of the two systems 10, 20 (e.g., system B 20, i.e., the triggered system) when its counter (e.g., counter 12) reaches a certain predefined count value, for example, on an I / O line. Throughout this disclosure, this count value is labeled with the letter "Y."

[0034] In an example, the trigger signal T can be a pulse-shaped signal (wherein a pulse indicates a trigger event) or a binary signal with two states (wherein a transition from one state to another indicates a trigger event) or a predefined signal pattern or value (wherein the pattern or value indicates a trigger event).

[0035] When the triggered system (e.g., system B 20) detects a trigger event of the trigger signal T, the triggered system may control the counter 22 to load a value of Y+Δ (where the value of Δ depends on the transmission delay of the trigger signal T and the optional internal delay of the trigger signal T path (e.g., how many sampling triggers are in the trigger signal path)).

[0036] However, due to the fact that the two counters 12, 22 of the two systems 10, 20 operate on phase-unaligned clocks, the triggered system (e.g. system B 20) may include an initial synchronization circuit (Sync) 26 (synchronizer) for the trigger signal T, shifting or adapting the trigger signal to the timing of its own clock signal CLK_IN, i.e. its own CLK_IN domain.

[0037] A synchronization circuit 26 can be provided at both systems 10 and 20 and can be used as an interface to ensure that the trigger signal T from the trigger system is reliably interpreted by the triggered system. Thus, whenever there is a transfer of the trigger signal T between two systems 10 and 20 operating at the same frequency but with different phases, the synchronization circuit 26 serves as an interface. In an example, the synchronization circuit 26 can use a flip-flop circuit that provides a single or double latency delay at its output. For example, the synchronization circuit 26 can have a delay of anywhere between two and three cycles of the clock signal CLK_IN.

[0038] However, the synchronization circuit 26 adds a delay of an uncertain fraction of one CLK_IN cycle because it is unknown when the next rising edge of the clock signal CLK_IN will occur after the trigger signal T (e.g., the trigger event) is detected. As a result, the inaccuracy of the synchronization process can be as much as a single cycle of the clock signal CLK_IN. Due to the uncertain nature of this inherent inaccuracy, it is impossible to compensate for it by hardware or software based on a predetermined fixed compensation value that will always be valid.

[0039] Figure 3 1 is a schematic diagram explaining the above-mentioned uncertainty characteristics of synchronizing two systems using examples of the waveforms of the trigger signal T (the second waveform from the top) and the related clock signal.

[0040] The trigger system (system A) operates on the basis of the first clock signal CLK_IN (the uppermost waveform). In addition, Figure 3 Three options I to III are shown for example timing of the second clock signal CLK_IN at the triggered system (system B), where the next rising edge of the second clock signal CLK_IN relative to the rising edge of the trigger signal T (trigger event) can be delayed by less than half a clock cycle (option I, middle waveform), more than half a clock cycle (option II, second to last waveform from the top), and close to but less than one clock cycle (option III, bottom waveform).

[0041] If you can Figure 3As known in the prior art, when the counter 12 of the triggering system (system A) 10 has reached the trigger value "Y", the trigger signal T is activated, for example by changing its binary state and creating a rising edge, and vice versa. By the next rising edge of the clock signal CLK_IN at the triggered system (system B) 20, the adjusted or compensated value of Y+Δ will be latched into the counter 22 at the triggered system 20 after a deterministic delay of, for example, two clock cycles (time period) of the clock signal CLK_IN caused by the synchronization circuit 26.

[0042] Thus, the total delay until the compensated value of Y+Δ is latched at the counter 22 of the triggered system 20 depends on the initial uncertainty delay caused by the phase difference between the first clock signal CLK_IN of the first system 10 and the second clock signal CLK_IN of the second system 20. For Option I, the total delay amounts to approximately two time periods of the clock signal CLK_IN. For Option II, the total delay amounts to approximately two and a half time periods of the clock signal CLK_IN. For Option III, the total delay amounts to approximately three time periods of the clock signal CLK_IN.

[0043] As a result, selecting a delay compensation value Δ of “2” for counter 22 of triggered system 20 may result in an inaccuracy of plus one CLK_IN cycle, while selecting a delay compensation value Δ of “3” may result in an inaccuracy of minus one CLK_IN cycle.

[0044] Figure 4 is a schematic block diagram of an example system with an enhanced synchronization method to improve accuracy.

[0045] Note that, with the equivalent Figure 1 and 2 The blocks with the same reference numerals as in have the same or similar functions and structures and are therefore not described again here.

[0046] In an example embodiment, the triggered system (e.g., system B) 20 includes a "recorder" module or circuit 27 that is configured to detect edges (e.g., rising and / or falling edges) of the trigger signal T and record the value of the counter 22 of the triggered system 20 after the edges of the trigger signal T are detected. The recorder circuit 27 may include Figure 2 The recorder circuit 27 and the synchronization circuit are similar to the synchronization circuit 26. With respect to their clock timing, both the recorder circuit 27 and the synchronization circuit are configured to become active at the rising and falling edges of the clock cycle of the clock signal CLK_IN (i.e., double data rate (DDR) capability). Therefore, if the recorder circuit 27 has this synchronization circuit at its input, an uncertainty of one sampling period (i.e., 0.5 CLK_IN clocks) is introduced.

[0047] The recorder circuit 27 is a data acquisition module that includes an on-board memory (not shown) or a cooperating memory for storing the acquired data (i.e., counter values). In an example, the memory may be a battery-powered static random access memory, a flash memory, or an electrically erasable programmable read-only memory (EEPROM), etc.

[0048] As indicated above, in the exemplary embodiment, the recorder circuit 27 is configured to operate according to the CLK_IN domain and to sample the counter value at a double sampling rate (i.e., on both the rising and falling edges of the clock signal CLK_IN). Thus, the recorded counter value may be an integer (rising edge sample) or an integer + 0.5 (falling edge sample).

[0049] Furthermore, in an example embodiment, the triggered system 20 may include a configurable delay module or circuit 28 that can add a delay to the input clock signal CLK_IN provided to the counter 22 and can be controlled by a fast clock generated at the output of the PLL circuit 24 of the triggered system 20. In an example, the delay of the configurable delay circuit 28 can be implemented by a software routine (e.g., compensated by a software routine), a controllable delay line, a series of controllable logic gates, etc. In other sampling embodiments, the configurable delay circuit 28 can be configured to add a delay to the output value of the counter 22 (e.g., by delaying the binary code output of the counter 22). In additional sampling embodiments, the configurable delay circuit 28 can be configured to add a delay to a trigger output generated based on the output value of the counter 22 (e.g., when the output value of the counter 22 reaches a predetermined value).

[0050] Additionally, in an example embodiment, the triggered system 20 may include a control circuit 25 (e.g., a central processing unit (CPU) or another programmable logic) that may be configured to read the recorded counter value of the recorder circuit 27 and apply an offset value to the counter 22 and / or set a delay value at the configurable delay circuit 28 based on the recorded counter value.

[0051] Figure 5 1 is a schematic diagram illustrating the uncertain nature of synchronization using the waveform of the common clock signal CLK_IN at the triggered system 20 and the example of four regions A to D. The edge(s) of the trigger signal T (e.g., a pulse train) received from the trigger system 10 (e.g., system A) may be received in one of the four regions A to D compared to the CLK_IN domain of the triggered system 20 (e.g., system B).

[0052] More specifically, in an example, region A may specify a region with appropriate setup and hold times that precedes the rising edge of the clock signal CLK_IN. Region A thus results in a stable and consistent recording of counter samples for all edges of the trigger signal T and the recording of counter values ​​will have integer values ​​(i.e., the least significant bit (LSB) of the binary counter value is equal to "0"). Furthermore, in an example, region B may specify a region with insufficient setup and hold times that surrounds the rising edge of the clock signal CLK_IN. Region B thus results in an unstable recording of counter samples for pulse train edges, where some counter values ​​are latched on the rising edge (i.e., LSB=0) while other counter values ​​are latched on the next falling edge (i.e., LSB=1). Thus, region B in fact creates an uncertain characteristic of the synchronization circuit at the input of the recorder circuit 27. Additionally, in an example, region C may specify a region with appropriate setup and hold times that precedes the falling edge of the clock signal CLK_IN. Thus, this region C results in a stable and consistent recording of counter samples for all burst edges of the trigger signal T and the recorded counter values ​​will have an integer +0.5 value (LSB=1). Finally, in the example, region D may specify a region with insufficient setup and hold times around the falling edge of the clock signal CLK_IN. Thus, this region D also results in an unstable recording of counter samples for the edges of the trigger signal T, with some counter values ​​being latched on the falling edge (LSB=1) and other counter values ​​being latched on the next rising edge (LSB=0). Similar to region B, this region D in fact creates an uncertain characteristic of the synchronization circuit at the input of the recorder circuit 27.

[0053] Figure 6 is a schematic flow chart of an example of an enhanced synchronization procedure with improved accuracy according to a sample embodiment.

[0054] The triggering system (e.g., system A) will respond to its counter (e.g., Figure 2 The trigger signal T is generated by the counter 12 in the trigger system. Thus, the edge of the pulse (rising edge and / or falling edge) will appear at the predefined value of the counter of the trigger system. These predefined counter values ​​of the trigger system will be marked as an array [Y(0), Y(1), ..., Y(N-1)]. In step S610, these counter values ​​Y(i) of the trigger system will be controlled by the control circuit (e.g., Figure 4 These values ​​are predetermined and can be stored in or signaled to the triggered system.

[0055] Then, in step S620, the recorder circuit of the triggered system (eg, Figure 4The recorder circuit 27) will record the counter of the triggered system (e.g. Figure 4 The values ​​of the counter 22 after the edges of the trigger signal T are detected at the triggered system. These values ​​will be labeled as an array [X(0), X(1), …, X(N-1)]. Note that the counter value X(i) recorded at the triggered system may be an integer or an integer + 0.5 due to the double sampling rate of the DDR mechanism.

[0056] In other words, each counter value X(i) recorded by the triggered system has one more bit than each counter value Y(i) collected by the triggering system. This additional bit (i.e., the LSB) indicates whether the counter value X(i) is an integer (LSB=0) or an integer + 0.5 (LSB=1).

[0057] In step S630 , the control circuit of the triggered system reads array X after recording is completed. Then, in step S640 , the control circuit of the triggered system analyzes the recorded array X based on the collected array Y and accordingly sets at least one of an offset and a configurable delay of a counter of the triggered system in step S650 to improve the accuracy of synchronization of the triggered system.

[0058] Thus, as shown above, in the example embodiment, the edge of the trigger signal T is generated based on the clock signal CLK_IN at the triggering system and is sampled at the triggered system based on the clock signal CLK_IN of the triggered system. Note that because the two systems are frequency aligned (even if they are not phase aligned), when they share a common clock source (e.g., Figure 1 When the same clock signal of the clock source 30) is used, all edges of the pulse train of the trigger signal T will be Figure 5 Arriving from area A to the same area in D.

[0059] By analyzing the recorded counter values ​​of the recorder circuit 27, the offset between the counters of the two systems can be determined with a resolution of a single period of the clock signal CLK_IN. As an additional option, based on the above-mentioned areas A to D where the edge has reached, a configurable delay can be determined and set to "fine-tune" the offset of the counter of the triggered system with a resolution lower than a single period of the clock signal CLK_IN.

[0060] In the following, detailed procedures for improving synchronization accuracy according to example embodiments are referred to. Figure 7 and 8 Described based on the corresponding flow chart, it is assumed that the number of bits in the counter of the triggered system is "M" and the number of bits of the counter values ​​recorded by the recorder circuit at the rising and falling edges of the clock signal CLK_IN is "M+1" (due to double rate sampling (DDR)).

[0061] The procedure may be triggered by the control circuitry of the system (e.g. Figure 4 The control circuit 25) is executed to determine at least one of the optimal offset and configurable delay of the counter of the triggered system, wherein Figure 7 and 8 The flowchart of the procedure involves the counter of the system being triggered (e.g., Figure 4 The initial count value X0 of the counter 22 is selected to determine different situations or branches, such as whether an integer value (X0[0]=0) or a non-integer value (X0[0]=1) has been detected as the first count value (i.e., the timestamp). The maximum value N of the operating parameter i corresponds to the number of considered edges of the trigger signal T. As an example, the value N=10 (i.e., 5 periods) or a larger value may be selected.

[0062] Figure 7 is the first branch of the flow chart, which is selected in the following case: the LSB of the initial counter value X0 is "1" after receiving the relevant edge of the trigger signal T, that is, the initial counter value is a non-integer count value (roughly corresponding to Figure 5 However, is the relevant edge located in Figure 5 Whether one of the regions B or D is in the region is unclear.

[0063] In step S701, the counter offset is set to the difference (Y0-X0[M:1]) between the initial M-bit counter value Y0 of the triggering system's counter and the initial M-bit counter value X0 of the triggered system's counter (excluding the LSB), and the configurable delay is initially set to one-quarter of the clock cycle of the clock signal CLK_IN (i.e., 0.25*CLK_IN). Then, in step S702, the operating parameter i is set to "1." Thereafter, in step S703, the current (M+1)-bit counter value (timestamp) Xi[M:0] of the triggered system's counter is checked. If its LSB value is determined to be "1," the procedure branches to step S704 and checks whether the difference (excluding the LSB) between the collected relevant M-bit counter value Yi of the triggering system's counter and the current M-bit counter value Xi of the triggered system's counter is equal to the initial difference (excluding the LSB) between the collected initial M-bit counter value Y0 of the triggering system's counter and the initial M-bit counter value X0 of the triggered system's counter. If not, the procedure branches to step S705 and determines an error. This error indicates that the measured result is meaningless, which should not normally occur. If so, the procedure can be restarted (e.g., the pulse train of the trigger signal can be sent and measured again). If the difference is equal, the procedure branches to step S706, where the operating parameter i is incremented (e.g., by 1) and a check is made as to whether the maximum value N of the operating parameter i has been reached. If not, the procedure jumps back to step S703. Otherwise, if the operating parameter i has reached the maximum value N, the procedure branches to step S707 and determines success, i.e., the correct offset and delay for optimal synchronization have been found.

[0064] Otherwise, if it is determined in step S703 that the LSB value of the current counter value Xi is "0", the procedure proceeds to step S708, where it is checked whether the difference between the collected relevant M-bit counter value Yi of the counter of the triggering system and the current M-bit counter value Xi of the counter of the triggered system (excluding the LSB) is equal to the initial difference between the collected initial M-bit counter value Y0 of the counter of the triggering system and the initial M-bit counter value X0 of the counter of the triggered system (excluding the LSB). If not, the procedure branches to step S709, where it is checked whether the initial difference between the collected initial M-bit counter value Y0 of the counter of the triggering system and the initial M-bit counter value X0 of the counter of the triggered system is equal to the difference between the collected relevant M-bit counter value Yi of the counter of the triggering system and the current M-bit counter value Xi of the counter of the triggered system (excluding the LSB) plus 1. If not, the procedure branches to step S710 and an error is determined.

[0065] If it is determined in step S709 that the difference is equal, the procedure continues to step S711, where the counter offset is set to the initial difference (Y0-X0[M:1]) between the collected initial M-bit counter value Y0 of the counter of the triggering system and the initial M-bit counter value X0 of the counter of the triggered system, and the configurable delay is set to half a period of the clock signal CLK_IN (i.e., 0.5*CLK_IN). The procedure then continues to step S712, where the operating parameter i is incremented and where it is checked whether the operating parameter i has reached its maximum value N. If so, the procedure branches to step S713 and determines success, i.e. Figure 5 The optimal values ​​for region B have been set for the counter offset and the configurable delay.

[0066] If the operating parameter i has not reached its maximum value N in step S712, the procedure proceeds to step S714 and checks the current (M+1)-bit counter value (timestamp) Xi[M:0] of the counter of the triggered system. Then, in step S715, it is checked whether the following is true: the difference between the collected relevant M-bit counter value Yi of the counter of the triggering system and the current M-bit counter value Xi of the counter of the triggered system (excluding LSB) is equal to the initial difference between the collected initial M-bit counter value Y0 of the counter of the triggering system and the initial M-bit counter value X0 of the counter of the triggered system (excluding LSB) and the LSB (Xi[0]) is "1", or the difference between the collected relevant M-bit counter value Yi of the counter of the triggering system and the current M-bit counter value Xi of the counter of the triggered system (excluding LSB) plus 1 is equal to the initial difference between the collected initial M-bit counter value Y0 of the counter of the triggering system and the initial M-bit counter value X0 of the counter of the triggered system (excluding LSB) and the LSB (Xi[0]) is "0". If not, the procedure continues to step S716 where an error is determined. Otherwise, if it is determined in step S715 that the difference values ​​are equal for one case, the procedure jumps back to step S712 and the operating parameter is incremented again.

[0067] If it is determined in step S708 that the difference is equal, the procedure continues to step S717, where the counter offset is set to the initial difference (Y0-X0[M:1]) between the collected initial M-bit counter value Y0 of the counter of the triggering system and the initial M-bit counter value X0 of the counter of the triggered system, and the configurable delay is set to zero. The procedure then continues to step S718, where the operating parameter i is incremented and where it is checked whether the operating parameter i has reached its maximum value N. If so, the procedure branches to step S719 and determines success, i.e. Figure 5 The optimal values ​​of area D have been set for the counter offset and the configurable delay.

[0068] If, in step S718, the operating parameter i has not yet reached its maximum value N, the procedure proceeds to step S720 and checks the current (M+1)-bit counter value (timestamp) Xi[M:0] of the counter of the triggered system. Then, in step S721, it is checked whether the difference (excluding the LSB) between the collected relevant M-bit counter value Yi of the counter of the triggering system and the current M-bit counter value Xi of the counter of the triggered system is equal to the initial difference (excluding the LSB) between the collected initial M-bit counter value Y0 of the counter of the triggering system and the initial M-bit counter value X0 of the counter of the triggered system. If not, the procedure proceeds to step S722, where an error is determined. Otherwise, if, in step S721, it is determined that the difference is equal, the procedure jumps back to step S718 and the operating parameter is incremented again.

[0069] Figure 8 is the second branch of the flow chart, which is selected in the following case: the LSB of the initial counter value X0 after receiving the relevant edge of the trigger signal T is "0", that is, the initial counter value is an integer count value (approximately corresponding to Figure 5 However, is the relevant edge located in Figure 5 Whether one of the regions B or D is in the region is unclear.

[0070] In step S801, the counter offset is set to the initial difference between the initial M-bit counter value Y0 of the triggering system's counter and the initial M-bit counter value X0 of the triggered system's counter plus 1 (Y0-X0[M:1]+1), and the configurable delay is set to three-quarters of the clock cycle of the clock signal CLK_IN (i.e., 0.75*CLK_IN). Then, in step S802, the operating parameter i is set to "1." Thereafter, in step S803, the current (M+1)-bit counter value (timestamp) Xi[M:0] of the triggered system's counter is checked. If the LSB value is determined to be "0," the procedure branches to step S804 and checks whether the difference between the collected relevant M-bit counter value Yi of the triggering system's counter and the current M-bit counter value Xi of the triggered system's counter (excluding the LSB) is equal to the initial difference between the collected initial M-bit counter value Y0 of the triggering system's counter and the initial M-bit counter value X0 of the triggered system's counter (excluding the LSB). If not, the procedure branches to step S805 and determines an error. If the differences are equal, the procedure branches to step S806, where the operating parameter i is incremented (e.g., by 1) and a check is made to see whether the maximum value N of the operating parameter i has been reached. If not, the procedure jumps back to step S803. Otherwise, if the operating parameter i has reached the maximum value N, the procedure branches to step S807 and determines success, i.e. Figure 5 The optimal values ​​for region A have been set for the counter offset and the configurable delay.

[0071] Otherwise, if it is determined in step S803 that the LSB value of the current counter value Xi is "1", the procedure proceeds to step S808, where it is checked whether the difference (excluding the LSB) between the collected relevant M-bit counter value Yi of the counter of the triggering system and the current M-bit counter value Xi of the counter of the triggered system is equal to the initial difference (excluding the LSB) between the collected initial M-bit counter value Y0 of the counter of the triggering system and the initial M-bit counter value X0 of the counter of the triggered system. If not, the procedure branches to step S809, where it is checked whether the difference (excluding the LSB) between the collected relevant M-bit counter value Yi of the counter of the triggering system and the current M-bit counter value Xi of the counter of the triggered system is equal to the initial difference (excluding the LSB) between the collected initial M-bit counter value Y0 of the counter of the triggering system and the initial M-bit counter value X0 of the counter of the triggered system plus 1. If not, the procedure branches to step S810 and an error is determined.

[0072] If it is determined in step S809 that the difference is equal, the procedure continues to step S811, where the counter offset is set to the initial difference between the collected initial M-bit counter value Y0 of the counter of the triggering system and the initial M-bit counter value X0 of the counter of the triggered system plus 1 (Y0-X0[M:1]+1), and the configurable delay is set to half a period of the clock signal CLK_IN (i.e., 0.5*CLK_IN). The procedure then continues to step S812, where the operating parameter i is incremented and where it is checked whether the operating parameter i has reached its maximum value N. If so, the procedure branches to step S813 and determines success, i.e. Figure 5 The optimal values ​​for region B have been set for the counter offset and the configurable delay.

[0073] If the operating parameter i has not reached its maximum value N in step S812, the procedure continues to step S814 and checks the current (M+1)-bit counter value (timestamp) Xi[M:0] of the counter of the triggered system. Then, in step S815, it is checked whether the following is true: the difference between the collected relevant M-bit counter value Yi of the counter of the triggering system and the current M-bit counter value Xi of the counter of the triggered system (excluding LSB) is equal to the initial difference between the collected initial M-bit counter value Y0 of the counter of the triggering system and the initial M-bit counter value X0 of the counter of the triggered system (excluding LSB) and the LSB (Xi[0]) is "0", or the difference between the collected relevant M-bit counter value Yi of the counter of the triggering system and the current M-bit counter value Xi of the counter of the triggered system (excluding LSB) is equal to the initial difference between the collected initial M-bit counter value Y0 of the counter of the triggering system and the initial M-bit counter value X0 of the counter of the triggered system plus 1 and the LSB (Xi[0]) is "1". If not, the procedure continues to step S816 where an error is determined. Otherwise, if it is determined in step S815 that the difference values ​​are equal for one case, the procedure jumps back to step S812 and the operating parameter is incremented again.

[0074] If it is determined in step S808 that the difference is equal, the procedure continues to step S817, where the counter offset is set to the initial difference (Y0-X0[M:1]) between the collected initial M-bit counter value Y0 of the counter of the triggering system and the initial M-bit counter value X0 of the counter of the triggered system, and the configurable delay is set to zero. The procedure then continues to step S818, where the operating parameter i is incremented and where it is checked whether the operating parameter i has reached its maximum value N. If so, the procedure branches to step S819 and determines success, i.e. Figure 5 The optimal values ​​of area D have been set for the counter offset and the configurable delay.

[0075] If, in step S818, the operating parameter i has not yet reached its maximum value N, the procedure proceeds to step S820 and checks the current (M+1)-bit counter value (timestamp) Xi[M:0] of the counter of the triggered system. Then, in step S821, it is checked whether the difference (excluding the LSB) between the collected relevant M-bit counter value Yi of the counter of the triggering system and the current M-bit counter value Xi of the counter of the triggered system is equal to the initial difference (excluding the LSB) between the collected initial M-bit counter value Y0 of the counter of the triggering system and the initial M-bit counter value X0 of the counter of the triggered system. If not, the procedure proceeds to step S822, where an error is determined. Otherwise, if, in step S821, it is determined that the difference is equal, the procedure jumps back to step S818 and the operating parameter is incremented again.

[0076] Therefore, according to Figure 7 and 8 In a sample embodiment of the procedure, the binary value of the LSB of the initially recorded (M+1)-bit counter value of the counter of the triggered system is used to initially set the counter offset at the triggered system to the initial difference between the initial M-bit counter value Y0 of the counter of the triggering system and the initial M-bit counter value X0 of the triggered system (if LSB=1) or the initial difference plus 1 (if LSB=0) and to initially set the configurable delay at the triggered system to 0.25 CLK_IN (if LSB=1, which corresponds to region C) or 0.75 CLK_IN (if LSB=0, which corresponds to region A). These initial settings are maintained in the following conditions: the difference between the predetermined number N of subsequently correlated collected counter values ​​Yi and the recorded counter values ​​Xi of the two systems remains equal to the initial difference between the initial counter values ​​Y0 and X0.

[0077] However, if it is determined that the binary value of the LSB of one of the predetermined number N of subsequently recorded counter values ​​Xi has changed, the initial setting of the configurable delay at the triggered system is set to zero (if the above differences are equal, which corresponds to region D) or 0.5 CLK_IN (if the above differences differ by 1, which corresponds to region B). In addition, the counter offset at the triggered system can then be set to the above initial difference plus 1 if the LSB has become "1".

[0078] Note that optimal performance is achieved if all four regions A to D are of equal size (ie, 0.25 CLK_IN periods). This results in a synchronization accuracy of one-eighth of a period of the clock signal CLK_IN (ie, - / +(CLK_IN periods) / 8).

[0079] In an example scenario, the setup and hold times may be very small, thereby making regions B and D negligible compared to regions A and C. This scenario would then result in a synchronization accuracy of a quarter cycle period of the clock signal CLK_IN (ie, - / +(CLK_IN period) / 4).

[0080] Therefore, the above procedure for determining the offset and configurable delay of a counter of a triggered system can take advantage of the uncertainty of the synchronization circuit to improve the overall accuracy.

[0081] In an example, counter offset adjustment alone may be used for coarse compensation with an accuracy of 1 clock cycle, while adjustment of the configurable delay may be used for fine compensation with an accuracy of less than one clock cycle (e.g., between one-eighth clock cycle and one-quarter clock cycle).

[0082] To verify that the synchronization process was successful, the system can rerun the procedure while switching the roles of the triggering system (e.g., system A) and the triggered system (e.g., system B, so that system B is now triggering and system A is triggered) and verify that the calculated offset is zero. As another option, verification can be achieved by having both systems drive signals when they reach specific counter values ​​and then measuring the time difference between the two signals, for example using test equipment.

[0083] Figure 6 、 7 The processing steps or operations of the procedures of 8 can be performed by a control circuit (e.g., Figure 4 The control circuit 25) may be implemented by a software routine or by a hardware circuit or a digital signal processor (DSP) or an application specific integrated circuit (ASIC) or a programmable logic device (PLD) or a programmable gate array (PGA).

[0084] A Matlab simulation was performed that simulated the two systems. The simulation covered both the synchronization procedures (i.e., the physical connections between the two systems, the pulse trains, the recording of the recorder circuits, etc.) and Figure 7 and 8 A procedure for determining the optimal offset and configurable delay to synchronize the two systems with improved accuracy was described. The simulation was performed 1000 times, each time with a random phase shift between the clock signals CLK_IN of the triggering system (System A) and the triggered system (System B). The frequency of the clock signal CLK_IN was set to 20 MHz, the initial offset between the counters of the triggering system and the triggered system was set to 1000, the number of pulses in the pulse train of the triggering signal was set to 8 (i.e., 16 edges), and the frequency of the fast clock at the output of the PLL circuit was set to 150 MHz. The parameter values ​​determine the resolution with which the procedure can set the configurable delay.

[0085] the following Figure 9 and 10 The diagram in shows the corresponding histogram of the resulting inaccuracy between the two counters after performing this synchronization procedure, in ns.

[0086] Figure 9 The synchronization is performed with a long hold and setup time of 6 ns so that Figure 5 An example of a histogram of the resulting inaccuracy between two systems after the sizes of regions A, B, C, and D are approximately equal. Figure 9 As known from , the inaccuracy is approximately - / +6ns, which is equal to one eighth cycle period of the clock signal CLK_IN (ie, - / +(CLK_IN period) / 8).

[0087] Figure 10 is a diagram showing an example of a histogram of the resulting inaccuracy between two systems after synchronization with shorter hold and setup times equal to only 1 ns such that regions A and C are much larger than regions B and D. As can be seen from Figure 10 As known from , the inaccuracy is slightly less than - / +12ns, which is equal to a quarter cycle period of the clock signal CLK_IN (ie, - / +(CLK_IN period) / 4).

[0088] The present disclosure has presented example embodiments of an apparatus and procedure for synchronizing the time bases of two systems with a high accuracy of less than one clock cycle period, wherein a triggered system is synchronized to a triggering system by tracking the timing of rising and falling edges of a clock signal at the triggered system and using the tracked timing values ​​to phase-shift the time base at the triggered system.

[0089] More generally, according to one aspect disclosed herein, there is provided an apparatus for synchronizing a synchronization signal to an input trigger signal, the apparatus comprising:

[0090] recorder circuitry for sampling and recording a value of the counter in response to detecting a rising edge and / or a falling edge of the input trigger signal, wherein the sampling is performed at rising and falling edges of a common clock signal provided to the counter; and

[0091] A control circuit is configured to read the recorded value and calculate at least one of an offset and a configurable delay of the counter based on the recorded value.

[0092] In various embodiments, the apparatus may further include a synchronization circuit, wherein the recorder circuit and the synchronization circuit are configured to become active at rising and falling edges of a common clock signal.

[0093] In various embodiments, the apparatus may further include a configurable delay circuit configured to add a configurable delay to the common clock signal, or an output of the counter, or a trigger output generated based on the output of the counter before the common clock signal is provided to the counter.

[0094] In various embodiments, the configurable delay circuit may be controlled by a fast clock signal having a clock frequency higher than a clock frequency of the common clock signal.In various examples, the fast clock signal may be generated based on the common clock signal.

[0095] In various embodiments, the control circuit may be configured to collect predefined counter values ​​corresponding to rising and / or falling edges of the input trigger signal and calculate at least one of an offset and a configurable delay of the counter based on a comparison of the recorded values ​​with the collected predefined counter values.

[0096] In various embodiments, the recorded value may have one more bit than the collected counter value, and the extra bit is used to indicate whether the recorded value is an integer or non-integer value, depending on whether it is sampled at the rising or falling edge of the clock signal.

[0097] In various embodiments, the control circuitry may be configured to use the binary value of the least significant bit (LSB) of the initial value in the recorded values ​​to initially set the offset of the counter to an initial difference between the initial value in the collected counter values ​​and one of the recorded values ​​if the LSB indicates a non-integer value, or to initially set the offset of the counter to the initial difference plus one if the LSB indicates an integer value.

[0098] In various embodiments, the control circuitry may be configured to use the binary value of the LSB of the initial value in the recorded values ​​to initially set the configurable delay to a quarter of a clock period of the common clock signal if the LSB indicates a non-integer value, or to initially set the configurable delay to three-quarters of a clock period of the common clock signal if the LSB indicates an integer value.

[0099] In various embodiments, the control circuit may be configured to maintain the preliminary setting if respective differences between a predetermined number of subsequently correlated collected counter values ​​and the recorded value remain equal to the initial difference.

[0100] In various embodiments, if the control circuit determines that the binary value of the LSB of one of the predetermined number N of subsequently recorded values ​​has changed, the control unit may be configured to set the preliminary setting of the configurable delay to zero if the corresponding difference value and the initial difference value are equal, or to set the preliminary setting of the configurable delay to half a clock period of the common clock signal if the corresponding difference value differs from the initial difference by 1.

[0101] In various embodiments, the control circuit may be configured to set the offset of the counter to the initial difference value plus one if the LSB has changed to indicate a non-integer value.

[0102] According to another aspect disclosed herein, a method for synchronizing a synchronization signal to an input trigger signal is provided, the method comprising:

[0103] sampling and recording a value of the counter in response to detecting a rising edge and / or a falling edge of the input trigger signal, wherein the sampling is performed at rising and falling edges of a common clock signal provided to the counter; and

[0104] At least one of an offset and a configurable delay of the counter is calculated based on the recorded value.

[0105] In various embodiments, the method may further include adding a configurable delay to the common clock signal before it is provided to the counter, or to an output of the counter, or to a trigger output generated based on the output of the counter.

[0106] According to yet another aspect of the present disclosure, a computer program implemented on a computer-readable storage is provided. The computer program includes code configured to execute the method of any one of the embodiments disclosed herein when executed on one or more processors.

[0107] The examples and embodiments described herein may be implemented as logical steps in one or more computer systems. Logical operations may be implemented as: (1) a sequence of processor-implemented steps executed in one or more computer systems; and (2) interconnected machine or circuit modules within one or more computer systems. The implementation is a matter of choice depending on the performance requirements of the computer systems used for implementation. Thus, the logical operations that make up each example or embodiment described herein may be variously referred to as operations, steps, objects, or modules. Furthermore, it should be understood that logical operations may be performed in any order, added as needed, or omitted unless expressly stated or a particular order is inherently required by the claim language.

[0108] Other variations and applications of the disclosed technology may become apparent to those skilled in the art once this disclosure is given.The scope of the present disclosure is not limited to the above-described embodiments, but is only defined by the appended claims.

Claims

1. A device for synchronizing a counter to an input trigger signal, the device comprising: a data acquisition module for sampling and recording the value of the counter in response to detecting a rising edge and / or a falling edge of the input trigger signal, wherein the sampling is performed at rising and falling edges of a common clock signal provided to the counter and the data acquisition module; a control circuit for reading the recorded value and calculating at least one of an offset and a configurable delay of the counter based on the recorded value and a predetermined collected value; as well as A configurable delay circuit is configured to add the configurable delay to the common clock signal before the common clock signal is provided to the counter, or to an output of the counter, or to a trigger output generated based on the output of the counter. 2 . The apparatus of claim 1 , further comprising a synchronization circuit, wherein the data acquisition module and the synchronization circuit are configured to become active at rising and falling edges of the common clock signal. 3 . The apparatus of claim 1 , wherein the configurable delay circuit is controlled by a fast clock signal having a clock frequency higher than a clock frequency of the common clock signal. The apparatus of claim 3 , wherein the fast clock signal is generated based on the common clock signal.

5. The apparatus of any one of the preceding claims, wherein the control circuit is configured to obtain the predetermined collected value by collecting predefined counter values ​​corresponding to the rising and / or falling edges of the input trigger signal and to calculate at least one of the offset and the configurable delay of the counter based on a comparison of the recorded value with the collected predefined counter values.

6. The apparatus of claim 5 , wherein the recorded value has one more bit than the collected counter value, and wherein the extra bit is used to indicate whether the recorded value is an integer value or a non-integer value, depending on whether it is sampled at a rising edge or a falling edge of the clock signal.

7. The apparatus of claim 6 , wherein the control circuit is configured to use a binary value of a least significant bit (LSB) of an initial value in the recorded values ​​to initially set the offset of the counter to an initial difference between the initial value in the collected counter values ​​and one of the recorded values ​​if the LSB indicates a non-integer value, or to initially set the offset of the counter to the initial difference plus 1 if the LSB indicates an integer value.

8. The apparatus of claim 7 , wherein the control circuit is configured to use a binary value of the LSB of an initial value in the recorded values ​​to preliminarily set the configurable delay to a quarter of a clock period of the common clock signal if the LSB indicates a non-integer value, or to preliminarily set the configurable delay to three-quarters of a clock period of the common clock signal if the LSB indicates an integer value.

9. An apparatus as claimed in claim 7 or 8, wherein the control circuit is configured to maintain the preliminary setting if the respective differences between a predetermined number of subsequent associated collected counter values ​​and the recorded value remain identical to the initial difference.

10. The apparatus of claim 9 , wherein if the control circuitry determines that the binary value of the LSB of one of a predetermined number N of subsequently recorded values ​​has changed, the control circuitry is configured to set the preliminary setting of the configurable delay to zero if the corresponding difference value and the initial difference value are equal, or to set the preliminary setting of the configurable delay to one-half a clock period of the common clock signal if the corresponding difference value differs from the initial difference by one.

11. The apparatus of claim 10, wherein the control circuit is configured to set the offset of the counter to the initial difference value plus 1 if the LSB has changed to indicate a non-integer value.

12. A method for synchronizing a counter to an input trigger signal, the method comprising: sampling and recording a value of a counter in response to detecting a rising edge and / or a falling edge of the input trigger signal, wherein the sampling is performed at rising and falling edges of a common clock signal provided to the counter; calculating at least one of an offset and a configurable delay of the counter based on the recorded value and a predetermined collected value; as well as The configurable delay is added to the common clock signal before it is provided to the counter, or to an output of the counter, or to a trigger output generated based on the output of the counter.

13. A computer-readable storage medium storing code, the code being configured to perform the method of claim 12 when executed on one or more processors.

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