Peripheral circuit, memory and system, electronic device, test device and method

Abstract

This disclosure provides a peripheral circuit, a memory and system, an electronic device, a test device, and a method. The peripheral circuit includes: a first counter configured to generate a first count value based on a read enable signal; a second counter configured to generate a second count value based on a data strobe signal; and a comparator, wherein a first input terminal of the comparator is coupled to the output terminal of the first counter, and a second input terminal of the comparator is coupled to the output terminal of the second counter, and the comparator is configured to compare the first count value and the second count value.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a peripheral circuit, a memory and system, an electronic device, a test device and method. Background Technology

[0002] In a memory system comprising a memory controller and one or more memories, the memory controller samples data signals based on the rising and / or falling edges of a data strobe signal (DQS). The data strobe signal is used to synchronize data transmission between the memories and the memory controller, facilitating accurate data reading by the memory controller. If the output of the data strobe signal malfunctions, the memory controller will be unable to read data correctly. Summary of the Invention

[0003] This disclosure provides a peripheral circuit, a memory and system, an electronic device, a test device, and a method.

[0004] According to a first aspect of this disclosure, a peripheral circuit is provided, comprising:

[0005] A first counter is configured to generate a first count value based on a read enable signal; wherein the signal value of the read enable signal switches between a first signal value and a second signal value, and the first count value is used to indicate the number of times the read enable signal switches between the first signal value and the second signal value;

[0006] A second counter is configured to generate a second count value based on a data strobe signal; wherein the signal value of the data strobe signal switches between a third signal value and a fourth signal value, and the second count value is used to indicate the number of times the data strobe signal switches between the third signal value and the fourth signal value; and,

[0007] A comparator, wherein a first input of the comparator is coupled to the output of the first counter, and a second input of the comparator is coupled to the output of the second counter, the comparator being configured to compare the first count value and the second count value.

[0008] According to a second aspect of this disclosure, a memory is provided, comprising:

[0009] Memory cell array;

[0010] The peripheral circuit described above is coupled to the memory cell array and is configured to control the memory cell array.

[0011] According to a third aspect of this disclosure, a memory system is provided, comprising:

[0012] The memory described above is configured to store data;

[0013] A memory controller, coupled to the memory, is configured to control the memory.

[0014] According to a fourth aspect of this disclosure, an electronic device is provided, comprising:

[0015] The memory system described above includes a memory controller;

[0016] The host, coupled to the memory controller, is configured to communicate.

[0017] According to a fifth aspect of this disclosure, a test apparatus is provided for testing a device including the peripheral circuitry described above, the test apparatus comprising:

[0018] The test unit is configured to send a test command to the device and receive a test result generated by the device based on the test command; wherein the test result includes the comparison result output by the comparator;

[0019] An analysis unit, coupled to the test unit, is configured to determine, based on the comparison result, whether there is an anomaly in the peripheral circuit that generates the data strobe signal.

[0020] According to a sixth aspect of this disclosure, a testing method is provided, comprising:

[0021] During the time period of executing the preset command, a first count value is generated based on the read enable signal; wherein, the signal value of the read enable signal switches between a first signal value and a second signal value, and the first count value is used to indicate the number of times the read enable signal switches between the first signal value and the second signal value;

[0022] During the time period of executing a preset command, a second count value is generated based on a data strobe signal; wherein the signal value of the data strobe signal switches between a third signal value and a fourth signal value, and the second count value is used to indicate the number of times the data strobe signal switches between the third signal value and the fourth signal value;

[0023] The first count value and the second count value are compared.

[0024] The peripheral circuit provided in this embodiment includes a first counter that counts the number of read enable signal switching times during the entire preset command execution period and generates a first count value, and a second counter that counts the number of data strobe signal switching times during the entire preset command execution period and generates a second count value. After the memory completes the preset command execution, a comparator compares the first and second count values ​​to generate a comparison result. Based on the comparison result indicating whether the first and second count values ​​are consistent, it can be determined whether the memory has experienced data strobe signal loss or additional switching.

[0025] In this disclosure, the ability of peripheral circuitry to stably output a data strobe signal can be tested during the execution of any read command or a combination sequence including read commands, providing greater coverage than using a dedicated data strobe test sequence. For example, a dedicated data strobe test sequence can only test the data strobe signal output when a specified read command is executed (e.g., reading data from a specified block), whereas in this disclosure, the data strobe signal output can be tested simultaneously during the execution of any read command or a combination sequence of read commands.

[0026] Furthermore, when testing the peripheral circuits provided in the embodiments of this disclosure, it is not necessary to write a test sequence specifically for the data strobe signal output, making the testing method more flexible and shortening the testing time. Moreover, the requirements for testing equipment are lower; commonly used automated test equipment (ATE), and even test machines based on field-programmable logic arrays (FPGAs), can complete the testing of the memory's data strobe signal output, demonstrating good compatibility with existing test equipment. Furthermore, it is not necessary to use automated test equipment supporting DQS sync functionality, thereby saving testing costs. Attached Figure Description

[0027] Figure 1 A schematic diagram of an electronic device provided in an embodiment of this disclosure;

[0028] Figure 2A and 2B A schematic diagram of a memory system provided in an embodiment of this disclosure;

[0029] Figure 3 A schematic circuit diagram of a memory including peripheral circuitry provided for embodiments of this disclosure;

[0030] Figure 4 A schematic diagram of the peripheral circuit provided in the embodiments of this disclosure;

[0031] Figure 5 A schematic diagram of a peripheral circuit provided for yet another embodiment of this disclosure;

[0032] Figure 6 Timing diagram of the read operation provided for implementation of this disclosure;

[0033] Figure 7 A schematic diagram of a peripheral circuit provided for yet another embodiment of this disclosure;

[0034] Figure 8 A flowchart illustrating the testing method provided in this embodiment of the disclosure;

[0035] Figure 9 A schematic diagram of the test equipment provided in an embodiment of this disclosure. Detailed Implementation

[0036] The technical solution of this application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0037] In the description of this application, it should be understood that the terms "length", "width", "depth", "upper", "lower", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0038] Figure 1 This is a block diagram of an electronic device provided in an embodiment of this disclosure. The electronic device 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, electronic device 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memories 104 and a memory controller 106. The host 108 may be a processor of the electronic device (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 is coupled to the memory controller 106 and may be configured to send data to or receive data from the memories 104.

[0039] Memory 104 can be any memory disclosed herein. For example, a non-volatile memory device or dynamic random access memory (DRAM). The non-volatile memory device may include NAND flash memory (e.g., three-dimensional (3D) NAND flash memory, two-dimensional NAND flash memory).

[0040] In some embodiments, memory controller 106 is coupled to memory 104 and host 108 and is configured to control memory 104. Memory controller 106 can manage data stored in memory 104 and communicate with host 108. In some embodiments, memory controller 106 is configured to perform test methods provided in embodiments of this disclosure to test memory 104.

[0041] In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0042] In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment within an SSD or embedded multimedia card (eMMC), which serves as data storage for mobile devices such as smartphones, tablets, laptops, etc., as well as enterprise storage arrays. The memory controller 106 can be configured to control the operation of the memory 104, such as read, erase, and program operations.

[0043] The memory controller 106 can also be configured to manage various functions related to data stored or to be stored in the memory 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc.

[0044] In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory 104. The memory controller 106 may communicate with external devices (e.g., host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with external devices via at least one of a variety of interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0045] The memory controller 106 and one or more memories 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products.

[0046] In such Figure 2A In one embodiment shown, the memory controller 106 and a single memory 104 may be integrated into the memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The memory card connector 204 is coupled to the host 108.

[0047] In such Figure 2B In another embodiment shown, the memory controller 106 and a plurality of memories 104 may be integrated into the SSD 206. The SSD 206 may also include a connection between the SSD 206 and a host (e.g., Figure 1 The SSD connector 208 is coupled to the host 108 in the host. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0048] Figure 3 A schematic circuit diagram of a memory 300 including peripheral circuitry provided for embodiments of this disclosure. The memory 300 may be... Figure 1 An example of memory 104 is shown. Memory 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 may be a NAND memory cell array, wherein memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown).

[0049] In some embodiments, the peripheral circuit 302 is configured to perform the test methods provided in the embodiments of this disclosure. It is understood that the peripheral circuit 302 may be configured to perform the test methods provided in the embodiments of this disclosure according to instructions received from the memory controller 106.

[0050] In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 that are series-coupled and vertically stacked. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell that includes a floating-gate transistor, or a charge-trapping type memory cell that includes a charge-trapping transistor.

[0051] In some embodiments, each memory cell 306 is a single-level memory cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. Figure 3 As shown, each NAND memory string 308 may include a source select gate (SSG) 310 at its source end and a drain select gate (DSG) 312 at its drain end. The SSG 310 and DSG 312 may be configured to activate the selected NAND memory string 308 (column of the array) during read and program operations.

[0052] In some embodiments, the sources of NAND memory strings 308 in the same block 304 are coupled through the same source line (SL) 314 (e.g., common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same block 304 have an array common source (ACS). According to some embodiments, the DSG 312 of each NAND memory string 308 is coupled to a corresponding bit line 316, and data can be read from or written to the bit line 316 via an output bus (not shown).

[0053] In some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having DSG 312) or a deselection voltage (e.g., 0V) to the corresponding DSG 312 via one or more DSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having SSG 310) or a deselection voltage (e.g., 0V) to the corresponding SSG 310 via one or more SSG lines 315.

[0054] like Figure 3As shown, the NAND memory string 308 can be organized into multiple blocks 304, each of which may have a common source line 314 (e.g., coupled to ground). In some embodiments, each block 304 is a basic data unit for an erase operation, i.e., all memory cells 306 on the same block 304 are erased simultaneously. To erase memory cells 306 in a selected block, a source line 314 biased to the selected block and unselected blocks on the same plane as the selected block can be used. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at any suitable number of blocks or any suitable fraction of blocks.

[0055] Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a page 320 of memory cells 306, which is a basic unit of data used for programming operations. The size of a page 320, in bits, can be related to the number of NAND memory strings 308 coupled by word lines 318 in a block 304. Each word line 318 may include multiple control gates (gate electrodes) at each memory cell 306 in the corresponding page 320, as well as gate lines coupling the control gates.

[0056] Peripheral circuitry 302 can be coupled to memory cell array 301 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313. Peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry for facilitating operation of memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 and sensing voltage and / or current signals from each target memory cell 306 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313. Peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology.

[0057] For example, Figure 4 This is a schematic diagram of the peripheral circuitry provided in an embodiment of the present disclosure. The peripheral circuitry 302 includes control logic 512, I / O circuitry (input / output circuitry) 516, page buffer / sensor amplifier 504, column decoder / bit line (BL) driver 506, row decoder / word line (WL) driver 508, voltage generator 510, and data bus 518. It should be understood that in some embodiments, it may also include... Figure 4 Additional peripheral circuitry not shown, such as ready / busy control circuitry.

[0058] Page buffer / sensor amplifier 504 can be configured to read data from memory cell array 301 and program (write) data to memory cell array 301 according to control signals from control logic 512. In one example, during a read operation, page buffer / sensor amplifier 504 can sense data on the bit lines of memory cell array 301 and buffer the sensed data for output. In some embodiments, page buffer / sensor amplifier 504 can store one page of programming data (write data) to be programmed into one or more pages 320 of memory cell array 301. In some embodiments, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In some embodiments, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during a read operation.

[0059] The column decoder / bit line driver 506 can be configured to be controlled by control logic 512 and to select one or more NAND memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0060] The line decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect block 304 of memory cell array 301 and select / deselect word line 318 of block 304. The line decoder / word line driver 508 can also be configured to drive word line 318 using word line voltages generated from voltage generator 510. In some embodiments, the line decoder / word line driver 508 can also select / deselect and drive SSG line 315 and DSG line 313.

[0061] The voltage generator 510 can be configured to be controlled by control logic 512 and generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, source line voltages, SSG line voltages, and DSG line voltages, etc., to be supplied to the memory cell array 301.

[0062] Register 514 can be coupled to control logic 512 and I / O circuit 516, and includes a status register, a command register and an address register to store status information, command opcode (OP code) and command address used to control the operation of each peripheral circuit module.

[0063] I / O circuitry 516 can be coupled to control logic 512 and register 514. I / O circuitry 516 can act as a control buffer, for example, buffering control commands received from memory controller 106 and relaying them to register 514. In one example, I / O circuitry 516 receives status information received from control logic 512 via register 514 and relays the status information to memory controller 106. I / O circuitry 516 can also be coupled to page buffer / sensor amplifier 504 via data bus 518 to write data to memory cell array 301 via page buffer / sensor amplifier 504 during write operations, or to read data from memory cell array 301 via page buffer / sensor amplifier 504 during read operations.

[0064] Control logic 512 can be coupled to each of the peripheral circuit modules described above and is configured to control the operation of each peripheral circuit module. Control logic 512 receives various control signals, such as Chip Enable (CE), Command Latch Enable (CLE), Address Latch Enable (ALE), Write Enable (WE), and Read Enable (RE). In one example, control logic 512 controls I / O circuit 516 to receive control commands from memory controller 106 via various control signals and relays the control commands to the command register and address register accordingly. In one example, during a read operation, control logic 512 can control the corresponding peripheral circuit module to operate according to the control command.

[0065] In memory systems including NAND flash memory, the memory controller samples the data signal on the DQ[7:0] pins (DQ0, DQ1, ... DQ7 pins) based on the rising and / or falling edges of the data strobe signal DQS. The transition of the digital strobe signal DQS from low to high is called a rising edge, and the transition from high to low is called a falling edge. For example, the memory controller can sample data at either the rising or falling edge of the data strobe signal, i.e., perform one sample per signal cycle. Also for example, the memory controller can sample data at both the rising and falling edges of the data strobe signal, i.e., perform two samples per signal cycle, which is more efficient than one sample per signal cycle.

[0066] When the memory controller reads data from the memory, it sends a read enable (RE) signal to the memory. Upon receiving the read enable (RE) signal, the memory prepares the data signal on the DQ[7:0] pins and simultaneously generates a switching data strobe signal on the DQS pin. The memory controller samples the data signal on the DQ[7:0] pins based on the rising and / or falling edges of the data strobe signal. The data strobe signal is used to synchronize data transmission between the memory and the memory controller, facilitating accurate data reading by the memory controller.

[0067] If the memory fails to output a data strobe signal due to a fault, or if the data strobe signal does not toggle between high and low levels, or if the data strobe signal toggles with a delay, the memory controller will wait indefinitely for the data strobe signal to switch, potentially causing the memory controller to freeze. Therefore, during the memory development phase, sufficient testing is required to ensure that the memory can stably output a data strobe signal during data reading periods.

[0068] Because of the high integration density of memory, memory testing is typically performed by automated test equipment (ATE). During testing, the presence of a fault in the memory is determined by comparing the data written to and read from the memory.

[0069] Some automated test equipment (ATUs) supporting Data QS sync can detect whether a memory is stably outputting a data strobe signal. Specifically, ATUs supporting DQS sync can count the number of data strobe signal toggles throughout the entire test sequence and compare it to the expected number of toggles. If they differ, it indicates that the memory experienced data strobe signal loss (DQS missing) or extra toggle during the execution of the test sequence. This means the memory cannot stably output a data strobe signal. ATUs supporting DQS sync are expensive, increasing testing costs. Furthermore, even when using ATUs supporting DQS sync, a dedicated test sequence for data strobe signal output must be written, and it cannot be shared with other test sequences. In other words, the ATU cannot simultaneously test the data strobe signal output while testing other functions of the memory, resulting in limited coverage of test sequences for data strobe signal output, failing to cover all situations where data strobe signals are used.

[0070] Therefore, embodiments of this disclosure provide a peripheral circuit, such as... Figure 5As shown, the peripheral circuit includes:

[0071] A first counter 601 is configured to generate a first count value based on a received read enable signal; wherein the signal value of the read enable signal switches between a first signal value and a second signal value, and the first count value is used to indicate the number of times the read enable signal switches between the first signal value and the second signal value.

[0072] The second counter 602 is configured to generate a second count value based on a received data strobe signal; wherein the signal value of the data strobe signal switches between a third signal value and a fourth signal value, and the second count value is used to indicate the number of times the data strobe signal switches between the third signal value and the fourth signal value; and,

[0073] Comparator 603 has its first input coupled to the output of the first counter 601 and its second input coupled to the output of the second counter 602. Comparator 603 is configured to compare the first count value and the second count value.

[0074] For example, one of the first signal value and the second signal value is high, and the other is low. The read enable signal switches between high and low levels. A first counter 601 counts the number of times the read enable signal switches between high and low levels. Specifically, when the read enable signal switches from high to low, the first count value of the first counter 601 is incremented by one. When the read enable signal switches from low to high, the first count value of the first counter 601 is incremented by one again.

[0075] For example, one of the third and fourth signal values ​​is high, and the other is low. The data strobe signal also switches between high and low levels. The second counter 602 counts the number of times the strobe signal switches between high and low levels. Specifically, when the data strobe signal switches from high to low, the second count value of the second counter 602 is incremented by one; when the data strobe signal switches from low to high, the second count value of the second counter 602 is incremented by one again.

[0076] For example, the first counter 601 and the second counter 602 are binary counters. Taking the first counter 601 as an example, incrementing the first count value of the first counter 601 by one means increasing it in binary increments, such as when a bit of the first counter 601 changes from 0 to 1, or from 1 to 0 and carries over. In some other embodiments, the first counter 601 and the second counter 602 may also be decimal counters or counters of any base.

[0077] In some embodiments, the number of bits in the first counter 601 and the second counter 602 can be set relatively small. When the first count value reaches the maximum value that the number of bits in the first counter 601 can count, the first counter 601 automatically resets to zero and starts counting again from zero. Similarly, when the second count value reaches the maximum value that the number of bits in the second counter 602 can count, the second counter 602 automatically resets to zero and starts counting again from zero. This reduces the memory space occupied by the counters and saves costs.

[0078] For example, the first counter 601 and the second counter 602 may be four-bit binary counters.

[0079] Here, the comparator 603 compares the received first count value and second count value and outputs the comparison result; wherein the comparison result is used to indicate whether the first count value and the second count value are consistent.

[0080] In some embodiments, comparator 603 is specifically configured to output a failure signal as a comparison result when the second count value is inconsistent with the first count value.

[0081] In some embodiments, comparator 603 can output a pass signal or a fail signal as the comparison result. Specifically:

[0082] When the second count value matches the first count value, the comparator 603 outputs a signal as the comparison result.

[0083] When the second count value is inconsistent with the first count value, the comparator 603 outputs a failure signal as the comparison result.

[0084] The comparison result output by comparator 603 can be used to determine whether the memory has experienced a loss or additional switching of the data strobe signal. If comparator 603 outputs a pass signal, it means that the number of switching times for the data strobe signal and the read enable signal are the same, indicating that the memory can stably output the data strobe signal. If comparator 603 outputs a failure signal, it means that the number of switching times for the data strobe signal and the read enable signal are different, indicating that the memory cannot stably output the data strobe signal.

[0085] Here, the pass signal and the failure signal can be binary signals 0 or 1. For example, it can be that the pass signal is 0 and the failure signal is 1, or it can be that the pass signal is 1 and the failure signal is 0.

[0086] Figure 6 This is a timing diagram of a read operation provided in one embodiment of the present disclosure. Figure 6 This simply illustrates the memory during a read operation. pins, Signals on the pins, DQ[7:0] pins, and DQS pins. For example... Figure 6 As shown, when the memory controller reads data from the memory, it sends a read command to the memory via the DQ[7:0] pins. For example, this read command includes: 00h + address (ADDR) + 30h. Upon receiving the read command, the memory reads the data from the memory cell at the corresponding address and latches the data into the page buffer / sensor amplifier.

[0087] Here, when the memory reads data from the memory cell at the corresponding address, it is ready / busy. A low level signal indicates a busy state. A high level signal indicates a ready state after data is latched into the page buffer / sensor amplifier.

[0088] The memory controller generates a read enable signal (RE) after the ready / busy signal switches from low to high. For example... Figure 6 As shown, the read enable signal is a periodic signal of 1010…1010, where 1 is high level and 0 is low level, and the read enable signal switches between high and low levels.

[0089] memory through When the pin receives the switching read enable signal, it then transmits the data latched on the page buffer / sensor amplifier to the I / O circuit via the data bus. For example, the data latched in the page buffer / sensor amplifier can be transmitted to the I / O circuit when the read enable signal is low, or when the read enable signal is high, allowing for two data read operations to be completed within one signal cycle.

[0090] Simultaneously, upon receiving the read enable signal, the memory generates a data strobe signal for switching and transmits this strobe signal to the DQS output buffer. For example... Figure 6 As shown, the data strobe signal is a periodic signal of 1010…1010, where 1 is high level and 0 is low level, and the data strobe signal switches between high and low levels.

[0091] After the memory controller obtains the switching data strobe signal through the DQS pin, it reads the data signal on the DQ[7:0] pin at the rising and falling edges of the data strobe signal.

[0092] Understandably, during the process of the memory controller reading data from the memory, if the data strobe signal generated by the memory does not switch within a certain period, the memory controller will not read the data signal and will instead wait for the data strobe signal to switch, which can easily cause the memory controller to freeze. If the data strobe signal generated by the memory switches more times than the read enable signal within a certain period, it will lead to the memory controller reading incorrect data.

[0093] It should be noted that when the test equipment directly tests the memory, it can act as a memory controller, sending read commands or combinations thereof, along with read enable signals, to the memory. The test equipment can also acquire data strobe signals and read data signals based on the rising and / or falling edges of these strobe signals.

[0094] The peripheral circuit provided in this disclosure can test whether the memory can stably output a data strobe signal during the execution of any read command or a combination sequence including read commands. When the memory completes the read command, the first counter 601 counts the number of times the read enable signal switches during the entire read command execution period, generating a first count value, and the second counter 602 counts the number of times the data strobe signal switches during the entire read command execution period, generating a second count value. After the memory completes the read command, the comparator 603 compares the first count value and the second count value. Based on the comparison result indicating whether the first count value and the second count value are consistent, it can be determined whether the memory has experienced a data strobe signal loss or additional switching.

[0095] The peripheral circuit provided in this disclosure can test whether the memory is experiencing insufficient or excessive switching of the data strobe signal by comparing the number of switching times of the read enable signal and the data strobe signal. In this disclosure, the stability of the memory's data strobe signal output can be tested during the execution of any read command or a combination sequence including read commands, providing greater coverage than a dedicated data strobe signal test sequence. For example, a dedicated data strobe signal test sequence can only test the data strobe signal output when a specified read function command (e.g., reading data from a specified block) is executed, while in this disclosure, the data strobe signal output can be tested simultaneously during the execution of any read command or a combination sequence of read commands. For example, the data strobe signal output can be tested under read commands such as reading a specified block, a specified area, or a specified page. In other words, this disclosure can test the stability of the data strobe signal output under a wider range of read commands, thus providing more reliable test results for the data strobe signal output.

[0096] It is understood that in some embodiments, the testing equipment primarily tests the memory by writing data to the memory, then reading and verifying that data. However, the peripheral circuitry provided in this disclosure can test whether the memory can stably output a data strobe signal while executing any read command. In other words, in this disclosure, the peripheral circuitry can simultaneously test the data strobe signal output while performing other functional tests, significantly improving the coverage of data strobe signal testing. Furthermore, it eliminates the need to write a dedicated test sequence for the data strobe signal output, thereby shortening the testing time.

[0097] Furthermore, in this disclosure, the number of switching times of the read enable signal and the data strobe signal in the memory is compared, and the comparison result is directly output. The test equipment only needs to obtain the comparison result, and does not need to obtain the data strobe signal, nor does it need to compare the number of switching times of the data strobe signal and the read enable signal. Therefore, even automatic test equipment that does not support DQS sync function can test the data strobe signal output of the memory of this disclosure. That is, the test method provided by this disclosure has low requirements for test equipment. Commonly used automatic test equipment (ATE) and even test machines based on field-programmable logic arrays (FPGAs) can complete the test of the data strobe signal output of the memory. It has good compatibility with existing test equipment and can save test costs.

[0098] In some embodiments, the peripheral circuitry further includes a result register 604, the input of which is coupled to the output of the comparator 603. The result register 604 is configured to store a failure signal when the second count value is inconsistent with the first count value.

[0099] In some embodiments, the result register 604 is configured to store the comparison result. Specifically, when the second count value is inconsistent with the first count value, a failure signal is stored; when the second count value is consistent with the first count value, a pass signal is stored.

[0100] For example, the result register 604 can store the binary signal 0 or 1 sent by the comparator 603.

[0101] After the memory completes the read command sequence, the test device can read the comparison result (0 or 1) stored in the result register 604 to determine whether the memory lost the data strobe signal or switched the data strobe signal extra during the execution of the entire read command.

[0102] In some embodiments, the first counter 601 includes a signal input terminal for receiving an enable signal. It should be noted that this disclosure does not restrict which specific peripheral circuit module the signal input terminal of the first counter 601 is coupled to, as long as the signal input terminal of the first counter 601 can acquire the read enable signal.

[0103] In some embodiments, the peripheral circuitry further includes a first buffer 605, which is configured to buffer the received read enable signal. The output of the first buffer 605 is coupled to the signal input of the first counter 601 to transmit the read enable signal to the first counter 601.

[0104] Here, the first buffer 605 can be coupled to Pin.

[0105] memory through The pin receives a read enable signal from the memory controller or test equipment and buffers the read enable signal in the first buffer. For example, the first buffer 605 is a RE input buffer.

[0106] The signal input terminal of the first counter 601 is coupled to the output terminal of the first buffer 605 to receive the read enable signal buffered by the first buffer 605.

[0107] It is understood that, in some embodiments, the signal input terminal of the first counter 601 may also be coupled to... The pin is used to directly receive read enable signals from the memory controller or test equipment.

[0108] In some embodiments, control logic 512 is configured to generate a data strobe signal. Control logic 512 may generate the data strobe signal based on a read enable signal.

[0109] In some embodiments, the input of control logic 512 is coupled to the output of the first buffer 605. Control logic 512 receives a read enable signal from the first buffer 605 and generates a data strobe signal. For example, the data strobe signal switches after a preset delay based on the switching start time of the read enable signal. This preset delay is very short, and it can be considered that the data strobe signal starts switching at the switching start time of the read enable signal.

[0110] It is also understandable that the data strobe signal is generated based on the read enable signal. Theoretically, during the time period when the memory executes a read command, the number of times the read enable signal is switched is the same as the number of times the data strobe signal is switched. Therefore, this disclosure can determine whether the control logic 512 can stably generate the data strobe signal by comparing the number of times the read enable signal and the data strobe signal are switched.

[0111] In some embodiments, the peripheral circuitry further includes a second buffer 607, the input of which is coupled to the output of the control logic 512, and the second buffer 607 is configured to buffer a data strobe signal.

[0112] Here, the second buffer 607 may be coupled to the DQS pin to transmit the data strobe signal to the memory controller or test equipment. For example, the second buffer 607 is a DQS output buffer.

[0113] Understandably, the second counter 602 is used to count the number of times the data strobe signal is switched. Therefore, the signal input terminal of the second counter 602 can be coupled to the output terminal of the control logic 512 to receive the data strobe signal generated by the control logic 512. The signal input terminal of the second counter 602 can also be coupled to the output terminal of the second buffer 607 to receive the data strobe signal buffered by the second buffer 607.

[0114] In some embodiments, the peripheral circuit further includes a clock source 608, the output of which is coupled to the clock input of a first counter 601, the clock input of a second counter 602, and the clock input of a comparator 603, respectively. The clock source 608 is configured to generate a clock signal. The first counter is configured to generate a first count value based on the received clock signal and a read enable signal; the second counter is configured to generate a second count value based on the received clock signal and a data strobe signal; and the comparator is configured to compare the first count value and the second count value based on the received clock signal, the first count value, and the second count value.

[0115] Here, it should be noted that, Figure 6 What is shown is The read enable signal of the DQS pin and the data strobe signal of the DQS pin are used, not the read enable signal received by the control logic and the data strobe signal generated by the control logic. It is understood that after the control logic generates the data strobe signal, the data strobe signal will be buffered through at least a second buffer before being transmitted to the DQS pin. Therefore, Figure 6 The data strobe signal shown has a longer delay time than the read enable signal.

[0116] In this embodiment, the signal input terminal of the second counter can be coupled to the output terminal of the control logic, and the signal input terminal of the first counter can be coupled to the output terminal of the first buffer. Therefore, the data strobe signal received by the second counter and the read enable signal received by the first counter switch almost synchronously. Thus, the second counter 602 and the first counter 601 can synchronously count the number of times the data strobe signal and the read enable signal switch, generating a first count value and a second count value. The comparator 603 can synchronously compare the second count value and the first count value once to monitor in real time whether the control logic can stably output the data strobe signal.

[0117] Specifically, such as Figure 5 As shown, the first counter 601 counts the number of times the read enable signal switches according to a clock signal, and the second counter 602 counts the number of times the data strobe signal switches according to the same clock signal. The comparator 603 samples the first count value of the first counter 601 and the second count value of the second counter 602 according to the same clock signal. Therefore, the comparator 603 can compare the number of times the read enable signal and the strobe signal switch each time the read enable signal switches. During the execution of the read command, if the comparator 603 finds that the first count value and the second count value are inconsistent, it outputs a failure signal as the comparison result.

[0118] Understandably, during the execution of the read command sequence, the data strobe signal may switch once more than the read enable signal in the first time period, and once less than the read enable signal in the second time period, which is different from the first time period. After the memory completes the read command sequence, the first count value and the second count value may be the same, but in reality, the control logic has resulted in either fewer or more switches of the data strobe signal.

[0119] In this embodiment, the first counter 601, the second counter 602, and the comparator 603 are synchronized by a clock signal emitted from the same clock source 608. The comparator 603 compares the number of times the data strobe signal and the read enable signal have switched each time the read enable signal switches, preventing the loss of the data strobe signal or undetected extra switches. If the comparator 603 outputs a pass signal, it indicates that the data strobe signal switches accordingly when the read enable signal switches, demonstrating that the memory can stably output the data strobe signal.

[0120] It should be noted that during the execution of the read command sequence, if the first count value and the second count value are inconsistent, the comparator 603 will output a failure signal. When the comparator 603 samples the first count value and the second count value again, even if both the first count value and the second count value are incremented by one, the comparator 603 will still output a failure signal.

[0121] Furthermore, comparator 603 can only switch from a pass signal to a failure signal, but not from a failure signal to a pass signal. For example, it can only switch from 0 to 1, but not from 1 to 0. That is, if the number of switches for the data strobe signal is less than the number of switches for the read enable signal, and comparator 603 outputs a failure signal, even if subsequent additional switches for the data strobe signal occur, resulting in the same number of switches for the data strobe signal and the read enable signal, comparator 603 cannot switch from the failure signal to the pass signal. In other words, after the first instance of a discrepancy between the data strobe signal and the read enable signal, comparator 603 will consistently output a failure signal. This avoids situations where the data strobe signal is lost or additional switches go undetected.

[0122] In some embodiments, the input of clock source 608 is coupled to the output of first buffer 605, and clock source 608 is configured to generate a clock signal based on a received read enable signal.

[0123] For example, the frequency of the clock signal is the same as the frequency of the read enable signal. That is, the signal period of the clock signal is the same as the signal period of the read enable signal.

[0124] As described above, the first counter 601 and the second counter 602 sample the read enable signal and the data strobe signal according to the clock signal. Therefore, the first counter 601 and the second counter 602 can receive the clock signal before or simultaneously with receiving the read enable signal and the data strobe signal, respectively, to prevent undercounting the number of switching times of the read enable signal and the data strobe signal.

[0125] In this implementation, the clock source 608 generates a clock signal based on the read enable signal, which can achieve basic synchronization between the clock signal and the read enable signal, so that the clock signal and the read enable signal arrive at the first counter 601 almost synchronously, and the clock signal arrives at the second counter 602 before the data strobe signal, ensuring that the first counter 601 and the second counter 602 can accurately count the number of switching between the read enable signal and the data strobe signal respectively.

[0126] Furthermore, it is understood that in some embodiments, the first counter 601 and the second counter 602 are constituted by latches, and the first counter 601 can temporarily store a first count value. Therefore, when the time point at which the data strobe signal is transmitted to the first counter is slightly delayed compared to the time point at which the read enable signal is transmitted to the second counter (for example, the delay time is less than half a signal cycle of the read enable signal), the comparator can also compare the number of times the data strobe signal has switched based on that switch of the read enable signal with the number of times the read enable signal has switched after any switch of the read enable signal.

[0127] In some embodiments, the time when the data strobe signal is transmitted to the first counter is delayed by a relatively long time relative to the time when the read enable signal is transmitted to the second counter (e.g., this delay is greater than half a signal cycle of the read enable signal). This long delay may be caused by a longer delay between the start of the data strobe signal switching and the start of the read enable signal switching, or by the second counter being connected to a second buffer, resulting in a longer delay in the received data strobe signal. In this case, even if the control logic 512 outputs the data strobe signal normally, the second count value and the first count value cannot remain consistent. Therefore, this problem can be overcome by setting a delay circuit in the external circuitry.

[0128] For example, a delay circuit can be added between the first counter 601 and the comparator 603 to delay the arrival time of the first count value at the comparator 603, so that the first count value and the second count value arrive at the comparator 603 synchronously.

[0129] The following is combined with Figure 7 This disclosure provides a detailed description of an embodiment of the peripheral circuitry. For example... Figure 7 As shown, the peripheral circuit includes an RE input buffer 705, control logic 512, a DQS output buffer 707, a page buffer / sensor amplifier 504, an I / O circuit 516, a clock source 608, a first counter 601, a second counter 602, a comparator 603, and a P / F register 704.

[0130] The input of the RE input buffer 705 is coupled to The pin, output terminal is coupled to control logic 512, first counter 601 and clock source 608. RE input buffer 705 buffers the read enable signal from the memory controller or test equipment and transmits the read enable signal to control logic 512, first counter 601 and clock source 608.

[0131] The input of the page buffer / sensor amplifier 504 is coupled to the RE input buffer 705, and the output is coupled to the I / O circuit 516. The page buffer / sensor amplifier 504 transmits the data signal to the I / O circuit 516 according to the received read enable signal.

[0132] The input of I / O circuit 516 is coupled to page buffer / sensor amplifier 504, and the output is coupled to DQ[7:0] pins. I / O circuit 516 transmits data signals to memory controller or test equipment through DQ[7:0] pins.

[0133] The input of control logic 512 is coupled to RE input buffer 705, and the output is coupled to second counter 602 and DQS output buffer 707. Control logic 512 generates a data strobe signal based on the received read enable signal.

[0134] The input of the DQS output buffer 707 is coupled to the control logic 512, and the output is coupled to the DQS pin. The DQS output buffer 707 can buffer the data strobe signal and transmit the data strobe signal to the memory controller or test equipment through the DQS pin.

[0135] The input of clock source 608 is coupled to RE input buffer 705, and the output is coupled to first counter 601, second counter 602, and comparator 603. Clock source 608 generates a clock signal based on the received read enable signal.

[0136] The input of the first counter 601 is coupled to the RE input buffer 705 and the clock source 608, and the output is coupled to the comparator 603. The first counter 601 counts the number of times the read enable signal is switched according to the received clock signal, generates a first count value, and transmits the first count value to the comparator 603.

[0137] The input of the second counter 602 is coupled to the control logic 512 and the clock source 608, and the output is coupled to the comparator 603. The second counter 602 counts the number of times the data strobe signal is switched according to the received clock signal, generates a second count value, and transmits the second count value to the comparator 603.

[0138] The input of comparator 603 is coupled to the first counter 601, the second counter 602, and the clock source 608, while its output is coupled to the P / F register 704. Comparator 603 samples and compares the first and second count values ​​based on the received clock signal, and then transmits the comparison result to the P / F register 704. Specifically, when the first and second count values ​​match, a pass signal is transmitted to the P / F register; when the first and second count values ​​do not match, a failure signal is transmitted to the P / F register. For example, the pass signal is 0 (low level), and the failure signal is 1 (high level).

[0139] like Figure 7 As shown, the RE input buffer 705 receives and buffers the read enable signal from the memory controller or test device. For example, the read enable signal is a periodically switching high and low level of 101010… After receiving the read enable signal, the page buffer / sensor amplifier 504 loads data onto the read enable signal to generate a data signal and transmits the data signal to the I / O circuit 516.

[0140] During the transmission of data signals to I / O circuit 516, clock source 608 receives the read enable signal, generates a clock signal, and transmits the clock signal to first counter 601, second counter 602, and comparator 603. First counter 601 receives the read enable signal and clock signal almost simultaneously, starts counting the number of times the read enable signal switches, and transmits the first count value to comparator 603.

[0141] During the data signal transmission to I / O circuit 516, control logic 512 receives a read enable signal, generates a periodically switching data strobe signal (101010…), and transmits the data strobe signal to DQS output buffer 707 and second counter 602. The memory controller or test equipment samples the data signal based on the data strobe signal. Second counter 602 receives the clock signal and data strobe signal sequentially, begins counting the data strobe signal, and transmits the second count value to comparator 603. Comparator 603 receives the clock signal, the first count value, and the second count value, compares the first count value and the second count value, and transmits the comparison result to P / F register 704.

[0142] After the read command is executed, the test device can read the value (0 or 1) in the P / F register 704 through the memory controller to determine whether the data strobe signal generated by the memory has been lost or additionally switched. In some embodiments, the test device can also act as a memory controller, directly sending read commands and read enable signals to the memory and directly obtaining the comparison result stored in the P / F register 704. For example, the comparison result can be represented by a low level as a pass signal and a high level as a failure signal.

[0143] This disclosure also provides a test method for testing whether a memory including the above-described peripheral circuitry can stably output a data strobe signal. Figure 8 This is a schematic flowchart of a testing method provided in an embodiment of the present disclosure, as shown below. Figure 8 As shown, the test method includes:

[0144] S100: During the time period of executing the preset command, a first count value is generated based on the read enable signal; wherein, the signal value of the read enable signal switches between a first signal value and a second signal value, and the first count value is used to indicate the number of times the read enable signal switches between the first signal value and the second signal value;

[0145] S200: During the time period of executing the preset command, a second count value is generated based on the data strobe signal; wherein, the signal value of the data strobe signal switches between a third signal value and a fourth signal value, and the second count value is used to indicate the number of times the data strobe signal switches between the third signal value and the fourth signal value;

[0146] S300: Compare the first count value and the second count value.

[0147] In some embodiments, the preset command includes a read command. The preset command may be a sequence of read commands or a combination sequence that includes read commands.

[0148] In some embodiments, step S300 specifically includes:

[0149] The first count value and the second count value are compared. When the second count value matches the first count value, a pass signal is generated as the comparison result; or...

[0150] The first count value and the second count value are compared. When the second count value is inconsistent with the first count value, a failure signal is generated as the comparison result.

[0151] The test method provided in this disclosure can test whether the memory can stably output a data strobe signal during the execution of any read command or a combination sequence of read commands. During the execution of the read command sequence, a first counter in the memory counts the number of times the read enable signal switches during the entire read command execution, generating a first count value. A second counter in the memory counts the number of times the data strobe signal switches during the entire read command execution, generating a second count value. After the read command is executed, a comparator in the memory compares the first count value with the second count value. Based on whether the first count value and the second count value are consistent, it can be determined whether the memory has experienced data strobe signal loss or additional switching.

[0152] It is understood that in some embodiments, the testing equipment primarily tests the memory by writing data to the memory and then reading that data. However, the testing method provided in this disclosure can test whether the memory can stably output a data strobe signal during any data read operation. In other words, the testing method provided in this disclosure can simultaneously test the data strobe signal output while performing other functional tests, significantly improving the coverage of data strobe signal testing. Furthermore, it eliminates the need to write a dedicated test sequence for the data strobe signal output, thereby shortening the testing time.

[0153] Furthermore, in this disclosure, the number of switching times of the read enable signal and the data strobe signal in the memory is compared, and the comparison result is directly output. The test equipment only needs to obtain the comparison result, and does not need to obtain the data strobe signal, nor does it need to compare the number of switching times of the data strobe signal and the read enable signal. Therefore, it is not necessary to use an automated test equipment that supports DQS sync function. That is, the test method provided by this disclosure has low requirements for the test equipment. Commonly used automated test equipment (ATE), and even test machines based on field-programmable logic arrays (FPGAs), can complete the test of the data strobe signal output of the memory. It has good compatibility with existing test equipment and can save test costs.

[0154] In some embodiments, the testing method further includes:

[0155] Storage failure signal;

[0156] Alternatively, store the comparison results, which may include data obtained through a signal or data obtained through a signal.

[0157] For example, a preset command device is executed in the memory, and the comparison result is stored in the registers in the memory so that the test device can read the comparison result in the registers after the test is completed.

[0158] In some embodiments, the testing method further includes:

[0159] The data strobe signal is generated based on the read enable signal.

[0160] In some embodiments, the peripheral circuitry includes a clock source, the output of which is coupled to the clock input of a first counter, the clock input of a second counter, and the clock input of a comparator, respectively. The clock source is configured to generate a clock signal. Correspondingly, the test method includes:

[0161] During the time period of executing the preset command, a first count value is generated based on the clock signal and the read enable signal; wherein, the signal value of the read enable signal switches between a first signal value and a second signal value, and the first count value is used to indicate the number of times the read enable signal switches between the first signal value and the second signal value;

[0162] During the time period of executing the preset command, a second count value is generated based on the clock signal and the data strobe signal; wherein, the signal value of the data strobe signal switches between a third signal value and a fourth signal value, and the second count value is used to indicate the number of times the data strobe signal switches between the third signal value and the fourth signal value;

[0163] Based on a clock signal, a first count value, and a second count value, the first count value and the second count value are compared; a comparison result is generated; wherein the comparison result is used to indicate whether the first count value and the second count value are consistent.

[0164] In this embodiment, the first counter, the second counter, and the comparator are synchronized using a clock signal from the same clock source. During read command execution, the comparator samples the first count value of the first counter and the second count value of the second counter according to the clock signal. If a discrepancy occurs between the first and second count values, a failure signal is output. That is, the comparator compares the number of times the data strobe signal and the read enable signal have switched each time the read enable signal switches, preventing the loss or undetected extra switching of the data strobe signal. If the comparator outputs a pass signal, it indicates that the data strobe signal switches accordingly when the read enable signal switches, demonstrating that the memory can stably output the data strobe signal.

[0165] In some embodiments, the testing method further includes:

[0166] A clock signal is generated based on the read enable signal. Thus, the clock signal has the same frequency as the read enable signal, and the clock signal and read enable signal arrive at the first counter almost synchronously. The clock signal arrives at the second counter before the data strobe signal, ensuring that the first and second counters can accurately count the number of times the read enable signal and data strobe signal switch, respectively.

[0167] This disclosure also provides a testing apparatus for testing devices including the aforementioned peripheral circuitry. Figure 9 As shown, the test device 901 includes: a test unit 902, configured to send test commands to the device and receive test results generated by the device based on the test commands; wherein the test results include comparison results output by the comparator.

[0168] In some embodiments, the test device 901 can test a memory system, which includes a memory and a memory controller. The test device can send test commands to the memory controller and read comparison results from the memory controller.

[0169] In some embodiments, such as Figure 9As shown, the test device 901 can also test the memory 904 (e.g., a non-volatile memory device). The test device 901 can directly send test commands to the memory 904. For example, test signals can be directly applied to the pins of the memory 904. In some embodiments, the test unit 902 of the test device 901 can apply a pulse containing address information and command information, or a signal wave formed by multiple pulses, to the DQ[7:0] pins of the memory 904. The test unit 902 can also directly apply test commands to the DQ[7:0] pins of the memory 904. A read enable signal that switches between high and low levels is applied to the pin. Test unit 902 can accept a DQS signal that switches between high and low levels output from the DQS pin of memory 904, as well as data signals sampled on the DQ[7:0] pins based on the data strobe signal.

[0170] In some embodiments, the test device 901 may also directly obtain the comparison result stored in the register in the memory 904. For example, the test device 901 may directly obtain the level of the register output, such as a low level indicating a pass signal and a high level indicating a failure signal.

[0171] In some embodiments, testers can determine whether the control logic that generates the data strobe signal is abnormal based on the comparison results. In other embodiments, the test device 901 further includes an analysis unit 903, coupled to the test unit 902, configured to determine whether the control logic that generates the data strobe signal is abnormal based on the comparison results. For example, the analysis unit 903 is specifically configured to:

[0172] If the comparison result indicates that the first count value and the second count value are the same, it is determined that there is no abnormality in the control logic;

[0173] If the comparison result indicates that the first count value and the second count value are inconsistent, an anomaly is determined in the control logic.

[0174] In this embodiment, the test equipment can simultaneously test the data strobe signal output while performing other functional tests, significantly improving the coverage of data strobe signal testing. Furthermore, it eliminates the need to write a dedicated test sequence for the data strobe signal output, thereby shortening the test time. Moreover, in this disclosure, the number of switching times of the read enable signal and the data strobe signal in the memory is compared, and the comparison result is directly output. The test equipment only needs to obtain the comparison result, without needing to obtain the data strobe signal or compare the switching times of the data strobe signal and the read enable signal. Therefore, it is not necessary to use an automated test equipment supporting DQS sync functionality. That is, the test method provided in this disclosure does not place high demands on the test equipment; commonly used automated test equipment (ATE), and even test machines based on field-programmable logic arrays (FPGAs), can complete the testing of the memory's data strobe signal output, thus saving test costs.

[0175] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A peripheral circuit, characterized in that, include: A first counter is configured to generate a first count value based on a read enable signal; wherein the signal value of the read enable signal switches between a first signal value and a second signal value, and the first count value is used to indicate the number of times the read enable signal switches between the first signal value and the second signal value; A second counter is configured to generate a second count value based on a data strobe signal; wherein the signal value of the data strobe signal switches between a third signal value and a fourth signal value, and the second count value is used to indicate the number of times the data strobe signal switches between the third signal value and the fourth signal value; and, A comparator, wherein a first input terminal of the comparator is coupled to the output terminal of the first counter, and a second input terminal of the comparator is coupled to the output terminal of the second counter, the comparator being configured to compare the first count value and the second count value and output a comparison result; the comparison result can be used to determine whether the data strobe signal is normal.

2. The peripheral circuit according to claim 1, characterized in that, The comparator is specifically configured as follows: When the second count value matches the first count value, a pass signal is output; When the second count value is inconsistent with the first count value, a failure signal is output.

3. The peripheral circuit according to claim 2, characterized in that, The peripheral circuit also includes: A result register, the input of which is coupled to the output of the comparator, is configured to store the failure signal when the second count value is inconsistent with the first count value.

4. The peripheral circuit according to claim 1, characterized in that, The peripheral circuit also includes: A first buffer, the output of which is coupled to the signal input of the first counter, is configured to buffer the read enable signal; The control logic, whose input is coupled to the output of the first buffer, is configured to generate the data strobe signal based on the read enable signal.

5. The peripheral circuit according to claim 4, characterized in that, The peripheral circuit also includes: A second buffer, the input of which is coupled to the control logic, is configured to buffer the data strobe signal; Wherein, the output terminal of the second buffer is coupled to the signal input terminal of the second counter; or, the output terminal of the control logic is coupled to the signal input terminal of the second counter.

6. The peripheral circuit according to claim 4, characterized in that, The peripheral circuit also includes: A clock source, the output of which is coupled to the clock input of the first counter, the clock input of the second counter, and the clock input of the comparator, respectively, and the clock source is configured to generate a clock signal; The first counter is configured to generate the first count value based on the clock signal and the read enable signal; the second counter is configured to generate the second count value based on the clock signal and the data strobe signal; the comparator is configured to compare the first count value and the second count value based on the clock signal, the first count value and the second count value.

7. The peripheral circuit according to claim 6, characterized in that, The input of the clock source is coupled to the output of the first buffer, and the clock source is configured to generate the clock signal based on the read enable signal.

8. A memory, characterized in that, include: Memory cell array; The peripheral circuitry as described in any one of claims 1 to 7, wherein the peripheral circuitry is coupled to the memory cell array and is configured to control the memory cell array.

9. A memory system, characterized in that, include: The memory as described in claim 8; A memory controller, coupled to the memory, is configured to control the memory.

10. An electronic device, characterized in that, include: The memory system of claim 9, wherein the memory system includes a memory controller; The host, coupled to the memory controller, is configured to communicate.

11. A testing device, characterized in that, The test equipment is used for testing devices including peripheral circuits as described in any one of claims 1 to 7, the test equipment comprising: The test unit is configured to send a test command to the device and receive a test result generated by the device based on the test command; wherein the test result includes the comparison result output by the comparator; An analysis unit, coupled to the test unit, is configured to determine, based on the comparison result, whether there is an anomaly in the peripheral circuit that generates the data strobe signal.

12. The testing equipment according to claim 11, characterized in that, The analysis unit is specifically configured as follows: When the comparison result indicates that the first count value and the second count value are consistent, it is determined that there is no abnormality in the peripheral circuit; When the comparison result indicates that the first count value and the second count value are inconsistent, it is determined that there is an abnormality in the peripheral circuit.

13. A testing method, characterized in that, include: During the time period of executing the preset command, a first count value is generated based on the read enable signal; wherein, the signal value of the read enable signal switches between a first signal value and a second signal value, and the first count value is used to indicate the number of times the read enable signal switches between the first signal value and the second signal value; During the time period of executing a preset command, a second count value is generated based on a data strobe signal; wherein the signal value of the data strobe signal switches between a third signal value and a fourth signal value, and the second count value is used to indicate the number of times the data strobe signal switches between the third signal value and the fourth signal value; The first count value and the second count value are compared, and the comparison result is output; the comparison result can be used to determine whether the data strobe signal is normal.

14. The test method according to claim 13, characterized in that, The comparison of the first count value and the second count value, and the output of the comparison result, includes: When the second count value matches the first count value, a pass signal is output; When the second count value is inconsistent with the first count value, a failure signal is output.

15. The test method according to claim 14, characterized in that, The testing method also includes: Store the failure signal.

16. The test method according to claim 13, characterized in that, The testing method also includes: The data strobe signal is generated based on the read enable signal.

17. The test method according to claim 13, characterized in that, The peripheral circuit includes: a clock source, the output of which is coupled to the clock input of a first counter, the clock input of a second counter, and the clock input of a comparator, respectively, and the clock source is configured to generate a clock signal; The step of generating a first count value based on the read enable signal includes: generating a first count value based on the clock signal and the read enable signal; The step of generating a second count value based on a data strobe signal includes: generating a second count value based on the clock signal and the data strobe signal; The step of comparing the first count value and the second count value based on the first count value and the second count value includes: comparing the first count value and the second count value based on the clock signal, the first count value and the second count value.

18. The test method according to claim 17, characterized in that, The testing method also includes: The clock signal is generated based on the read enable signal.

19. The test method according to claim 13, characterized in that, The preset commands include read commands.

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