Semiconductor epitaxial structure, semiconductor device and preparation method thereof

Abstract

Embodiments of the present invention provide a semiconductor epitaxial structure, a semiconductor device, and a method for fabricating the same, relating to the field of semiconductor epitaxial technology. The semiconductor epitaxial structure comprises a silicon substrate, an aluminum-rich silicon layer, and an AlN nucleation layer. The Al-rich silicon layer is formed on the silicon substrate, and then the nucleation layer is formed on the Al-rich silicon layer. The Al-rich silicon layer can inhibit the formation of amorphous SiN on the surface of the silicon substrate. Compared to the prior art, the Al-rich silicon layer prevents the silicon substrate from directly reacting with NH3 during the AlN nucleation layer formation process, thereby preventing the amorphous SiN from affecting epitaxial growth and ensuring the quality of epitaxial growth.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor epitaxial technology, and in particular to a semiconductor epitaxial structure, a semiconductor device and a preparation method thereof. Background Art

[0002] Gallium nitride (GaN)-based compound semiconductor materials are widely used in the fabrication of high-voltage, high-frequency electronic and light-emitting devices due to their wide bandgap, excellent thermal stability, radiation resistance, acid and alkali resistance, direct bandgap, and ease of forming heterojunction structures. However, due to GaN's high melting point and high nitrogen dissociation pressure, GaN substrates must be prepared under high-temperature and high-pressure conditions, resulting in small single crystal sizes that cannot meet the requirements of low-cost production. Currently, commercial GaN-based devices are typically grown on sapphire, silicon carbide, or silicon substrates using heteroepitaxial growth.

[0003] As an important GaN heteroepitaxial substrate material, Si substrates offer advantages such as high crystal quality, low substrate unit price, large size, high thermal conductivity, and controllable electrical conductivity through doping. Si substrates used for GaN epitaxy are generally (111)-faced silicon substrates because the three-dimensional symmetry of the Si (111) face facilitates the epitaxy of (0001)-face GaN. Due to the severe intermetallic solubility between silicon substrates and metallic Ga, GaN thin films cannot be grown directly on silicon substrates. Therefore, an AlN nucleation layer must be grown first. However, due to the material's specificity, when growing the AlN nucleation layer, silicon atoms on the silicon substrate surface easily react with ammonia to form a large amount of amorphous SiN, which affects the epitaxial continuity and, in turn, the quality of the epitaxial growth. Summary of the Invention

[0004] The objects of the present invention include, for example, providing a semiconductor epitaxial structure and a method for preparing a semiconductor epitaxial structure, which can inhibit the formation of amorphous SiN on the surface of a silicon substrate, improve the window period for growing high-quality AlN on a silicon substrate, and ensure epitaxial continuity, thereby improving the quality of epitaxial growth.

[0005] The embodiments of the present invention can be implemented as follows:

[0006] In a first aspect, the present invention provides a semiconductor epitaxial structure, comprising:

[0007] Silicon substrate;

[0008] an aluminum-rich silicon layer disposed on the silicon substrate;

[0009] A nucleation layer is provided on the aluminum-rich silicon layer.

[0010] In an optional embodiment, the aluminum doping concentration of the aluminum-rich silicon layer is greater than 1E19 / cm 3 and less than 1E22 / cm3 .

[0011] In an optional embodiment, the thickness of the aluminum-rich silicon layer is less than 500 nm.

[0012] In an optional embodiment, the aluminum-rich silicon layer is distributed in a patterned manner on the surface of the silicon substrate.

[0013] In a second aspect, the present invention provides a semiconductor device comprising:

[0014] Silicon substrate;

[0015] an aluminum-rich silicon layer disposed on the silicon substrate;

[0016] a nucleation layer disposed on the aluminum-silicon rich layer;

[0017] a first buffer layer located on the nucleation layer;

[0018] a second buffer layer located on the buffer layer;

[0019] and a device layer located on the buffer layer.

[0020] In an optional embodiment, the doping concentration of aluminum atoms in the aluminum-rich silicon layer is greater than 1E19 / cm 3 and less than 1E22 / cm 3 .

[0021] In an optional embodiment, the thickness of the aluminum-rich silicon layer is less than 500 nm.

[0022] In an optional embodiment, the aluminum-rich silicon layer is distributed in a patterned manner on the surface of the silicon substrate.

[0023] In an optional embodiment, the thickness of the nucleation layer is 20-500 nm; the thickness of the first buffer layer is 100-5000 nm; and the thickness of the second buffer layer is 1000 nm-5000 nm.

[0024] In a third aspect, the present invention provides a method for preparing a semiconductor epitaxial structure, comprising:

[0025] providing a silicon substrate;

[0026] forming an aluminum-rich silicon layer on a silicon substrate;

[0027] A nucleation layer is formed on the aluminum-rich silicon layer.

[0028] In an optional embodiment, the step of forming an aluminum-rich silicon layer on a silicon substrate includes:

[0029] An aluminum-rich silicon layer heavily doped with aluminum is formed on the surface of the silicon substrate by using an ion implantation process.

[0030] In an optional embodiment, the step of forming an aluminum-rich silicon layer heavily doped with aluminum on the surface of the silicon substrate by an ion implantation process includes:

[0031] Laying a patterned mask on the silicon substrate;

[0032] implanting aluminum atoms into the surface of the silicon substrate using an ion implantation process;

[0033] The patterned mask is removed.

[0034] In an optional embodiment, the step of forming an aluminum-rich silicon layer on a silicon substrate includes:

[0035] forming an aluminum layer by evaporation on the silicon substrate;

[0036] forming a silicon dioxide layer by evaporation deposition on the aluminum layer;

[0037] The aluminum layer and the silicon dioxide layer are subjected to annealing treatment to form the aluminum-rich silicon layer.

[0038] In an optional embodiment, the step of tempering the aluminum layer and the silicon dioxide layer comprises:

[0039] Laying a patterned mask on the silicon dioxide layer;

[0040] etching the silicon dioxide layer and the aluminum layer in sequence;

[0041] removing the patterned mask to obtain the patterned aluminum layer and the patterned silicon dioxide layer;

[0042] The remaining aluminum layer and the silicon dioxide layer are subjected to annealing treatment to form the patterned aluminum-rich silicon layer.

[0043] In a fourth aspect, the present invention provides a method for preparing a semiconductor device, comprising:

[0044] forming an aluminum-rich silicon layer on a silicon substrate;

[0045] forming a nucleation layer on the aluminum-rich silicon layer;

[0046] forming a first buffer layer on the AlN nucleation layer;

[0047] forming a second buffer layer on the first buffer layer;

[0048] A device layer is formed on the second buffer layer.

[0049] In an optional embodiment, the doping concentration of aluminum atoms in the aluminum-rich silicon layer is greater than 1E19 / cm 3and less than 1E22 / cm 3 .

[0050] In an optional embodiment, the thickness of the aluminum-rich silicon layer is less than 500 nm.

[0051] In an optional embodiment, the aluminum-rich silicon layer is distributed in a patterned manner on the surface of the silicon substrate.

[0052] The beneficial effects of the embodiments of the present invention include, for example:

[0053] An embodiment of the present invention provides a semiconductor epitaxial structure and a method for fabricating the same. This structure forms an aluminum-rich silicon layer on one side of a silicon substrate, and then forms an AlN nucleation layer on the side of the aluminum-rich silicon layer facing away from the silicon substrate. The aluminum-rich silicon layer inhibits the formation of amorphous SiN on the surface of the silicon substrate. Compared to existing techniques, the aluminum-rich silicon layer prevents the silicon substrate from directly reacting with NH3 during the AlN nucleation layer formation process, thereby preventing the amorphous SiN from affecting epitaxial growth and ensuring epitaxial growth quality. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying any creative work.

[0055] Figure 1 A schematic structural diagram of a semiconductor epitaxial structure provided by a first embodiment of the present invention;

[0056] Figure 2 A schematic structural diagram of a semiconductor device provided in accordance with a first embodiment of the present invention;

[0057] Figure 3 and Figure 4 A schematic diagram of a process flow of a method for preparing a semiconductor epitaxial structure provided in accordance with a second embodiment of the present invention;

[0058] Figure 5 A schematic structural diagram of a semiconductor epitaxial structure provided in the third embodiment of the present invention.

[0059] Icon: 100-semiconductor epitaxial structure; 110-silicon substrate; 130-aluminum-rich silicon layer; 131-aluminum layer; 133-silicon dioxide layer; 135-patterned groove; 150-AlN nucleation layer; 170-first buffer layer; 180-second buffer layer; 190-device layer; 200-semiconductor device. DETAILED DESCRIPTION

[0060] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings herein can be arranged and designed in various different configurations.

[0061] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention as claimed, but rather merely represents selected embodiments of the present invention. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort shall fall within the scope of protection of the present invention.

[0062] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, it does not need to be further defined or explained in subsequent drawings.

[0063] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the accompanying drawings, or is the orientation or position relationship in which the product of the invention is usually placed when in use. It is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be understood as a limitation on the present invention.

[0064] In addition, the terms "first", "second", etc., if used, are merely used to distinguish and describe, and should not be understood as indicating or implying relative importance.

[0065] As described in the background technology, in the prior art, when epitaxially growing an AlN nucleation layer on a silicon substrate, NH3 needs to be introduced into the reaction chamber, which makes NH3 easily react with silicon atoms on the surface of the silicon substrate, thereby forming amorphous SiN on the surface of the silicon substrate, affecting the subsequent epitaxial growth process.

[0066] Furthermore, the prior art also provides a solution for pre-passing an Al atomic layer on the silicon substrate to achieve blocking. However, the introduction of the Al atomic layer is usually affected by the design of the epitaxial growth equipment and the substrate temperature distribution, resulting in relatively large differences in growth parameters such as the pre-passing time of Al and the Al atomic precursor flow rate, and a small window period, making the preparation of the Al atomic layer more difficult. In addition, the preparation of the Al atomic layer usually needs to be carried out under high temperature conditions (above 400°C), and the diffusion of Al atoms into the substrate is affected by the temperature, resulting in the Al atomic layer being easily unevenly distributed, affecting the quality of epitaxial growth. At the same time, since the direct preparation of the Al atomic layer requires epitaxial growth on the Al atomic layer, its growth quality is poor, making it difficult to prepare high-quality GaN-based epitaxial films and difficult to apply in the mass production of silicon-based GaN power electronic devices.

[0067] In order to solve the above problems, the present invention provides a novel semiconductor epitaxial structure and a method for preparing the same. It should be noted that the features in the embodiments of the present invention can be combined with each other without conflict.

[0068] First embodiment

[0069] This embodiment provides a semiconductor epitaxial structure 100 that can suppress the formation of amorphous SiN on the surface of a silicon substrate 110, improve the window period for growing high-quality AlN on the silicon substrate 110, ensure epitaxial continuity, and improve epitaxial growth quality.

[0070] Please refer to Figure 1 This embodiment provides a semiconductor epitaxial structure 100, including a silicon substrate 110, an aluminum-rich silicon layer 130 and a nucleation layer 150, wherein the aluminum-rich silicon layer 130 is arranged on the silicon substrate 110, and the nucleation layer 150 is arranged on the aluminum-rich silicon layer 130, wherein the nucleation layer 150 can be an AlN nucleation layer, the aluminum-rich silicon layer 130 is located on one side of the silicon substrate 110, and the AlN nucleation layer 150 is located on the side of the aluminum-rich silicon layer 130 away from the silicon substrate 110, wherein the aluminum-rich silicon layer 130 contains at least aluminum atoms and silicon atoms, and the aluminum-rich silicon layer 130 covers the surface of the silicon substrate 110 to inhibit the formation of amorphous SiN on the surface of the silicon substrate 110.

[0071] It is worth noting that the preparation process of the AlN nucleation layer 150 here is consistent with that of the conventional epitaxial structure, and both require the introduction of NH3. However, by providing the aluminum-rich silicon layer 130 in this embodiment, it is possible to avoid the silicon substrate 110 directly reacting with NH3 during the formation of the AlN nucleation layer 150 to form amorphous SiN on the surface of the silicon substrate 110, thereby avoiding the influence of amorphous SiN on the epitaxial growth and ensuring the quality of the epitaxial growth.

[0072] It should be noted that, in this embodiment, the aluminum-rich silicon layer 130 includes aluminum atoms and silicon atoms, and can be formed specifically by doping epitaxial growth, and the aluminum-rich silicon layer 130 uniformly covers the top side surface of the silicon substrate 110, thereby preventing the silicon atoms at the top side surface of the silicon substrate 110 from reacting with NH3 to generate amorphous SiN and affecting subsequent epitaxial growth.

[0073] In this embodiment, the silicon substrate 110 may be a low-resistance (111) surface silicon substrate 110 with a thickness ranging from 500 μm to 1500 μm, and the doping concentration of the silicon substrate 110 may be in the range of 1E16 / cm 3 -1E20 / cm 3 , wherein the structure of the silicon substrate 110 is consistent with the conventional epitaxial structure and is not described in detail here. Preferably, the silicon substrate 110 here is a P-type (111) crystal plane silicon substrate 110 with a thickness of 1000um and a resistivity of 0.005ohm.cm, and the deposition method of the silicon substrate 110 may include CVD (Chemical Vapor Deposition), VPE (Vapour Phase Epitaxy), MOCVD (Metal-organic Chemical Vapor Deposition), LPCVD (Low Pressure Chemical Vapor Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), PLD (Pulsed Laser Deposition), atomic layer epitaxy, MBE (Molecular Beam Epitaxy), sputtering, evaporation, etc.

[0074] In this embodiment, the aluminum-rich silicon layer 130 includes a silicon layer heavily doped with aluminum, and the silicon layer is located on the surface of the silicon substrate 110. Specifically, the silicon layer here can be a silicon layer that is grown separately after the silicon substrate 110 is formed, and is heavily doped with aluminum during the growth process. At the same time, the silicon layer here can also be a silicon layer near the top side surface of the silicon substrate 110, and is directly doped on the top side surface of the silicon substrate 110 to form a silicon layer heavily doped with aluminum. Specifically, the doping of the aluminum-rich silicon layer 130 here can be achieved by an ion implantation process, that is, by heavily doping with Al by ion implantation and tempering to form an Al-rich silicon layer, that is, a silicon layer heavily doped with aluminum is formed.

[0075] In this embodiment, the aluminum doping concentration of the silicon layer is greater than 1E19 / cm 3 and less than 1E22 / cm 3Preferably, the Al doping concentration of 5E19 / cm2 can be prepared on the surface of the silicon substrate 110 by ion implantation. 3 Of course, the doping concentration of aluminum in the silicon layer is not specifically limited here, and the doping concentration that can suppress the formation of SiN is the limit.

[0076] In this embodiment, the thickness of the silicon layer is less than 500 nm. Preferably, the thickness of the silicon layer can be 200 nm and is located on the top side surface of the silicon substrate 110. The thickness can be determined by the ion implantation depth.

[0077] It should be noted that the silicon layer can be doped by multiple ion implantations to ensure that the doping concentration meets the requirements. In addition, the temperature during ion implantation in this embodiment can be controlled below 400°C to achieve low-temperature preparation and formation of the aluminum-rich silicon layer 130, avoiding the phenomenon of uneven diffusion of aluminum atoms and ensuring the doping uniformity of the silicon layer. The basic principles and process of the ion implantation process will not be described in detail here. For details, please refer to the ion implantation process in the prior art.

[0078] In this embodiment, the nucleation layer 150 can be grown on the surface of the aluminum-rich silicon layer 130 under high temperature conditions. In this embodiment, the nucleation layer 150 is an AlN layer. Of course, the nucleation layer 150 can also be a III-V semiconductor material that can be used for epitaxial growth. For example, the nucleation layer can be made of a III-V nitride material. The III-V nitride material can be made of In x A ly Ga 1-x-yN, where x+y≤1. The nucleation layer 150 in this embodiment is described using AlN as an example and does not serve as a limitation. In this embodiment, the AlN nucleation layer 150 can be grown at a growth temperature of 1100°C. Furthermore, the thickness of the AlN nucleation layer 150 can be 20-500 nm. Preferably, the thickness of the AlN nucleation layer 150 is 200 nm. It should be noted that the AlN nucleation layer 150 here can also be prepared by methods including CVD (Chemical Vapor Deposition), VPE (Vapour Phase Epitaxy), MOCVD (Metal-organic Chemical Vapor Deposition), LPCVD (Low Pressure Chemical Vapor Deposition), PECVD (Plasma Enhanced Chemical Vapor Deposition), PLD (Pulsed Laser Deposition), atomic layer epitaxy, MBE (Molecular Beam Epitaxy), sputtering, evaporation, etc. Preferably, in this embodiment, the AlN nucleation layer 150 can be prepared using the MOCVD (Metal-organic Chemical Vapor Deposition) process.

[0079] See also Figure 2 This embodiment further provides a semiconductor device 200, which includes the aforementioned semiconductor epitaxial structure 100, and may further include a first buffer layer 170, a second buffer layer 180, and a device layer 190, wherein the device layer 190 may be a GaN-based device layer, the first buffer layer 170 may be an AlGaN layer, and the second buffer layer 180 may be a GaN layer. Of course, the first buffer layer 170 and the second buffer layer 180 may also be other III-V semiconductor materials that can be used for epitaxial growth, for example, the first buffer layer 170 or the second buffer layer 180 may be made of a III-V nitride material, and the III-V nitride material may be made of In x A ly Ga 1-x-yN, where x+y≤1. The first buffer layer 170 is located on the side of the AlN nucleation layer 150 away from the silicon substrate 110, the second buffer layer 180 is located on the side of the first buffer layer 170 away from the silicon substrate 110, and the GaN-based device layer 190 is located on the side of the second buffer layer 180 away from the silicon substrate 110. The GaN-based device layer 190 is a HEMT device layer or an LED device layer.

[0080] In this embodiment, the thickness of the first buffer layer 170 is 100-5000 nm, and the Al composition is between 0% and 100%. The thickness of the second buffer layer 180 is 1000 nm-5000 nm.

[0081] This embodiment further provides a method for preparing a semiconductor epitaxial structure 100, which is used to prepare the aforementioned semiconductor epitaxial structure 100, and includes the following steps:

[0082] S1: forming an aluminum-rich silicon layer 130 on a silicon substrate 110 .

[0083] Specifically, a silicon substrate 110 is first provided, and then an aluminum-rich silicon layer 130 heavily doped with aluminum is formed on the surface of the silicon substrate 110 using an ion implantation process. The aluminum-rich silicon layer 130 contains at least aluminum atoms and silicon atoms, and the aluminum-rich silicon layer 130 covers the surface of the silicon substrate 110 to inhibit the formation of amorphous SiN on the surface of the silicon substrate 110.

[0084] It should be noted that here, the surface of the silicon substrate 110 may be heavily doped with aluminum by a low-temperature (below 400° C.) ion implantation process, thereby forming a heavily aluminum-doped aluminum-rich silicon layer 130 .

[0085] In other preferred embodiments of the present invention, the aluminum-rich silicon layer 130 can also be patterned and distributed on the surface of the silicon substrate 110, wherein the patterning of the aluminum-rich silicon layer 130 can be formed by local ion implantation. For example, a patterned mask can be set on the silicon substrate 110, and then an ion implantation process can be performed, so as to achieve local implantation and patterning of the aluminum-rich silicon layer 130, so that a similar patterned substrate effect can be formed during the subsequent growth of the nucleation layer 150, thereby reducing the dislocation density and improving the crystal quality.

[0086] S2 : forming a nucleation layer 150 on the aluminum-rich silicon layer 130 .

[0087] Specifically, the AlN nucleation layer 150 may be prepared using a MOCVD (Metal-organic Chemical Vapor Deposition) process. For example, at a growth temperature of 1100° C., a 200 nm thick AlN nucleation layer 150 may be formed on the surface of the silicon layer.

[0088] When actually growing the AlN nucleation layer 150, the silicon dioxide on the surface of the aluminum-rich silicon layer 130 can be first desorbed at high temperature, and then the AlN nucleation layer 150 can be grown on the surface of the aluminum-rich silicon layer 130. Specifically, the surface silicon dioxide layer 133 can be desorbed at high temperature using an MOCVD process to improve the quality of epitaxial growth.

[0089] This embodiment further provides a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device also needs to perform the aforementioned steps S1 and S2. After step S2, the method for manufacturing a semiconductor device may further include the following steps:

[0090] S3: forming a first buffer layer 170 on the nucleation layer 150;

[0091] S4: forming a second buffer layer 180 on the first buffer layer 170;

[0092] S5 : forming a device layer 190 on the second buffer layer 180 .

[0093] Specifically, a first buffer layer 170 is first formed on the surface of the AlN nucleation layer 150 using an MOCVD process. The Al content of the buffer layer gradually decreases along the epitaxial growth direction, and the thickness of the AlGaN layer ranges from 100 to 5000 nm. A second buffer layer 180 is then grown on the AlGaN layer using an MOCVD process, with a thickness ranging from 1000 nm to 5000 nm. Finally, a GaN-based device layer 190, i.e., a HEMT device layer or an LED device layer, is grown on the second buffer layer 180. The HEMT device layer includes a GaN channel layer, an AlGaN barrier layer, and a GaN cap layer, while the LED device layer includes an n-type GaN layer, a GaN-based multi-quantum well layer, and a p-type GaN layer.

[0094] The actual process steps and growth conditions of the method for preparing the semiconductor device 200 are described below:

[0095] Step 1: Select a P-type (111) crystal silicon substrate 110 with a thickness of 1000 μm and a resistivity of 0.005 ohm.cm;

[0096] Step 2: Prepare a 200nm thick Al-doped 5E19 / cm2 layer on the surface of the silicon substrate 110 by ion implantation. 3 The heavily doped Al-rich layer is tempered;

[0097] Step 3: using MOCVD to grow a high-temperature AlN nucleation layer 150 on the surface of the Al-rich Si layer 130 at a growth temperature of 1100° C. and a thickness of 200 nm;

[0098] Step 4: Continue to grow the first buffer layer 170 on the surface of the AlN nucleation layer 150 after step 3, that is, grow an AlGaN layer. The total thickness of the first buffer layer 170 is 2000nm, including 300nm of high Al component Al 0.8 Ga 0.2 N, 800nm ​​Al component Al 0.5 Ga 0.5 N and 900nm low Al component Al 0.2 Ga 0.8 N;

[0099] Step 5: Continue growing a 1500nm thick GaN high-resistance layer on the first buffer layer 170 completed in step 4, i.e., growing the second buffer layer 180, at a growth temperature of 970°C;

[0100] Step 6: Grow the HEMT device layer on the second buffer layer 180. The device layer includes: a 300nm channel layer, a 20nm Al 0.25 Ga 0.75 N barrier layer and 3nm GaN cap layer.

[0101] In summary, the semiconductor epitaxial structure 100, semiconductor device 200, and fabrication method thereof provided in this embodiment form an aluminum-rich silicon layer 130 on one side of a silicon substrate 110 using an ion implantation process, and then form an AlN nucleation layer 150 on the side of the aluminum-rich silicon layer 130 away from the silicon substrate 110. The aluminum-rich silicon layer 130 is a silicon layer heavily doped with aluminum, and the aluminum-rich silicon layer 130 covers the surface of the silicon substrate 110 to inhibit the formation of amorphous SiN on the surface of the silicon substrate 110. By providing the aluminum-rich silicon layer 130, the embodiment of the present invention prevents the silicon substrate 110 from directly reacting with NH3 during the formation of the AlN nucleation layer 150, thereby preventing the amorphous SiN from affecting the epitaxial growth and ensuring the quality of the epitaxial growth.

[0102] Second embodiment

[0103] See also Figure 1 and Figure 3 This embodiment provides a semiconductor epitaxial structure 100. Its basic structure, principles, and technical effects are the same as those of the first embodiment. For the sake of brevity, any details not mentioned in this embodiment may be referred to the corresponding contents of the first embodiment. The difference from the first embodiment is the preparation method of the aluminum-rich silicon layer 130.

[0104] In this embodiment, see Figure 3 and Figure 4The aluminum-rich silicon layer 130 is formed by high-temperature tempering of the aluminum layer 131 and the silicon dioxide layer 133. Specifically, the aluminum layer 131 can be first formed on the surface of the silicon substrate 110, and then a silicon dioxide layer 133 can be formed on the surface of the aluminum layer 131. Then, high-temperature tempering is performed. This can also form the aluminum-rich silicon layer 130 and inhibit the formation of amorphous SiN on the surface of the silicon substrate 110. Among them, the silicon dioxide layer 133 can play a good protective role. Of course, the silicon dioxide layer 133 here can also be replaced by a single silicon layer, which can also play a good protective role.

[0105] In this embodiment, an aluminum layer 131 is formed on the surface of the silicon substrate 110 by evaporation, and then a layer of silicon dioxide is evaporated to provide protection. The thickness of the aluminum layer 131 is less than 10 nm to prevent excessive thickness of the aluminum layer 131 from affecting the quality of epitaxial growth. Preferably, the thickness of the aluminum layer 131 can be 3 nm, and the thickness of the silicon dioxide layer 133 can be 20 nm.

[0106] This embodiment also provides a method for fabricating a semiconductor epitaxial structure 100. The basic steps, principles, and technical effects of this method are the same as those of the first embodiment. For the sake of brevity, any details not mentioned in this embodiment are referenced to the corresponding contents of the first embodiment. The only difference from the first embodiment is the method for forming the aluminum-rich silicon layer 130.

[0107] In this embodiment, the preparation method includes step S1: forming an aluminum-rich silicon layer 130 on the surface of the silicon substrate 110. Figure 3 and Figure 4 First, an aluminum layer 131 and a silicon dioxide layer 133 are sequentially evaporated on the surface of the silicon substrate 110 ; then the aluminum layer 131 and the silicon dioxide layer 133 are subjected to a high-temperature annealing treatment to form an aluminum-rich silicon layer 130 .

[0108] The actual process steps and growth conditions of the method for preparing the semiconductor epitaxial structure 100 provided in this embodiment are described below:

[0109] Step 1: Select a P-type (111) crystal silicon substrate 110 with a thickness of 1000 μm and a resistivity of 0.005 ohm.cm.

[0110] Step 2: A 3nm thick metal Al layer is evaporated on the surface of the substrate, and then a 20nm thick SiO2 protective layer is evaporated on the surface of the Al layer.

[0111] Step 3: Tempering the completed silicon dioxide layer 133 and decomposing the silicon dioxide on the surface in a high-temperature hydrogen environment to form an aluminum-rich silicon layer 130 .

[0112] Step 4: using MOCVD to grow a high-temperature AlN nucleation layer 150 on the surface of the Al-rich Si layer 130 formed in step 3, with a growth temperature of 1100° C. and a thickness of 200 nm;

[0113] Step 5: Continue to grow the first buffer layer 170 on the surface of the AlN nucleation layer 150. The total thickness of the first buffer layer 170 is 1500nm, including 200nm of high Al component Al 0.8 Ga 0.2 N, 600nm Al component Al 0.5 Ga 0.5 N and 700nm low Al component Al 0.2 Ga 0.8 N.

[0114] Step 6: Continue growing a 2000 nm thick GaN high-resistance layer on the first buffer layer 170 , i.e., growing the second buffer layer 180 , at a growth temperature of 970° C.;

[0115] Step 7: Grow the HEMT device layer on the second buffer layer 180. The device layer includes: 200nm channel layer, 15nmA l0.2 Ga 0.8 N barrier layer and 100nm P-type doped GaN cap layer.

[0116] The semiconductor epitaxial structure 100 and the preparation method thereof provided in this embodiment utilize sequential evaporation of an aluminum layer 131 and a silicon dioxide layer followed by annealing to form an aluminum-rich silicon layer 130. This can also prevent the silicon substrate 110 from directly reacting with NH3 to form amorphous SiN on the surface of the silicon substrate 110 during the formation of the AlN nucleation layer 150, thereby preventing the amorphous SiN from affecting the epitaxial growth and ensuring the quality of the epitaxial growth.

[0117] Third embodiment

[0118] See also Figure 5 This embodiment provides a semiconductor epitaxial structure 100. Its basic structure, principles, and technical effects are the same as those of the first or second embodiment. For the sake of brevity, any details not mentioned in this embodiment may be referred to the corresponding contents of the first or second embodiment. Compared with the first or second embodiment, this embodiment differs in the structure and preparation method of the aluminum-rich silicon layer 130.

[0119] In this embodiment, the aluminum-rich silicon layer 130 is patterned and distributed on the surface of the silicon substrate 110. After forming the aluminum layer 131 and the silicon dioxide layer 133, a patterned mask can be set on the silicon dioxide layer 133, and the silicon dioxide layer 133 and the aluminum layer 131 can be etched in sequence to form patterned grooves 135, thereby achieving patterning of the aluminum-rich silicon layer 130. Specifically, the aluminum-rich silicon layer 130 can be provided with patterned grooves 135, and the patterned grooves 135 pass through the silicon substrate 110. Specifically, after forming the aluminum-rich silicon layer 130, a nano-pattern can be etched on the silicon dioxide surface using a photolithography process, and the aluminum layer 131 under the etched silicon dioxide can be removed by wet etching, thereby achieving patterning of the aluminum-rich silicon layer 130.

[0120] It should be noted that in this embodiment, after patterning the surface of the aluminum-rich silicon layer 130 to form patterned grooves 135, silicon nitride can be locally generated when growing the AlN nucleation layer 150 to form a patterned substrate-like effect, thereby reducing interface dislocations and improving the crystal quality of subsequent epitaxial layers.

[0121] This embodiment also provides a method for fabricating a semiconductor epitaxial structure 100. The method is used to fabricate the aforementioned semiconductor epitaxial structure 100. The basic steps, principles, and technical effects of this method are the same as those of the first embodiment. For the sake of brevity, any details not mentioned in this embodiment may be referred to the corresponding contents of the first or second embodiment. The difference between this embodiment and the first or second embodiment lies in the method for forming the aluminum-rich silicon layer 130.

[0122] In this embodiment, the preparation method includes step S1: forming an aluminum-rich silicon layer 130 on the surface of a silicon substrate 110. Specifically, an aluminum layer 131 and a silicon dioxide layer 133 are first formed on the surface of the silicon substrate 110 by sequentially evaporating the aluminum layer 131 and the silicon dioxide layer 133; then, the aluminum layer 131 and the silicon dioxide layer 133 are annealed to form the aluminum-rich silicon layer 130; and then, the surface of the aluminum-rich silicon layer 130 is patterned using a photolithography process, thereby forming patterned grooves 135 on the surface of the aluminum-rich silicon layer 130.

[0123] The actual process steps and growth conditions of the method for preparing the semiconductor epitaxial structure 100 provided in this embodiment are described below:

[0124] Step 1: Select a P-type (111) crystal silicon substrate 110 with a thickness of 1000 μm and a resistivity of 0.005 ohm.cm;

[0125] Step 2: Vapor-deposit a 3nm thick metal Al layer on the surface of the substrate, and then vapor-deposit a 20nm thick SiO2 protective layer on the surface of the Al layer;

[0126] Step 3: Use photolithography to etch nano-patterns on the silicon dioxide surface, use wet etching to remove the metal Al layer under the SiO2 protective layer, clean the epitaxial wafer and spin dry to seal;

[0127] Step 4: Temper the patterned Al nanolayer prepared in step 3 by MOCVD at elevated temperature and decompose SiO2 on the surface in a high-temperature hydrogen environment to expose the patterned Al-rich silicon layer 130;

[0128] Step 5: Using MOCVD to grow a high-temperature AlN nucleation layer 150 on the surface of the Al-rich Si layer 130 patterned in step 4, at a growth temperature of 1100° C. and a thickness of 200 nm;

[0129] Step 6: Continue to grow the first buffer layer 170 on the surface of the AlN nucleation layer 150. The total thickness of the first buffer layer 170 is 1500nm, including 200nm of high Al component Al 0.8 Ga 0.2 N, 600nm Al component Al 0.5 Ga 0.5 N and 700nm low Al component Al 0.2 Ga 0.8 N;

[0130] Step 7: Continue growing a 2000 nm thick GaN high-resistance layer on the first buffer layer 170 , i.e., growing the second buffer layer 180 , at a growth temperature of 970° C.;

[0131] Step 8: Grow the HEMT device layer on the second buffer layer 180. The device layer includes: 200nm channel layer, 15nmAl 0.20 Ga 0.80 N barrier layer and 100nm P-type doped GaN cap layer.

[0132] The semiconductor epitaxial structure 100 and the preparation method thereof provided in this embodiment can form a patterned substrate-like effect when the AlN nucleation layer 150 grows by patterning the surface of the Al-rich silicon layer 130 , thereby reducing dislocation density and improving crystal quality.

[0133] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present invention should be included in the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be based on the scope of protection of the claims.

Claims

1. A semiconductor epitaxial structure, characterized in that: include: Silicon substrate; an aluminum-rich silicon layer disposed on the silicon substrate; a nucleation layer disposed on the aluminum-silicon rich layer; Wherein, the aluminum-rich silicon layer comprises a heavily aluminum-doped silicon layer, and the heavily aluminum-doped silicon layer is located on the surface of the silicon substrate; Wherein, the nucleation layer is a group III nitride, and the doping concentration of aluminum atoms in the aluminum-rich silicon layer is greater than 1E19 / cm 3 and less than 1E22 / cm 3 , and the thickness of the aluminum-rich silicon layer is greater than or equal to 200 nm and less than 500 nm.

2. The semiconductor epitaxial structure according to claim 1, wherein: The aluminum-rich silicon layer is distributed in a patterned manner on the surface of the silicon substrate.

3. A semiconductor device, characterized in that include: Silicon substrate; an aluminum-rich silicon layer disposed on the silicon substrate; a nucleation layer disposed on the aluminum-silicon rich layer; a first buffer layer located on the nucleation layer; a second buffer layer located on the buffer layer; and, a device layer located on the buffer layer; Wherein, the aluminum-rich silicon layer comprises a heavily aluminum-doped silicon layer, and the heavily aluminum-doped silicon layer is located on the surface of the silicon substrate; Wherein, the nucleation layer is a group III nitride, and the doping concentration of aluminum atoms in the aluminum-rich silicon layer is greater than 1E19 / cm 3 and less than 1E22 / cm 3 , and the thickness of the aluminum-rich silicon layer is greater than or equal to 200 nm and less than 500 nm.

4. The semiconductor device according to claim 3, wherein The aluminum-rich silicon layer is distributed in a patterned manner on the surface of the silicon substrate.

5. A method for preparing a semiconductor epitaxial structure, characterized in that: include: providing a silicon substrate; forming an aluminum-rich silicon layer on a silicon substrate; forming a nucleation layer on the aluminum-rich silicon layer; Wherein, the aluminum-rich silicon layer comprises a heavily aluminum-doped silicon layer, and the heavily aluminum-doped silicon layer is located on the surface of the silicon substrate; Wherein, the nucleation layer is a group III nitride, and the doping concentration of aluminum atoms in the aluminum-rich silicon layer is greater than 1E19 / cm 3 and less than 1E22 / cm 3 , and the thickness of the aluminum-rich silicon layer is greater than or equal to 200 nm and less than 500 nm.

6. The method for preparing a semiconductor epitaxial structure according to claim 5, wherein: The step of forming an aluminum-rich silicon layer on a silicon substrate comprises: An aluminum-rich silicon layer heavily doped with aluminum is formed on the surface of the silicon substrate by using an ion implantation process.

7. The method for preparing a semiconductor epitaxial structure according to claim 6, wherein: The step of forming an aluminum-rich silicon layer heavily doped with aluminum on the surface of the silicon substrate by an ion implantation process comprises: Laying a patterned mask on the silicon substrate; implanting aluminum atoms into the surface of the silicon substrate using an ion implantation process; The patterned mask is removed.

8. A method for preparing a semiconductor device, characterized in that: include: forming an aluminum-rich silicon layer on a silicon substrate; forming a nucleation layer on the aluminum-rich silicon layer; forming a first buffer layer on the nucleation layer; forming a second buffer layer on the first buffer layer; forming a device layer on the second buffer layer; Wherein, the aluminum-rich silicon layer comprises a heavily aluminum-doped silicon layer, and the heavily aluminum-doped silicon layer is located on the surface of the silicon substrate; Wherein, the nucleation layer is a group III nitride, and the doping concentration of aluminum atoms in the aluminum-rich silicon layer is greater than 1E19 / cm 3 and less than 1E22 / cm 3 , and the thickness of the aluminum-rich silicon layer is greater than or equal to 200 nm and less than 500 nm.

9. The method for preparing a semiconductor device according to claim 8, wherein: The aluminum-rich silicon layer is distributed in a patterned manner on the surface of the silicon substrate.

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