A reference voltage source based on IGZO thin film transistor and its preparation method

Abstract

The present invention provides a method for preparing a reference voltage source based on an IGZO thin-film transistor, comprising: obtaining a substrate; forming a gate electrode layer on the substrate; forming a gate dielectric layer on the gate electrode layer; forming an IGZO active layer on the gate dielectric layer; forming a source electrode and a drain electrode on the IGZO active layer; and forming a depletion-mode thin-film transistor by locally treating the IGZO active layer of the thin-film transistor with hydrogen plasma. The hydrogen plasma treatment process achieves hydrogen doping, increasing the channel carrier concentration and transforming the n-type enhancement-mode IGZO thin-film transistor into an n-type depletion-mode IGZO thin-film transistor. This process is simple, rapid, highly compatible, and easily achievable in large-scale production. The present invention also provides a reference voltage source based on an IGZO thin-film transistor, comprising a current source subcircuit and a reference voltage subcircuit. This improves upon the traditional CMOS topology by innovatively utilizing n-type IGZO thin-film transistors operating in both enhancement and depletion modes to achieve a low-linear-sensitivity reference voltage source.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic devices and their preparation, in particular to an IGZO thin film transistor-based reference voltage source and a preparation method thereof. Background Art

[0002] Flexible electronics, an emerging electronics technology that fabricates electronic devices such as metal oxides, organic materials, and carbon nanotubes on flexible, stretchable substrates, has garnered widespread attention from both academia and industry. Power management (PM) is an essential technology in electronic systems, and a voltage reference source, which provides a stable reference voltage for downstream circuits, is indispensable in this system. However, due to the lack of flexible voltage reference sources, current power management systems for flexible electronic products still rely heavily on traditional solid-state devices, preventing true "full flexibility." Therefore, a stable and reliable flexible voltage reference source is urgently needed.

[0003] Since traditional silicon-based devices cannot be "flexible", metal oxide thin-film transistors have become their most promising alternative. In addition to good flexibility, metal oxide thin-film transistors also have advantages such as higher mobility and lower preparation temperature. Indium gallium zinc oxide (IGZO) is a mainstream active layer material in metal oxide thin-film transistors. It has advantages such as high mobility and low off-state current, making it an ideal semiconductor material for the preparation of flexible electronic products. The traditional reference voltage source topology adopts a CMOS structure, but the current process and preparation process make it difficult to manufacture p-type IGZO thin-film transistors with good performance. Therefore, it is unrealistic to simply apply the CMOS topology and replace the devices with corresponding n-type and p-type IGZO thin-film transistors in order to prepare a reference voltage source. In existing research, there are no reports on reference voltage sources based on IGZO thin-film transistors.

[0004] Therefore, how to realize a reference voltage source based on IGZO thin-film transistors is a difficult problem in the process of achieving "full flexibility" in electronic products. Solving this problem is of great significance to the development of flexible electronics. Summary of the Invention

[0005] In order to solve the current problem of lack of flexible reference voltage source, the present invention provides a reference voltage source based on IGZO thin film transistor and a preparation method thereof.

[0006] The present invention adopts the following technical solutions:

[0007] A method for preparing a reference voltage source based on an IGZO thin film transistor comprises the following steps:

[0008] obtaining a substrate;

[0009] forming a gate electrode layer on the substrate;

[0010] forming a gate dielectric layer on the gate electrode layer;

[0011] forming an IGZO active layer on the gate dielectric layer;

[0012] forming a source electrode and a drain electrode on the IGZO active layer to form an enhancement-mode depletion-mode thin film transistor;

[0013] The IGZO active layer of the thin film transistor is locally treated with hydrogen plasma to form a depletion-mode thin film transistor.

[0014] As an embodiment of the present invention, the gate electrode layer is a molybdenum (Mo) metal layer with excellent conductivity, and is manufactured using a magnetron sputtering process. The gate electrode thickness is 100 nm.

[0015] As an embodiment of the present invention, the gate dielectric layer is made of silicon oxide and is manufactured using a PECVD process. The thickness of the prepared gate dielectric layer is 100 nm.

[0016] As an embodiment of the present invention, the IGZO active layer is prepared by a magnetron sputtering process and has a thickness of 20 nm.

[0017] As an embodiment of the present invention, the IGZO active layer is annealed at 350° C. for 1 hour in an Ar gas environment.

[0018] As an embodiment of the present invention, the source and drain are aluminum (Al) metal layers with excellent conductivity, and are manufactured using an electron beam evaporation process.

[0019] As an embodiment of the present invention, when performing local hydrogen plasma treatment on the IGZO active layer of the thin film transistor, the hydrogen plasma flow rate is 170 sccm and the process temperature is 30°C.

[0020] And, a reference voltage source based on an IGZO thin film transistor, comprising a current source subcircuit and a reference voltage subcircuit.

[0021] The current source subcircuit includes a first power dissipation transistor (D1), a second power dissipation transistor (D2), a first enhancement transistor (M1), a second enhancement transistor (M2), and a feedback transistor (MR1). The first power dissipation transistor (D1) has a drain connected to a power supply (VDD), a gate connected to a gate of a second power dissipation transistor (D2), and a source connected to the drain of the first enhancement transistor (M1); the second power dissipation transistor (D2) has a drain connected to a power supply (VDD), and both its gate and source are connected to the drain of the second enhancement transistor (M2); the first enhancement transistor (M1) has a drain and gate connected to the gate of the second enhancement transistor (M2), and its source is grounded (GND); the second enhancement transistor (M2) has a source connected to the drain of the feedback transistor (MR1); and the feedback transistor (MR1) has a source connected to the ground (GND).

[0022] The reference voltage subcircuit includes a third power transistor (D3), a fourth power transistor (D4), a fifth power transistor (D5), a third enhancement transistor (M3), a fourth enhancement transistor (M4), a fifth enhancement transistor (M5), a sixth enhancement transistor (M6), and a seventh enhancement transistor (M7). Among them: the third power transistor (D3) has a drain connected to the power supply (VDD), a gate connected to the gate of the fourth power transistor (D4) and the gate of the fifth power transistor (D5), and a source connected to the drain of the third enhancement transistor (M3); the fourth power transistor (D4) has a drain connected to the power supply (VDD), and a source connected to the drain of the fifth enhancement transistor (M5); the fifth power transistor (D5) has a drain connected to the power supply (VDD), and a source connected to the reference voltage output terminal (Vref); the third enhancement transistor (M3) has a gate connected to the power supply (VDD), and a source connected to the reference voltage output terminal (Vref); The first circuit of the first transistor (M4) is connected to the gate of the fourth enhancement tube (M4), and the source is connected to the drain of the fourth enhancement tube (M4); the fourth enhancement tube (M4) has a drain connected to the source of the sixth enhancement tube (M6), and the source is grounded (GND); the fifth enhancement tube (M5) has a gate connected to the gate of the sixth enhancement tube (M6), and the source is connected to the drain of the sixth enhancement tube (M6); the sixth enhancement tube (M6) has a drain connected to the source of the seventh enhancement tube (M7); the seventh enhancement tube (M7) has a gate and a drain both connected to a reference voltage output terminal (Vref).

[0023] The connection between the current source subcircuit and the reference voltage subcircuit is achieved by connecting the gate of the feedback tube (MR1) to the reference voltage output terminal (Vref) and connecting the gate of the first consumption tube (D1) to the gate of the third consumption tube (D3).

[0024] The beneficial effects of the present invention are as follows: the traditional CMOS topology of the reference voltage source is improved, and n-type IGZO thin-film transistors in both enhancement and depletion working modes are innovatively utilized to realize a high-performance reference voltage source; hydrogen doping is achieved through hydrogen plasma treatment to increase the carrier concentration in the channel, thereby converting the n-type enhancement-mode IGZO thin-film transistor into an n-type depletion-mode IGZO thin-film transistor; the process flow is simple, fast, and has good compatibility; and the gas source is easily available, facilitating large-scale production. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly and concisely illustrate the embodiments of the present invention, the present invention provides a number of drawings. The additional details or examples used to describe the drawings should not be considered to limit the scope of the disclosed invention, the presently described embodiments and / or examples, and any of the best modes of these inventions currently understood.

[0026] Figure 1 1 is a circuit diagram of a reference voltage source based on an IGZO thin film transistor in one embodiment of the present invention;

[0027] Figure 2 This is a flow chart of a method for preparing a reference voltage source based on an IGZO thin film transistor in one embodiment;

[0028] Figure 3 is a schematic structural diagram of an n-type enhancement mode IGZO thin film transistor in one embodiment;

[0029] Figure 4 is a schematic structural diagram of an n-type depletion-mode IGZO thin film transistor in one embodiment;

[0030] Figure 5 4 is a curve diagram showing the relationship between the power supply voltage and the reference voltage according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] To facilitate understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings.

[0032] Attachment Figure 1 Examples of the present invention are provided in the accompanying drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these examples are provided to provide the reader with a more thorough and comprehensive understanding of the present disclosure. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one skilled in the art to which this invention belongs.

[0033] Figure 1 FIG1 is a circuit diagram of a reference voltage source based on an IGZO thin film transistor in one embodiment of the present invention. Figure 2This is a flow chart of a method for preparing a reference voltage source based on an IGZO thin film transistor in an embodiment. The method can be used to prepare Figure 1 The reference voltage source based on the IGZO thin film transistor shown includes the following steps:

[0034] S10, obtaining a substrate.

[0035] The substrate can be a rigid substrate (e.g., glass) or a flexible substrate known in the art. In one embodiment of the present invention, the substrate is a semiconductor substrate, such as a silicon / silicon oxide substrate. The substrate is ultrasonically cleaned in deionized water, acetone, anhydrous ethanol, and deionized water, in that order, at a power of 100 W for five minutes each, to obtain a substrate suitable for subsequent operations.

[0036] S20, forming a gate electrode layer on the substrate.

[0037] In one embodiment of the present invention, a patterned photoresist is obtained by performing a coating process on the surface of the substrate (S10), performing photolithography, drying, exposing, and developing processes, and a stripper is used to treat any residual adhesive that may exist in the patterned area. A molybdenum metal layer is formed on the substrate (where the patterned photoresist exists on the substrate surface) using a magnetron sputtering process, and a patterned gate electrode layer is further obtained using a lift-off process. Other materials / structures known in the art may also be used as the gate electrode layer. In this embodiment, the thickness of the prepared gate electrode layer is 100 nm.

[0038] S30 , forming a gate dielectric layer on the gate electrode layer.

[0039] In this embodiment, a gate dielectric layer made of silicon dioxide is deposited on the gate electrode layer (S20) using a PECVD process. The PECVD process parameters used in this embodiment are as follows: operating pressure of 1000 mTorr, a flow ratio of 710:170 of N2O and 5% SiH4, power of 100 W, and reaction temperature of 300°C. In this embodiment, the gate dielectric layer is 100 nm thick.

[0040] S40 , forming an IGZO active layer on the gate dielectric layer.

[0041] In this embodiment, an IGZO active layer is formed on the gate dielectric layer (S30) using a radio frequency magnetron sputtering process. The reaction conditions used in this embodiment are as follows: a sputtering pressure of 0.5 Pa, an Ar and O2 ratio of 45:5, a sputtering power of 80 W, and a sputtering time of 1000 s. A patterned photoresist is obtained by performing a coating, photolithography, drying, exposure, and development process on the surface of the IGZO active layer. The IGZO active layer is then etched using dilute hydrochloric acid (~1%) (a patterned photoresist is present on the surface of the IGZO active layer at this point). After a stripping process, the patterned IGZO active layer is obtained, and an annealing process is then performed. The annealing conditions in this embodiment are as follows: a temperature of 350°C, an Ar atmosphere, and an annealing time of 1 hour. In this embodiment, the thickness of the prepared IGZO active layer is 20 nm.

[0042] S50, forming a source electrode and a drain electrode on the IGZO active layer.

[0043] In this embodiment, an aluminum (Al) metal layer is covered on the surface of the IGZO active layer (S40) using an electron beam evaporation process. A patterned photoresist is obtained on the surface of the Al metal layer through coating, photolithography, drying, exposure and development. The Al metal layer is etched using an aluminum (Al) etching solution (a patterned photoresist is present on the surface of the Al metal layer at this time). After de-bonding, a source and a drain are formed on the surface of the IGZO active layer. Both are made of aluminum (Al). In other embodiments, other materials known in the art can also be used as the source / drain material. In this embodiment, the thickness of the prepared source and drain is 100 nm.

[0044] At the end of step S50, the n-type enhanced IGZO thin film transistor is completed, and its structure is as follows: Figure 3 As shown, it includes a substrate 110 , a gate electrode layer 120 , a gate dielectric layer 130 , an IGZO active layer 140 , a source 150 and a drain 152 .

[0045] S60 , performing a local hydrogen plasma treatment on the IGZO active layer of the thin film transistor to form a depletion-mode thin film transistor.

[0046] In this embodiment, a hydrogen doping window is created on the surface of the IGZO active layer through photoresist, photolithography, exposure, and development. Hydrogen plasma treatment is then applied to the surface to increase the carrier concentration, forming a depletion-mode thin-film transistor. The hydrogen plasma treatment process conditions are: a reaction power of 1000W, a chamber pressure of 1200mTorr, a hydrogen flow rate of 170sccm, a reaction temperature of 350°C, and a reaction time of 200s.

[0047] At the end of step S60, the n-type depletion-type IGZO thin film transistor is completed, and its structure is as follows: Figure 4 As shown, it includes a substrate 210 , a gate electrode layer 220 , a gate dielectric layer 230 , an IGZO active layer 240 , a normally-on channel 242 , a source 250 and a drain 252 .

[0048] The present invention also provides a reference voltage source based on IGZO thin film transistors, such as Figure 1 As shown, the technical solution includes: a current source subcircuit and a reference voltage subcircuit.

[0049] The current source subcircuit includes a first dissipation transistor (D1), a second dissipation transistor (D2), a first enhancement transistor (M1), a second enhancement transistor (M2), and a feedback transistor (MR1).

[0050] A first power transistor (D1) has a drain connected to a power supply (VDD), a gate connected to a gate of a second power transistor (D2), and a source connected to a drain of a first enhancement transistor (M1);

[0051] The second drain (D2) has a drain connected to the power supply (VDD), and a gate and a source both connected to the drain of the second enhancement tube (M2);

[0052] The drain and gate of the first enhancement tube (M1) are both connected to the gate of the second enhancement tube (M2), and the source is grounded (GND);

[0053] The second enhancement tube (M2) has a source connected to the drain of the feedback tube (MR1);

[0054] Feedback tube (MR1), source grounded (GND).

[0055] The reference voltage subcircuit includes a third consumption transistor (D3), a fourth consumption transistor (D4), a fifth consumption transistor (D5), a third enhancement transistor (M3), a fourth enhancement transistor (M4), a fifth enhancement transistor (M5), a sixth enhancement transistor (M6), and a seventh enhancement transistor (M7).

[0056] The third power transistor (D3) has a drain connected to the power supply (VDD), a gate connected to the gate of the fourth power transistor (D4) and the gate of the fifth power transistor (D5), and a source connected to the drain of the third enhancement transistor (M3);

[0057] The fourth drain (D4) has a drain connected to the power supply (VDD) and a source connected to the drain of the fifth enhancement tube (M5);

[0058] a fifth drain (D5) having a drain connected to the power supply (VDD) and a source connected to the reference voltage output terminal (Vref);

[0059] The third enhancement tube (M3) has a gate connected to the gate of the fourth enhancement tube (M4), and a source connected to the drain of the fourth enhancement tube (M4);

[0060] The fourth enhancement tube (M4) has a drain connected to the source of the sixth enhancement tube (M6), and the source is grounded (GND);

[0061] A fifth enhancement tube (M5), whose gate is connected to the gate of the sixth enhancement tube (M6), and whose source is connected to the drain of the sixth enhancement tube (M6);

[0062] The sixth enhancement tube (M6) has a drain connected to the source of the seventh enhancement tube (M7);

[0063] The gate and drain of the seventh enhancement tube (M7) are both connected to the reference voltage output terminal (Vref).

[0064] The connection between the current source subcircuit and the reference voltage subcircuit is achieved by connecting the gate of the feedback tube (MR1) to the reference voltage output terminal (Vref) and connecting the gate of the first consumption tube (D1) to the gate of the third consumption tube (D3).

[0065] The principle of a reference voltage source based on an IGZO thin-film transistor is as follows: the circuit consists of a current source subcircuit and a reference voltage subcircuit; the current source subcircuit adopts a classic self-biased current mirror structure, replacing the p-type transistor therein with an n-type depletion-type IGZO thin-film transistor, thereby generating a current (i.e., PTAT current) that does not vary with the supply voltage (VDD) and whose magnitude is proportional to the absolute temperature; at the same time, considering the process limitations of circuit integration and actual IGZO thin-film transistors, the resistor used to constrain the current magnitude in the self-biased current mirror structure is replaced with the feedback tube MR1 in the circuit of the present invention; the current is generated by the current source subcircuit composed of the consumption tubes D3 to D5 and the consumption tubes D1 to D2. A mirror is used to copy the PTAT current from the current source subcircuit to the reference voltage subcircuit. Except for the feedback tube MR1 operating in the amplification region, the other transistors in the reference voltage source operate in the subthreshold region, so the power consumption of the circuit is extremely small. The gate-source voltage of the enhancement tubes M3 to M7 and the feedback tube MR1 form a closed loop, so that the reference voltage subcircuit generates two voltages with opposite temperature coefficients (TC), namely, the threshold voltage of the thin film transistor with a negative temperature coefficient and the thermal voltage with a positive temperature coefficient. The sum of the temperature coefficients of the two is zero, thereby generating a reference voltage Vref with a zero temperature coefficient. The reference voltage Vref has low temperature sensitivity and linear sensitivity.

[0066] Figure 5 is a graph showing the relationship between the power supply voltage and the reference voltage according to an embodiment of the present invention, wherein the horizontal axis is the power supply voltage V DD The vertical axis is the size of the reference voltage Vref. It can be seen that the supply voltage V DDWhen the voltage Vref changes from 4V to 20V, the reference voltage Vref also changes from 1.4767V to 1.732V, with very good linear sensitivity of approximately 15.8mV / V within the specified supply voltage range. The embodiment provided by the present invention has excellent performance and successfully implements a reference voltage source based on IGZO thin-film transistors.

Claims

1. A reference voltage source based on an IGZO thin film transistor, characterized in that: include: a current source subcircuit and a reference voltage subcircuit; The current source sub-circuit comprises a first depletion-type IGZO thin-film transistor (D1), a second depletion-type IGZO thin-film transistor (D2), a first enhancement-type IGZO thin-film transistor (M1), a second enhancement-type IGZO thin-film transistor (M2), and a feedback tube (MR1), wherein: a first depletion-mode IGZO thin-film transistor (D1), a drain connected to a power supply (VDD), a gate connected to a gate of a second depletion-mode IGZO thin-film transistor (D2), and a source connected to a drain of a first enhancement-mode IGZO thin-film transistor (M1); a second depletion-mode IGZO thin-film transistor (D2), the drain of which is connected to the power supply (VDD), and the gate and source of which are both connected to the drain of the second enhancement-mode IGZO thin-film transistor (M2); a first enhanced IGZO thin film transistor (M1), wherein the drain and the gate are both connected to the gate of the second enhanced IGZO thin film transistor (M2), and the source is grounded (GND); a second enhanced IGZO thin film transistor (M2), whose source is connected to the drain of the feedback tube (MR1); Feedback tube (MR1), source grounded (GND); The enhanced IGZO thin film transistor comprises, from bottom to top, a substrate, a gate electrode layer, a gate dielectric layer, and an IGZO active layer, on which a source electrode and a drain electrode are arranged; The depletion-mode IGZO thin-film transistor includes a substrate, a gate electrode layer, a gate dielectric layer, and an IGZO active layer from bottom to top. A source and a drain are arranged on the IGZO active layer, and the IGZO active layer between the source and the drain is defined as a window for realizing hydrogen doping.

2. The reference voltage source according to claim 1, wherein: The hydrogen doping is achieved by hydrogen plasma treatment.

3. The reference voltage source according to claim 2, wherein: During the hydrogen plasma treatment, the hydrogen plasma flow rate was 170 sccm and the process temperature was 30°C.

4. The reference voltage source according to claim 1, wherein: The reference voltage subcircuit includes a third depletion-type IGZO thin-film transistor (D3), a fourth depletion-type IGZO thin-film transistor (D4), a fifth depletion-type IGZO thin-film transistor (D5), a third enhancement-type IGZO thin-film transistor (M3), a fourth enhancement-type IGZO thin-film transistor (M4), a fifth enhancement-type IGZO thin-film transistor (M5), a sixth enhancement-type IGZO thin-film transistor (M6), and a seventh enhancement-type IGZO thin-film transistor (M7), wherein: a third depletion-mode IGZO thin-film transistor (D3), the drain of which is connected to the power supply (VDD), the gate of which is simultaneously connected to the gate of the fourth depletion-mode IGZO thin-film transistor (D4) and the gate of the fifth depletion-mode IGZO thin-film transistor (D5), and the source of which is connected to the drain of the third enhancement-mode IGZO thin-film transistor (M3); a fourth depletion-mode IGZO thin-film transistor (D4), having a drain connected to a power supply (VDD) and a source connected to a drain of a fifth enhancement-mode IGZO thin-film transistor (M5); a fifth depletion-mode IGZO thin-film transistor (D5), having a drain connected to a power supply (VDD) and a source connected to a reference voltage output terminal (Vref); a third enhanced IGZO thin film transistor (M3), having a gate connected to the gate of the fourth enhanced IGZO thin film transistor (M4), and a source connected to the drain of the fourth enhanced IGZO thin film transistor (M4); a fourth enhancement-mode IGZO thin-film transistor (M4), having a drain connected to a source of a sixth enhancement-mode IGZO thin-film transistor (M6), and a source connected to ground (GND); a fifth enhancement-mode IGZO thin-film transistor (M5), having a gate connected to the gate of the sixth enhancement-mode IGZO thin-film transistor (M6), and a source connected to the drain of the sixth enhancement-mode IGZO thin-film transistor (M6); a sixth enhancement-mode IGZO thin-film transistor (M6), the drain of which is connected to the source of the seventh enhancement-mode IGZO thin-film transistor (M7); A seventh enhancement-mode IGZO thin-film transistor (M7) has a gate and a drain both connected to the reference voltage output terminal (Vref).

5. The reference voltage source according to claim 1, wherein: The connection between the current source subcircuit and the reference voltage subcircuit is achieved by connecting the gate of the feedback tube (MR1) to the reference voltage output terminal (Vref), and connecting the gate of the first depletion-type IGZO thin-film transistor (D1) to the gate of the third depletion-type IGZO thin-film transistor (D3).

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