A High-Voltage Spike Bidirectional Absorption Circuit with Adjustable Response and Absorption Method

Abstract

The present invention discloses a high-voltage spike bidirectional absorption circuit with adjustable response and an absorption method, belonging to the field of power supply control. The high-voltage spike bidirectional absorption circuit with adjustable response and the absorption method of the present invention can effectively clamp the forward or reverse impact voltage generated at the load end, can set the voltage threshold according to the product performance requirements, absorb the bidirectional high-voltage spikes exceeding the threshold within an adjustable range, effectively relieve the influence of the high-voltage impact on the electrical performance of the product, and improve the reliability of the product. The present invention can absorb the bidirectional spike voltage at the load end of a product with a high-voltage output power supply, and relieve the influence of the high-voltage impact on the electrical performance of the product.

Description

Technical Field

[0001] The present invention belongs to the field of power supply control, and in particular, to a high-voltage spike bidirectional absorption circuit with adjustable response and an absorption method. Background Art

[0002] For a DC / DC converter with a high-voltage output, if there is a high-voltage spike with unknown polarity at its load end, it will cause a large impact on the power supply product and even damage the normal operation of the power supply product. Existing power supply products usually use an RC or RCD absorption circuit to suppress the high-voltage spike at the output end. This circuit can absorb the instantaneous spike, but the energy suppression effect on the high-voltage spike is weak. Summary of the Invention

[0003] The purpose of the present invention is to overcome the above-mentioned disadvantages of the prior art and provide a high-voltage spike bidirectional absorption circuit with adjustable response and an absorption method.

[0004] To achieve the above object, the present invention adopts the following technical solutions:

[0005] A high-voltage spike bidirectional absorption circuit with adjustable response includes a first switching diode D1 and a second switching diode D2. The negative electrode of the first switching diode D1 is connected to the negative electrode of a first voltage regulator Z1. The positive electrode of the first voltage regulator Z1 is simultaneously connected to one end of a first resistor R1 and a second resistor R2. The other end of the first resistor R1 is simultaneously connected to the negative electrode of a third voltage regulator Z3 and the G pole of a first N-type MOS transistor Q1. The S pole of the first N-type MOS transistor Q1 is simultaneously connected to the S pole of a second N-type MOS transistor Q2, the positive electrode of the third voltage regulator Z3, and the positive electrode of a fourth voltage regulator Z4. The D pole of the first N-type MOS transistor Q1 is connected to the positive electrode of the first switching diode D1. The other end of the second resistor R2 is simultaneously connected to one end of a third resistor R3, the positive electrode of the fourth voltage regulator Z4. The other end of the third resistor R3 is simultaneously connected to the positive electrode of a second voltage regulator Z2 and one end of a fourth resistor R4. The other end of the fourth resistor R4 is simultaneously connected to the negative electrode of the fourth voltage regulator Z4 and the G pole of the second N-type MOS transistor Q2. The negative electrode of the second voltage regulator Z2 is connected to the negative electrode of the second switching diode D2. The positive electrode of the second switching diode D2 is connected to the D pole of the second N-type MOS transistor Q2. The positive electrodes of the first switching diode D1 and the second switching diode D2 also serve as the input of the load terminal voltage at the same time.

[0006] Furthermore, the first N-type MOS transistor Q1 is connected with a parasitic first anti-parallel diode D3.

[0007] Furthermore, the positive electrode of the first anti-parallel diode D3 is connected to the S pole of the first N-type MOS transistor Q1, and the negative electrode of the first anti-parallel diode D3 is connected to the D pole of the first N-type MOS transistor Q1.

[0008] Furthermore, the second N-type MOS transistor Q2 is connected to a parasitic second anti-parallel diode D4.

[0009] Furthermore, the anode of the second anti-parallel diode D4 is connected to the S pole of the second N-type MOS transistor Q2 , and the cathode of the second anti-parallel diode D4 is connected to the D pole of the second N-type MOS transistor Q2 .

[0010] Furthermore, the first capacitor C1 and the third voltage-stabilizing diode Z3 are connected in parallel.

[0011] Furthermore, the second capacitor C2 is connected in parallel with the fourth voltage regulator diode Z4.

[0012] Furthermore, the values of the third voltage-stabilizing tube Z3 and the fourth voltage-stabilizing tube Z4 enable the MOS tubes in the first N-type MOS tube Q1 and the second N-type MOS tube Q2 to be saturated and turned on.

[0013] A bidirectional absorption method for a high-voltage spike bidirectional absorption circuit with adjustable response,

[0014] Connect the anode of the first switching diode D1 and the anode of the second switching diode D2 to the load terminal voltage;

[0015] When the load-end voltage suddenly changes and generates a large spike voltage, if the potential at the anode of the first switching diode D1 is higher than the potential at the anode of the second switching diode D2 and higher than the threshold voltage, the first switching diode D1 is turned on, and the first voltage-stabilizing diode Z1 and the third voltage-stabilizing diode Z3 are reversely broken down. Since the voltage across the third voltage-stabilizing diode Z3 is also the voltage across the gate-source of the first N-type MOS transistor Q1, the first N-type MOS transistor Q1 is turned on, and current flows from the anode of the first switching diode D1 through the first N-type MOS transistor Q1 and the second anti-parallel diode D4 to the anode of the second switching diode D2. The potential between the anode of the first switching diode D1 and the anode of the second switching diode D2 is clamped to the conduction voltage drop of the first N-type MOS transistor Q1 and the second anti-parallel diode D4.

[0016] If the potential of the anode of the second switching diode D2 is higher than that of the anode of the first switching diode D1 and higher than the threshold voltage, the second switching diode D2 is turned on, and the second voltage regulator Z2 and the fourth voltage regulator Z4 are reversely broken down. Since the voltage across the fourth voltage regulator Z4 is also the voltage across the gate-source of the second N-type MOS transistor Q2, the second N-type MOS transistor Q2 is turned on, and current flows from the anode of the second switching diode D2 through the second N-type MOS transistor Q2 and the first anti-parallel diode D3 to the anode of the first switching diode D1. The potential between the anodes of the first switching diode D1 and the second switching diode D2 is clamped to the conduction voltage drop of the second N-type MOS transistor Q2 and the first anti-parallel diode D3.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] A high-voltage spike bidirectional absorption circuit with adjustable response and an absorption method thereof according to the present invention can effectively clamp the forward or reverse impact voltage generated at the load end, can set a voltage threshold according to the product performance requirements, absorb the bidirectional high-voltage spikes exceeding the threshold within an adjustable range, effectively alleviate the influence of the high-voltage impact on the electrical performance of the product, and improve the reliability of the product. The present invention can absorb the bidirectional spike voltage at the load end of a product with a high-voltage output power supply, and alleviate the influence of the high-voltage impact on the electrical performance of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a circuit diagram of a specific application example of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] In order to enable those skilled in the art to better understand the solution of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of the present invention.

[0021] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0022] The present invention will be further described in detail below in conjunction with the accompanying drawings:

[0023] A high-voltage spike bidirectional absorption circuit with adjustable response according to the present invention, a specific application example is as Figure 1 shown. In the figure, points A and B can be used as any two nodes generating high-voltage spikes. The proposed circuit is arranged between the two nodes of the high-voltage spike voltage. The circuit consists of the following components. The functions of each component in the circuit will be described below:

[0024] A high-voltage spike bi-directional absorption circuit with adjustable response, comprising a first switching diode D1 and a second switching diode D2. The negative electrode of the first switching diode D1 is connected to the negative electrode of a first voltage regulator diode Z1. The positive electrode of the first voltage regulator diode Z1 is simultaneously connected to one end of a first resistor R1 and a second resistor R2. The other end of the first resistor R1 is simultaneously connected to the negative electrode of a third voltage regulator diode Z3 and the G pole of a first N-type MOS transistor Q1. The S pole of the first N-type MOS transistor Q1 is simultaneously connected to the S pole of a second N-type MOS transistor Q2, the positive electrode of the third voltage regulator diode Z3, and the positive electrode of a fourth voltage regulator diode Z4. The D pole of the first N-type MOS transistor Q1 is connected to the positive electrode of the first switching diode D1. The other end of the second resistor R2 is simultaneously connected to one end of a third resistor R3 and the positive electrode of the fourth voltage regulator diode Z4. The other end of the third resistor R3 is simultaneously connected to the positive electrode of a second voltage regulator diode Z2 and one end of a fourth resistor R4. The other end of the fourth resistor R4 is simultaneously connected to the negative electrode of the fourth voltage regulator diode Z4 and the G pole of the second N-type MOS transistor Q2. The negative electrode of the second voltage regulator diode Z2 is connected to the negative electrode of the second switching diode D2. The positive electrode of the second switching diode D2 is connected to the D pole of the second N-type MOS transistor Q2. The positive electrodes of the first switching diode D1 and the second switching diode D2 also serve as the input of the load terminal voltage simultaneously.

[0025] The first N-type MOS transistor Q1 is connected with a parasitic first anti-parallel diode D3, and the second N-type MOS transistor Q2 is connected with a parasitic second anti-parallel diode D4.

[0026] A first capacitor C1 is arranged in parallel with the third voltage regulator diode Z3, and a second capacitor C2 is arranged in parallel with the fourth voltage regulator diode Z4.

[0027] Among them, the breakdown voltages of the first voltage regulator diode Z1, the second voltage regulator diode Z2, the third voltage regulator diode Z3, and the fourth voltage regulator diode Z4 also determine the threshold voltage in this circuit. The values of the third voltage regulator diode Z3 and the fourth voltage regulator diode Z4 are such that the MOS transistors in the first N-type MOS transistor Q1 and the second N-type MOS transistor Q2 can be saturated and turned on.

[0028] The working mechanism of the present invention is as follows:

[0029] When the voltage between points A and B suddenly changes and a large peak voltage is generated, if the potential of point A is higher than that of point B and higher than the threshold voltage (this threshold is determined by the regulated voltages of the first voltage regulator diode Z1 and the third voltage regulator diode Z3), the first switching diode D1 conducts, the first voltage regulator diode Z1 and the third voltage regulator diode Z3 are reverse breakdown and in a regulated voltage state. Since the voltage across the third voltage regulator diode Z3 is also the voltage across the gate-source of the first N-type MOS transistor Q1, the first N-type MOS transistor Q1 conducts, and the current flows from point A through the first N-type MOS transistor Q1 and the second anti-parallel diode D4 to point B. The potential between points A and B is clamped to the conduction voltage drop of the first N-type MOS transistor Q1 and the second anti-parallel diode D4. If the potential of point B is higher than that of point A and higher than the threshold voltage (this threshold is determined by the regulated voltages of the second voltage regulator diode Z2 and the fourth voltage regulator diode Z4), the second switching diode D2 conducts, the second voltage regulator diode Z2 and the fourth voltage regulator diode Z4 are reverse breakdown and in a regulated voltage state. Since the voltage across the fourth voltage regulator diode Z4 is also the voltage across the gate-source of the second N-type MOS transistor Q2, the second N-type MOS transistor Q2 conducts, and the current flows from point B through the second N-type MOS transistor Q2 and the first anti-parallel diode D3 to point A. The potential between points A and B is clamped to the conduction voltage drop of the second N-type MOS transistor Q2 and the first anti-parallel diode D3. Thus, when a bidirectional voltage peak is generated between points A and B, this circuit can clamp the voltage. In practical applications, the breakdown voltage of the MOS transistor can be selected according to the magnitude of the estimated peak voltage, and the threshold voltage can be set without affecting the performance of the power supply product, so that this circuit is suitable for this application scenario.

[0030] The above content is only to illustrate the technical idea of the present invention and cannot be used to limit the protection scope of the present invention. Any modification made on the basis of the technical solution according to the technical idea proposed by the present invention falls within the protection scope of the claims of the present invention.

Claims

1. A high-voltage spike bidirectional absorption circuit with adjustable response, characterized in that It includes a first switching diode D1 and a second switching diode D2. The negative electrode of the first switching diode D1 is connected to the negative electrode of a first voltage regulator diode Z1. The positive electrode of the first voltage regulator diode Z1 is simultaneously connected to one end of a first electrode R1 and a second electrode R2. The other end of the first electrode R1 is simultaneously connected to the negative electrode of a third voltage regulator diode Z3 and the G pole of a first N-type MOS transistor Q1. The S pole of the first N-type MOS transistor Q1 is simultaneously connected to the S pole of a second N-type MOS transistor Q2, the positive electrode of the third voltage regulator diode Z3, and the positive electrode of a fourth voltage regulator diode Z4. The D pole of the first N-type MOS transistor Q1 is connected to the positive electrode of the first switching diode D1; the other end of the second electrode R2 is simultaneously connected to one end of a third electrode R3, the positive electrode of the fourth voltage regulator diode Z4. The other end of the third electrode R3 is simultaneously connected to the positive electrode of a second voltage regulator diode Z2 and one end of a fourth electrode R4. The other end of the fourth electrode R4 is simultaneously connected to the negative electrode of the fourth voltage regulator diode Z4 and the G pole of the second N-type MOS transistor Q2. The negative electrode of the second voltage regulator diode Z2 is connected to the negative electrode of the second switching diode D2. The positive electrode of the second switching diode D2 is connected to the D pole of the second N-type MOS transistor Q2; the positive electrodes of the first switching diode D1 and the second switching diode D2 also serve as the input of the load terminal voltage at the same time.

2. The adjustable-response high-voltage spike bi-directional absorption circuit according to claim 1, characterized in that The first N-type MOS transistor Q1 is connected with a parasitic first anti-parallel diode D3.

3. The high-voltage spike bi-directional absorption circuit with adjustable response according to claim 2, characterized in that, The positive electrode of the first anti-parallel diode D3 is connected to the S pole of the first N-type MOS transistor Q1, and the negative electrode of the first anti-parallel diode D3 is connected to the D pole of the first N-type MOS transistor Q1.

4. A high-voltage spike bidirectional absorption circuit with adjustable response according to claim 1, characterized in that The second N-type MOS transistor Q2 is connected with a parasitic second anti-parallel diode D4.

5. A high-voltage spike bidirectional absorption circuit with adjustable response according to claim 4, characterized in that, The positive electrode of the second anti-parallel diode D4 is connected to the S pole of the second N-type MOS transistor Q2, and the negative electrode of the second anti-parallel diode D4 is connected to the D pole of the second N-type MOS transistor Q2.

6. The adjustable-response high-voltage spike bi-directional absorption circuit according to claim 1, wherein The first capacitor C1 is arranged in parallel with the third voltage regulator diode Z3.

7. A high-voltage spike bi-directional absorption circuit with adjustable response according to claim 1, characterized in that, The second capacitor C2 is arranged in parallel with the fourth voltage regulator diode Z4.

8. A high-voltage spike bi-directional absorption circuit with adjustable response according to claim 1, characterized in that The values of the third voltage regulator diode Z3 and the fourth voltage regulator diode Z4 are such that the MOS transistors in the first N-type MOS transistor Q1 and the second N-type MOS transistor Q2 can be saturated and conduct.

9. A two-way absorption method of a high-voltage spike two-way absorption circuit with adjustable response according to any one of claims 1-8, characterized in that: Connect the positive electrodes of the first switching diode D1 and the second switching diode D2 to the load terminal voltage; When the potential at the positive electrode of the first switching diode D1 is higher than the potential at the positive electrode of the second switching diode D2 and higher than the threshold voltage, the first switching diode D1 conducts, and the first voltage regulator diode Z1 and the third voltage regulator diode Z3 are reversely broken down. Since the voltage across the third voltage regulator diode Z3 is also the voltage across the gate-source of the first N-type MOS transistor Q1, the first N-type MOS transistor Q1 conducts, and the current flows from the positive electrode of the first switching diode D1 through the first N-type MOS transistor Q1 and the second anti-parallel diode D4 to the positive electrode of the second switching diode D2. The potential between the positive electrode of the first switching diode D1 and the positive electrode of the second switching diode D2 is clamped to the conduction voltage drop of the first N-type MOS transistor Q1 and the second anti-parallel diode D4; When the positive electrode potential of the second switching diode D2 is higher than that of the first switching diode D1 and higher than the threshold voltage, the second switching diode D2 conducts, and the second voltage stabilizing diode Z2 and the fourth voltage stabilizing diode Z4 are reversely broken down. Since the voltage across the fourth voltage stabilizing diode Z4 is also the voltage between the gate and source of the second N-type MOS transistor Q2, the second N-type MOS transistor Q2 conducts. The current flows from the positive electrode of the second switching diode D2 through the second N-type MOS transistor Q2 and the first anti-parallel diode D3 to the positive electrode of the first switching diode D1. The potential between the positive electrodes of the first switching diode D1 and the second switching diode D2 is clamped to the conduction voltage drops of the second N-type MOS transistor Q2 and the first anti-parallel diode D3.

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