A generalized virtual vector modulation method and system for three-level inverter

Abstract

The present invention belongs to the technical field of power electronic power conversion, and provides a generalized virtual vector modulation method and system for a three-level inverter, the method comprising: sector and region discrimination, virtual vector definition and selection, duty cycle calculation, capacitor voltage independent control, duty cycle update, switch sequence design, PWM signal generation. Among them, the capacitor voltage independent control strategy can be further divided into neutral current calculation and optimal allocation factor acquisition. The method of the present invention is applicable to both balanced and unbalanced operating conditions of the DC side midpoint voltage, ensuring high-quality output current; the duty cycle of the basic voltage vector can be obtained by relying only on algebraic operations, greatly reducing the complexity of the implementation process; and flexible control of the capacitor voltage can be achieved at the same time.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronic power conversion, and in particular relates to a generalized virtual vector modulation method and system for a three-level inverter. Background Art

[0002] The statements in this section merely provide background information related to the present invention and do not necessarily constitute prior art.

[0003] The three-level inverter has obvious advantages such as low voltage stress of power switch tube, high output waveform quality, and small filter size. It is widely used in renewable energy generation, composite energy storage, power quality management and other fields. Diode clamped and T-type three-level inverters are the two most commonly used three-level inverter topologies, but both require a large number of power switch tubes, which inevitably increases system cost and volume.

[0004] In order to further reduce the number of power switches, reduce system size and cost, Tung Ngo and other scholars from Auckland University of Technology in New Zealand proposed a Simplified Neutral-Point Clamped (SNPC) three-level inverter topology, which contains ten power switches, which is further reduced than the traditional T-type three-level inverter topology, and does not require a clamping diode.

[0005] The inventors found that the existing modulation method for three-level inverters is only applicable to the DC side midpoint voltage balanced condition. However, when the three-level inverter is used in centralized photovoltaic power generation, composite energy storage, new energy vehicles and other systems, setting two independent input power supplies on the DC side is of great significance to improving system efficiency, but the current modulation scheme cannot be applied to both the DC side midpoint voltage balanced and unbalanced operating conditions. Summary of the invention

[0006] In order to solve at least one technical problem existing in the above-mentioned background technology, the present invention provides a generalized virtual vector modulation method and system for a three-level inverter, which is suitable for balanced and unbalanced operating conditions of the DC side midpoint voltage to ensure high-quality output current; the duty cycle of the basic voltage vector can be obtained only by algebraic operations, which greatly reduces the complexity of the implementation process; and at the same time, flexible control of the capacitor voltage can be achieved.

[0007] In order to achieve the above object, the present invention adopts the following technical solution:

[0008] A first aspect of the present invention provides a generalized virtual vector modulation method for a three-level inverter, comprising the following steps:

[0009] Define a virtual voltage vector according to the space voltage vector expression;

[0010] According to the amplitude and phase angle of the reference voltage vector, the sector and region where the reference voltage vector is currently located are determined. If the reference voltage vector is located in sector 1, based on the relative position relationship between the reference voltage and the space vector diagram, the corresponding virtual voltage vector selection rule method is adopted to synthesize the reference voltage vector, establish the volt-second balance equation, and calculate the duty cycle of each virtual voltage vector using coordinate transformation. If the reference voltage vector is located in a sector other than sector 1, the phase angle of the reference voltage vector is converted to sector 1 through a mapping relationship;

[0011] The method of selecting a corresponding virtual voltage vector based on the relative position relationship between the reference voltage and the space vector diagram specifically includes:

[0012] When the reference voltage vector is located in the inner area of ​​the space vector diagram, the three nearest virtual voltage vectors are selected to synthesize the reference vector, and the duty cycle of each virtual vector is solved by the direct method;

[0013] When the reference voltage vector is located outside the space vector diagram, the four nearest virtual voltage vectors are selected to synthesize the reference vector, and the duty cycle of each virtual vector is solved by an indirect method;

[0014] Convert the duty cycle of each virtual vector into the duty cycle of the basic vector, design the optimal capacitor voltage controller, accurately adjust the neutral current, obtain the optimal allocation factor of the duty cycle of the P-type and N-type small vectors, and update the duty cycle of each basic vector;

[0015] A switching sequence is designed based on the updated duty cycle of the basic vector and the sector and region where the reference voltage vector is located, and the switching sequence is converted into a PWM drive signal for the power switch tube.

[0016] A second aspect of the present invention provides a generalized virtual vector modulation system for a three-level inverter, comprising:

[0017] A virtual voltage vector definition module, used for defining a virtual voltage vector according to a space voltage vector expression;

[0018] The virtual voltage vector selection and duty cycle calculation module is used to determine the sector and region where the reference voltage vector is currently located according to the amplitude and phase angle of the reference voltage vector. If the reference voltage vector is located in sector 1, based on the relative position relationship between the reference voltage and the space vector diagram, the corresponding virtual voltage vector selection rule method is adopted to synthesize the reference voltage vector, establish the volt-second balance equation, and calculate the duty cycle of each virtual voltage vector by coordinate transformation. If the reference voltage vector is located in a sector other than sector 1, the phase angle of the reference voltage vector is converted to sector 1 through a mapping relationship;

[0019] The method of selecting a corresponding virtual voltage vector based on the relative position relationship between the reference voltage and the space vector diagram specifically includes:

[0020] When the reference voltage vector is located in the inner area of ​​the space vector diagram, the three nearest virtual voltage vectors are selected to synthesize the reference vector, and the duty cycle of each virtual vector is solved by the direct method;

[0021] When the reference voltage vector is located outside the space vector diagram, the four nearest virtual voltage vectors are selected to synthesize the reference vector, and the duty cycle of each virtual vector is solved by an indirect method;

[0022] The capacitor voltage independent control module is used to convert the duty cycle of each virtual vector into the duty cycle of the basic vector, design the capacitor voltage optimal controller, accurately adjust the neutral current, obtain the optimal allocation factor of the duty cycle of the P-type and N-type small vectors, and update the duty cycle of each basic vector;

[0023] The drive signal generation module is used to design a switch sequence based on the updated duty cycle of the basic vector and the sector and area where the reference voltage vector is located, and convert the switch sequence into a PWM drive signal for the power switch tube.

[0024] A third aspect of the present invention provides a computer-readable storage medium.

[0025] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps in the generalized virtual vector modulation method for a three-level inverter as described above.

[0026] A fourth aspect of the present invention provides a computer device.

[0027] A computer device comprises a memory, a processor and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps in the generalized virtual vector modulation method for a three-level inverter as described above are implemented.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] (1) The method of the present invention is applicable to both balanced and unbalanced operating conditions of capacitor voltage on the DC side of a three-level inverter, ensuring high-quality output current, through sector and region discrimination, virtual vector definition and selection, duty cycle calculation, capacitor voltage independent control, duty cycle update, switch sequence design, and PWM signal generation. Among them, the capacitor voltage independent control strategy can be further divided into neutral line current calculation and optimal allocation factor acquisition. The duty cycle of the basic voltage vector can be obtained only by algebraic operations, which greatly reduces the complexity of the implementation process and can realize flexible control of capacitor voltage.

[0030] (2) When the method of the present invention is adopted, the voltage fluctuation amplitude of the capacitor on the DC side of the three-level inverter is very small, and a capacitor with a smaller capacity can be used, which is conducive to achieving cost reduction and efficiency improvement of the system;

[0031] (3) The method of the present invention can flexibly control the difference between the two capacitor voltages on the DC side, and the adjustment time is significantly shortened compared with the traditional proportional integral (PI) controller.

[0032] Advantages of additional aspects of the present invention will be given in part in the following description, and in part will become obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings in the specification, which constitute a part of the present invention, are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0034] Figure 1 This is the overall control block diagram of the system;

[0035] Figure 2 is a circuit topology diagram of a three-level inverter;

[0036] Figure 3 It is the space vector diagram of the three-level inverter when the DC side unbalance factor is greater than 0;

[0037] Figure 4 It is the space vector diagram of the three-level inverter when the DC side unbalance factor is less than 0;

[0038] Figure 5 A spatial vector diagram of the method of the present invention;

[0039] Figure 6 Schematic diagram of the switching sequence in sector 1 and area A;

[0040] Figure 7 Schematic diagram of the switching sequence in sector 1 and region B;

[0041] Figure 8(a)-Figure 8(c) It is a steady-state working waveform diagram of the method of the present invention when the modulation index m=0.8;

[0042] Figure 9(a)-Figure 9(b) This is a comparison diagram of the working waveforms of the capacitor voltage control method using the method of the present invention and the traditional PI control method when the modulation index m=0.8;

[0043] Figure 10(a)-Figure 10(c) It is a steady-state working waveform diagram of the method of the present invention when the modulation index m=0.4;

[0044] Figure 11(a)-Figure 11(b) The following is a comparison diagram of working waveforms when the modulation index m=0.4 and the capacitor voltage control method using the method of the present invention and the traditional PI control method. DETAILED DESCRIPTION

[0045] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0046] It should be noted that the following detailed descriptions are all illustrative and intended to provide further explanation of the present invention. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present invention belongs.

[0047] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments according to the present invention. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprising" and / or "including" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0048] Embodiment 1

[0049] This embodiment provides a generalized virtual vector modulation method for a three-level inverter, such as Figure 1 As shown, the following steps are included:

[0050] Step 1: Define a virtual vector according to the definition of the space voltage vector and the expression of the basic voltage vector;

[0051] Step 2: Based on the amplitude and phase angle of the reference voltage vector, determine the sector and region where the reference voltage vector is currently located;

[0052] Step 3: According to the sector where the reference voltage vector is currently located, a virtual voltage vector selection rule is designed, the reference voltage vector is synthesized, the volt-second balance equation is established, and the volt-second balance equation is solved by coordinate transformation to obtain the duty cycle of each virtual vector;

[0053] Step 4: Design the optimal capacitor voltage controller to accurately adjust the neutral current, obtain the optimal allocation factor of the duty cycle of the P-type and N-type small vectors, and update the duty cycle of each basic vector based on the corresponding relationship between the virtual vector and the basic vector;

[0054] Step 5: Design a switching sequence based on the sector and region where the reference voltage vector is currently located; when the reference voltage vector is located in a sector other than sector 1, convert the phase angle of the reference voltage vector to sector 1 through a mapping relationship; convert the switching sequence into a PWM drive signal for the power switch tube.

[0055] Figure 2The circuit topology diagram of the three-level inverter system includes the following components: two groups of photovoltaic arrays (PV1 and PV2), two DC side support capacitors (C1 and C2), ten power switch tubes (S1, S2, ..., S 10 ).

[0056] Among them, the values ​​of the two DC side support capacitors are equal, that is, C1=C2=C dc Each capacitor is connected to a photovoltaic array at both ends to achieve independent maximum power point tracking (MPPT) function, thereby improving the power generation efficiency of the system.

[0057] The four power switch tubes S1, S2, S3 and S4 are connected in series to form a common switch unit, S5 and S6 are connected in series to form the first group of independent switch units, S7 and S8 are connected in series to form the second group of independent switch units, S9, S 10 The third group of independent switch units is formed by connecting in series.

[0058] The connection point of S2 and S3 is used as the neutral point of the inverter, the connection point of capacitors C1 and C2 is used as the neutral point of the DC input power supply, and the neutral point of the inverter is connected to the neutral point of the DC input power supply. The on and off of each power switch tube is controlled by using pulse width modulation (PWM).

[0059] It can be understood that the power switch tube in this embodiment can be an insulated gate bipolar transistor (IGBT), or other forms of transistors can be used to implement it, and the specific selection can be based on the actual needs of technical personnel in this field.

[0060] The three-level inverter has three switching states: [P], [O] and [N].

[0061] Select the DC side neutral point (i.e. Figure 2 Point O1 in the figure is used as a reference. When the switch state is [P], the output voltage of the bridge arm is +V C1 ; When the switch state is [O], the bridge arm output voltage is 0; when the switch state is [N], the bridge arm output voltage is -V C2 .

[0062] The basic voltage vectors, switch states and switched-on switches of the three-level inverter are shown in Table 1. It can be seen that the basic voltage vectors of the three-level inverter include large vectors, small vectors and zero vectors.

[0063] Table 1 Basic voltage vectors, switch states and enabled switch tubes of three-level inverter

[0064]

[0065]

[0066] In order to describe the difference between the two capacitor voltages on the DC side, the DC side unbalance factor is defined as

[0067]

[0068] Among them, V C1 and V C2 are the voltages across capacitors C1 and C2, V dc =V C1 +V C2 .

[0069] When the DC side unbalance factor is greater than or less than 0, the space vector diagram of the three-level inverter is as follows: Figure 3 , Figure 4 As shown. It can be seen that under the condition of unbalanced midpoint voltage on the DC side, the positions of the large vector and the zero vector remain unchanged, that is, the same as when the midpoint voltage is balanced; the position of the small vector is offset, and the positions of the P-type small vector and the N-type small vector no longer coincide, making the implementation process of the space vector modulation method extremely complicated.

[0070] To this end, this embodiment provides a generalized virtual vector modulation method and system applicable to a three-level inverter, which can effectively solve the above-mentioned problem. Without loss of generality, the specific implementation process is described in detail by taking sector 1 as an example.

[0071] Step 1: Define a virtual vector according to the space voltage vector definition expression;

[0072] As one or more embodiments, in step 1, according to the definition of the space voltage vector, the expression of the basic voltage vector in sector 1 can be obtained as follows:

[0073]

[0074] Define the virtual vector as:

[0075]

[0076] Wherein, α is the allocation factor of the P-type small vector and the N-type small vector.

[0077] It can be seen that the virtual large vector is the same as the large vector; the virtual zero vector is the same as the zero vector; the virtual small vector is a combination of the P-type small vector and the N-type small vector. When α takes different values, the vertices of the virtual small vector are different.

[0078] In this embodiment, for the convenience of solving, α is taken to be equal to 1 / 2.

[0079] Step 2: Based on the amplitude and phase angle of the reference voltage vector, determine the sector and region where the reference voltage vector is currently located;

[0080] Step 3: According to the sector where the reference voltage vector is currently located, a virtual voltage vector selection rule is designed, the reference voltage vector is synthesized, the volt-second balance equation is established, and the volt-second balance equation is solved by coordinate transformation to obtain the duty cycle of each virtual vector;

[0081] As one or more embodiments, in step 3, in order to simplify the calculation process, a 60° coordinate system is established, that is, the g-axis is rotated 60° counterclockwise to obtain the h-axis (see Figure 4 ). The coordinate transformation process can be expressed as:

[0082]

[0083] Among them, v rg represents the g-axis component of the reference voltage vector, v rh represents the h-axis component of the reference voltage vector, v rα represents the α-axis component of the reference voltage vector, v rβ Represents the β-axis component of the reference voltage vector.

[0084] ① When the reference voltage vector is in region A in sector 1 (i.e., the outer region of the space vector diagram), select the four nearest virtual voltage vectors, including two virtual large vectors and two virtual small vectors (i.e., V L1 、V L2 、V S1 and V S2 ) synthesizes the reference voltage vector, and the volt-second balance equation is:

[0085]

[0086] Among them, V r is the reference voltage vector, d L1 d L2 d S1 and d S2 V L1 、V L2 、V S1 and V S2 duty cycle.

[0087] The following indirect calculation method is used to solve the duty cycle d L1 d L2 d S1 and d S2 :

[0088] Using the coordinate transformation given by equation (4), the volt-second balance equation can be simplified to:

[0089]

[0090] Among them, V rg and V rh They are the g-axis and h-axis components of the reference voltage vector respectively.

[0091] Further get d S1 and d S2 satisfy

[0092]

[0093] Introducing the allocation factor β (0<β<1), d S1 and d S2 It can be expressed as:

[0094]

[0095] d L1 and d L2 It can be expressed as:

[0096]

[0097] Cause L1 and d L2 is the duty cycle, obviously: d L1 >0,d L2 >0, and further, the distribution factor β satisfies

[0098]

[0099] Combined with 0<β<1, we can get the upper limit value of the allocation factor β max and the lower limit β min They are:

[0100]

[0101] Select the allocation factor β as its upper limit β max and the lower limit β min The average value of is:

[0102]

[0103] Substituting the allocation factor given by equation (13) into the above expression of duty cycle, the duty cycle of each virtual vector can be obtained. It can be converted into the duty cycle of the basic vector, as shown in equation (14).

[0104]

[0105] Among them, d1, d2, d 7p d 7n d8p and d 8n They are V1[PNN], V2[PPN], V 7p [POO], V 7n [ONN], V 8p [PPO] and V 8n ξ is the duty cycle allocation factor of the P-type small vector and the N-type small vector, which can be used to control the capacitor voltage deviation.

[0106] ② When the reference voltage vector is in region B in sector 1 (i.e., the inner region of the space vector diagram), the three nearest virtual voltage vectors are selected, including two virtual small vectors and a virtual zero vector (i.e., V S1 、V S2 and V Z ) synthesizes the reference voltage vector, and the volt-second balance equation is:

[0107]

[0108] Among them, V r is the reference voltage vector, d S1 d S2 and d Z V S1 、V S2 and V Z The following direct calculation method is used to solve the duty cycle d S1 d S2 and d Z :

[0109] Using the coordinate transformation given by equation (4), the duty cycle of each virtual vector can be obtained as:

[0110]

[0111] Convert it to the duty cycle of the basic vector, as shown in equation (17).

[0112]

[0113] Among them, d 7p d 7n d 8p d 8n and d0 are V 7p [POO], V 7n [ONN], V 8p [PPO], V 8n The duty cycle of V0[OON] and V0[OOO].

[0114] Step 4: Design the optimal capacitor voltage controller to accurately adjust the neutral current, obtain the optimal allocation factor of the duty cycle of the P-type and N-type small vectors, and update the duty cycle of each basic vector based on the corresponding relationship between the virtual vector and the basic vector;

[0115] As one or more embodiments, after obtaining the duty cycle of each virtual vector, the neutral line current is accurately adjusted by designing a capacitor voltage optimal controller to obtain the duty cycle distribution factors of the P-type and N-type small vectors, and the duty cycle of each basic vector is updated in combination with the corresponding relationship between the virtual vector and the basic vector, which specifically includes the following steps:

[0116] The mathematical model of the neutral current is:

[0117]

[0118] Among them, C dc is the value of the DC side support capacitor (i.e. C1 = C2 = C dc ), V diff is the voltage difference between the two capacitors on the DC side (i.e. V diff =V C1 –V C2 ).

[0119] The discrete form of the mathematical model of the neutral current is:

[0120]

[0121] Among them, T s is the sampling period of the digital controller, V diff (k) and V diff (k+1) is the voltage difference between the two capacitors on the DC side at time k and time k+1 respectively.

[0122] Let V diff (k+1) is the given value of capacitor voltage deviation V diff_ref , then the reference value of the neutral current can be expressed as:

[0123]

[0124] When the reference voltage vector is located in sector 1 (including region A and region B), the relationship between the actual neutral current of the system and the three-phase output current and the basic vector duty cycle can be expressed as:

[0125] i np =i a ·(d 7n +d 8n )+i b ·(d 8n +d 7p )+i c ·(d7p +d 8p ) (twenty one)

[0126] Combining equations (17), (20) and (21), we can get the optimal allocation factor ξ opt for

[0127]

[0128] Using similar analysis and solution methods, the optimal allocation factor ξ in other sectors can be obtained: opt The optimal allocation factors within each sector are as follows:

[0129] When the reference voltage vector is located in sector 1, the optimal allocation factor is:

[0130]

[0131] When the reference voltage vector is located in sector 2, the optimal allocation factor is:

[0132]

[0133] When the reference voltage vector is located in sector 3, the optimal allocation factor is:

[0134]

[0135] When the reference voltage vector is located in sector 4, the optimal allocation factor is:

[0136]

[0137] When the reference voltage vector is located in sector 5, the optimal allocation factor is:

[0138]

[0139] When the reference voltage vector is located in sector 6, the optimal allocation factor is:

[0140]

[0141] Step 5: Design a switching sequence based on the sector and region where the reference voltage vector is currently located;

[0142] As one or more embodiments, in step 5, the switch sequence is designed by taking into account factors such as low harmonic content of the output waveform of the three-level inverter and a small number of power switch tube operations.

[0143] The designed switching sequence is a seven-stage or nine-stage switching sequence, including:

[0144] When the reference voltage vector is located in region A within sector 1, the seven-segment switching sequence is designed as follows: [PNN]-[ONN]-[OON]-[PPN]-[PPO]-[POO]-[PNN] (e.g. Figure 5 shown).

[0145] When the reference voltage vector is located in region B within sector 1, the nine-segment switching sequence is designed as follows: [ONN]-[OON]-[OOO]-[POO]-[PPO]-[POO]-[OOO]-[OON]-[ONN] (e.g. Figure 6 shown).

[0146] Step 6: When the reference voltage vector is located in a sector other than sector 1, the phase angle of the reference voltage vector is converted to sector 1 through a mapping relationship; and the switching sequence is converted into a PWM drive signal of the power switch tube.

[0147] As one or more embodiments, in step 6, when the reference voltage vector is located in other sectors (i.e., sectors 2 to 6), the phase angle of the reference voltage vector is converted to sector 1 through a mapping relationship (i.e., equation (14)), i.e.

[0148]

[0149] Wherein, θ is the phase angle of the reference voltage vector, N is the sector number, and θ' is the value of the phase angle of the reference voltage vector mapped to sector 1.

[0150] On this basis, the duty cycle calculation formula in sector 1 is used to calculate the duty cycle of the corresponding basic voltage vector. Then the basic voltage vector in the sector where the reference voltage vector is located is selected to design the switching sequence. The switching sequence designs in different sectors and regions are as follows:

[0151] When the reference voltage vector is located in region A within sector 2, the seven-segment switching sequence is designed as follows: [PPN]-[OON]-[NON]-[NPN]-[OPO]-[PPO]-[PPN].

[0152] When the reference voltage vector is located in region B within sector 2, the nine-segment switching sequence is designed as follows: [NON]-[OON]-[OOO]-[OPO]-[PPO]-[OPO]-[OOO]-[OON]-[NON].

[0153] When the reference voltage vector is located in region A within sector 3, the seven-segment switching sequence is designed as follows: [NPN]-[NON]-[NOO]-[NPP]-[OPP]-[OPO]-[NPN].

[0154] When the reference voltage vector is located in region B within sector 3, the nine-segment switching sequence is designed as follows: [NON]-[NOO]-[OOO]-[OPO]-[OPP]-[OPO]-[OOO]-[NOO]-[NON].

[0155] When the reference voltage vector is located in region A within sector 4, the seven-segment switching sequence is designed as follows: [NPP]-[NOO]-[NNO]-[NNP]-[OOP]-[OPP]-[NPP].

[0156] When the reference voltage vector is located in region B within sector 4, the nine-segment switching sequence is designed as follows: [NNO]-[NOO]-[OOO]-[OOP]-[OPP]-[OOP]-[OOO]-[NOO]-[NNO].

[0157] When the reference voltage vector is located in region A within sector 5, the seven-segment switching sequence is designed as follows: [NNP]-[NNO]-[ONO]-[PNP]-[POP]-[OOP]-[NNP].

[0158] When the reference voltage vector is located in region B within sector 5, the nine-segment switching sequence is designed as follows: [NNO]-[ONO]-[OOO]-[OOP]-[POP]-[OOP]-[OOO]-[ONO]-[NNO].

[0159] When the reference voltage vector is located in region A within sector 6, the seven-segment switching sequence is designed as follows: [PNP]-[ONO]-[ONN]-[PNN]-[POO]-[POP]-[PNP].

[0160] When the reference voltage vector is located in region B within sector 6, the nine-segment switching sequence is designed as follows: [ONN]-[ONO]-[OOO]-[POO]-[POP]-[POO]-[OOO]-[ONO]-[ONN].

[0161] Figure 7 The control block diagram of the method of the present invention includes: sector and region identification, virtual vector selection, duty cycle calculation, capacitor voltage independent control, duty cycle update, switch sequence design, PWM generation. Among them, the capacitor voltage independent control strategy can be further divided into neutral line current calculation, optimal allocation factor calculation, and amplitude limiting.

[0162] When the modulation index is 0.8, the steady-state operating waveform of the three-level inverter is as follows: Figure 8(a)-Figure 8(c)When the running time is between 0.15s and 0.2s, the capacitor voltage deviation is set to 0V; when the running time is between 0.25s and 0.3s, the capacitor voltage deviation is set to 100V; when the running time is between 0.35s and 0.4s, the capacitor voltage deviation is set to -100V. At the same time, Figure 8(a)-Figure 8(c) The total harmonic distortion rate (THDv) of the output line voltage and the total harmonic distortion rate (THDi) of the output current are given. It is not difficult to see that the method of the present invention can ensure high-quality output current under both balanced and unbalanced conditions of the DC side capacitor voltage.

[0163] When the system modulation index is equal to 0.8 and the capacitor voltage deviation given value undergoes a step change, the performance comparison between the method of the present invention and the traditional PI control method is as follows: Figure 9(a)-Figure 9(b) shown.

[0164] It can be seen that: by adopting the method of the present invention, the DC side capacitor voltage regulation time is significantly shortened compared with the traditional PI control method.

[0165] When the modulation index is 0.4, the steady-state operating waveform of the three-level inverter is as follows: Figure 10(a)-Figure 10(c) When the running time is between 0.15s and 0.2s, the capacitor voltage deviation is set to 0V; when the running time is between 0.25s and 0.3s, the capacitor voltage deviation is set to 100V; when the running time is between 0.35s and 0.4s, the capacitor voltage deviation is set to -100V. At the same time, Figure 10(a)-Figure 10(c) The total harmonic distortion rate (THDv) of the output line voltage and the total harmonic distortion rate (THDi) of the output current are given. It can be seen that the method of the present invention is applicable to both balanced and unbalanced operating conditions of the DC side capacitor voltage, ensuring the stable and reliable operation of the inverter system.

[0166] When the system modulation index is equal to 0.4 and the capacitor voltage deviation given value undergoes a step change, the performance comparison between the method of the present invention and the traditional PI control method is as follows: Figure 11(a)-Figure 11(b) shown.

[0167] It can be seen that the method of the present invention can realize fast and accurate tracking and control of capacitor voltage, and has obvious advantages compared with the traditional PI control method.

[0168] Embodiment 2

[0169] This embodiment provides a generalized virtual vector modulation system for a three-level inverter, including:

[0170] A virtual voltage vector definition module, used for defining a virtual voltage vector according to a space voltage vector expression;

[0171] The virtual voltage vector selection and duty cycle calculation module is used to determine the sector and region where the reference voltage vector is currently located according to the amplitude and phase angle of the reference voltage vector. If the reference voltage vector is located in sector 1, based on the relative position relationship between the reference voltage and the space vector diagram, the corresponding virtual voltage vector selection rule method is adopted to synthesize the reference voltage vector, establish the volt-second balance equation, and calculate the duty cycle of each virtual voltage vector by coordinate transformation. If the reference voltage vector is located in a sector other than sector 1, the phase angle of the reference voltage vector is converted to sector 1 through a mapping relationship;

[0172] The method of selecting a corresponding virtual voltage vector based on the relative position relationship between the reference voltage and the space vector diagram specifically includes:

[0173] When the reference voltage vector is located in the inner area of ​​the space vector diagram, the three nearest virtual voltage vectors are selected to synthesize the reference vector, and the duty cycle of each virtual vector is solved by the direct method;

[0174] When the reference voltage vector is located outside the space vector diagram, the four nearest virtual voltage vectors are selected to synthesize the reference vector, and the duty cycle of each virtual vector is solved by an indirect method;

[0175] The capacitor voltage independent control module is used to convert the duty cycle of each virtual vector into the duty cycle of the basic vector, design the capacitor voltage optimal controller, accurately adjust the neutral current, obtain the optimal allocation factor of the duty cycle of the P-type and N-type small vectors, and update the duty cycle of each basic vector;

[0176] The drive signal generation module is used to design a switch sequence based on the updated duty cycle of the basic vector and the sector and area where the reference voltage vector is located, and convert the switch sequence into a PWM drive signal for the power switch tube.

[0177] Embodiment 3

[0178] This embodiment provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the steps in the generalized virtual vector modulation method for a three-level inverter as described above are implemented.

[0179] Embodiment 4

[0180] This embodiment provides a computer device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps in the generalized virtual vector modulation method for a three-level inverter as described above are implemented.

[0181] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of hardware embodiments, software embodiments, or embodiments combining software and hardware. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage and optical storage, etc.) containing computer-usable program code.

[0182] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0183] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0184] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0185] A person skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0186] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A generalized virtual vector modulation method for a three-level inverter, characterized in that: The steps include: A virtual voltage vector is defined according to a space voltage vector expression, wherein the virtual voltage vector includes a virtual large vector, a virtual small vector and a virtual zero vector, wherein the virtual large vector is the same as the large vector; the virtual zero vector is the same as the zero vector; and the virtual small vector is a combination of a P-type small vector and an N-type small vector; The space vector diagram is divided into 6 sectors, and each sector is further divided into two areas, which are recorded as area A and area B. Area A is the outer area of ​​the space vector diagram, and area B is the inner area of ​​the space vector diagram. The boundary line between area A and area B is the connecting line of two virtual voltage small vectors. The inner side of the connecting line of the end points of the two virtual voltage small vectors represents area B, and the outer side represents area A. According to the amplitude and phase angle of the reference voltage vector, the sector and region where the reference voltage vector is currently located are determined. If the reference voltage vector is located in sector 1, based on the relative position relationship between the reference voltage and the space vector diagram, the corresponding virtual voltage vector selection rule method is adopted to synthesize the reference voltage vector, establish the volt-second balance equation, and calculate the duty cycle of each virtual voltage vector using coordinate transformation. If the reference voltage vector is located in a sector other than sector 1, the phase angle of the reference voltage vector is converted to sector 1 through a mapping relationship; The method of selecting a corresponding virtual voltage vector based on the relative position relationship between the reference voltage and the space vector diagram specifically includes: When the reference voltage vector is located in the inner area of ​​the space vector diagram, the three nearest virtual voltage vectors are selected to synthesize the reference vector, and the duty cycle of each virtual voltage vector is solved by a direct method; When the reference voltage vector is located outside the space vector diagram, the four nearest virtual voltage vectors are selected to synthesize the reference vector, and the duty cycle of each virtual voltage vector is solved by the indirect method; the duty cycle of each virtual voltage vector is converted into the duty cycle of the basic voltage vector, and the capacitor voltage optimal controller is designed to accurately adjust the neutral current, obtain the optimal allocation factor of the duty cycle of the P-type and N-type small vectors, and update the duty cycle of each basic voltage vector; Design a switch sequence based on the updated duty cycle of the basic voltage vector and the sector and region where the reference voltage vector is located, and convert the switch sequence into a PWM drive signal for the power switch tube; The duty cycle expression of each virtual voltage vector obtained by the direct method is: The corresponding duty cycle of each basic voltage vector is: The duty cycle expression of each virtual voltage vector obtained by the indirect method is: in, The duty cycle of each basic voltage vector is: Where, d S1 d S2 and d Z is the duty cycle of the three virtual voltage vectors, V rg and V rh are the g-axis and h-axis components of the reference voltage vector, is the unbalance factor on the DC side, α is the allocation factor of the P-type small vector and the N-type small vector, V dc is the sum of the voltages across the capacitor, d 7p d 7n d 8p d 8n and d0 are the basic voltage vectors V 7p [POO], V 7n [ONN], V 8p [PPO], V 8n The duty cycle of V0[OOO] and V0[OOO], ξ is the duty cycle allocation factor of P-type small vector and N-type small vector; d L1 d L2 d S1 and d S2 is the duty cycle of the four virtual voltage vectors.

2. The generalized virtual vector modulation method for a three-level inverter according to claim 1, characterized in that: The optimal allocation factor is specifically: When the reference voltage vector is located in sector 1, the optimal allocation factor is: When the reference voltage vector is located in sector 2, the optimal allocation factor is: When the reference voltage vector is located in sector 3, the optimal allocation factor is: When the reference voltage vector is located in sector 4, the optimal allocation factor is: When the reference voltage vector is located in sector 5, the optimal allocation factor is: When the reference voltage vector is located in sector 6, the optimal allocation factor is: Among them, the reference value of the neutral current is C dc is the value of the DC side support capacitor, V diff_ref is the given value of capacitor voltage deviation, T s is the sampling period of the digital controller, V diff (k) is the voltage difference between the two capacitors on the DC side at time k, i a 、i b and i c is the three-phase output current.

3. The generalized virtual vector modulation method for a three-level inverter according to claim 1, characterized in that: The designed switching sequence is a seven-stage or nine-stage switching sequence.

4. The generalized virtual vector modulation method for a three-level inverter according to claim 3, characterized in that: The seven-stage or nine-stage switch sequence is specifically: When the reference voltage vector is located in region A within sector 1, the designed switching sequence is as follows: [PNN]-[ONN]-[OON]-[PPN]-[PPO]-[POO]-[PNN]; When the reference voltage vector is located in region B within sector 1, the designed switching sequence is as follows: [ONN]-[OON]-[OOO]-[POO]-[PPO]-[POO]-[OOO]-[OON]-[ONN]; When the reference voltage vector is located in region A within sector 2, the designed switching sequence is as follows: [PPN]-[OON]-[NON]-[NPN]-[OPO]-[PPO]-[PPN]; When the reference voltage vector is located in region B within sector 2, the designed switching sequence is as follows: [NON]-[OON]-[OOO]-[OPO]-[PPO]-[OPO]-[OOO]-[OON]-[NON]; When the reference voltage vector is located in region A within sector 3, the switching sequence is designed as follows: [NPN]-[NON]-[NOO]-[NPP]-[OPP]-[OPO]-[NPN]; When the reference voltage vector is located in region B within sector 3, the switching sequence is designed as follows: [NON]-[NOO]-[OOO]-[OPO]-[OPP]-[OPO]-[OOO]-[NOO]-[NON]; When the reference voltage vector is located in region A within sector 4, the switching sequence is designed as follows: [NPP]-[NOO]-[NNO]-[NNP]-[OOP]-[OPP]-[NPP]; When the reference voltage vector is located in region B within sector 4, the designed switching sequence is as follows: [NNO]-[NOO]-[OOO]-[OOP]-[OPP]-[OOP]-[OOO]-[NOO]-[NNO]; When the reference voltage vector is located in region A within sector 5, the switching sequence is designed as follows: [NNP]-[NNO]-[ONO]-[PNP]-[POP]-[OOP]-[NNP]; When the reference voltage vector is located in region B within sector 5, the designed switching sequence is as follows: [NNO]-[ONO]-[OOO]-[OOP]-[POP]-[OOP]-[OOO]-[ONO]-[NNO]; When the reference voltage vector is located in region A within sector 6, the switching sequence is designed as follows: [PNP]-[ONO]-[ONN]-[PNN]-[POO]-[POP]-[PNP]; When the reference voltage vector is located in region B within sector 6, the switching sequence is designed as follows: [ONN]-[ONO]-[OOO]-[POO]-[POP]-[POO]-[OOO]-[ONO]-[ONN].

5. A generalized virtual vector modulation system for a three-level inverter, characterized in that: include: A virtual voltage vector definition module, used for defining a virtual voltage vector according to a space voltage vector expression; The virtual voltage vector includes a virtual large vector, a virtual small vector and a virtual zero vector, wherein the virtual large vector is the same as the large vector; the virtual zero vector is the same as the zero vector; and the virtual small vector is a combination of a P-type small vector and an N-type small vector; The space vector diagram is divided into 6 sectors, and each sector is further divided into two areas, which are recorded as area A and area B. Area A is the outer area of ​​the space vector diagram, and area B is the inner area of ​​the space vector diagram. The boundary line between area A and area B is the connecting line of two virtual voltage small vectors. The inner side of the connecting line of the end points of the two virtual voltage small vectors represents area B, and the outer side represents area A. The virtual voltage vector selection and duty cycle calculation module is used to determine the sector and region where the reference voltage vector is currently located according to the amplitude and phase angle of the reference voltage vector. If the reference voltage vector is located in sector 1, based on the relative position relationship between the reference voltage and the space vector diagram, the corresponding virtual voltage vector selection rule method is adopted to synthesize the reference voltage vector, establish the volt-second balance equation, and calculate the duty cycle of each virtual voltage vector by coordinate transformation. If the reference voltage vector is located in a sector other than sector 1, the phase angle of the reference voltage vector is converted to sector 1 through a mapping relationship; The method of selecting a corresponding virtual voltage vector based on the relative position relationship between the reference voltage and the space vector diagram specifically includes: When the reference voltage vector is located in the inner area of ​​the space vector diagram, the three nearest virtual voltage vectors are selected to synthesize the reference vector, and the duty cycle of each virtual voltage vector is obtained by using the direct method; when the reference voltage vector is located in the outer area of ​​the space vector diagram, the four nearest virtual voltage vectors are selected to synthesize the reference vector, and the duty cycle of each virtual voltage vector is obtained by using the indirect method; The duty cycle expression of each virtual voltage vector obtained by the direct method is: The corresponding duty cycle of each basic voltage vector is: The duty cycle expression of each virtual voltage vector obtained by the indirect method is: in, The duty cycle of each basic voltage vector is: Where, d S1 d S2 and d Z is the duty cycle of the three virtual voltage vectors, V rg and V rh are the g-axis and h-axis components of the reference voltage vector, is the unbalance factor on the DC side, α is the allocation factor of the P-type small vector and the N-type small vector, V dc is the sum of the voltages across the capacitor, d 7p d 7n d 8p d 8n and d0 are the basic voltage vectors V 7p [POO], V 7n [ONN], V 8p [PPO], V 8n The duty cycle of V0[OOO] and V0[OOO], ξ is the duty cycle allocation factor of P-type small vector and N-type small vector; d L1 d L2 d S1 and d S2 is the duty cycle of the four virtual voltage vectors; The capacitor voltage independent control module is used to convert the duty cycle of each virtual voltage vector into the duty cycle of the basic voltage vector, design the capacitor voltage optimal controller, accurately adjust the neutral line current, obtain the optimal allocation factor of the duty cycle of the P-type and N-type small vectors, and update the duty cycle of each basic voltage vector; The drive signal generation module is used to design a switch sequence based on the updated duty cycle of the basic voltage vector and the sector and area where the reference voltage vector is located, and convert the switch sequence into a PWM drive signal for the power switch tube.

6. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the steps of a generalized virtual vector modulation method for a three-level inverter as claimed in any one of claims 1 to 4 are implemented.

7. A computer device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the steps in the generalized virtual vector modulation method for a three-level inverter according to any one of claims 1 to 4 are implemented.

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