A wide-range frequency divider chain based on the CML structure

Abstract

The present invention discloses a wide-range frequency divider chain based on a CML structure, belonging to the field of integrated circuit design, which includes a main frequency divider chain and a multiplexer; the main frequency divider chain divides the input signal and makes a preliminary screening, and the multiplexer makes a final screening on the output of the main frequency divider chain. The main frequency divider chain includes four 2 / 3 dual-mode frequency dividers connected in series in sequence; each 2 / 3 dual-mode frequency divider receives the corresponding input for frequency division by two and frequency division by three respectively, and transmits the frequency division by two output to the next 2 / 3 dual-mode frequency divider for further frequency division; each 2 / 3 dual-mode frequency divider selects the output of the frequency division by two circuit or the frequency division by three circuit as the input of the multiplexer according to the corresponding control signal. The frequency divider of the present invention has more diverse frequency division ratios, a larger output frequency coverage range, and a smaller chip area occupation, which is more conducive to integration in the entire digital phase-locked loop, greatly reducing the area of the phase-locked loop chip.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and particularly relates to a wide-range frequency divider chain based on a CML structure. Background Art

[0002] As an important building block, a frequency divider is widely used in the design of microwave and radio frequency (RF) systems; a frequency divider chain composed of frequency dividers can achieve multi-mode frequency division and is widely used in circuits such as phased locked loops (PLLs), playing a dominant role in the operating frequency and power consumption of the entire circuit.

[0003] In the current integrated circuit design entering the deep sub-micron process, and with the development of 5G and even 6G communication technologies, the signal frequencies processed by RF chips are getting higher and higher. At lower frequencies, frequency dividers can be implemented digitally; as the frequency increases, due to the limitations of the inherent delay of digital circuits, using digital circuits to divide high-frequency signals often results in errors. In high-speed frequency dividers, current mode logic (CML) frequency dividers are widely used due to advantages such as the widest locking range, no need for inductors, and small occupied area. Summary of the Invention

[0004] The purpose of the present invention is to provide a wide-range frequency divider chain based on a CML structure to achieve a wider coverage of the output frequency range, flexible and easy adjustment of the frequency division ratio, and less required hardware.

[0005] To solve the above technical problems, the present invention provides a wide-range frequency divider chain based on a CML structure, including a main frequency divider chain and a multiplexer;

[0006] The main frequency divider chain divides the input signal and makes a preliminary screening, and the multiplexer makes a final screening of the output of the main frequency divider chain.

[0007] In an embodiment of the invention, the main frequency divider chain includes four 2 / 3 dual-mode frequency dividers connected in series in sequence; among them, each 2 / 3 dual-mode frequency divider respectively receives the corresponding input for frequency division by two and frequency division by three, and transmits the output of frequency division by two to the next 2 / 3 dual-mode frequency divider for further frequency division;

[0008] Each 2 / 3 dual-mode frequency divider selects the output of the frequency division by two circuit or the output of the frequency division by three circuit as the input of the multiplexer according to the corresponding control signal; where when the control signal is high, the output of the frequency division by two circuit is selected, and when the control signal is low, the output of the frequency division by three circuit is selected.

[0009] In an embodiment of the invention, each 2 / 3 dual-mode frequency divider has the same structure and is composed of a frequency divider by two and a frequency divider by three. The input end of the 2 / 3 dual-mode frequency divider is connected to the input ends of both the frequency divider by two and the frequency divider by three at the same time. The output end of the frequency divider by two serves as the first output end of the 2 / 3 dual-mode frequency divider. The control end controls whether the output end of the frequency divider by two or the output end of the frequency divider by three serves as the second output end of the 2 / 3 dual-mode frequency divider, and this second output end is connected to the multiplexer.

[0010] In an embodiment of the invention, the main frequency divider chain includes a zeroth 2 / 3 dual-mode frequency divider, a first 2 / 3 dual-mode frequency divider, a second 2 / 3 dual-mode frequency divider, and a third 2 / 3 dual-mode frequency divider; the input end of the main frequency divider chain is connected to the input end of the zeroth 2 / 3 dual-mode frequency divider, the first output end of the zeroth 2 / 3 dual-mode frequency divider is connected to the input end of the first 2 / 3 dual-mode frequency divider, the first output end of the first 2 / 3 dual-mode frequency divider is connected to the input end of the second 2 / 3 dual-mode frequency divider, and the first output end of the second 2 / 3 dual-mode frequency divider is connected to the input end of the third 2 / 3 dual-mode frequency divider.

[0011] In an embodiment of the invention, the zeroth control end controls the zeroth 2 / 3 dual-mode frequency divider to select either the output end of the frequency divider by two or the output end of the frequency divider by three as the zeroth output end of the main frequency divider chain; the first control end controls the first 2 / 3 dual-mode frequency divider to select either the output end of the frequency divider by two or the output end of the frequency divider by three as the first output end of the main frequency divider chain; the second control end controls the second 2 / 3 dual-mode frequency divider to select either the output end of the frequency divider by two or the output end of the frequency divider by three as the second output end of the main frequency divider chain; the third control end controls the third 2 / 3 dual-mode frequency divider to select either the output end of the frequency divider by two or the output end of the frequency divider by three as the third output end of the main frequency divider chain;

[0012] When the level of the zeroth control end is 1'b0, the frequency division ratio achieved by the signal output from the zeroth output end is 2; when the level of the zeroth control end is 1'b1, the frequency division ratio achieved by the signal output from the zeroth output end is 3;

[0013] When the level of the first control end is 1'b0, the frequency division ratio achieved by the signal output from the first output end is 4; when the level of the first control end is 1'b1, the frequency division ratio achieved by the signal output from the first output end is 6;

[0014] When the level of the second control end is 1'b0, the frequency division ratio achieved by the signal output from the second output end is 8; when the level of the second control end is 1'b1, the frequency division ratio achieved by the signal output from the second output end is 12;

[0015] When the level of the third control terminal is 1'b0, the frequency division ratio achieved by the signal output from the third output terminal is 16; when the level of the third control terminal is 1'b1, the frequency division ratio achieved by the signal output from the third output terminal is 24.

[0016] In an embodiment of the invention, the multiplexer has four input terminals, a zeroth discrete voltage control terminal Vb0, and a first discrete voltage control terminal Vb1; the four input terminals are respectively connected to the second output terminals of four 2 / 3 dual-mode frequency dividers.

[0017] When [Vb1, Vb0] = 2'b00, the multiplexer selects the second output terminal of the zeroth 2 / 3 dual-mode frequency divider for output.

[0018] When [Vb1, Vb0] = 2'b01, the multiplexer selects the second output terminal of the first 2 / 3 dual-mode frequency divider for output.

[0019] When [Vb1, Vb0] = 2'b10, the multiplexer selects the second output terminal of the second 2 / 3 dual-mode frequency divider for output.

[0020] When [Vb1, Vb0] = 2'b11, the multiplexer selects the second output terminal of the third 2 / 3 dual-mode frequency divider for output.

[0021] In the wide-range frequency divider chain based on the CML structure provided by the present invention, the following beneficial effects are achieved:

[0022] (1) The present invention adopts a current-mode logic structure, which not only achieves a wide frequency locking range but also saves chip area.

[0023] (2) The use of the 2 / 3 dual-mode frequency divider enables more diverse selections of the frequency division ratio of the frequency divider chain, and through the use of the main frequency divider chain control terminal and the multiplexer, the frequency division ratio of the frequency divider chain is flexible and easy to adjust, achieving an output frequency coverage range from a lower frequency to a higher frequency.

[0024] (3) The present invention has a more diverse frequency division ratio, a larger output frequency coverage range, and a smaller chip area occupied, which is more conducive to integration into the entire digital phase-locked loop, greatly reducing the area of the phase-locked loop chip. Description of the Drawings

[0025] Figure 1 It is a structural block diagram of a frequency divider chain based on the CML structure provided by the present invention.

[0026] Figure 2 It is a circuit schematic diagram of the 2 / 3 dual-mode frequency divider in the frequency divider chain.

[0027] Figure 3 It is a circuit schematic diagram of a frequency divider chain based on the CML structure.

[0028] Figure 4 It is a working schematic diagram of a frequency divider chain based on the CML structure. Detailed implementation mode

[0029] The following further elaborates on a frequency divider chain based on the CML structure proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description and the claims, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0030] The present invention provides a frequency divider chain based on the CML structure, and its structural block diagram is as Figure 1 shown, including a main frequency divider chain and a multiplexer. The main frequency divider chain is used to divide the input signal and make a preliminary screening, and the multiplexer makes a final screening of the output of the main frequency divider chain.

[0031] The basic module of the main frequency divider chain is a 2 / 3 dual-mode frequency divider, and the circuit diagram is as Figure 2 shown. Each 2 / 3 dual-mode frequency divider includes a frequency divider-by-two circuit and a frequency divider-by-three circuit; the input end FD_IN is simultaneously connected to the input end IN_A of the frequency divider-by-two circuit and the input end IN_B of the frequency divider-by-three circuit. The output end of the frequency divider-by-two circuit is used as the first output end FD_O1 of the 2 / 3 dual-mode frequency divider. According to the control end signal, the output end of the frequency divider-by-two circuit or the output end of the frequency divider-by-three circuit is selected as the second output end FD_O2 of the 2 / 3 dual-mode frequency divider. Among them, when the control end signal is high (i.e., MC = 1'b1), the second output end FD_O2 selects the output of the frequency divider-by-two circuit for output. When the control end signal is low (i.e., MC = 1'b0), the second output end FD_O2 selects the output of the frequency divider-by-three circuit for output. Compared with a single frequency divider-by-two circuit or a single frequency divider-by-three circuit, the 2 / 3 dual-mode frequency divider integrating the frequency divider-by-two circuit and the frequency divider-by-three circuit in one module is used in the main frequency divider chain, making the main frequency divider chain have greater operability and flexibility in the change of the frequency division ratio.

[0032] The circuit schematic diagram of the frequency divider chain based on the CML structure is as Figure 3As shown, the input end is connected to the input end of the zero 2 / 3 dual-modulus frequency divider FD0. The first output end of the zero 2 / 3 dual-modulus frequency divider FD0 is connected to the input end of the first 2 / 3 dual-modulus frequency divider FD1. The first output end of the first 2 / 3 dual-modulus frequency divider FD1 is connected to the input end of the second 2 / 3 dual-modulus frequency divider FD2. The first output end of the second 2 / 3 dual-modulus frequency divider FD2 is connected to the input end of the third 2 / 3 dual-modulus frequency divider FD3. The zero control end MC0 is connected to the zero 2 / 3 dual-modulus frequency divider FD0. The first control end MC1 is connected to the first 2 / 3 dual-modulus frequency divider FD1. The second control end MC2 is connected to the second 2 / 3 dual-modulus frequency divider FD2. The third control end MC3 is connected to the third 2 / 3 dual-modulus frequency divider FD3. The second output end of the zero 2 / 3 dual-modulus frequency divider FD0 serves as the zero output end OUT0 of the main frequency divider chain and is connected to the zero input end of the multiplexer. The second output end of the first 2 / 3 dual-modulus frequency divider FD1 serves as the first output end OUT1 of the main frequency divider chain and is connected to the first input end of the multiplexer. The second output end of the second 2 / 3 dual-modulus frequency divider FD2 serves as the second output end OUT2 of the main frequency divider chain and is connected to the second input end of the multiplexer. The second output end of the third 2 / 3 dual-modulus frequency divider FD3 serves as the third output end OUT3 of the main frequency divider chain and is connected to the third input end of the multiplexer.

[0033] When the level of the zero - th control terminal MC0 is MC0 = 1'b0, the division ratio achieved by the signal output from the zero - th output terminal OUT0 of the main frequency - divider chain is 2; when the level of the zero - th control terminal MC0 is MC0 = 1'b1, the division ratio achieved by the signal output from the zero - th output terminal OUT0 is 3. When the level of the first control terminal MC1 is MC1 = 1'b0, the division ratio achieved by the signal output from the first output terminal OUT1 is 4; when the level of the first control terminal MC1 is MC1 = 1'b1, the division ratio achieved by the signal output from the first output terminal OUT1 is 6. When the level of the second control terminal MC2 is MC2 = 1'b0, the division ratio achieved by the signal output from the second output terminal OUT2 is 8; when the level of the second control terminal MC2 is MC2 = 1'b1, the division ratio achieved by the signal output from the second output terminal OUT2 is 12. When the level of the third control terminal MC3 is MC3 = 1'b0, the division ratio achieved by the signal output from the third output terminal OUT3 is 16; when the level of the third control terminal MC3 is MC3 = 1'b1, the division ratio achieved by the signal output from the third output terminal OUT3 is 24. When the levels of the two discrete voltage control terminals Vb0 and Vb1 of the multiplexer are [Vb1, Vb0] = 2'b00, the division ratio achieved by the output signal of the multiplexer is 2 or 3; when the levels of the two discrete voltage control terminals Vb0 and Vb1 of the multiplexer are [Vb1, Vb0] = 2'b01, the division ratio achieved by the output signal of the multiplexer is 4 or 6; when the levels of the two discrete voltage control terminals Vb0 and Vb1 of the multiplexer are [Vb1, Vb0] = 2'b10, the division ratio achieved by the output signal of the multiplexer is 8 or 12; when the levels of the two discrete voltage control terminals Vb0 and Vb1 of the multiplexer are [Vb1, Vb0] = 2'b11, the division ratio achieved by the output signal of the multiplexer is 16 or 24.

[0034]

[0035]

[0036] Table 1 Relationship between the division ratio achieved by the output signal of the multiplexer and the control - terminal signal

[0037] To analyze the principle of achieving wide - range frequency - division output in the present invention, its working schematic diagram is as Figure 4 shown. Figure 4The input signal frequency range is 20 - 30 GHz. After entering the main frequency divider chain, it passes through the zeroth 2 / 3 dual-mode frequency divider FD0 and outputs signals in the frequency range of 10 - 15 GHz and signals in the frequency range of 6.66 - 10 GHz. The signals in the frequency range of 10 - 15 GHz pass through the first 2 / 3 dual-mode frequency divider FD1 and output signals in the frequency range of 5 - 7.5 GHz and signals in the frequency range of 3.33 - 5 GHz. The signals in the frequency range of 5 - 7.5 GHz pass through the second 2 / 3 dual-mode frequency divider FD2 and output signals in the frequency range of 2.5 - 3.75 GHz and signals in the frequency range of 1.66 - 2.5 GHz. The signals in the frequency range of 2.5 - 3.75 GHz pass through the third 2 / 3 dual-mode frequency divider FD3 and output signals in the frequency range of 1.25 - 1.875 GHz and signals in the frequency range of 0.83 - 1.25 GHz.

[0038] After the input signal passes through the main frequency divider chain, eight frequency-divided output signals in different ranges are obtained. Then, through the preliminary screening of the main frequency divider chain and the final screening of the multiplexer, signals in the frequency range of 0.83 - 15 GHz can be obtained.

[0039]

[0040] Table 2 Relationship between the frequency range of the multiplexer output signal and the control terminal signal

[0041] When the upper limit of the input signal range is less than 1.5 times its lower limit, the output signals of the frequency divider chain based on the CML structure provided by the present invention can achieve full-range coverage from a lower frequency to a higher frequency range. Compared with the existing frequency divider chain, the present invention has greater functional and area advantages when applied in radio frequency system design.

[0042] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the art of the present invention based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A wide-range frequency divider chain based on a CML structure, characterized in that, It includes a main frequency divider chain and a multiplexer; The main frequency divider chain divides the input signal and makes a preliminary screening, and the multiplexer makes a final screening on the output of the main frequency divider chain; The main frequency divider chain includes four 2 / 3 dual-mode frequency dividers connected in series in sequence; among them, each 2 / 3 dual-mode frequency divider respectively receives the corresponding input for dividing by two and dividing by three, and transmits the output of dividing by two to the next 2 / 3 dual-mode frequency divider for further frequency division; Each 2 / 3 dual-mode frequency divider selects the output of the dividing-by-two circuit or the dividing-by-three circuit as the input of the multiplexer according to the corresponding control signal; among them, when the control signal is high, it selects the output of the dividing-by-two circuit, and when the control signal is low, it selects the output of the dividing-by-three circuit; The structure of each 2 / 3 dual-mode frequency divider is the same and is composed of a dividing-by-two circuit and a dividing-by-three circuit. The input end of the 2 / 3 dual-mode frequency divider is simultaneously connected to the input ends of the dividing-by-two circuit and the dividing-by-three circuit. The output end of the dividing-by-two circuit is used as the first output end of the 2 / 3 dual-mode frequency divider. The control end controls whether the output end of the dividing-by-two circuit or the output end of the dividing-by-three circuit is used as the second output end of the 2 / 3 dual-mode frequency divider, and this second output end is connected to the multiplexer.

2. The wide-range frequency divider chain based on the CML structure according to claim 1, characterized in that The main frequency divider chain includes a zero 2 / 3 dual-mode frequency divider, a first 2 / 3 dual-mode frequency divider, a second 2 / 3 dual-mode frequency divider, and a third 2 / 3 dual-mode frequency divider; the input end of the main frequency divider chain is connected to the input end of the zero 2 / 3 dual-mode frequency divider, the first output end of the zero 2 / 3 dual-mode frequency divider is connected to the input end of the first 2 / 3 dual-mode frequency divider, the first output end of the first 2 / 3 dual-mode frequency divider is connected to the input end of the second 2 / 3 dual-mode frequency divider, and the first output end of the second 2 / 3 dual-mode frequency divider is connected to the input end of the third 2 / 3 dual-mode frequency divider.

3. The wide-range frequency divider chain based on the CML structure according to claim 2, characterized in that, The zero control end controls the zero 2 / 3 dual-mode frequency divider to select the output end of the dividing-by-two circuit or the output end of the dividing-by-three circuit as the zero output end of the main frequency divider chain; the first control end controls the first 2 / 3 dual-mode frequency divider to select the output end of the dividing-by-two circuit or the output end of the dividing-by-three circuit as the first output end of the main frequency divider chain; the second control end controls the second 2 / 3 dual-mode frequency divider to select the output end of the dividing-by-two circuit or the output end of the dividing-by-three circuit as the second output end of the main frequency divider chain; The third control end controls the third 2 / 3 dual-mode frequency divider to select the output end of the dividing-by-two circuit or the output end of the dividing-by-three circuit as the third output end of the main frequency divider chain; When the level of the zero control end is 1’b0, the frequency division ratio achieved by the signal output from the zero output end is 2; When the level of the zero control end is 1’b1, the frequency division ratio achieved by the signal output from the zero output end is 3; When the level of the first control end is 1’b0, the frequency division ratio achieved by the signal output from the first output end is 4; When the level of the first control end is 1’b1, the frequency division ratio achieved by the signal output from the first output end is 6; When the level of the second control end is 1’b0, the frequency division ratio achieved by the signal output from the second output end is 8; When the level of the second control end is 1’b1, the frequency division ratio achieved by the signal output from the second output end is 12; When the level of the third control terminal is 1'b0, the frequency division ratio achieved by the signal output from the third output terminal is 16; when the level of the third control terminal is 1'b1, the frequency division ratio achieved by the signal output from the third output terminal is 24.

4. The wide-range frequency divider chain based on the CML structure according to claim 3, characterized in that, The multiplexer has four input terminals, a zero discrete voltage control terminal Vb0, and a first discrete voltage control terminal Vb1; the four input terminals are respectively connected to the second output terminals of four 2 / 3 dual-mode frequency dividers. When [Vb1, Vb0] = 2'b00, the multiplexer selects the second output terminal of the zero 2 / 3 dual-mode frequency divider for output. When [Vb1, Vb0] = 2'b01, the multiplexer selects the second output terminal of the first 2 / 3 dual-mode frequency divider for output. When [Vb1, Vb0] = 2'b10, the multiplexer selects the second output terminal of the second 2 / 3 dual-mode frequency divider for output. When [Vb1, Vb0] = 2'b11, the multiplexer selects the second output terminal of the third 2 / 3 dual-mode frequency divider for output.

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