A topological recognition receiving module

Abstract

A topological recognition receiving module, comprising: a magnetic concentrating ring, a magnetic sensing chip and a signal processing circuit; the magnetic sensing chip includes a measuring capacitor and a reference capacitor, the measuring capacitor is formed by connecting a plurality of measuring magnetic capacitor elements in parallel, the measuring magnetic capacitor element includes a lower electrode layer, a pinned layer, a first insulating layer, a free layer and an upper electrode layer, the magnetization direction of the pinned layer of the measuring magnetic capacitor element remains unchanged, and the magnetization direction of the free layer of the measuring magnetic capacitor element changes with the external magnetic field; the reference capacitor is formed by connecting a plurality of reference magnetic capacitor elements in parallel, the reference magnetic capacitor element includes a lower electrode layer, a pinned layer, a first insulating layer, a free layer, an upper electrode layer, a second insulating layer and a magnetic shielding layer, and the magnetization directions of the free layer and the pinned layer of the reference magnetic capacitor element remain unchanged; the signal processing circuit includes a capacitance detection circuit and a microcontroller processor. The topological recognition receiving module of the present invention uses a TMC magnetic sensing chip, and the TMC effect is greater than the TMR effect under the same conditions, achieving higher sensitivity.

Description

Technical Field

[0001] The invention belongs to the technical field of current sensing, and particularly relates to a topology recognition receiving module for feature current signal recognition. Background Art

[0002] Topology recognition of low-voltage power distribution areas is an important link in the construction of smart grids. Due to the complex line structure, large power consumption, imperfect area archives, untimely update of meter replacement information, insufficient management investment, etc. in low-voltage power distribution areas, it is often impossible to ensure the reliability of the topology relationship in low-voltage power distribution areas. Therefore, it is necessary to introduce topology recognition technology in low-voltage power distribution areas to verify and correct the existing area topology relationship. Currently, the main power area recognition technologies include data correlation analysis recognition technology, power line carrier voltage injection recognition technology, and pulsed current input recognition technology. Among them, the characteristic signals of the data correlation analysis recognition technology are uncontrollable, and the power line carrier voltage injection recognition technology cannot recognize the branch nodes of the topology. Therefore, the current low-voltage power distribution area topology recognition mainly adopts the pulsed current injection recognition technology.

[0003] Pulsed current injection recognition is mainly realized through a topology signal injection module and a topology recognition receiving module. The topology signal injection module is used to inject characteristic current signals (pulsed currents) into the line, and the topology recognition receiving module is used to perform topology recognition based on the characteristic current signals in the line. The topology recognition receiving module includes a topology recognition receiving module based on a Rogowski coil and a topology recognition receiving module based on a magnetic sensing chip. The topology recognition receiving module based on a Rogowski coil is based on the principle of electromagnetic induction. When a pulsed single-current signal flows through the primary side, the current in the secondary side winding wound around the air-core magnetic flux concentrating ring is proportional to the measured current on the primary side. By processing and analyzing the current signal on the secondary side, the information of the pulsed current is restored to judge the topology structure. Compared with an instrument transformer, the Rogowski coil has no magnetic core saturation phenomenon, a high bandwidth, and a low cost, but due to the lack of a magnetic core with high magnetic permeability, the sensitivity is relatively low.

[0004] The topology recognition receiving module based on a TMR magnetic sensing chip detects the pulsed current signal on the primary side through the TMR magnetic sensing chip and converts it into a differential voltage signal for output; the pulsed current information is restored by processing the signal output by the TMR magnetic sensing chip to judge the topology structure. In the topology recognition system, it is required that the topology signal injection module has low power consumption. Therefore, the injected topology signal (pulsed current) is usually small, which requires the magnetic sensing chip used in the topology recognition receiving module to have relatively high sensitivity, and the preparation of a TMR magnetic sensing chip with high sensitivity will increase the cost of the topology recognition receiving module. Summary of the Invention

[0005] The purpose of the invention is to provide a TMC topology recognition receiving module for low-voltage power distribution area topology recognition with high sensitivity and low cost.

[0006] To achieve the above object, the present invention adopts the following technical solution:

[0007] A topology recognition receiving module, comprising: a magnetic focusing ring, a magnetic sensing chip disposed at a notch or an opening of the magnetic focusing ring, and a signal processing circuit connected to the magnetic sensing chip; the magnetic sensing chip includes a measuring capacitor and a reference capacitor, wherein the measuring capacitor is formed by connecting a plurality of measuring magnetic capacitor elements in parallel, and the measuring magnetic capacitor element sequentially includes a lower electrode layer, a pinned layer, a first insulating layer, a free layer and an upper electrode layer from bottom to top, the magnetization direction of the pinned layer of the measuring magnetic capacitor element remains unchanged, and the magnetization direction of the free layer of the measuring magnetic capacitor element changes with an external magnetic field; the reference capacitor is formed by connecting a plurality of reference magnetic capacitor elements in parallel, and the reference magnetic capacitor element sequentially includes a lower electrode layer, a pinned layer, a first insulating layer, a free layer, an upper electrode layer, a second insulating layer and a magnetic shielding layer from bottom to top, and the magnetization directions of the free layer and the pinned layer of the reference magnetic capacitor element remain unchanged; the signal processing circuit includes a capacitance detection circuit and a microcontroller processor connected to the capacitance detection circuit. The capacitance detection circuit is configured to obtain the capacitance value of the measuring capacitor and output the result to the microcontroller processor; the microcontroller processor is configured to perform topology recognition according to the result output by the capacitance detection circuit.

[0008] Further, the ratio of the difference between the capacitance value of the measuring capacitor and the capacitance value of the reference capacitor to the capacitance value of the reference capacitor is less than 1 / 4.

[0009] Further, magnetic focusing layers are symmetrically disposed on both sides of the measuring capacitor.

[0010] Further, the reference capacitor is disposed beside the measuring capacitor, and the magnetic focusing layer on one side of the measuring capacitor serves as the measuring shielding layer of the reference capacitor, and the magnetic shielding layer is made of a magnetically conductive material.

[0011] Further, the capacitance detection circuit includes: a dual-channel analog switch, a reverse trigger and a capacitance measurement chip, the common terminal of the dual-channel analog switch is connected to the reverse trigger, and the control terminal is connected to the capacitance measurement chip and is controlled by a sequence generator in the capacitance measurement chip; the first channel in the dual-channel analog switch is connected to the reference capacitor, and the second channel is connected to the measuring capacitor; the common terminal of the dual-channel analog switch is also respectively connected to the charging pin and the discharging pin of the capacitance measurement chip; the direction trigger is connected to a TDC measurement unit in the capacitance measurement chip; the capacitance measurement chip outputs a result to the microcontroller processor.

[0012] Further, the common terminal of the dual-channel analog switch is respectively connected to the charging pin and the discharging pin of the capacitance measurement chip through a charging resistor and a discharging resistor.

[0013] Further, the microcontroller processor includes a phase-locked amplifier for performing phase-locked amplification on the result output by the capacitance detection circuit and filtering to extract the amplitude of a signal having the same frequency as a preset reception frequency.

[0014] Further, the maximum sensitivity gain frequency point of the magnetic sensing chip is the same as the frequency of the injected characteristic current.

[0015] Further, the preset reception frequency of the topology identification receiving module is the same as the frequency of the injected characteristic current.

[0016] As can be seen from the above technical solutions, the topology identification receiving module of the present invention uses a TMC magnetic sensing chip to detect changes in the capacitance of the MTJ element. The capacitance detection circuit collects the capacitance value changes detected by the TMC magnetic sensing chip. The microcontroller processor performs phase-locked amplification on the signal output by the capacitance detection circuit according to a preset frequency to obtain a frequency selection signal having the same frequency as the preset frequency. By analyzing the frequency selection signal output by the phase-locked amplifier, a pulse current signal having the same frequency as the preset frequency can be extracted, and the reception and discrimination of the topology signal can be performed. Since the TMC magnetic sensing chip is used, compared with a Rogowski coil type pulse current receiving module, it has higher sensitivity, and due to the high sensitivity characteristic of the TMC magnetic sensing chip at a specific frequency point, compared with a TMR magnetic sensing chip having the same structure and material formulation, higher sensitivity can be achieved at a lower cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present invention, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the following drawings are only some embodiments of the present invention, and for those of ordinary skill in the art, other drawings can be obtained according to these drawings without creative efforts.

[0018] Figure 1 is a schematic structural diagram of an embodiment of the present invention;

[0019] Figure 2 is a schematic structural diagram of measuring a magnetic capacitance element according to an embodiment of the present invention;

[0020] Figure 3 is a schematic structural diagram of referring to this capacitance element according to an embodiment of the present invention;

[0021] Figure 4 is a plan view of the TMC magnetic sensing chip of this embodiment;

[0022] Figure 5 is a process diagram of preparing a reference magnetic capacitance element according to this embodiment;

[0023] Figure 6Graphs of capacitance values and resistance values of the TMC magnetic sensing chip and the TMR magnetic sensing chip under the action of a magnetic field;

[0024] Figure 7 Characteristic diagram of the TMC effect with different spin polarization rates P;

[0025] Figure 8 Graph of the variation of different relaxation time TMC values with frequency;

[0026] Figure 9 Circuit diagram of the capacitance detection circuit;

[0027] Figure 10 Block diagram of the signal processing circuit;

[0028] Figure 11 Schematic diagram of the quadrature lock-in amplifier.

[0029] The following further describes in detail the specific embodiments of the present invention in conjunction with the accompanying drawings. Specific Embodiments

[0030] The present invention will be described in detail below in conjunction with the accompanying drawings. When describing the embodiments of the present invention in detail, for the convenience of explanation, the drawings showing the device structure will be enlarged locally in a non-general proportion, and the schematic diagrams are only examples and should not limit the scope of protection of the present invention here. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, only for the purpose of conveniently and clearly assisting in explaining the embodiments of the present invention.

[0031] As Figure 1 shown, the topology recognition receiving module of this embodiment includes a magnetic focusing ring 1, a magnetic sensing chip 2, a signal processing circuit 3, an input / output terminal 4 and a housing 5. The magnetic focusing ring 1, the magnetic sensing chip 2, the signal processing circuit 3 and the input / output terminal 4 are all arranged in the housing 5. The housing 5 of this embodiment is an openable and closable structure, including an upper housing 5-1 and a lower housing 5-2. The upper housing 5-1 is semi-circular and hinged to the lower housing 5-2. When the upper housing 5-1 rotates, the upper housing 5-1 and the lower housing 5-2 can be opened and closed. When the upper housing 5-1 and the lower housing 5-2 are closed, a through hole 5a for the conductor 6 to be measured to pass through is formed between them. By rotating the upper housing 5-1, the housing 5 (receiving module) can be conveniently sleeved around the conductor 6 to be measured for current signal detection.

[0032] The magnetic focusing ring 1 of this embodiment includes three arc-shaped iron cores enclosing a circular ring shape, which can form a receiving module with a ring-shaped openable structure. In other embodiments, the magnetic focusing ring 1 can also be a fixed structure composed of a C-shaped iron core. The magnetic focusing ring 1 can be made of magnetic materials such as silicon steel sheets, permalloys, and nanocrystals. A notch 1a is provided on the magnetic focusing ring 1, and the magnetic sensing chip 2 is disposed at the notch 1a (or opening) of the magnetic focusing ring 1. The magnetic sensing chip 2 is used for magnetic field detection, and the magnetic sensitive direction of the magnetic sensing chip 2 is perpendicular to the conductor 6 to be measured. The magnetic sensing chip 2 is connected to the signal processing circuit 3 through pins or wires. The signal processing circuit 3 is disposed on a circuit board, and input / output terminals 4 are provided on the circuit board. The input / output terminals 4 are used for power supply and communication.

[0033] The magnetic sensing chip of this embodiment is a TMC (Tunneling magneto capacitance) magnetic sensing chip. The main difference between the TMC magnetic sensing chip and the traditional TMR magnetic sensing chip is that in the TMR magnetic sensing chip, MJT elements (magnetic tunnel junction elements) or MJT arrays are connected into a bridge circuit structure for magnetic field induction, while the TMC magnetic sensing chip of the present invention forms a capacitive circuit by connecting MTJ elements or MJT arrays in parallel for magnetic field induction. The TMC magnetic sensing chip includes a measuring capacitor Cm and a reference capacitor Cr. The measuring capacitor Cm is composed of multiple measuring magnetic capacitance elements connected in parallel, and the reference capacitor Cr is composed of multiple reference magnetic capacitance elements connected in parallel. The number of the measuring magnetic capacitance elements and the reference magnetic capacitance elements is not limited and can be adjusted according to the required capacitance value. The reference capacitor Cr and the measuring capacitor Cm are independent of each other, and the capacitance values of the reference capacitor Cr and the measuring capacitor Cm can be different. Optionally, the ratio of the difference between the capacitance value of the measuring capacitor Cm and the capacitance value of the reference capacitor Cr to the capacitance value of the reference capacitor Cr is less than 1 / 4 to improve the accuracy of the measurement result.

[0034] As Figure 2 shown, the measuring magnetic capacitance element (MTJ) sequentially includes a lower electrode layer 7, a pinned layer 8, a first insulating layer 9, a free layer 10, and an upper electrode layer 11 from bottom to top. The free layer 10 is made of a ferromagnetic material, and the magnetization direction of the free layer 10 changes with the external magnetic field. The pinned layer 8 is composed of a magnetic layer with a fixed magnetization direction and an antiferromagnetic layer (not shown), and the magnetization direction of the pinned layer 8 is pinned in a fixed direction and will not change with the external magnetic field. When an external magnetic field is applied, the magnetization direction of the free layer 10 of the measuring magnetic capacitance element approaches the external magnetic field direction, and the capacitance value of the measuring magnetic capacitance element changes with the change of the included angle between the magnetization directions of the pinned layer 8 and the free layer 10.

[0035] As Figure 3As shown in the figure, the reference magneto-capacitive element includes, from bottom to top, a lower electrode layer 7, a pinned layer 8, a first insulating layer 9, a free layer 10, an upper electrode layer 11, a second insulating layer 12, and a magnetic shielding layer 13. The difference between the reference magneto-capacitive element and the measurement magneto-capacitive element lies in that the reference magneto-capacitive element has an additional second insulating layer 12 and a magnetic shielding layer 13. The magnetic shielding layer 13 is used to shield the external magnetic field. The magnetic shielding layer 13 located above the second insulating layer 12 can keep the magnetization direction of the free layer 10 of the reference magneto-capacitive element unchanged, so that the capacitance value of the reference magneto-capacitive element does not change with the external magnetic field. The magnetic shielding layer 13 is made of a magnetic conductive material such as permalloy. In addition to shielding the MTJ below it from the external magnetic field, two adjacent magnetic shielding layers can also form a magnetic flux concentrator, which has the effect of amplifying the magnetic field and helps to improve the sensitivity of the TMC magnetic sensing chip. The MTJ located between the two shielding layers is similar to the TMR chip placed in the magnetic core gap.

[0036] A plurality of measurement magneto-capacitive elements a are connected in parallel to form a group of measurement capacitors Cm, and a plurality of reference magneto-capacitive elements b are connected in parallel to form a group of reference capacitors Cr. As Figure 4 shown, in this embodiment, two groups of measurement capacitors Cm and two groups of reference capacitors Cr are provided, and the reference capacitor Cr is located outside the two groups of measurement capacitors Cm. The measurement capacitor Cm is connected to the signal processing circuit through a pair of measurement capacitor external pads 14, and the reference capacitor Cr is connected to the signal processing circuit through four reference capacitor external pads 15. Preferably, in order to improve the magnetic field sensing sensitivity, in this embodiment, a magnetic concentrating layer 16 is symmetrically arranged on both sides of each group of measurement capacitors Cm to form uniform magnetic lines of force, which is beneficial to magnetic field sensing. Since the magnetic shielding layer 13 of the reference capacitor Cr can play a role in concentrating the magnetic field, and the reference capacitor Cr is located beside the measurement capacitor Cm, the magnetic shielding layer 13 of the reference capacitor Cr can be used as the magnetic concentrating layer 16, and it can cooperate with the magnetic concentrating layer 16 located on the other side of the group of measurement capacitors Cm to form a magnetic concentrating effect.

[0037] The preparation process of the reference magneto-capacitive element is as follows: 1) Sputter and deposit a film stack on the wafer according to the TMC chip material formula; 2) Etch according to the layout shown in a in Figure 5 to obtain the lower electrode layer; 3) Etch according to the layout shown in b in Figure 5 to obtain the pinned layer; 4) Sputter and deposit a first insulating material (SIO2), and etch according to the layout shown in c in Figure 5 to form the first insulating layer; 5) Sputter and deposit an upper electrode material (Au), and etch according to the layout shown in d in Figure 5 to obtain the upper electrode layer; 6) Sputter and deposit a magnetic shielding material (NiFe), and etch according to the layout shown in e in Figure 5 to obtain the magnetic shielding layer, and finally obtain as shown in Figure 5The grains shown in Fig. f are wire bonded and packaged. The preparation process of the magnetic capacitance element is similar, except that the second insulating layer and the magnetic shielding layer do not need to be fabricated for the measurement magnetic capacitance element. The preparation process of the magnetic capacitance element can be referred to.

[0038] Figure 6 This is a graph of the capacitance value (TMC) and a graph of the resistance value (TMR) of the TMC magnetic sensing chip of the present invention and the traditional TMR magnetic sensing chip under the action of an external magnetic field. When the TMC value or TMR value of the magnetic sensing chip is higher, it indicates that the magnetic sensing chip (capacitance value or resistance value) has a higher sensitivity to the magnetic field. From Figure 6 It can be seen that for the TMC magnetic sensing chip and the TMR magnetic sensing chip composed of MTJs made of the same layer structure and formulation, when the spin polarization rate P is the same, the TMC value (TMC effect) is greater than the TMR value (TMR effect), and it becomes more obvious as the spin polarization rate P increases. Thus, it can be known that under the same structure and formulation, for the same MTJ element, the change amount of the capacitance value at both ends of the MTJ element is larger than the change amount of the resistance value. That is, under the same process and material formulation, a higher-sensitivity magnetic field sensor chip can be obtained using the TMC effect.

[0039] Figure 7 This is a characteristic diagram of the TMC effect for different spin polarization rates P. From Figure 7 It can be seen that the frequency characteristics of the TMC effect for different spin polarization rates P are the same, and the TMC effect reaches the maximum value at a certain specific frequency point. That is, the TMC magnetic sensing chip has different sensitivities at different frequencies. Therefore, the frequency of the characteristic current to be injected into the circuit can be set at this specific frequency point to achieve the highest sensitivity, and the preset reception frequency of the topology recognition receiving module is consistent with the frequency of the characteristic current.

[0040] Figure 8 This is a graph of the TMC value varying with frequency for different relaxation times (Tp). The maximum frequency point of the TMC effect can be adjusted by adjusting the relaxation time Tp, so as to obtain the desired pulse current injection frequency point.

[0041] The signal processing circuit of this embodiment includes a capacitance detection circuit and a microcontroller processor. The measurement capacitance and the reference capacitance in the TMC magnetic sensing chip are connected through the capacitance detection circuit and the microcontroller processor. Figure 9 This is the circuit diagram of the capacitance detection circuit. Figure 9Cr in it represents the reference capacitor in the TMC magnetic sensing chip, and Cm represents the measurement capacitor in the TMC magnetic sensing chip. The capacitance detection circuit includes a dual-channel analog switch S, an inverter U1, and a capacitance measurement chip U2. The capacitance measurement chip U2 in this embodiment uses a capacitance measurement chip with the model PS021 from German company ACAM. The TDC measurement unit in the capacitance measurement chip U2 is used to measure the capacitance discharge time. Two MOS transistors are used to control the discharge loop, and the Sequencer is used to generate a pulse square wave to control the conduction of the dual-channel analog switch. In other embodiments, a capacitance measurement chip of the same type can also be used to replace the PS210. The common terminal of the dual-channel analog switch S is connected to the inverter U1, and the control terminal is connected to the capacitance measurement chip U2 and is controlled by the Sequencer in the capacitance measurement chip U2. The first channel S1 in the dual-channel analog switch S is connected to the reference capacitor Cr, and the second channel S2 is connected to the measurement capacitor Cm. The common terminal of the dual-channel analog switch S in this embodiment is also respectively connected to the charging pin and the discharging pin of the capacitance measurement chip U2 through a charging resistor R and a discharging resistor Rd. The discharging resistor Rd and the charging resistor R are used to limit the current in the loop.

[0042] The principle of the capacitance detection circuit for measuring the capacitance value of the TMC magnetic sensing chip is as follows: Vc is the power supply terminal. During measurement, the capacitance measurement chip alternately controls the conduction or disconnection of different switches in the dual-channel analog switch, so that the reference capacitor Cr and the measurement capacitor Cm alternately go through the charging and discharging processes. For example, when the capacitance measurement chip controls the first switch S1 in the dual-channel analog switch to conduct and the second switch S2 to disconnect, the power supply charges the reference capacitor Cr at this time. When the charging reaches the supply voltage Vc, the charging stops, the trigger reverses, and the reference capacitor Cr starts to discharge through the discharging resistor Rd. When the voltage of the reference capacitor Cr drops to the threshold voltage of the inverter, the trigger reverses again, and the reference capacitor Cr starts to charge again. During the measurement process, the reference capacitor Cr repeats the charging and discharging process, and the charging and discharging time of the reference capacitor is measured by the TDC measurement unit of the capacitance measurement chip.

[0043] Similarly, the capacitance measurement chip controls the first switch S1 in the dual-channel analog switch to open and the second switch S2 to conduct. The measurement capacitor Cm also repeats the same capacitor charging and discharging process, and the charging and discharging time of the measurement capacitor Cm is measured by the capacitance detection capacitor. The capacitance value of the reference capacitor Cr is known and does not change with the external magnetic field. After the capacitance measurement chip respectively collects the charging and discharging times of the measurement capacitor Cm and the reference capacitor Cr, the ratio of the measurement capacitor Cm to the reference capacitor Cr can be obtained, and the capacitance value of the measurement capacitor Cm can be calculated. The TMC magnetic sensing chip is equivalent to two capacitors. The capacitor charging and discharging time is related to the capacitance value. The charging and discharging times of the two capacitors are different. The repeated charging and discharging process of the measurement capacitor and the reference capacitor is controlled by the capacitance measurement chip, and the capacitance detection circuit can output the charging and discharging time of the measurement capacitor.

[0044] As Figure 10 shown, the capacitance detection circuit outputs the detection result to the microcontroller processor. The microcontroller processor collects the change of the measurement capacitance of the TMC magnetic sensing chip through the capacitance detection circuit. The microcontroller in this embodiment includes a lock-in amplifier. The function of the lock-in amplifier is to filter out other frequency signals except the preset receiving frequency. The (voltage) signal output by the lock-in amplifier reflects the strength of the part of the input signal of the lock-in amplifier that is of the same frequency as the preset frequency. The microcontroller processor can directly determine whether the input signal contains a signal of the same frequency as the topology frequency (preset frequency) based on the output of the lock-in amplifier, that is, the microcontroller processor performs lock-in amplification on the digital signal output by the capacitance detection circuit, extracts the magnetic field amplitude R near the preset receiving frequency, and realizes the analysis and verification of the topology identification characteristic current. Analyzing and verifying the topology identification characteristic current according to the magnetic field amplitude R of the signal is a conventional technique in the art, and the existing analysis and verification methods of the topology identification receiving module can be used for discrimination, so it will not be elaborated here.

[0045] Next, in combination with Figure 1 、 10 、11, the working principle of this embodiment will be described:

[0046] As Figure 1 、 10 、11 shown, when the topology identification receiving module receives the pulsed current signal, the conductor to be measured 6 is passed through the through hole of the housing 5. When the master station starts the topology identification, the topology signal injection module injects the characteristic pulsed current signal into the conductor 6, and a magnetic field A is generated around the conductor to be measured 6;

[0047] The TMC magnetic sensing chip 2 detects the magnitude of the magnetic field at the notch 1a of the magnetic concentrating ring 1, and the capacitance detection circuit detects and outputs a digital signal V containing the fundamental wave (characteristic pulsed current signal) and the carrier wave characteristic M; During the process of the TMC magnetic sensing chip 2 detecting the magnetic field, the capacitance measurement chip in the capacitance detection circuit samples and outputs the capacitance value at a fixed sampling rate (generally more than ten times the fundamental frequency), and the digital signal V output by it M is a discrete digital signal sequence. The microcontroller processor can perform signal discrimination by performing phase-locked amplification or Fourier analysis on the discrete digital signal sequence;

[0048] The digital signal V output by the capacitance detection circuit M (discrete digital signal sequence) carries the fundamental wave and carrier characteristics. The microcontroller processor reads the digital signal V output by the capacitance detection circuit through the SPI bus M , and the phase-locked amplifier extracts the amplitude R of the signal with the same preset reception frequency as that of the topology recognition receiving module from V M . When the preset reception frequency is the same as the frequency of the characteristic pulse current signal, the output R of the quadrature phase-locked amplifier is not zero, so that the topology pulse current signal can be discriminated. The process of signal discrimination based on the discrete digital signal sequence is the same as the process of signal discrimination by the conventional topology recognition receiving module using the TMR magnetic sensing chip based on the digital signal, and the principle is also the same. This is not the innovative point of the present invention and will not be elaborated here.

[0049] The topology recognition receiving module of the present invention uses a TMC magnetic sensing chip including a capacitance circuit composed of MTJ elements. Since the TMC effect is greater than the TMR effect under the same conditions, higher sensitivity can be achieved, and the cost of the high-sensitivity magnetic sensing chip is reduced. Moreover, the TMC magnetic sensing chip has the maximum sensitivity at a certain specific frequency and suppresses signals of other frequencies to varying degrees. Therefore, when the maximum sensitivity gain frequency point of the TMC magnetic sensing chip is used as the injection pulse current frequency, the TMC magnetic sensing chip can suppress interference signals of other frequencies.

[0050] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present invention. Various modifications to these embodiments will be obvious to those skilled in the art. The general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A topological recognition receiving module, comprising: A magnetic focusing ring, a magnetic sensing chip disposed at a notch or an opening of the magnetic focusing ring, and a signal processing circuit connected to the magnetic sensing chip; It is characterized in that: The magnetic sensing chip includes a measurement capacitor and a reference capacitor, wherein, The measurement capacitor is formed by connecting a plurality of measurement magnetic capacitor elements in parallel. The measurement magnetic capacitor elements successively include a lower electrode layer, a pinned layer, a first insulating layer, a free layer and an upper electrode layer from bottom to top. The magnetization direction of the pinned layer of the measurement magnetic capacitor element remains unchanged, and the magnetization direction of the free layer of the measurement magnetic capacitor element changes with the external magnetic field; The reference capacitor is formed by connecting a plurality of reference magnetic capacitor elements in parallel. The reference magnetic capacitor elements successively include a lower electrode layer, a pinned layer, a first insulating layer, a free layer, an upper electrode layer, a second insulating layer and a magnetic shielding layer from bottom to top. The magnetization directions of the free layer and the pinned layer of the reference magnetic capacitor element remain unchanged; The signal processing circuit includes a capacitance detection circuit for obtaining the capacitance value of the measurement capacitor and a microcontroller processor connected to the capacitance detection circuit.

2. The topology recognition receiving module according to claim 1, characterized in that: The ratio of the difference between the capacitance value of the measurement capacitor and the capacitance value of the reference capacitor to the capacitance value of the reference capacitor is less than 1 / 4.

3. The topology recognition receiving module according to claim 1, wherein: Magnetic focusing layers are symmetrically arranged on both sides of the measurement capacitor.

4. The topology recognition receiving module according to claim 3, wherein: The reference capacitor is disposed beside the measurement capacitor. The magnetic focusing layer on one side of the measurement capacitor serves as the magnetic shielding layer of the reference capacitor, and the magnetic shielding layer is made of a magnetic conductive material.

5. The topology recognition receiving module according to claim 1, wherein: The capacitance detection circuit includes: a dual-channel analog switch, an inverter trigger and a capacitance measurement chip. The common terminal of the dual-channel analog switch is connected to the inverter trigger, and the control terminal is connected to the capacitance measurement chip and is controlled by a sequence generator in the capacitance measurement chip; the first channel in the dual-channel analog switch is connected to the reference capacitor, and the second channel is connected to the measurement capacitor; the common terminal of the dual-channel analog switch is also respectively connected to the charging pin and the discharging pin of the capacitance measurement chip; the inverter trigger is connected to a TDC measurement unit in the capacitance measurement chip; the capacitance measurement chip outputs a result to the microcontroller processor.

6. The topological recognition receiving module according to claim 5, wherein: The common terminal of the dual-channel analog switch is respectively connected to the charging pin and the discharging pin of the capacitance measurement chip through a charging resistor and a discharging resistor.

7. The topology recognition receiving module according to claim 1, characterized in that: The microcontroller processor includes a phase-locked amplifier for performing phase-locked amplification on the result output by the capacitance detection circuit and filtering to extract the amplitude of a signal having the same frequency as a preset reception frequency.

8. The topological recognition receiving module according to claim 1, characterized in that: The maximum sensitivity gain frequency point of the magnetic sensing chip is the same as the frequency of the injected characteristic current.

9. The topology recognition receiving module according to claim 1, characterized in that: The preset reception frequency of the topology identification receiving module is the same as the frequency of the injected characteristic current.

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