Layout design method for optimizing parasitic capacitance and layout

Abstract

The embodiment of the present application provides a layout design method and layout for optimizing parasitic capacitance, wherein the layout design method comprises: arranging a plurality of first MOS transistors side by side along a first direction, and arranging a second MOS transistor below each first MOS transistor; connecting the source of each first MOS transistor with the source of the corresponding second MOS transistor arranged below, connecting the drain of each first MOS transistor with the drain of the corresponding second MOS transistor arranged below, connecting the gate of N first MOS transistors arranged in sequence with a first control line, and connecting the gate of N second MOS transistors arranged below and corresponding to the first control line; extending and arranging the first control line from the middle position of the N first MOS transistors arranged in sequence along a second direction, and extending and arranging the second control line from the middle position of the N second MOS transistors arranged in sequence along the second direction, wherein the second direction is perpendicular to the first direction. The layout design method provided by the embodiment of the present application can optimize the parasitic capacitance in the chip.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of integrated circuits, and in particular to a layout design method for optimizing parasitic capacitance and a layout. BACKGROUND

[0002] The development of electronic products has provided convenience in all aspects of life, and the performance improvement of electronic products mainly depends on the progress of chips. Chips are mainly composed of semiconductor devices such as metal oxide semiconductor field effect transistors (MOS tubes), diodes, polysilicon resistors, capacitors, and triodes. In digital-analog hybrid chips, MOS tubes are usually used as analog switches to transmit and control signals. The structure of the chip is extremely small. In the structure of the chip, parasitic capacitance is generated due to the close distance between semiconductor devices or metal wires, which makes the performance of the chip not as expected when it is running. Under the size limitation of the chip, the distance between semiconductor devices or metal wires cannot be arbitrarily lengthened. Therefore, how to reduce the influence of parasitic capacitance on the performance of the chip on the basis of the original space has become a difficult problem that cannot be ignored. SUMMARY

[0003] In view of the above problems, embodiments of the present application provide a layout design method for optimizing parasitic capacitance and a layout, which can optimize the parasitic capacitance in the chip to reduce the influence of the parasitic capacitance on the key signal and improve the performance of the chip.

[0004] In a first aspect, embodiments of the present application provide a layout design method for optimizing parasitic capacitance, the method comprising:

[0005] arranging a plurality of first MOS tubes side by side along a first direction, and arranging a second MOS tube below each first MOS tube;

[0006] connecting the source of each first MOS tube with the source of the corresponding second MOS tube arranged below, connecting the drain of each first MOS tube with the drain of the corresponding second MOS tube arranged below, sequentially arranging the gate of N first MOS tubes with a first control line, and sequentially arranging the gate of N second MOS tubes corresponding to the N first MOS tubes arranged below with a second control line;

[0007] extending and arranging the first control line from the middle position of the N sequentially arranged first MOS tubes along a second direction, and extending and arranging the second control line from the middle position of the N sequentially arranged second MOS tubes along the second direction, wherein the second direction is perpendicular to the first direction, and N is an even number.

[0008] In a possible implementation, when N is greater than or equal to 4, the plurality of first MOS transistors located on both sides of the first control line and the plurality of second MOS transistors located on both sides of the second control line are simultaneously set to be connected in series or in parallel.

[0009] In a possible implementation, the N sequentially arranged first MOS transistors are recorded as a first MOS group, and the N sequentially arranged second MOS transistors are recorded as a second MOS group, and the method further includes:

[0010] A closed and symmetrical ground wire is arranged around the periphery of the first MOS group and the second MOS group; the gate in the first MOS group and the gate in the second MOS group are both partially located outside the ground wire.

[0011] In a possible implementation, a power supply line is arranged around the periphery of the ground wire, and the power supply line is parallel to the first direction.

[0012] In a possible implementation, the source of each of the plurality of first MOS transistors and the plurality of second MOS transistors is connected to a source lead-out line;

[0013] The drain of each of the plurality of first MOS transistors and the plurality of second MOS transistors is connected to a drain lead-out line.

[0014] The source lead-out line and the drain lead-out line are arranged around the periphery of the ground wire and are parallel to the first direction.

[0015] In a possible implementation, the source lead-out line and the drain lead-out line are arranged around the periphery of the ground wire, including:

[0016] The source lead-out line and the drain lead-out line are arranged on the same side of the ground wire, or are arranged on two sides of the ground wire respectively.

[0017] In a possible implementation, the distance between the source lead-out line and the ground wire is greater than or equal to a first threshold value, and the distance between the drain lead-out line and the ground wire is greater than or equal to the first threshold value.

[0018] In a possible implementation, the source lead-out line and the drain lead-out line are arranged on a first metal layer.

[0019] The source lead-out line and the drain lead-out line are arranged in a U-shaped metal shielding layer, and an opening of the U-shaped metal shielding layer faces the first metal layer; the source is connected to the source lead-out line through a first opening on a first side face of the metal shielding layer, and the drain is connected to the drain lead-out line through a second opening on a second side face of the metal shielding layer, the first side face being a side face facing the source, and the second side face being a side face facing the drain.

[0020] In a possible implementation, the first control line and the second control line are both clock lines.

[0021] In a second aspect, the embodiments of the present application provide a layout for optimizing parasitic capacitance, comprising a plurality of first MOS transistors, a plurality of second MOS transistors, a first control line and a second control line.

[0022] The plurality of first MOS transistors are arranged side by side along a first direction, and each first MOS transistor is correspondingly arranged with a second MOS transistor below.

[0023] The source of each first MOS transistor is connected with the source of the second MOS transistor correspondingly arranged below, and the drain of each first MOS transistor is connected with the drain of the second MOS transistor correspondingly arranged below.

[0024] The first control line is arranged to extend from the middle position of the N sequentially arranged first MOS transistors along a second direction, and the second control line is arranged to extend from the middle position of the N sequentially arranged second MOS transistors along the second direction, and the second direction is perpendicular to the first direction, wherein N is an even number.

[0025] The layout for optimizing parasitic capacitance provided by the embodiments of the present application can ensure that, when the first control line or the second control line is extended from the sequentially arranged MOS transistors along the second direction, the parasitic capacitance generated between the first control line and the source D connection line on both sides can be offset, the parasitic capacitance generated between the first control line and the drain S connection line on both sides can be offset, the parasitic capacitance between the second control line and the source D connection line on both sides can be offset, and the parasitic capacitance generated between the second control line and the drain S connection line on both sides can be offset, thereby optimizing the parasitic capacitance in the chip, reducing the influence of the parasitic capacitance on the key signal, and improving the performance of the chip.

[0026] The above description is only a summary of the technical solutions of the embodiments of the present application, in order to more clearly understand the technical means of the embodiments of the present application, the embodiments of the present application can be implemented according to the content of the specification, and in order to make the above and other purposes, characteristics and advantages of the embodiments of the present application more obvious and easy to understand, the following specific embodiments of the present application are described. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort.

[0028] Figure 1 is a schematic diagram of an application circuit provided by an embodiment of the present application.

[0029] Figure 2 is a layout provided by an embodiment of the present application corresponding to Figure 1 .

[0030] Figure 3 is a method flowchart provided by an embodiment of the present application.

[0031] Figure 4 is a layout structure schematic diagram provided by an embodiment of the present application corresponding to Figure 3 .

[0032] Figure 5 is a layout provided by an embodiment of the present application corresponding to Figure 4 . DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solutions and advantages of the embodiments of the present application more clear, the following will combine the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are some embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without any creative effort are within the scope of protection of the present application.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description of the specification of the application is only for the purpose of describing specific embodiments and is not intended to limit the application; the terms "comprise" and "have" and any variations thereof in the specification and claims of the application and the drawings description are intended to cover non-exclusive inclusion.

[0035] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearance of the phrase "an embodiment" in various places in the specification does not necessarily all refer to the same embodiment, nor is it necessarily independent or alternative embodiments to other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0036] The term "and / or", used in the present application, only describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the three cases of A existing, A and B existing, and B existing. In addition, the character " / " in the present application generally represents that the front and rear associated objects are in an "or" relationship.

[0037] In addition, the terms "first", "second", and the like in the description and claims of the present application or the above-mentioned drawings are used to distinguish different objects, and are not used to describe a specific order, which can be explicitly or implicitly included one or more features.

[0038] In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more (including two), and similarly, "a plurality of groups" means two or more groups (including two groups).

[0039] In the description of the present application, it should be noted that, unless otherwise specified and limited, the terms "mounting", "connection" and "connection" should be understood in a broad sense, for example, the "connection" or "connection" of the mechanical structure can mean a physical connection, for example, the physical connection can be a fixed connection, for example, a fixed connection by a fixing member, for example, a fixed connection by a screw, bolt or other fixing member; the physical connection can also be a detachable connection, for example, a mutual clamping or clamping connection; the physical connection can also be integrally connected, for example, welded, bonded or integrally formed to form a connection for connection. The "connection" or "connection" of the circuit structure can mean a physical connection, an electrical connection or a signal connection, for example, it can be directly connected, that is, physically connected, or indirectly connected through at least one intermediate element, as long as the circuit is connected, it can also be the connection between two elements; signal connection can be signal connection through circuit, or signal connection through media medium, for example, radio wave. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0040] In order for those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the drawings.

[0041] With the development of science and technology, the performance requirements of devices on chips are becoming higher and higher. The chip is mainly composed of MOS tubes, and multiple MOS tubes can be combined into logic gates, such as AND gate, NOT gate, NAND gate, NOR gate, etc. The logic gate can be combined into flip-flop, latch, etc. The flip-flop and latch can be combined into adder, multiplier, memory, etc. By combining MOS tubes with different functions, the computing function of the chip is realized.

[0042] The structure of the chip is extremely small, so the distance between semiconductor devices or metal wires in the circuit structure of the chip is close. When the semiconductor devices or metal wires are powered on, if the distance is close, a parasitic capacitance is generated between the two semiconductor devices or the two metal wires. The parasitic capacitance does not belong to the part of the circuit scheme and has an influence on the performance of the circuit, so that the performance when the circuit is running is not as expected. When the distance between the semiconductor devices or the metal wires is far, the parasitic capacitance can be reduced or disappeared, but under the limitation of the size of the chip, the distance between the semiconductor devices or the metal wires cannot be arbitrarily lengthened. Therefore, how to reduce the influence of the parasitic capacitance on the performance of the chip on the basis of the original space has become a difficult problem that cannot be ignored.

[0043] The layout design method for optimizing the parasitic capacitance provided by the embodiment of the present application can be used to optimize the parasitic capacitance in the chip, so as to reduce the influence of the parasitic capacitance on the key signal and improve the performance of the chip. Figure 1 is a schematic diagram of an application circuit provided by the embodiment of the present application. As shown in Figure 1 , in a certain transmission gate switch structure circuit, N-channel MOS tubes MN1, MN2 and MN3 and P-channel MOS tubes MP1, MP2 and MP3 are included, wherein MN1 and MP1, MN2 and MP2, and MN3 and MP3 are respectively arranged in parallel, the substrates of MN1, MN2 and MN3 are respectively connected to a ground line GND, the substrates of MP1, MP2 and MP3 are respectively connected to a power supply line VDD, the gates G of MP1, MP2 and MP3 are respectively connected to control lines G1, G2 and G3, the gates G of MN1, MN2 and MN3 are respectively connected to control lines G1i, G2i and G3i, and the sources D of MN1, MN2, MN3, MP1, MP2 and MP3 are all connected to a source lead-out line netp, and the drains S are all connected to a drain lead-out line netn.

[0044] Figure 2 is a layout corresponding to Figure 1 provided by the embodiment of the present application. As shown in Figure 2As shown, a plurality of N-channel MOS tubes 01 are distributed side by side, a plurality of P-channel MOS tubes 02 are distributed below the plurality of N-channel MOS tubes 01, the position of the plurality of N-channel MOS tubes 01 is recorded as area 03, and the position of the plurality of P-channel MOS tubes 02 is recorded as area 04, then the source lead netp is arranged above the area 04, the drain lead netn is arranged below the area 03, and the source lead netp and the drain lead netn have a distance therebetween. The side of the source lead netp close to the area 04 is recorded as a first side, the ground wire GND is arranged around the other three sides of the N area, the side of the drain lead netn close to the area 03 is recorded as a second side, and the power supply wire VDD is arranged around the other three sides of the P area. The control lines G1, G2, and G3 pass through the power supply wire VDD between the source D and the drain S of each N-channel MOS tube 01 in the area 03 and extend outside the power supply wire VDD, and the control lines G1i, G2i, and G3i pass through the ground wire GND between the source D and the drain S of each P-channel MOS tube 02 in the area 04 and extend outside the ground wire GND.

[0045] The layout shown in Figure 2 can realize the function of the circuit in Figure 1 , but as can be seen from Figure 2 , the source lead netp and the ground wire GND overlap more, the drain lead netn and the power supply wire VDD overlap more, and the source lead netp or the drain lead netn has natural inconsistency with the power supply wire VDD and the ground wire GND, so Figure 2 the layout shown in the working process of power-on, the parasitic capacitance between the source lead netp and the control line, the parasitic capacitance between the drain lead netn and the control line cannot be matched, and the parasitic capacitance between the source lead netp and the power supply wire VDD, the parasitic capacitance between the source lead netp and the ground wire GND, the parasitic capacitance between the drain lead netn and the power supply wire VDD, and the parasitic capacitance between the drain lead netn and the ground wire GND also cannot be matched with each other, which greatly affects the power supply rejection ratio (PSRR) and common-mode rejection ratio (CMRR) performance of the circuit.

[0046] In order to solve the above problems, the embodiment of the present application provides a layout design method and layout for optimizing parasitic capacitance, which can optimize the parasitic capacitance in the chip and improve the performance of the chip.

[0047] The technical solutions in the present application will be described in detail below with reference to the drawings. It should be noted that, in the case of no conflict, different technical features in the present application can be combined with each other.

[0048] Figure 3is a method flowchart provided by an embodiment of the present application. As shown in Figure 3 The layout design method for optimizing parasitic capacitance provided by the embodiment of the present application comprises the following steps.

[0049] S101, a plurality of first MOS transistors are arranged side by side along a first direction, and a second MOS transistor is arranged below each first MOS transistor.

[0050] Optionally, the first MOS transistor and the second MOS transistor can each include any one or more of an enhancement mode N-channel MOS transistor, an enhancement mode P-channel MOS transistor, a depletion mode N-channel MOS transistor, and a depletion mode P-channel MOS transistor. For example, the first MOS transistor can only include a depletion mode N-channel MOS transistor, or the first MOS transistor can include an enhancement mode P-channel MOS transistor and a depletion mode N-channel MOS transistor, or the first MOS transistor can include an enhancement mode N-channel MOS transistor, an enhancement mode P-channel MOS transistor, a depletion mode N-channel MOS transistor, and a depletion mode P-channel MOS transistor. For example, as shown in Figure 1 the circuit diagram, the first MOS transistor can be an enhancement mode N-channel MOS transistor, and the corresponding second MOS transistor can be an enhancement mode P-channel MOS transistor.

[0051] A MOS transistor is composed of a source D, a drain S, and a gate G, Figure 4 is a layout structure diagram corresponding to Figure 3 provided by an embodiment of the present application, Figure 5 is a layout corresponding to Figure 4 provided by an embodiment of the present application. As shown in Figure 4 and Figure 5 , Figure 4 there are six first MOS transistors 10 and six second MOS transistors 20, and the first direction is the left-to-right direction in Figure 4 . According to step S101, the six first MOS transistors 10 can be arranged above the layout along the first direction, and the six second MOS transistors 20 can be arranged below the layout along the first direction, and the six first MOS transistors 10 and the six second MOS transistors 20 can be corresponded one by one.

[0052] S102, the source D of each first MOS transistor is connected to the source D of the corresponding second MOS transistor arranged below, the drain S of each first MOS transistor is connected to the drain S of the corresponding second MOS transistor arranged below, the gate G of N first MOS transistors arranged in sequence is connected to a first control line, and the gate G of N second MOS transistors arranged below the N first MOS transistors is connected to a second control line.

[0053] As shown in Figure 4 and Figure 5As shown, after step S101, the first MOSFET 10 and the second MOSFET 20 are arranged such that the source D is vertically aligned with the source D, and the drain S is vertically aligned with the drain S. Therefore, the source D can be directly connected to the source D, and the drain S can be directly connected to the drain S, making the wiring on the layout simple and efficient.

[0054] Furthermore, in order to control the circuit via MOSFETs, the gate G of each MOSFET is connected to a control line. For example, combined with... Figure 4 and Figure 5 As shown, the gates G of the two first MOS transistors 10 arranged in sequence are both connected to the first control line G1, and the gates G of the two second MOS transistors 20 arranged in sequence are both connected to the second control line G1i.

[0055] Optionally, the control line can be a clock line or other signal control line, and this application does not limit this.

[0056] like Figure 4 As shown, in one implementation, both the first control line and the second control line are clock lines.

[0057] Clock signals have a fixed frequency and are typically used in synchronization circuits to ensure that related electronic components operate synchronously. Synchronizing different processing steps of a chip using clock signals is fundamental to the chip's proper functioning.

[0058] Clock lines provide a synchronized clock signal for the chip, so the ability of clock lines to operate without interference is particularly important for chip performance.

[0059] It should be understood that the clock lines can be reverse clocks, all positive clocks, or all reverse clocks; this application does not impose any restrictions on this. Since both the first and second control lines are clock lines, it ensures that the clock lines are not interfered with by parasitic capacitance, thereby ensuring that the MOS transistors connected to the first and second control lines can operate normally and improving chip performance.

[0060] S103. The first control line extends from the middle position of N sequentially arranged first MOS transistors along the second direction, and the second control line extends from the middle position of N sequentially arranged second MOS transistors along the second direction, the second direction being perpendicular to the first direction, where N is an even number.

[0061] by Figure 4 For example, the second direction is Figure 4 From top to bottom, it can be seen that the length directions of the source D and drain S of the first and second MOS transistors are parallel to the second direction. The gate G is between the source D and drain S of each MOS transistor, and there is a gap between the two MOS transistors arranged in sequence, so the control line connected to the gate G can pass through the gap.

[0062] The first control line G1 extends from the middle position of the sequentially arranged plurality of first MOS tubes 10 along the second direction, and the second control line G1i extends from the middle position of the sequentially arranged plurality of second MOS tubes 20 along the second direction. The first control line G1 can be located in the middle of the gate G of the plurality of first MOS tubes 10 and the middle of the gate G of the plurality of second MOS tubes 20, and the second control line G1i can be located in the middle of the gate G of the plurality of second MOS tubes, so that the parasitic capacitances on both sides of the first control line G1 and / or the second control line G1i are matched when the chip is powered on, and the parasitic capacitances between the source D connection line and the first control line G1 and between the drain S connection line and the first control line G1 are inconsistent, and the parasitic capacitances between the source D connection line and the second control line G1i and between the drain S connection line and the second control line G1i are inconsistent, and then the parasitic capacitances on both sides of the first control line G1 and the second control line G1i are offset, and the influence of the parasitic capacitance on the performance of the chip is reduced.

[0063] It should be noted that the source D connection line and the drain S connection line are the connection lines between the source D and the source D and between the drain S and the drain S of the upper and lower corresponding MOS tubes. In the embodiment of the application, since the first MOS tube and the second MOS tube are upper and lower corresponding, the connection lines of the corresponding structures between the first MOS tube and the second MOS tube are straight lines along the second direction, such as the source D connection line and the drain S connection line.

[0064] For example Figure 4 As shown in FIG. 1, the control line G1 extends from the middle position of the two adjacent first MOS tubes along the second direction, and passes through the middle position of the second MOS tube. The control line G1i extends from the middle position of the two adjacent second MOS tubes along the second direction. It should be understood that the control line G1 and the control line G1i are partially overlapped in the direction of the top view, and are parallel to each other in the thickness direction in the side view. Figure 4 As shown in FIG. 1, the control line G1 extends from the middle position of the two adjacent first MOS tubes along the second direction, and passes through the middle position of the second MOS tube. The control line G1i extends from the middle position of the two adjacent second MOS tubes along the second direction. It should be understood that the control line G1 and the control line G1i are partially overlapped in the direction of the top view, and are parallel to each other in the thickness direction in the side view.

[0065] Alternatively, the first control line and / or the second control line can also extend along the opposite direction of the second direction. For example, the first control line can extend upward along the opposite direction of the second direction, and the second control line can extend downward along the second direction; or the first control line and the second control line can both extend upward along the opposite direction of the second direction; or the first control line and the second control line can both extend downward along the second direction. It can be understood that the first control line and the second control line both extend from the middle position of the MOS tube along the second direction or the opposite direction of the second direction, so that the distance between the control line and the source D connection line and the drain S connection line is equal, and then the parasitic capacitances on both sides of the control line are offset, the parasitic capacitance in the chip is optimized, the influence of the parasitic capacitance on the key signal is reduced, and the performance of the chip is improved.

[0066] The layout design method for optimizing parasitic capacitance provided by the embodiment of the present application can ensure that, when the first control line or the second control line is extended from the sequentially arranged MOS transistors along the second direction, the parasitic capacitances generated between the first control line and the source D wires on both sides can be offset, the parasitic capacitances generated between the first control line and the drain S wires on both sides can be offset, the parasitic capacitances between the second control line and the source D wires on both sides can be offset, and the parasitic capacitances generated between the second control line and the drain S wires on both sides can be offset, thereby optimizing the parasitic capacitance in the chip, reducing the influence of the parasitic capacitance on the key signal, and improving the performance of the chip.

[0067] Optionally, when N is greater than or equal to 4, the plurality of first MOS transistors located on both sides of the first control line and the plurality of second MOS transistors located on both sides of the second control line are simultaneously set to be connected in series or in parallel.

[0068] It can be understood that two or more MOS transistors can be set to be connected in series or in parallel as needed. When the N first MOS transistors 10 are connected in series, the second MOS transistors 20 corresponding to them below the layout are also connected in series. When the N first MOS transistors 10 are connected in parallel, the second MOS transistors 20 corresponding to them below the layout are also connected in parallel.

[0069] Through the consistent connection mode of the MOS transistors corresponding above and below, it can be ensured that the source D and the drain S of the MOS transistors on both sides of the control line always remain consistent, thereby further optimizing the parasitic capacitance and improving the performance of the chip.

[0070] Optionally, the N sequentially arranged first MOS transistors are recorded as a first MOS group, and the N sequentially arranged second MOS transistors are recorded as a second MOS group. The method provided by the embodiment of the present application further comprises:

[0071] A closed and symmetrical ground wire is arranged around the periphery of the first MOS group and the second MOS group. The gate in the first MOS group and the gate in the second MOS group are both partially located outside the ground wire.

[0072] Specifically, a closed and symmetrical ground line is arranged around the source (D) and drain (S) of N sequentially arranged first MOSFETs and the source (D) and drain (S) of N sequentially arranged second MOSFETs. The gates (G) of the first and second MOSFETs are partially located outside the ground line. The gate (G) of the first MOSFETs is connected to the control line G1, and the gate (G) of the second MOSFETs is connected to the control line G1i. Both control lines G1 and G1i are inside the ground line, and the control lines are shielded by the ground line to reduce parasitic resistance in the chip.

[0073] Combination Figure 4 and Figure 5 ,by Figure 5 Taking the ground line 30 as an example, the first control line G2 is located between two adjacent first MOS transistors 10 and two adjacent second MOS transistors 20, and the second control line G2i is located between two adjacent second MOS transistors 20. A closed square ground line 30 is set around the source D and drain S of the above four MOS transistors, so that the parasitic capacitance generated by the source D, drain S and ground line 30 is consistent, thereby canceling the parasitic capacitance on both sides of the control line, and the control line can be located in the middle position of the ground line 30.

[0074] It is understandable that the multiple first MOSFETs and multiple second MOSFETs can be divided into multiple groups, with multiple ground lines surrounding each group. The specific grouping method is designed according to the circuit requirements. This application does not limit the grouping method. It should be noted that the middle position of each group along the first direction must be the location of the control line. By placing the control line in the middle of the multiple MOSFETs, the parasitic capacitance on both sides of the control line is made consistent, thereby canceling the parasitic capacitance generated between the control line and the MOSFETs and improving chip performance.

[0075] By extending control lines from the middle of N sequentially arranged MOS transistors along a second direction, and setting closed and symmetrical ground lines around the source D and drain S of the N sequentially arranged MOS transistors, the parasitic capacitances between the source D, drain S and ground lines can be made consistent. Placing a portion of the gate G connected to the control lines outside the ground lines ensures that the parasitic capacitances generated between the first control line and ground line and between the second control line and ground line located at the middle of the ground lines are consistent. This allows the parasitic capacitances between the control lines and ground line, and between the source and drain and ground lines, to cancel each other out, reducing the impact of parasitic capacitances on critical signals and improving chip performance.

[0076] Optionally, a power line can be installed around the ground wire, with the power line parallel to the first direction.

[0077] Outside the ground wire, along the first direction, the power line can be positioned above the first MOSFET or below the second MOSFET. For example, Figure 4 and Figure 5In the embodiment, the power line VDD is arranged above the first MOS transistor 10.

[0078] By arranging the power line VDD along the first direction on the periphery of the ground line, the parasitic capacitance between each control line and the power line VDD can be ensured to be consistent, so that the parasitic capacitance between the power line VDD and the control line is offset, the parasitic capacitance in the chip is optimized, and the performance of the chip is improved.

[0079] Optionally, the sources D of the plurality of first MOS transistors and the plurality of second MOS transistors are connected with the source lead-out line netp, the drains S of the plurality of first MOS transistors and the plurality of second MOS transistors are connected with the drain lead-out line netn, and the source lead-out line netp and the drain lead-out line netn are arranged on the periphery of the ground line and are parallel to the first direction.

[0080] The source D of the MOS transistor is connected with the source lead-out line netp, and the drain S of the MOS transistor is connected with the drain lead-out line netn, and the source lead-out line netp and the drain lead-out line netn are parallel to the first direction, so that the parasitic capacitance generated between each control line and the source lead-out line netp or the drain lead-out line netn can be ensured to be consistent, so as to offset the parasitic capacitance between the source lead-out line netp and the control line and the parasitic capacitance between the drain lead-out line netn and the control line.

[0081] Optionally, the source lead-out line netp and the drain lead-out line netn are arranged on the periphery of the ground line, and the source lead-out line netp and the drain lead-out line netn are parallel to the first direction.

[0082] The source lead-out line netp and the drain lead-out line netn are arranged on the same side of the ground line, or are arranged on two sides of the ground line respectively.

[0083] As shown in FIGS. 1, 2 and 3, the source lead-out line netp is arranged above the ground line GND, the drain lead-out line netn is arranged above the ground line GND, and the source lead-out line netp and the drain lead-out line netn extend along the first direction one above the other. Figure 4 and Figure 5 The source lead-out line netp and the drain lead-out line netn are arranged on the same side of the ground line GND, which can save the area occupied by the circuit and save the layout resource.

[0084] It can be understood that, if the size of the layout allows, the source lead-out line netp and the drain lead-out line netn can be arranged on two sides of the ground line GND.

[0085] Through the two arrangement modes of the source lead-out line netp and the drain lead-out line netn, two feasible designs for layout designers when facing different design requirements are provided.

[0086] Optionally, the distance between the source lead netp and the ground line is greater than or equal to the first threshold, and the distance between the drain lead netn and the ground line is greater than or equal to the first threshold.

[0087] The minimum value of the distance between the source lead netp and the ground line GND and the distance between the drain lead netn and the ground line GND is greater than or equal to the first threshold. Figure 5 It can be seen that the distance between the source lead netp or the drain lead netn and the ground line GND is greater than the distance between the power line VDD and the ground line GND, thereby reducing the mutual influence between the source lead netp or the drain lead netn and the ground line GND.

[0088] By setting the distance between the source lead netp and the drain lead netn and the ground line GND to be greater than or equal to the first threshold, the mutual influence between the source lead netp or the drain lead netn and the ground line GND is reduced, thereby reducing the parasitic capacitance between the source lead netp or the drain lead netn and the ground line GND, further optimizing the parasitic capacitance, reducing the influence of the parasitic capacitance on the key signal, and improving the performance of the chip.

[0089] Optionally, the source lead netp and the drain lead netn are arranged in the first metal layer.

[0090] The source lead and the drain lead are arranged in the U-shaped metal shielding layer, and the opening of the U-shaped metal shielding layer faces the first metal layer; the source D is connected to the source lead netp through the first opening in the first side of the metal shielding layer, and the drain S is connected to the drain lead netn through the second opening in the second side of the metal shielding layer, the first side being the side facing the source D, and the second side being the side facing the drain S.

[0091] The chip is made of a material having a thickness, and the circuit in the chip has multiple layers in the thickness direction. Therefore, the layout manufactured for the chip should include multiple layers. On this basis, in order to further reduce the occurrence of parasitic capacitance, the source lead netp and the drain lead netn are arranged in the U-shaped metal shielding layer to prevent parasitic capacitance from being generated with other electronic elements when the circuit is powered on. It can be understood that the U-shaped of the U-shaped metal shielding layer refers to the U-shaped or inverted U-shaped seen from the thickness direction of the chip.

[0092] When the source lead netp and the drain lead netn are arranged in the U-shaped metal shielding layer, and the source D and the drain S of the first MOS and the second MOS need to be connected with the source lead netp and the drain lead netn respectively, a hole is needed to be opened on the side of the U-shaped metal shielding layer facing the source D or the drain S, and the hole is located at the intersection of the source D or the drain S and the side of the U-shaped metal shielding layer along the second direction, so that the connection line between the source D and the source lead netp is a straight line, and the connection line between the drain S and the drain lead netn is a straight line, which makes the layout neat and reduces the processing difficulty.

[0093] Reference Figure 5 The embodiment of the present application also provides a layout for optimizing parasitic capacitance, which comprises a plurality of first MOS, a plurality of second MOS, a first control line and a second control line.

[0094] The plurality of first MOS are arranged side by side along a first direction, and each first MOS is correspondingly provided with a second MOS below.

[0095] The source D of each first MOS is connected with the source D of the second MOS correspondingly arranged below, the drain S of each first MOS is connected with the drain S of the second MOS correspondingly arranged below, the gate G of N first MOS arranged in sequence is connected with the first control line, and the gate G of N second MOS correspondingly arranged below the N first MOS is connected with the second control line.

[0096] The first control line is arranged to extend from the middle position of the N first MOS arranged in sequence along a second direction, the second control line is arranged to extend from the middle position of the N second MOS arranged in sequence along the second direction, and the second direction is perpendicular to the first direction, wherein N is an even number.

[0097] Optionally, when N is greater than or equal to 4, the plurality of first MOS located on both sides of the first control line and the plurality of second MOS located on both sides of the second control line are connected in series or in parallel.

[0098] Optionally, the N first MOS arranged in sequence are regarded as a first MOS group, the N second MOS arranged in sequence are regarded as a second MOS group, and a closed and symmetrical ground wire is arranged around the periphery of the first MOS group and the second MOS group, and the gate in the first MOS group and the gate G in the second MOS group are both partially located outside the ground wire.

[0099] Optionally, a power supply line is arranged around the periphery of the ground wire, and the power supply line is parallel to the first direction.

[0100] Optionally, the source D of the plurality of first MOS and the source D of the plurality of second MOS are connected with the source lead netp.

[0101] The drain of the plurality of first MOS transistors and the drain of the plurality of second MOS transistors are connected with a drain lead-out line netn.

[0102] The source lead-out line netp and the drain lead-out line netn are arranged on the periphery of the ground line and are parallel to the first direction.

[0103] Optionally, the source lead-out line netp and the drain lead-out line netn are arranged on the same side of the ground line or are arranged on two sides of the ground line respectively.

[0104] Optionally, the distance between the source lead-out line netp and the ground line is greater than or equal to a first threshold value, and the distance between the drain lead-out line netn and the ground line is greater than or equal to the first threshold value.

[0105] Optionally, the source lead-out line netp and the drain lead-out line netn are arranged in the U-shaped metal shielding layer. The source D is connected with the source lead-out line netp through the first opening of the metal shielding layer on the first side, and the drain S is connected with the drain lead-out line netn through the second opening of the metal shielding layer on the second side. The first side is a side facing the source D, and the second side is a side facing the drain S.

[0106] Optionally, the first control line and the second control line are clock lines.

[0107] In summary, the layout design method for optimizing parasitic capacitance and the layout provided by the embodiments of the present application can ensure that, when the first control line or the second control line is extended from the MOS transistors arranged in sequence along the second direction, the parasitic capacitances generated between the first control line and the source D wires on both sides can be offset, the parasitic capacitances generated between the first control line and the drain S wires on both sides can be offset, the parasitic capacitances between the second control line and the source D wires on both sides can be offset, and the parasitic capacitances generated between the second control line and the drain S wires on both sides can be offset, thereby offsetting the parasitic capacitances between the control lines and the MOS transistors in the chip.

[0108] It should be understood that, in addition to being applicable to MOS transistors, the layout design method for optimizing parasitic capacitance provided by the embodiments of the present application can also be applicable to transistors with switching functions such as diodes and triodes. The layout obtained by arranging the transistors according to the layout design method provided by the embodiments of the present application can optimize the parasitic capacitance in the chip, offset the parasitic capacitances between the signal lines, reduce the influence of the parasitic capacitance on the key signals, and improve the performance of the chip.

[0109] In several embodiments and claims of the present application, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. It is possible that several embodiments of the present application can be implemented by means of both hardware and software, and that the present application can be implemented by means of an apparatus, such as a computer program running on a computer, software, or the like. The use of the terms "first", "second" and other such terminology does not imply any order but can be used to name different components. Steps in the embodiments described above are not to be construed as necessarily limited to the order in which they are presented.

[0110] The above-described embodiments are merely intended to illustrate the technical solutions of the present application, but not to limit the same; even though the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still make modifications to the technical solutions recorded in the foregoing embodiments, or make equivalent replacements to some of the technical features; and these modifications or replacements do not cause the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A layout design method for optimizing parasitic capacitance, characterized in that, The method includes: Multiple first MOS transistors are arranged side by side along a first direction, and a second MOS transistor is arranged below each first MOS transistor. The source of each first MOS transistor is connected to the source of the corresponding second MOS transistor located below it, and the drain of each first MOS transistor is connected to the drain of the corresponding second MOS transistor located below it. The gates of the N first MOS transistors arranged in sequence are connected to the first control line, and the gates of the N second MOS transistors located below the N first MOS transistors are connected to the second control line. The first control line extends from the middle position of the N sequentially arranged first MOS transistors along the second direction, and the second control line extends from the middle position of the N sequentially arranged second MOS transistors along the second direction, wherein the second direction is perpendicular to the first direction, and N is an even number. The method further includes: designating the N sequentially arranged first MOS transistors as the first MOS group, and the N sequentially arranged second MOS transistors as the second MOS group; A closed and symmetrical ground line is provided around the periphery of the first MOS group and the second MOS group; the gates of the first MOS group and the second MOS group are partially located outside the ground line.

2. The method according to claim 1, characterized in that, The method further includes: When N is greater than or equal to 4, the multiple first MOS transistors located on both sides of the first control line and the multiple second MOS transistors located on both sides of the second control line are simultaneously configured to be connected in series or in parallel.

3. The method according to claim 1, characterized in that, The method further includes: A power line is provided around the ground wire, and the power line is parallel to the first direction.

4. The method according to claim 1, characterized in that, The method further includes: The sources of the plurality of first MOS transistors and the plurality of second MOS transistors are all connected to the source leads; The drains of the plurality of first MOS transistors and the plurality of second MOS transistors are all connected to the drain leads; The source lead and the drain lead are positioned around the ground wire and parallel to the first direction.

5. The method according to claim 4, characterized in that, The step of placing the source lead and the drain lead around the ground wire includes: The source lead and the drain lead are located on the same side of the ground wire, or on opposite sides of the ground wire.

6. The method according to claim 4 or 5, characterized in that, The distance between the source lead and the ground line is greater than or equal to a first threshold, and the distance between the drain lead and the ground line is greater than or equal to the first threshold.

7. The method according to claim 6, characterized in that, The method further includes: The source lead and the drain lead are disposed on the first metal layer; The source lead and the drain lead are disposed within a U-shaped metal shielding layer, with the opening of the U-shaped metal shielding layer facing the first metal layer; The source electrode is connected to the source electrode lead through a first opening on the first side of the metal shielding layer, and the drain electrode is connected to the drain electrode lead through a second opening on the second side of the metal shielding layer. The first side faces the source electrode, and the second side faces the drain electrode.

8. The method according to claim 1, characterized in that, Both the first control line and the second control line are clock lines.

Images