Neuron unit circuit, spiking neural network and intelligent Internet of Things chip

Abstract

The present invention discloses a neuron unit circuit, a spiking neural network, and an intelligent Internet of Things chip. The neuron unit circuit includes: a dendrite circuit, a synaptic circuit containing a membrane potential capacitor, a cell body circuit, and a timing planning module. The dendrite circuit generates a reset signal and a calculation signal that does not overlap with the reset signal according to an input pulse signal or an output pulse signal of the cell body circuit of the previous layer of neurons. The synaptic circuit stores weights and performs a potential accumulation operation on the membrane potential capacitor according to the stored weights and the output of the dendrite circuit. The cell body circuit compares the membrane potential of the membrane potential capacitor with a threshold voltage to determine whether to output a pulse signal. The timing planning module is used to generate a timing according to an input pulse signal or an enable signal output by the previous layer of neuron units, so that the threshold voltage is stored in the threshold capacitor before the cell body performs a comparison operation, and to trigger the cell body to perform a comparison operation. The present invention realizes an ultimate event-driven circuit from the system level, module level to the circuit level.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular, to a neuron unit circuit, a spiking neural network, and an intelligent Internet of Things chip. Background Art

[0002] As more and more Internet of Things electronic devices emerge, the demand for Internet of Things chips is also increasing. For chips, power consumption and latency are important considerations for their performance.

[0003] Event-driven chips have gradually become the mainstream in the design of Internet of Things chips due to their low power consumption and latency. Figure 1 For the schematic diagram of the brain-like model, as Figure 1 shown, the spiking neural network (SNN for short) draws on the mechanism of the human brain to process information and simulates the working mode of the human brain. It directly uses the spike firing time of neurons as its input and output, makes full use of time information, and has spike sparsity. At the same time, when a spiking neuron receives a spike, it accumulates the input to the membrane potential and only fires a spike when the membrane potential reaches the threshold, which is event-driven. Due to the spike sparsity of SNN and its event-driven nature, it can process information more efficiently similar to the human brain, achieving low latency and low power consumption. Therefore, the application of SNN chips in the intelligent Internet of Things will become a trend.

[0004] Existing SNN chips are mainly digital circuits based on the global asynchronous local synchronous method to ensure the correct processing of spike trains. Due to the need for local synchronization, there are local clocks, which increase the hardware overhead and energy consumption. Moreover, the connections of neurons are not single. When a neuron is connected to multiple neurons, it will receive multiple spikes, and it is necessary to clarify the order of the spikes. Therefore, there are also waiting and conflict problems, which will be more serious when the network scale is large. Summary of the Invention

[0005] The present invention provides a neuron unit circuit, a spiking neural network, and an intelligent Internet of Things chip to overcome the technical problems existing in the above-mentioned prior art, realizing a clockless event-driven circuit at the circuit level, and each neuron can receive multiple spikes simultaneously without interfering with each other, avoiding waiting and conflicts.

[0006] A neuron unit circuit provided by the present invention includes: a dendrite circuit, a synaptic circuit containing a membrane potential capacitor, a cell body circuit, and a timing planning module. The dendrite circuit is configured to generate a reset signal and a calculation signal non-overlapping with the reset signal according to an input pulse signal or an output pulse signal of the cell body circuit of the previous layer of neurons. The synaptic circuit is configured to store weights and perform a potential accumulation operation on the membrane potential capacitor according to the stored weights and the output of the dendrite circuit. The weights are used to represent the connection strength between neurons and are stored in the synaptic circuit in digital complement form. The cell body circuit is configured to compare the membrane potential of the membrane potential capacitor with a threshold voltage to determine whether to output a pulse signal.

[0007] The timing planning module is configured to generate a timing according to an input pulse signal or an enable signal output by the previous layer of neuron units, so that the threshold voltage is stored in the threshold capacitor before the cell body performs a comparison operation, and to trigger the cell body to perform a comparison operation.

[0008] A pulse neural network provided by the present invention further includes a multi-layer neuron network. The neural network layers are in a fully connected structure. Each layer of neuron network includes at least two neuron unit circuits as described above. The input of the first layer of neuron network layer is an input pulse signal.

[0009] An intelligent Internet of Things chip provided by the present invention further includes: a wake-up chip and a high-performance module triggered by a wake-up signal output by the wake-up chip to enter a working mode. The wake-up chip includes a plurality of functional processing modules. Each functional processing module is triggered by an event to enter a working mode. Each functional processing module includes a plurality of circuit units. Each circuit unit includes the above-mentioned pulse neural network.

[0010] The present invention controls the operation of the synapse by generating a reset signal and a calculation signal non-overlapping with the reset signal according to an input pulse signal or an output pulse signal of the cell body circuit of the previous layer of neurons through the dendrite circuit, eliminating the need for a clock to generate timing and realizing a circuit-level asynchronous circuit; realizing digital-analog fusion and memory-computation integration through the synaptic circuit, improving the energy efficiency of the circuit; ensuring the correct comparison output of the cell body by generating timing according to an input pulse signal or an enable signal output by the previous layer of neuron units through the timing planning module. In addition, the weights represented by digital complements are stored in the synaptic circuit, the membrane potential is expressed by an analog level, and the membrane potential accumulation calculation is performed by an analog method, enabling the circuit to receive multiple pulses simultaneously and having an impact on the membrane potential voltage simultaneously without interference, thus avoiding the waiting and conflict problems between pulses. Since the membrane potential is expressed by an analog level, the natural leakage behavior of the analog circuit is utilized, and the time information between pulses is fully utilized in the continuous time domain, making the circuit more compatible with the neuron model. Description of the Drawings

[0011] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on these drawings.

[0012] Figure 1 It is a schematic diagram of a brain-like model;

[0013] Figure 2 It is a schematic diagram of a neuron unit circuit structure provided by an embodiment of the present invention;

[0014] Figure 3 It is a schematic diagram of a dendrite circuit structure provided by an embodiment of the present invention;

[0015] Figure 4 It is Figure 3 an input-output timing diagram;

[0016] Figure 5 It is a schematic diagram of a synaptic circuit structure provided by an embodiment of the present invention;

[0017] Figure 6 It is a schematic diagram of the charging process of the circuit when the synapse receives the excitatory reset signal Rst Ca;

[0018] Figure 7 It is a schematic diagram of the charge transfer when the synapse receives the excitatory calculation signal Excitation;

[0019] Figure 8 It is a schematic diagram of the discharging process of the circuit when the synapse receives the inhibitory reset signal Rst Cs;

[0020] Figure 9 It is a schematic diagram of the charge transfer when the synapse receives the inhibitory calculation signal Inhibition;

[0021] Figure 10 It is a schematic diagram of the equivalent structure of the membrane potential accumulation circuit;

[0022] Figure 11 It is a schematic diagram of the structure of a layer of network in a pulse neural network;

[0023] Figure 12 It is a schematic diagram of an intelligent Internet of Things chip structure provided by an embodiment of the present invention. Specific embodiments

[0024] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the described embodiments are only a part rather than all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0025] To make the technical solutions of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0026] Figure 2 A schematic diagram of a neuron unit circuit structure provided for an embodiment of the present invention is shown as Figure 2 shown. The neuron unit circuit includes: a dendrite circuit 10, a synaptic circuit 20 containing a membrane potential capacitor, a cell body circuit 30, and a timing planning module 40. The dendrite circuit 10 is configured to generate a reset signal and a calculation signal non-overlapping with the reset signal according to an input pulse signal or an output pulse signal of the cell body circuit of the previous layer of neurons. The synaptic circuit 20 is configured to store weights and perform a potential accumulation operation on the membrane potential capacitor according to the stored weights and the output of the dendrite circuit. The weights are used to represent the connection strength between neurons and are stored in the synaptic circuit in digital complement code. The cell body circuit 30 is configured to compare the membrane potential with a threshold voltage to determine whether to output a pulse signal. The timing planning module 40 is configured to generate a timing according to an input pulse signal or an enable signal output by the previous layer of neuron units, so that the threshold voltage is stored in the threshold capacitor before the cell body performs a comparison operation, and trigger the cell body to perform a comparison operation.

[0027] In this embodiment, the input of the neuron unit is an input pulse signal or a pulse signal output by the previous layer of neurons, without an internal clock. When the dendrite receives an input pulse, a reset signal and a calculation signal are generated by using a delay chain circuit, which are used to control the synaptic circuit. The operation of the synaptic circuit is triggered by the output signal of the dendrite, that is, the synaptic circuit is also an event-triggered circuit. Since the synaptic circuit itself stores calculation weights, it starts to work after receiving the trigger signal of the dendrite, and calculates the change in the voltage on the membrane potential capacitor according to the weights and the calculation signal of the dendrite circuit, that is, changes the membrane potential voltage. Since the timing planning module generates the timing of this layer according to the output pulse of the previous layer of neurons, controls the threshold voltage to be stored in the threshold capacitor in advance, and controls the cell body to compare the threshold capacitor with the membrane potential level according to the timing and output, the output of the cell body can be used as the input pulse signal of the dendrite of the next layer of neurons.

[0028] When the membrane potential accumulates to exceed a preset threshold voltage, the soma fires a pulse backward. If the membrane potential is lower than the threshold voltage, the membrane potential gradually returns to the resting level (Leakage). That is, the LIF neuron model is adopted in the embodiments of the present invention.

[0029] The membrane potential capacitor can simultaneously receive pulse signals from multiple dendrites to perform charge transfer, voltage increase and decrease calculations without conflict. At the same time, the synaptic circuit itself stores the weights involved in the calculations. The synaptic circuit weights are stored in the form of digital complements. The membrane potential is calculated using an analog potential in a digital-analog combination and memory-computation fusion method, which is actually a memory-computation integrated circuit. This enables the synaptic circuit in the embodiments of the present invention to avoid the work of data transfer within the neuron, thus having higher energy efficiency.

[0030] To achieve circuit-level event-driven without any clock, the dendrite circuit in the neurons of the present invention generates corresponding control and calculation signals based on the input pulse signals and makes them non-overlapping to ensure that the synaptic circuit can accurately calculate. Figure 3 FIG. [ID] is a schematic diagram of a dendrite circuit structure provided for an embodiment of the present invention. Figure 4 For Figure 3 the input-output timing diagram, as Figure 3 shown and Figure 4 shown, it uses a delay chain and corresponding logic gate structures to form pulse reset signals (Rst Ca and Rst Cs) and calculation signals (Excitation and Inhibition) with different time delays. Specifically, the reset signals include an excitatory reset signal Rst Ca and an inhibitory reset signal Rst Cs that is the inverse of the excitatory reset signal, and the calculation signals include an excitatory calculation signal Excitation and an inhibitory calculation signal Inhibition that is the inverse of the excitatory calculation signal.

[0031] The synaptic circuit includes: M excitatory units, N inhibitory units, M + N weight storage units, M + N logic AND gates, and a membrane potential capacitor. The M weight storage units and the excitatory calculation signal are correspondingly connected to the inputs of the M logic AND gates, the N weight storage units and the inhibitory calculation signal are correspondingly connected to the inputs of the N logic AND gates, the outputs of the M logic AND gates are correspondingly connected to the M excitatory units, the outputs of the N logic AND gates are correspondingly connected to the N inhibitory units. The excitatory reset signal output by the dendrite circuit is used to control whether the M excitatory units charge the membrane potential capacitor, and the inhibitory reset signal output by the dendrite circuit is used to control whether the N inhibitory units discharge the membrane potential capacitor, where M and N are both positive integers. Hereinafter, M = 3 and N = 1 are taken as examples for detailed description.

[0032] Figure 5 FIG. [ID] is a schematic diagram of a synaptic circuit structure provided for an embodiment of the present invention, as Figure 5As shown, the above-mentioned weight storage unit is a latch, and the weight is determined and controlled by the weight read / write module SPI. Each latch can store a one-bit (1bit) digital weight (1 or 0). The computing-in-memory synaptic circuit includes a 4-bit weight latch and an accumulation leakage circuit. The 4-bit (4bit) weight is stored in the latch in 4-bit two's complement form, which can simplify the hardware structure of the excitatory or inhibitory unit. The output of each latch is connected to the input of an AND logic gate, and the other input of the AND logic gate is the excitatory calculation signal or inhibitory calculation signal of the dendrite. The other input of the AND logic gates corresponding to bit0-bit2 is the excitatory calculation signal of the dendrite, and the other input of the AND logic gate corresponding to bit3 is the inhibitory calculation signal. Each synaptic circuit has 7 excitatory units and 1 inhibitory unit. The 7 excitatory units are divided into three groups (1, 2, 4) and are controlled by bit0-bit2 respectively, and the inhibitory unit is controlled by bit3. To better match the algorithm model in the excitatory and inhibitory behaviors, Cs / Ca is designed to be a linear relationship.

[0033] Figure 6 It is a schematic diagram of the charging process of the circuit when the synaptic receives the excitatory reset signal Rst Ca. Figure 7 It is a schematic diagram of the charge transfer when the synaptic receives the excitatory calculation signal Excitation. Figure 8 It is a schematic diagram of the discharging process of the circuit when the synaptic receives the inhibitory reset signal Rst Cs. Figure 9 It is a schematic diagram of the charge transfer when the synaptic receives the inhibitory calculation signal Inhibition. Figure 10 It shows a schematic diagram of the equivalent structure of the membrane potential accumulation circuit, as Figure 10 As shown, it can be seen from the equivalent structure on the right that the number of excitatory units and inhibitory units can be expanded according to the weight stored in the latch. Since it is an analog circuit charging for the membrane potential capacitor, multiple excitatory units charging it simultaneously will not conflict, and the charging and discharging do not affect each other. Moreover, the number of excitatory units that can participate in charging can be represented by the size of the digital stored weight value. Therefore, the digital-analog fusion and computing-in-memory are realized, which not only simplifies the hardware circuit but also effectively improves the energy efficiency of the circuit.

[0034] A single excitatory unit includes: a first PMOS transistor, a second PMOS transistor, and an excitatory unit capacitor. The drain of the first PMOS transistor is connected to the first power supply. The gate of the first PMOS transistor is connected to the excitatory reset signal output port of the dendrite circuit. The source of the first PMOS transistor is connected to the drain of the second PMOS transistor and the excitatory unit capacitor. The gate of the second PMOS transistor is connected to the excitatory calculation signal output port of the dendrite circuit. The source of the second PMOS transistor is connected to the membrane potential capacitor.

[0035] In this circuit, the first PMOS tube is controlled by the excitation reset signal connected to the gate to charge the excitation unit capacitor Ca, while the second PMOS tube is controlled by the excitation calculation signal connected to the gate to transfer the charge from the excitation unit capacitor Ca to the membrane potential capacitor Cmem.

[0036] Reference Figure 6 and Figure 7 During the operation of the above circuit, when the excitement reset signal pulse arrives, the excitement unit capacitor Ca is charged through the first PMOS tube, and its voltage is pulled to the power supply voltage VDD (1.2V). Subsequently, if any one of the M weight storage units is 1 and the excitement calculation signal arrives (the first PMOS tube is turned off), the gate voltage of the second PMOS tube is reduced from VDD (1.2V) to VSS (0.6V) by the corresponding AND logic gate, so that the drain and source of the second PMOS tube are turned on, and the charge is transferred from the excitement unit capacitor Ca to the membrane potential capacitor Cmem until the voltage on the excitement unit capacitor Ca drops to V DD / 2+|V thp | Turn off the second PMOS tube. When each pulse arrives, the charge transfer amount is the same, so the membrane potential increment is:

[0037]

[0038] Among them, V thp is the threshold voltage of the PMOS tube.

[0039] The following suppression units work similarly, see Figure 8 and Figure 9 The inhibition unit includes: a first NMOS tube, a second NMOS tube and an inhibition unit capacitor, the source of the first NMOS tube is grounded, the gate of the first NMOS tube is connected to the inhibition reset signal output port of the dendrite circuit, the drain of the first NMOS tube is connected to the source of the second NMOS tube and the inhibition unit capacitor, the gate of the second NMOS tube is connected to the inhibition calculation signal output port of the dendrite circuit, and the drain of the second NMOS tube is connected to the membrane potential capacitor.

[0040] The first NMOS transistor is controlled by the inhibition reset signal pulse connected to the gate to discharge the inhibition unit capacitor Cs, and the second NMOS transistor is controlled by the inhibition calculation signal of the gate to transfer charge from the membrane potential capacitor Cmem to the inhibition unit capacitor Cs. If any of the N weight storage units is 1 and the inhibition calculation signal arrives (the first NMOS transistor is turned off), the charge is transferred from the membrane potential capacitor Cmem to the inhibition unit capacitor Cs. The charge transfer amount is the same for each pulse, and the membrane potential reduction amount is:

[0041]

[0042] Among them, V thnis the threshold voltage of the NMOS transistor.

[0043] As Figure 10 shown, when M excitatory units and N inhibitory units charge and discharge the membrane potential simultaneously, the accumulation leakage circuit, that is, the membrane potential accumulation circuit, can be equivalent to including M excitatory units, N inhibitory units, and a membrane potential capacitor. Thus, when M excitatory units and N inhibitory units charge and discharge the membrane potential simultaneously, the change in the membrane potential voltage △Voltage can be obtained according to the following formula.

[0044]

[0045] It can be seen from the above formula that the neurons in the embodiments of the present invention can receive multiple pulses. Even if these pulses affect the membrane potential simultaneously, there will be no mutual interference, thus avoiding the problems of waiting and conflict between pulses.

[0046] From the above analysis and description, it can be known that the synaptic circuit not only realizes digital-to-analog fusion but also realizes memory and computing integration. The latch completes the digital storage of weights, the membrane potential accumulation circuit completes analog computing, and the stored digital weights participate in analog computing through the logic circuit.

[0047] In the embodiments of the present invention, the dendrite circuit generates a reset signal and a calculation signal that does not overlap with the reset signal according to the input pulse signal or the output pulse signal of the cell body circuit of the previous layer of neurons to control the operation of the synapse, eliminating the need for clock generation timing and realizing a circuit-level asynchronous circuit; the synaptic circuit realizes digital-to-analog fusion and memory and computing integration, improving the energy efficiency of the circuit; the time scheduling module generates timing according to the input pulse signal or the enable signal output by the previous layer of neuron units to ensure the correct comparison output of the cell body. In addition, the synaptic circuit can receive multiple pulses simultaneously and can affect the membrane potential voltage simultaneously without interfering with each other, thus avoiding the problems of waiting and conflict between pulses. Since the membrane potential is expressed by an analog level, the natural leakage behavior of the analog circuit is similar to the leakage behavior of neurons, making full use of the time information between pulses in the continuous time domain and making the neuron circuit of the present invention more consistent with the neuron model.

[0048] The embodiments of the present invention also provide a pulse neural network, including a multi-layer neuron network. The neural network layers are in a fully connected structure. Each layer of the neuron network includes at least two neuron unit circuits in the above embodiments. The input of the first layer of the neuron network layer is an input pulse signal. As can be seen from the above embodiments, each layer of operation is performed according to the LIF neuron model. Figure 11 is a schematic structural diagram of a layer of the network layer of the pulse neural network. As Figure 11As shown, the dendrite D of this layer of neurons receives the pulse output signal of the previous layer, generates a reset signal and a calculation signal to trigger a row of synapses S connected thereto. When the input of the dendrite is In, the weight of the synapse is W, and the change in membrane potential is ΔVmem, Figure 11 The change in membrane potential corresponding to the represented neuron can be expressed in the following matrix calculation form:

[0049]

[0050] Based on the above embodiments, Figure 12 This embodiment of the present invention provides a schematic diagram of the structure of an intelligent Internet of Things chip. As Figure 12 shown, the intelligent Internet of Things chip in this embodiment includes: a wake-up chip and a high-performance module that is driven by the wake-up signal output by the wake-up chip to trigger and enter the working mode. The wake-up chip includes multiple functional processing modules, and each functional processing module is triggered by an event to enter the working mode. Each functional processing module includes multiple circuit units, and each circuit unit includes the pulse neural network in the above embodiment. Since the above pulse neural network is a circuit-level event-driven circuit, the intelligent Internet of Things chip realizes the ultimate event drive from the system level to the module level and then to the circuit level, so that the data flow of each level of the circuit does not wait for each other, achieving the effect of real-time response.

[0051] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A neuron unit circuit, characterized in that, Comprising: a dendrite circuit, a synaptic circuit containing a membrane potential capacitor, a soma circuit, and a timing planning module, the dendrite circuit is configured to generate a reset signal and a calculation signal that does not overlap with the reset signal according to an input pulse signal or an output pulse signal of the soma circuit of the previous layer of neurons; the synaptic circuit is configured to store weights and perform a potential accumulation operation on the membrane potential capacitor according to the stored weights and the output of the dendrite circuit, where the weights are used to represent the connection strength between neurons and are stored in the synaptic circuit in digital complement code; the soma circuit is configured to compare the membrane potential of the membrane potential capacitor with a threshold voltage to determine whether to output a pulse signal; the timing planning module is configured to generate a timing according to an input pulse signal or an enable signal output by the previous layer of neuron units, so that the threshold voltage is stored in the threshold capacitor before the soma performs a comparison operation, and to trigger the soma to perform a comparison operation.

2. The circuit according to claim 1, wherein The reset signal includes an excitatory reset signal and an inhibitory reset signal that is inverted with respect to the excitatory reset signal, and the calculation signal includes an excitatory calculation signal and an inhibitory calculation signal that is inverted with respect to the excitatory calculation signal.

3. The circuit according to claim 2, wherein, The synaptic circuit includes: M excitatory units, N inhibitory units, M+N weight storage units, M+N logic AND gates, and a membrane potential capacitor. M weight storage units and the excitatory calculation signal are correspondingly connected to the inputs of M logic AND gates, N weight storage units and the inhibitory calculation signal are correspondingly connected to the inputs of N logic AND gates, the outputs of M logic AND gates are correspondingly connected to M excitatory units, the outputs of N logic AND gates are correspondingly connected to N inhibitory units. The excitatory reset signal output by the dendrite circuit is used to control whether the M excitatory units charge the membrane potential capacitor, and the inhibitory reset signal output by the dendrite circuit is used to control whether the N inhibitory units discharge the membrane potential capacitor. M and N are both positive integers.

4. The circuit according to claim 3, wherein The excitatory unit includes: a first PMOS transistor, a second PMOS transistor, and an excitatory unit capacitor. The drain of the first PMOS transistor is connected to a first power supply, the gate of the first PMOS transistor is connected to the excitatory reset signal output port of the dendrite circuit, the source of the first PMOS transistor is connected to the drain of the second PMOS transistor and the excitatory unit capacitor, the gate of the second PMOS transistor is connected to the excitatory calculation signal output port of the dendrite circuit, and the source of the second PMOS transistor is connected to the membrane potential capacitor.

5. The circuit according to claim 3, wherein The inhibitory unit includes: a first NMOS transistor, a second NMOS transistor, and an inhibitory unit capacitor. The source of the first NMOS transistor is grounded, the gate of the first NMOS transistor is connected to the inhibitory reset signal output port of the dendrite circuit, the drain of the first NMOS transistor is connected to the source of the second NMOS transistor and the inhibitory unit capacitor, the gate of the second NMOS transistor is connected to the inhibitory calculation signal output port of the dendrite circuit, and the drain of the second NMOS transistor is connected to the membrane potential capacitor.

6. The circuit according to claim 3, characterized in that, The weight storage unit is a latch.

7. The circuit according to any one of claims 1-6, characterized in that, The dendrite circuit includes a delay chain to generate asynchronous timing.

8. A spiking neural network, characterized in that, Comprising a multi-layer neuron network, where the neural network layers are in a fully connected structure. Each layer of neuron network includes at least two neuron unit circuits as described in any one of claims 1-7, and the input of the first layer of neuron network layer is an input pulse signal.

9. An intelligent Internet of Things chip, characterized in that, Comprising: A wake-up chip and a high-performance module that is triggered by a wake-up signal output by the wake-up chip to enter a working mode. The wake-up chip includes a plurality of functional processing modules, each functional processing module is triggered by an event to enter a working mode, each functional processing module includes a plurality of circuit units, and each circuit unit includes a pulsed neural network as described in claim 8.

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