An image sensor remote driver circuit that provides fast and stable line control signals

Abstract

The present disclosure relates to an image sensor remote driver circuit that provides fast and stable row control signals. The image sensor includes a pixel array having rows and columns of pixels. Each row of the pixel array has a first end opposite to a second end of each row of the pixel array. A control circuit is coupled to the first end of each row of the pixel array to provide a control signal from the first end of each row of the pixel array to each row of the pixel array. A remote driver circuit is coupled to the second end of each row of the pixel array to selectively further drive the control signal provided by the control circuit from the first end of each row of the pixel array from the second end of each row of the pixel array. The control circuit is further coupled to provide a remote control signal to the remote driver circuit.

Description

[0001] Relevant information of divisional application

[0002] This is a divisional application. The parent case of this divisional application is a patent application for invention with the application date of November 10, 2020, application number 202011247308.8, and invention title "Image sensor remote driver circuit for providing fast and stable row control signals". Technical Field

[0003] The present invention generally relates to image sensors, and more particularly but not exclusively to control circuits for generating row control signals for image sensors. Background Art

[0004] Image sensors have become ubiquitous. They are widely used in digital still cameras, cellular phones, security cameras, and medical, automotive, and other applications. The technology for manufacturing image sensors has been developing rapidly. For example, the demand for higher resolution and lower power consumption has driven the further miniaturization and integration of these devices.

[0005] In large format image sensors (e.g., 48 megapixel image sensors), when row control signals or horizontal drive signals are routed across the entire rows of the image sensor, they typically propagate relatively long distances. As a result, as the size of the image sensor increases, the row control signals may experience increasingly long resistor-capacitor (RC) delays. For example, assuming that the control circuit generating the row control signal is coupled to the left side of the pixel array, when the row control signal propagates from the left side to the right side of the pixel array, the drive strength of the row control signal causes an unbalanced output (e.g., shading) due to the RC delay on the row control signal. Summary of the Invention

[0006] One embodiment of the present application provides an image sensor, comprising: a pixel array including rows and columns of pixels, wherein each row of the pixel array has a first end opposite to a second end of each row of the pixel array; a control circuit coupled to the first end of each row of the pixel array to provide a control signal to each row of the pixel array from the first end of each row of the pixel array; and a remote driver circuit coupled to the second end of each row of the pixel array to selectively further drive the control signal provided by the control circuit from the first end of each row of the pixel array from the second end of each row of the pixel array, wherein the control circuit is further coupled to provide a remote control signal to the remote driver circuit.

[0007] Another embodiment of the present application provides an imaging system, which includes: a pixel array including a plurality of pixel units arranged in a plurality of rows and a plurality of columns, wherein each row of the plurality of rows of the pixel array has a first end opposite to a second end of each row of the plurality of rows of the pixel array; a control circuit coupled to the first end of each row of the plurality of rows of the pixel array to provide a control signal from the first end of each row of the plurality of rows of the pixel array to each row of the plurality of rows of the pixel array; a distal driver circuit coupled to the second end of each row of the plurality of rows of the pixel array to selectively further drive the control signal provided by the control circuit from the first end of each row of the plurality of rows of the pixel array from the second end of each row of the plurality of rows of the pixel array, wherein the control circuit is further coupled to provide a distal control signal to the distal driver circuit; and a readout circuit coupled to the pixel array to read out image data from the plurality of pixel units. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The non-limiting and non-exhaustive embodiments of the present invention are described with reference to the following drawings, wherein like reference numerals represent like components in the various views unless otherwise specified.

[0009] Figure 1 An example of an imaging system including an example distal driver circuit in accordance with the teachings of the present invention is shown.

[0010] Figure 2A An example of an example pixel in an example pixel array in accordance with the teachings of the present invention is shown.

[0011] Figure 2B An example timing diagram is shown, which shows an example row control signal that undergoes an RC time delay from the left side to the right side of the pixel array, and the example row control signal results in a slower settling time and an unbalanced image.

[0012] Figure 3 An example schematic diagram of a distal driver circuit in accordance with the teachings of the present invention is shown.

[0013] Figure 4 An example timing diagram is shown, which shows examples of control signals and distal control signals found in an example of a distal driver circuit.

[0014] Figure 5 Another example schematic diagram of a distal driver circuit in accordance with the teachings of the present invention is shown.

[0015] Figure 6 Yet another example schematic diagram of a distal driver circuit in accordance with the teachings of the present invention is shown.

[0016] Figure 7Shows yet another example schematic diagram of a distal driver circuit in accordance with the teachings of the present invention.

[0017] Figure 8 Shows another example timing diagram in accordance with the teachings of the present invention, which shows examples of control signals and distal control signals found in another example of a distal driver circuit.

[0018] In several views of the drawings, corresponding reference numerals denote corresponding components. Those skilled in the art will appreciate that the elements in the drawings are shown for simplicity and clarity purposes and are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be exaggerated relative to other elements to help improve the understanding of the various embodiments of the present invention. Also, commonly understood elements that are useful or necessary in a commercially viable embodiment are typically not described, so as to make the viewing of these various embodiments of the present invention clearer. Detailed Description

[0019] Examples are described herein for providing a fast settling time for row control signals of an image sensor in a distal driver circuit. In the following description, numerous specific details are set forth to provide a thorough understanding of the examples. However, those skilled in the relevant art will recognize that the techniques described herein may be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring certain aspects.

[0020] Throughout the specification, references to "an example" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present invention. Thus, the phrases "in an example" or "in an embodiment" appearing throughout the specification do not necessarily all refer to the same example. Additionally, the particular features, structures, or characteristics may be combined in any suitable manner in one or more examples.

[0021] Throughout the specification, several terms are used. These terms have their ordinary meaning in the art to which they pertain, unless the context of their use herein clearly dictates otherwise. It should be noted that the element names and symbols herein may be used interchangeably (e.g., Si for silicon); however, both have the same meaning.

[0022] The row control signal in an image sensor preferably has a fast settling time. However, in advanced technologies such as image sensors with a feature size of 40 nm and below, the parasitic RC values are very high. As will be discussed, examples in accordance with the teachings of the present invention include an image sensor having a pixel array including rows and columns. In various examples, a control circuit is coupled to one end of each row of the pixel array to provide a row control signal. Additionally, in accordance with the teachings of the present invention, a distal driver circuit is coupled to the opposite end of each row of the pixel array to further drive the row control signal provided by the control circuit and reduce the settling time of the row control signal. In accordance with the teachings of the present invention, as the settling time is reduced, the drive strength of the row control signal is more balanced between opposite sides of the pixel array, which enables the pixel array to provide a more balanced image with reduced shading.

[0023] For illustration, Figure 1 FIG. shows a block diagram of an example imaging system 100 including a distal driver circuit in accordance with the teachings of the present invention. The imaging system 100 may be implemented as a complementary metal oxide semiconductor (“CMOS”) image sensor. As Figure 1 shown in the example shown, the imaging system 100 includes a pixel array 102 that is coupled on one side (e.g., the “left” side) to a control circuit 110 to receive a control signal 116. The pixel array 102 is also coupled to a readout circuit 106, and the readout circuit 106 is coupled to functional logic 108. In the depicted example, the distal driver circuit is coupled to the pixel array 102 on the side opposite the control circuit 110 (e.g., on the “right” side) to further drive the control signal 116 that has propagated through the pixel array 102. In this example, the distal driver circuit 114 is coupled to receive a distal control signal 118 generated by the control circuit 110.

[0024] In one example, the pixel array 102 and the distal driver circuit 114 may be included in a pixel chip of the imaging system 100, and the control circuit, the readout circuit 106, and the functional logic 108 may be included in an application specific integrated circuit (ASIC) chip of the imaging system 100.

[0025] In the examples described in the present invention, it should be noted that, for purposes of explanation, the control circuit 110 is shown as being coupled to the “left” side pixel array 102, and the distal driver circuit 114 is shown as being coupled to the “right” side of the pixel array 102. However, in other examples, it can be understood that the control circuit 110 and the distal driver circuit 114 may be coupled to different sides of the pixel array 102, but they are coupled to opposite sides of the pixel array 102 such that the control signal 116 is driven by the control circuit 110 from one side of the pixel array 102 and further driven by the distal driver circuit 114 from the opposite side of the pixel array 102.

[0026] The illustrated embodiment of the pixel array 102 is a two-dimensional ("2D") array of imaging sensors or pixel cells 104 (e.g., pixel cells P1, P2, …, Pn). As shown in the depicted example, each pixel cell 104 is arranged in rows (e.g., rows R1 to Ry) and columns (e.g., columns C1 to Cx) to acquire image data of a person, place, object, etc., which can then be used to draw an image of the person, place, object, etc.

[0027] In one example, and then transferred to the functional logic 108, after each pixel cell 104 has acquired its image charge or image data, the image data is read out by the readout circuit 106 via the readout column bit lines 112. In various examples, the readout circuit 106 may include an amplification circuit (not shown), a column readout circuit including an analog-to-digital conversion (ADC) circuit, or other circuits. The functional logic 108 may simply store the image data or even manipulate the image data by applying post-image effects (e.g., cropping, rotation, red-eye removal, brightness adjustment, contrast adjustment, or others). In one example, the readout circuit 106 may read out one row of image data at a time along the readout column lines (shown), or may read out the image data using various other techniques (not shown), such as simultaneous serial readout or fully parallel readout of all pixels.

[0028] In one example, the control circuit 110 is coupled to drive the control signals 116 that will be received by the pixel array 102, thereby controlling the operating characteristics of the pixel array 102. For example, in one example, the control circuit 110 generates the control signals 116, which may include transfer gate signals, reset signals, row selection signals, and other control signals to control the transfer and readout of image data from one or more photodiodes of each pixel cell 104 of the pixel array 102. Additionally, in some examples, the control circuit 110 may generate a shutter signal for controlling image acquisition. In one example, the shutter signal is a global shutter signal for enabling all pixels within the pixel array 102 to simultaneously capture their respective image data during a single acquisition window. In another example, the shutter signal is a rolling shutter signal such that each row of pixels, each column of pixels, or each group of pixels is sequentially enabled during successive acquisition windows. The shutter signal may also establish the exposure time, which is the length of time the shutter remains open. In one embodiment, the exposure time for each frame is set to be the same.

[0029] Figure 2A An example of one of the multiple pixel cells 204 included in an example pixel array according to the teachings of the present invention is shown. It should be noted that Figure 2A the example pixel cell 204 shown in Figure 1An example of one of the pixel units 104, and like-named and numbered elements referred to below are coupled and function similar to those described above.

[0030] As shown in the depicted example, pixel unit 204 is coupled to be driven by row control signals 216 received from a control circuit (e.g., control circuit 110). In the example shown, row control signals 216 include a reset control signal (RST) 220, a floating diffusion capacitor control signal (FDC) 222, a transfer control signal (TX) 224, and a row select control signal (RS) 226. A photodiode 228 is coupled to generate photo-generated image charges (e.g., electrons) in response to incident light. In response to the transfer control signal 224, a transfer transistor 230 is coupled to the photodiode 228 to transfer the photo-generated image charges from the photodiode 228 to a floating diffusion capacitor (Cfdc) 240, which is coupled to a floating diffusion (FD) node 232. In response to the photo-generated image charges stored in the floating diffusion capacitor Cfdc 240, the gate terminal of an amplifier transistor, such as a source follower (SF) transistor 234, is coupled to the floating diffusion capacitor Cfdc 240 to generate an image data signal. In response to the row select control signal 226, a row select transistor is coupled to the source follower transistor 234 to output the image data signal from the source follower transistor 234 to a bit line 212. A reset transistor 238 is coupled between a power supply AVDD and the floating diffusion capacitor Cfdc 240 in response to the reset control signal 220 to reset the pixel unit 204. Additionally, in the depicted example, the floating diffusion node 232 and the floating diffusion capacitor Cfdc 240 are coupled between the floating diffusion capacitor control signal 222 and the floating diffusion node.

[0031] Figure 2AThe example depicted also shows the parasitic capacitances of the various row control signals 216 that can be coupled to each pixel unit 204. For example, there is a parasitic capacitance Ctx_fd between the transfer control signal 224 and the floating diffusion node 232. There is a parasitic capacitance Crst_fd between the reset control signal 220 and the floating diffusion node 232. There is a parasitic capacitance Crs_fd between the row select control signal 226 and the floating diffusion node 232. There is a parasitic capacitance Cavdd_bl between the power supply AVDD and the bit line 212. There is a parasitic capacitance Cfdc_bl between the floating diffusion capacitor control signal 222 and the bit line 212. There is a parasitic capacitance Ctx_bl between the transfer control signal 224 and the bit line 212. There is a parasitic capacitance Crs_bl between the row select control signal 226 and the bit line 212. The effects of all the parasitic capacitances accumulate as the row control signal 216 propagates across the pixel array from one side to the opposite side, which accumulates or increases the RC delay, and the RC delay slows down the settling time of the row control signal 216 as it propagates across the pixel units of the pixel array.

[0032] For illustration, Figure 2B An example timing diagram is shown that shows an example row control signal that undergoes an RC time delay from one side of the pixel array (e.g., the "left" side) to the opposite side of the pixel array (e.g., the "right" side or the far end), and the example row control signal thus results in a slower settling time and an unbalanced image output. In the depicted illustration, the row control signal 216 is initially at a high value and then transitions to a low value. As shown in the example, for the leftmost column of the pixel array, the row control signal 216 quickly settles from the high value to the low value. However, due to the RC time delay, the row control signal 216 on the rightmost column of the pixel array slowly settles from the high value to the low value. Therefore, the time point at which the column analog-to-digital converter (ADC) samples the signal is adversely affected by the RC time delay on the rightmost column or the far end column compared to the leftmost column of the pixel array, which results in an unbalanced image.

[0033] Figure 3 An example schematic diagram of a far-end driver circuit 314 according to the teachings of the present invention is shown. It should be noted that Figure 3 the example far-end driver circuit 314 and control signals shown in may be examples of the above-mentioned far-end driver circuit and control signals, and the similarly named and numbered elements cited below are coupled and function similarly to those described above. As will be in Figure 3 the example depicted, the far-end driver circuit 314 is configured to reduce the settling time of the reset control signal RST 320A and the floating diffusion capacitor control signal FDC 322A by pulling down these signals of the active row during the transition from a high level to a low level. In this example, the row select control signal RS 326A is configured to indicate the active row.

[0034] In Figure 3 the illustrated example, the control circuit 310 is disposed in the ASIC chip and is coupled to generate row control signals and far-end control signals. The illustrated example shows row control signals including a reset control signal RST 320, a floating diffusion capacitor control signal FDC 322, and a row selection control signal RS 326, which are coupled to be received by a hybrid bond (HB) or through a through-silicon via (TSV) on the "left" side or proximal side 367 of the pixel chip closest to the control circuit 310. The illustrated example also shows far-end control signals including a far-end floating diffusion capacitor control signal (FE_FDC_CTRL) 342 and a far-end reset control signal (FE_RST_CTRL) 344, which are coupled to be received by a hybrid bond (HB) or through a through-silicon via (TSV) on the "right" end or distal side 368 of the pixel chip opposite to the control circuit 310.

[0035] In the depicted example, the reset control signal RST 320A, the floating diffusion capacitor control signal FDC 322A, and the row selection control signal RS 326A are coupled to drive pixel cells (e.g., pixel cells 104, 204) of the active rows of the pixel array, while the reset control signal RST 320B, the floating diffusion capacitor control signal FDC 322B, and the row selection control signal RS 326B are coupled to drive pixel cells (e.g., pixel cells 104, 204) of the idle rows of the pixel array. Thus, it can be understood that in one example, the idle row control signal values are AVDD for the reset control signal RST 320B, NVDD for the row selection control signal RS 326B, and AGND for the floating diffusion capacitor control signal FDC 322B.

[0036] In the depicted example, the far-end driver circuit 314 includes six transistors coupled to the far end (e.g., adjacent to the rightmost column) of each row of the pixel array. Thus, it can be understood that after the control signals have propagated through all the pixels (e.g., 104, 204) of each row of the pixel array, the illustrated transistors of the far-end driver circuit 314 are coupled to receive the control signals. In the illustrated example, the six transistors of each row are NMOS transistors. In other examples, it can be understood that the polarities of the six transistors and the control signals may be reversed according to the logic of the system. In Figure 3In the illustrated example, the distal driver circuit 314 coupled to the active row includes a transistor 346A having a first end coupled to receive a reset control signal RST 320A and a second end coupled to a reference terminal such as ground (GND). The distal driver circuit 314 further includes a transistor 350A having a first end coupled to the control terminal of the transistor 346A and a second end coupled to receive a distal reset control signal FE_RST_CTRL 344. The control terminal of the transistor 350A is coupled to receive a row select control signal 326A. The distal driver circuit 314 further includes a transistor 352A coupled between the control terminal of the transistor 346A and the reference terminal (e.g., ground). The control terminal of the transistor 352A is coupled to receive the reset control signal RST 320A. Thus, it can be understood that the transistor 346A is coupled to selectively further drive the reset control signal RST 320A in response to the row select control signal RS 326A and the distal reset control signal FE_RST_CTRL 344.

[0037] In particular, the transistor 346A serves as a pull-down transistor to further drive the reset control signal RST 320A and reduce its settling time by pulling the reset control signal RST 320A down to a reference voltage or ground. The transistor 350A serves as a pass-through transistor to pass the distal reset control signal FE_RST_CTRL 344 in response to the row select control signal RS 326A (for the active row). If the reset control signal RST 320A is high, the transistor 352A serves as a disable transistor in response to the reset control signal RST 320A to inhibit the pull-down transistor 346A from pulling down the reset control signal RST 320A.

[0038] In Figure 3In the illustrated example, the distal driver circuit 314 coupled to the active row further includes a transistor 348A having a first end coupled to receive a floating diffusion capacitor control signal FDC 322A and a second end coupled to a reference terminal (e.g., ground). The distal driver circuit 314 further includes a transistor 354A having a first end coupled to the control terminal of the transistor 348A and a second end coupled to receive a distal floating diffusion capacitor control signal FE_FDC_CTRL 342. The control terminal of the transistor 354A is coupled to receive a row select control signal RS326A. The distal driver circuit 314 further includes a transistor 356A coupled between the control terminal of the transistor 348A and the reference terminal (e.g., ground). The control terminal of the transistor 356A is coupled to receive the floating diffusion capacitor control signal FDC 322A. Thus, it can be understood that the transistor 348A is coupled to selectively further drive the floating diffusion capacitor control signal FDC 322A in response to the row select control signal RS 326A and the distal floating diffusion capacitor control signal FE_FDC_CTRL 342.

[0039] Specifically, the transistor 348A serves as a pull-down transistor to further drive the floating diffusion capacitor control signal FDC 322A and reduce its settling time by pulling down the floating diffusion capacitor control signal FDC 322A to a reference voltage or ground. The transistor 354A serves as a pass-through transistor to pass through the distal floating diffusion capacitor control signal FE_FDC_CTRL 342 in response to the row select control signal RS 326A (for the active row). If the floating diffusion capacitor control signal FDC 322A is high, the transistor 356A serves as a disabling transistor in response to the floating diffusion capacitor control signal FDC 322A to prohibit the pull-down transistor 348A from pulling down the floating diffusion capacitor control signal FDC 322A.

[0040] For an idle row, it can be understood that the transistors 346B, 348B, 350B, 352B, 354B, and 356B are similarly coupled to the pixel unit as described above for the transistors 346A, 348A, 350A, 352A, 354A, and 356A of the pixel unit coupled to the active row. However, since the row is idle, the row select control signal RS 326B remains low, which prohibits the transistors 350B and 354B from passing through the distal control signals FE_FDC_CTRL 342 and FE_RST_CTRL 344 in the idle row.

[0041] For illustration, Figure 4Shows an example timing diagram in accordance with the teachings of the present invention, which shows examples of row control signals and far-end control signals found in an example of a far-end driver circuit. It should be noted that Figure 4 The example row control signals and far-end control signals shown in Figures 1 to 3 can be examples of the control signals and far-end control signals in the above

[0042] As shown, prior to time T1, the reset control signal RST 420A received at the left end of the pixel array (e.g., closest to the control circuit) rapidly transitions from a high value to a low value. The row selection control signal RS426, transfer control signal TX 424, and floating diffusion capacitor control signal FDC 422A at the left end of the pixel array are low. However, at the opposite right or far-end of the pixel array, due to the RC delay experienced by the reset control signal RST 420 as it propagates through the pixel array from the left end to the far-end, the reset control signal RST 420B begins to transition from a high value to a low value more slowly. However, at time T2, the active row selection control signal 426 and far-end reset control signal FE_RST_CTRL444 are activated, which further drives the reset control signal RST 420B by pulling the reset control signal RST down to a reference voltage or ground, thereby "accelerating" the transition and reducing the settling time in accordance with the teachings of the present invention. In one example, sampling of the reset level output of the pixel cell can occur at this point in correlated double sampling (CDS).

[0043] Continuing with the depicted example, at time T3, the floating diffusion capacitor control signal FDC 422A received at the left end of the pixel array (e.g., closest to the control circuit) rapidly transitions from a high value to a low value, but at the opposite right or far-end of the pixel array, due to the RC delay experienced by the floating diffusion capacitor control signal FDC 422 as it propagates through the pixel array from the left end to the far-end, the floating diffusion capacitor control signal FDC 422B begins to transition from a high value to a low value more slowly. However, at time T4, the active row selection control signal 426 and far-end floating diffusion capacitor control signal FE_FDC_CTRL442 are activated, which further drives the floating diffusion capacitor control signal FDC 422B by pulling the floating diffusion capacitor control signal FDC down to a reference voltage or ground, thereby "accelerating" the transition and reducing the settling time in accordance with the teachings of the present invention. In one example, sampling of the signal level output of the pixel cell can occur at this point in correlated double sampling (CDS).

[0044] Figure 5 Shows another example schematic diagram of a far-end driver circuit 514 in accordance with the teachings of the present invention. It should be noted that Figure 5The example distal driver circuit 514 and control signals shown in can be other examples of the distal driver circuit and control signals described above, and elements with similar names and numbers cited below are coupled and function similarly to those described above. As will be described in Figure 5 As shown in the example depicted in, the distal driver circuit 514 is also configured to reduce the settling time of the reset control signal RST 520A and the floating diffusion capacitor control signal FDC 522A by pulling down these signals of the active row during the transition from high to low.

[0045] It can also be understood that Figure 5 the example distal driver circuit 514 shown in is similar to Figure 3 the example distal driver circuit 314 shown in. For example, in the Figure 5 example depicted, the control circuit 510 is disposed in the ASIC chip and is coupled to generate row control signals and distal control signals. The example shown depicts row control signals including a reset control signal RST 520, a floating diffusion capacitor control signal FDC 522, and a row selection control signal RS 526, which are coupled to be received by a hybrid bond (HB) or through a through-silicon via (TSV) on the "left" side or proximal side 567 of the pixel chip closest to the control circuit 510. The example also depicts distal control signals including a distal floating diffusion capacitor control signal (FE_FDC_CTRL) 542 and a distal reset control signal (FE_RST_CTRL) 544, which are coupled to be received by a hybrid bond (HB) or through a through-silicon via (TSV) on the "right" end or distal side 568 of the pixel chip opposite the control circuit 510.

[0046] In the depicted example, the reset control signal RST 520A, the floating diffusion capacitor control signal FDC 522A, and the row selection control signal RS 526A are coupled to drive the pixel units (e.g., pixel units 104, 204) of the active rows of the pixel array, while the reset control signal RST 520B, the floating diffusion capacitor control signal FDC 522B, and the row selection control signal RS 526B are coupled to drive the pixel units (e.g., pixel units 104, 204) of the idle rows of the pixel array. Thus, it can be understood that in one example, the idle row control signal values are AVDD for the reset control signal RST 520B, NVDD for the row selection control signal RS 526B, and AGND for the floating diffusion capacitor control signal FDC 522B.

[0047] In the depicted example, the distal driver circuit 514 includes three transistors coupled to the distal end (e.g., adjacent to the rightmost column) of each row of the pixel array. Thus, it can be understood that after the control signal has propagated through all the pixels (e.g., 104, 204) of each row of the pixel array, the depicted transistors of the distal driver circuit 514 are coupled to receive the control signal. In the depicted example, the three transistors of each row are NMOS transistors. In other examples, it can be understood that the polarities of the three transistors and the control signal can be reversed according to the logic of the system. In Figure 5 the depicted example, the distal driver circuit 514 coupled to the active row includes a transistor 546A having a first end coupled to receive the reset control signal RST 520A through a transistor 558A and a second end coupled to a reference terminal (such as ground). The control terminal of the transistor 546A is coupled to receive the distal reset control signal FE_RST_CTRL 544. The transistor 558A has a first end coupled to receive the reset control signal RST 520A, and the second end of the transistor 558A is coupled to the first end of the transistor 546A. The control terminal of the transistor 558A is coupled to receive the row select control signal RS 526A. Thus, it can be understood that the transistor 546A is selectively coupled to receive the reset control signal RST 520A through the transistor 558A in response to the row select control signal RS 526A, and the transistor 546A is coupled to selectively further drive the reset control signal 520A in response to the row select control signal RS 526A and the distal reset control signal FE_RST_CTRL 544.

[0048] Specifically, the transistor 546A acts as a pull-down transistor to further drive the reset control signal RST 520A and reduce its settling time by pulling down the reset control signal RST 520A to a reference voltage or ground. The transistor 558A acts as a pass-through transistor to pass the reset control signal RST 520A in response to the row select control signal RS 526A (for the active row).

[0049] In Figure 5 the depicted example, the distal driver circuit 514 coupled to the active row further includes a transistor 548A having a first end coupled to receive the floating diffusion capacitor control signal FDC 522A and a second end coupled to a reference terminal such as ground. The control terminal of the transistor 548A is coupled to receive the distal floating diffusion capacitor control signal FE_FDC_CTRL 542. Thus, it can be understood that the transistor 548A is coupled to selectively further drive the floating diffusion capacitor control signal FDC 522A in response to the distal floating diffusion capacitor control signal FE_FDC_CTRL 542.

[0050] Specifically, transistor 548A serves as a pull-down transistor to further drive the floating diffusion capacitor control signal FDC 522A and reduce its settling time by pulling down the floating diffusion capacitor control signal FDC 522A to a reference voltage or ground in response to the far-end floating diffusion capacitor control signal FE_FDC_CTRL 542.

[0051] For an idle row, it can be understood that transistors 546B, 548B, and 558B are similarly coupled to the pixel unit as described above for transistors 546A, 548A, and 558A coupled to the pixel unit of the active row. However, since the row is idle, the row selection control signal RS 526B remains low, which prohibits transistor 558B from passing through the reset control signal RST520B in the idle row. Additionally, since the default signal of the floating diffusion capacitor control signal FDC 522B is AGND, no additional transistors are required for the floating diffusion capacitor control signal FDC 522B in the idle row.

[0052] It can be understood that the row control signals and far-end control signals associated with Figure 5 the example far-end driver circuit 514 are the same as those shown in the timing diagram shown in Figure 4 the example.

[0053] Figure 6 Another example schematic diagram of a far-end driver circuit 614 according to the teachings of the present invention is shown. It should be noted that Figure 6 the example far-end driver circuit 614 and control signals shown in Figure 6 can be other examples of the above-mentioned far-end driver circuit and control signals, and the similarly named and numbered elements cited below are coupled and function similarly to those described above. As shown in the example depicted in

[0054] It should also be understood that Figure 6 the example far-end driver circuit 614 shown in Figure 5 has similarities with the example far-end driver circuit 514 shown in Figure 6In the illustrated example, the control circuit 610 is disposed within the ASIC chip and is coupled to generate row control signals and far-end control signals. The illustrated example shows row control signals including a reset control signal RST 620, a floating diffusion capacitor control signal FDC 622, and a row select control signal RS 626, which are coupled to be received by a hybrid bond (HB) or through a through-silicon via (TSV) on the "left" side or proximal side 667 of the pixel chip closest to the control circuit 610. The illustrated example also shows far-end control signals including a far-end floating diffusion capacitor control signal (FE_FDC_CTRL) 642 and a far-end reset control signal (FE_RST_CTRL) 644, which are coupled to be received by a hybrid bond (HB) or through a through-silicon via (TSV) on the "right" end or distal end 668 of the pixel chip opposite the control circuit 610.

[0055] In the depicted example, the reset control signal RST 620A, the floating diffusion capacitor control signal FDC 622A, and the row select control signal RS 626A are coupled to drive pixel cells (e.g., pixel cells 104, 204) of the active rows of the pixel array, while the reset control signal RST 620B, the floating diffusion capacitor control signal FDC 622B, and the row select control signal RS 626B are coupled to drive pixel cells (e.g., pixel cells 104, 204) of the idle rows of the pixel array. Thus, it can be understood that in one example, the idle row control signal values are AVDD for the reset control signal RST 520B, NVDD for the row select control signal RS 626B, and AGND for the floating diffusion capacitor control signal FDC 622B.

[0056] In the depicted example, the far-end driver circuit 614 includes four transistors coupled to the far end (e.g., adjacent to the rightmost column) of each row of the pixel array. Thus, it can be understood that after the control signals have propagated through all the pixels (e.g., 104, 204) of each row of the pixel array, the illustrated transistors of the far-end driver circuit 614 are coupled to receive the control signals. In the illustrated example, the four transistors of each row are NMOS transistors. In other examples, it can be understood that the polarities of the four transistors and the control signals can be reversed according to the logic of the system. In Figure 6In the example shown, the distal driver circuit 614 coupled to the active row includes a transistor 646A having a first end coupled to receive a reset control signal RST 620A through a transistor 658A and a second end coupled to a reference terminal such as ground. The control terminal of the transistor 646A is coupled to receive a distal reset control signal FE_RST_CTRL 644. The transistor 658A has a first end coupled to receive the reset control signal RST 620A, and the second end of the transistor 658A is coupled to the first end of the transistor 646A. The control terminal of the transistor 658A is coupled to receive a row select control signal RS 626A. Thus, it can be understood that the transistor 646A is selectively coupled to receive the reset control signal RST 620A through the transistor 658A in response to the row select row select control signal RS 626A, and the transistor 646A is coupled to further drive the reset control signal RST 620A selectively in response to the row select control signal RS 626A and the distal reset control signal FE_RST_CTRL 644.

[0057] In particular, the transistor 646A serves as a pull-down transistor to further drive the reset control signal RST 620A and reduce its settling time by pulling down the reset control signal RST 620A to a reference voltage or ground. The transistor 658A serves as a pass-through transistor to pass the reset control signal RST 620A in response to the row select control signal RS 626A (for the active row).

[0058] In Figure 6 the example shown, the distal driver circuit 614 coupled to the active row further includes a transistor 648A having a first end coupled to receive a floating diffusion capacitor control signal FDC 622A through a transistor 660A and a second end coupled to a reference terminal (e.g., ground). The control terminal of the transistor 648A is coupled to receive a distal floating diffusion capacitor control signal FE_FDC_CTRL 542. The transistor 660A has a first end coupled to receive the floating diffusion capacitor control signal FDC 622A, and the second end of the transistor 660A is coupled to the first end of the transistor 648A. The control terminal of the transistor 660A is coupled to receive a row select control signal RS 626A. Thus, it can be understood that the transistor 648A is coupled to further drive the floating diffusion capacitor control signal FDC 622A selectively in response to the row select control signal RS 626A and the distal floating diffusion capacitor control signal FE_FDC_CTRL 642.

[0059] Specifically, transistor 648A serves as a pull - down transistor to further drive the floating diffusion capacitor control signal FDC 622A and reduce its settling time by pulling down the floating diffusion capacitor control signal FDC 622A to a reference voltage or ground in response to the far - end floating diffusion capacitor control signal FE_FDC_CTRL 642. Transistor 660A serves as a pass - through transistor to pass the floating diffusion capacitor control signal FDC 622A in response to the row - select control signal RS 626A (for the active row).

[0060] For an idle row, it can be understood that transistors 646B, 648B, 658B, and 660B are similarly coupled to the pixel unit as described above for transistors 646A, 648A, 658A, and 660B coupled to the pixel unit of the active row. However, since the row is idle, the row - select control signal RS 626B remains low, which prohibits transistor 558B from passing the reset control signal RST620B and prohibits transistor 560B from passing the floating diffusion capacitor control signal FDC 622B in the idle row.

[0061] It can be understood that the row control signals and far - end control signals associated with the Figure 6 example far - end driver circuit 614 are the same as those shown in the timing diagram of the Figure 4 example.

[0062] Figure 7 Another example schematic diagram of a far - end driver circuit 714 according to the teachings of the present invention is shown. It should be noted that Figure 7 the example far - end driver circuit 714 and control signals shown in can be examples of the above - mentioned far - end driver circuit and control signals, and the similarly named and numbered elements cited below are coupled and function similarly to those described above. As shown in the example depicted in Figure 7 the far - end driver circuit 714 is configured to reduce the settling time of the floating diffusion capacitor control signals FDC 722A and FDC 722C by pulling up the floating diffusion capacitor control signals FDC 722A and FDC 722C of the active row and the pre - charge row during the transition from low to high. In this example, the transfer control signals TX 724A and TX 724C are configured to indicate the active row and the pre - charge row.

[0063] In Figure 7In the illustrated example, the control circuit 710 is disposed within the ASIC chip and is coupled to generate row control signals and far-end control signals. The illustrated example shows row control signals that include a transfer control signal TX 724 and a floating diffusion capacitor control signal FDC 722, which are coupled to be received by a hybrid bond (HB) or through a through-silicon via (TSV) on the "left" side or proximal side 767 of the pixel chip closest to the control circuit 710. The illustrated example also shows far-end control signals that include a far-end floating diffusion capacitor up control signal (FE_FDC_UP_CTRL) 746, which is coupled to be received by a hybrid bond (HB) or through a through-silicon via (TSV) on the "right" end or distal end 768 of the pixel chip opposite the control circuit 710.

[0064] In the depicted example, the floating diffusion capacitor control signal FDC 722A and the transfer control signal TX 724A are coupled to drive pixel cells (e.g., pixel cells 104, 204) of an active row of the pixel array, the floating diffusion capacitor control signal FDC 722C and the transfer control signal TX 724C are coupled to drive pixel cells (e.g., pixel cells 104, 204) of a precharged row of the pixel array, and the floating diffusion capacitor control signal FDC 722B and the transfer control signal TX 724B are coupled to drive pixel cells (e.g., pixel cells 104, 204) of an idle row of the pixel array. Thus, it can be understood that in one example, the idle row control signal value is AGND for the floating diffusion capacitor control signal FDC 722B and NVDD for the transfer control signal TX 724B.

[0065] In the depicted example, the far-end driver circuit 714 includes two transistors coupled to the far end (e.g., adjacent to the rightmost column) of each row of the pixel array. Thus, it can be understood that after the control signals have propagated through all of the pixels (e.g., 104, 204) of each row of the pixel array, the illustrated transistors of the far-end driver circuit 714 are coupled to receive the control signals. In the illustrated example, the two transistors of each row are NMOS transistors. In other examples, it can be understood that the two transistors and the polarity of the control signals can be reversed depending on the logic of the system. In Figure 7In the example shown, the distal driver circuit 714 coupled to the active row includes a transistor 762A, which is serially coupled with a transistor 764A between a floating diffusion capacitor control signal FDC 722A and a power supply AVDD. The control terminal of the transistor 762A is coupled to receive a transfer control signal TX 724A, and the control terminal of the transistor 764A is coupled to receive a distal floating diffusion capacitor up control signal FE_FDC_UP_CTRL 746. Thus, the transistor control signal TX 724A and the distal floating diffusion capacitor up control signal FE_FDC_UP_CTRL 746 are coupled to selectively further drive the floating diffusion capacitor control signal FDC 722A in response to the transfer control signal TX 724A and the distal floating diffusion capacitor up control signal FE_FDC_UP_CTRL 746.

[0066] Specifically, the transistor 764A acts as a pull-up transistor to further drive the floating diffusion capacitor control signal FDC 722A and reduce its settling time by pulling up the floating diffusion capacitor control signal FDC 722A to the AVDD power supply voltage in response to the distal floating diffusion capacitor up control signal FE_FDC_UP_CTRL 746. The transistor 762A acts as a pass-through transistor to pass through the floating diffusion capacitor control signal FDC722A in response to the transfer control signal TX 724A (for the active row).

[0067] In Figure 7 In the example shown, the transistors coupled to the row being precharged are coupled in the same manner as the transistors coupled to the active row. Specifically, the distal driver circuit 714 coupled to the row being precharged includes a transistor 762C, which is serially coupled with a transistor 764C between a floating diffusion capacitor control signal FDC 722C and a power supply AVDD. The control terminal of the transistor 762C is coupled to receive a transfer control signal TX 724C, and the control terminal of the transistor 764C is coupled to receive a distal floating diffusion capacitor up control signal FE_FDC_UP_CTRL 746. Thus, the transistor control signal TX 724C and the distal floating diffusion capacitor up control signal FE_FDC_UP_CTRL 746 are coupled to selectively further drive the floating diffusion capacitor control signal FDC 722C in response to the transfer control signal TX 724C and the distal floating diffusion capacitor up control signal FE_FDC_UP_CTRL 746.

[0068] For an idle row, it can be understood that transistors 762B and 764B are similarly coupled to the pixel unit, as described above for transistors 762A and 764 coupled to the pixel unit of the active row and / or transistors 762C and 764C coupled to the pixel unit of the precharged row. However, since the row is idle, the transfer control signal TX 724B remains low (e.g., NVDD), which prohibits transistor 762B from controlling the floating diffusion capacitor control signal FDC 722B through the floating diffusion capacitor in the idle row.

[0069] For illustration, Figure 8 Another example timing diagram is shown, which shows examples of control signals and remote control signals found in another example of a remote driver circuit in accordance with the teachings of the present invention. It should be noted that Figure 8 The exemplary row control signals and remote control signals shown in may be examples of the control signals and remote control signals described above Figure 7 and the similarly named and numbered elements referred to below are coupled and function similarly to those described above.

[0070] As Figure 8 The upper part of shows, the timing diagram shows the row control signals and remote control signals of the remote driver circuit, which is coupled to the row of the precharged pixel array. As shown before time T5, and at the left end of the pixel array (e.g., closest to the control circuit), the floating diffusion capacitor control signal FDC 822A received is at a low value, the reset control signal RST 820 is pulsed, and the transfer control signal TX 824 transitions to a high value. At time T5, the floating diffusion capacitor control signal FDC 822A transitions sharply from a low value to a high value. However, at the opposite right or remote end of the pixel array, due to the RC delay experienced by the floating diffusion capacitor control signal FDC 822B as it propagates through the pixel array from the left end to the remote end, the floating diffusion capacitor control signal FDC 822B begins to transition from a low value to a high value more slowly. However, at time T6, the active remote floating diffusion capacitor upper row control signal FE_FDC_UP_CTRL 846 is activated, which further drives the floating diffusion capacitor control signal FDC by pulling up the floating diffusion capacitor control signal FDC 822B to the AVDD power supply voltage, thereby "accelerating" the transition and reducing the settling time in accordance with the teachings of the present invention. In this example, the remote floating diffusion capacitor upper row control signal FE_FDC_UP_CTRL 846 is deactivated at time T7, and the floating diffusion capacitor control signal FDC 822A at the left end transitions to a low value, causing the floating diffusion capacitor control signal FDC 822B at the remote end to fall as shown.

[0071] Continuing with the example described, Figure 8The lower portion of the timing diagram shown in [FIGURE] shows the row control signals and the distal control signals of the distal driver circuit, which is coupled to the active rows of the pixel array. As shown before time T9, the transfer control signal TX 824 and the floating diffusion capacitor control signal FDC 822A received at the left end of the pixel array (e.g., closest to the control circuit) are at a low value. At time T9, the floating diffusion capacitor control signal FDC 822A changes abruptly from a low value to a high value. However, at the opposite right or distal end of the pixel array, due to the RC delay experienced by the floating diffusion capacitor control signal FDC 822B as it propagates through the pixel array from the left end to the distal end, the floating diffusion capacitor control signal FDC 822B begins to change more slowly from a low value to a high value. However, at time T10, the distal floating diffusion capacitor up control signal FE_FDC_UP_CTRL 846 is activated, which further drives the floating diffusion capacitor control signal FDC by pulling up the floating diffusion capacitor control signal FDC 822B to the AVDD supply voltage, thereby "accelerating" the transition and reducing the settling time in accordance with the teachings of the present invention. In this example, the transfer control signal TX 824 and the distal floating diffusion capacitor up control signal FE_FDC_UP_CTRL 846 change to a low value at time T11, and then the floating diffusion capacitor control signal FDC822A changes to a low value at time T12, causing the floating diffusion capacitor control signal FDC 822B at the distal end to fall as shown.

[0072] The foregoing description of the illustrated embodiments of the invention, including what is described in the abstract, is not intended to be exhaustive or to limit the invention to the precise forms disclosed. While specific embodiments of the invention have been described herein for purposes of illustration, various modifications will be apparent to those skilled in the relevant art within the scope of the invention.

[0073] These modifications can be made to the invention in light of the above detailed description. The terms used in the following claims should not be construed as limiting the invention to the specific embodiments disclosed in the specification. Rather, the scope of the invention is defined entirely by the appended claims, which are to be interpreted in accordance with established principles of claim interpretation.

Claims

1. An image sensor, which comprises: a pixel array including rows and columns of pixels, wherein each row of the pixel array has a first end opposite to a second end of each row of the pixel array; a control circuit coupled to the first end of each row of the pixel array to provide control signals from the first end of each row of the pixel array to each row of the pixel array, wherein the control signals provided from the control circuit to the first end of each row of the pixel array include transfer signals and floating diffusion capacitor control signals; and a distal driver circuit coupled to the second end of each row of the pixel array to selectively further drive the control signals provided from the first end of each row of the pixel array by the control circuit from the second end of each row of the pixel array, wherein the control circuit is further coupled to provide a distal control signal to the distal driver circuit, wherein the distal driver circuit includes a ninth transistor serially coupled to a tenth transistor, wherein the ninth transistor and the tenth transistor are coupled between the floating diffusion capacitor control signal and a power supply, wherein a control terminal of the ninth transistor is coupled to receive the transfer signal, and wherein a control terminal of the tenth transistor is coupled to receive a distal floating diffusion up-control signal included in the distal control signal received from the control circuit, such that the ninth transistor and the tenth transistor are coupled to selectively further drive the floating diffusion capacitor control signal in response to the transfer signal and the distal floating diffusion up-control signal.

2. An imaging system, which comprises: a pixel array including a plurality of pixel units arranged in a plurality of rows and a plurality of columns, wherein each row of the plurality of rows of the pixel array has a first end opposite to a second end of each row of the plurality of rows of the pixel array; a control circuit coupled to the first end of each row of the plurality of rows of the pixel array to provide control signals from the first end of each row of the plurality of rows of the pixel array to each row of the plurality of rows of the pixel array, wherein the control signals generated by the control circuit for each row of the plurality of rows of the pixel array include transfer signals, floating diffusion capacitor control signals, reset signals, and row selection signals; A distal driver circuit, which is coupled to the second ends of each of the plurality of rows of the pixel array to selectively further drive the control signals provided by the control circuit from the first ends of each of the plurality of rows of the pixel array at the second ends of each of the plurality of rows of the pixel array, wherein the control circuit is further coupled to provide a distal control signal to the distal driver circuit, wherein the distal driver circuit includes a ninth transistor serially coupled with a tenth transistor, wherein the ninth transistor and the tenth transistor are coupled between the floating diffusion capacitor control signal and a power supply, wherein the control terminal of the ninth transistor is coupled to receive the transfer signal, and wherein the control terminal of the tenth transistor is coupled to a distal floating diffusion upward control signal included in the distal control signal received from the control circuit, such that the ninth transistor and the tenth transistor are coupled to selectively further drive the floating diffusion capacitor control signal in response to the transfer signal and the distal floating diffusion upward control signal; and A readout circuit, which is coupled to the pixel array to read out image data from the plurality of pixel units.

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